1 /* $NetBSD: amdgpu_object.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Jerome Glisse <glisse@freedesktop.org> 31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 32 * Dave Airlie 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdgpu_object.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $"); 36 37 #include <linux/list.h> 38 #include <linux/slab.h> 39 #include <drm/drmP.h> 40 #include <drm/amdgpu_drm.h> 41 #include <drm/drm_cache.h> 42 #include "amdgpu.h" 43 #include "amdgpu_trace.h" 44 45 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 46 struct ttm_mem_reg *mem) 47 { 48 u64 ret = 0; 49 if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { 50 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > 51 adev->mc.visible_vram_size ? 52 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 53 mem->size; 54 } 55 return ret; 56 } 57 58 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 59 struct ttm_mem_reg *old_mem, 60 struct ttm_mem_reg *new_mem) 61 { 62 u64 vis_size; 63 if (!adev) 64 return; 65 66 if (new_mem) { 67 switch (new_mem->mem_type) { 68 case TTM_PL_TT: 69 atomic64_add(new_mem->size, &adev->gtt_usage); 70 break; 71 case TTM_PL_VRAM: 72 atomic64_add(new_mem->size, &adev->vram_usage); 73 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 74 atomic64_add(vis_size, &adev->vram_vis_usage); 75 break; 76 } 77 } 78 79 if (old_mem) { 80 switch (old_mem->mem_type) { 81 case TTM_PL_TT: 82 atomic64_sub(old_mem->size, &adev->gtt_usage); 83 break; 84 case TTM_PL_VRAM: 85 atomic64_sub(old_mem->size, &adev->vram_usage); 86 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 87 atomic64_sub(vis_size, &adev->vram_vis_usage); 88 break; 89 } 90 } 91 } 92 93 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 94 { 95 struct amdgpu_bo *bo; 96 97 bo = container_of(tbo, struct amdgpu_bo, tbo); 98 99 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); 100 101 mutex_lock(&bo->adev->gem.mutex); 102 list_del_init(&bo->list); 103 mutex_unlock(&bo->adev->gem.mutex); 104 drm_gem_object_release(&bo->gem_base); 105 amdgpu_bo_unref(&bo->parent); 106 kfree(bo->metadata); 107 kfree(bo); 108 } 109 110 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 111 { 112 if (bo->destroy == &amdgpu_ttm_bo_destroy) 113 return true; 114 return false; 115 } 116 117 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 118 struct ttm_placement *placement, 119 struct ttm_place *placements, 120 u32 domain, u64 flags) 121 { 122 u32 c = 0, i; 123 124 placement->placement = placements; 125 placement->busy_placement = placements; 126 127 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 128 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && 129 adev->mc.visible_vram_size < adev->mc.real_vram_size) { 130 placements[c].fpfn = 131 adev->mc.visible_vram_size >> PAGE_SHIFT; 132 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 133 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN; 134 } 135 placements[c].fpfn = 0; 136 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 137 TTM_PL_FLAG_VRAM; 138 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) 139 placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN; 140 } 141 142 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 143 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 144 placements[c].fpfn = 0; 145 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 146 TTM_PL_FLAG_UNCACHED; 147 } else { 148 placements[c].fpfn = 0; 149 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 150 } 151 } 152 153 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 154 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 155 placements[c].fpfn = 0; 156 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | 157 TTM_PL_FLAG_UNCACHED; 158 } else { 159 placements[c].fpfn = 0; 160 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 161 } 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 165 placements[c].fpfn = 0; 166 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 167 AMDGPU_PL_FLAG_GDS; 168 } 169 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 170 placements[c].fpfn = 0; 171 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 172 AMDGPU_PL_FLAG_GWS; 173 } 174 if (domain & AMDGPU_GEM_DOMAIN_OA) { 175 placements[c].fpfn = 0; 176 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 177 AMDGPU_PL_FLAG_OA; 178 } 179 180 if (!c) { 181 placements[c].fpfn = 0; 182 placements[c++].flags = TTM_PL_MASK_CACHING | 183 TTM_PL_FLAG_SYSTEM; 184 } 185 placement->num_placement = c; 186 placement->num_busy_placement = c; 187 188 for (i = 0; i < c; i++) { 189 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 190 (placements[i].flags & TTM_PL_FLAG_VRAM) && 191 !placements[i].fpfn) 192 placements[i].lpfn = 193 adev->mc.visible_vram_size >> PAGE_SHIFT; 194 else 195 placements[i].lpfn = 0; 196 } 197 } 198 199 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) 200 { 201 amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, 202 rbo->placements, domain, rbo->flags); 203 } 204 205 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 206 struct ttm_placement *placement) 207 { 208 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 209 210 memcpy(bo->placements, placement->placement, 211 placement->num_placement * sizeof(struct ttm_place)); 212 bo->placement.num_placement = placement->num_placement; 213 bo->placement.num_busy_placement = placement->num_busy_placement; 214 bo->placement.placement = bo->placements; 215 bo->placement.busy_placement = bo->placements; 216 } 217 218 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 219 unsigned long size, int byte_align, 220 bool kernel, u32 domain, u64 flags, 221 struct sg_table *sg, 222 struct ttm_placement *placement, 223 struct reservation_object *resv, 224 struct amdgpu_bo **bo_ptr) 225 { 226 struct amdgpu_bo *bo; 227 enum ttm_bo_type type; 228 unsigned long page_align; 229 size_t acc_size; 230 int r; 231 232 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 233 #ifdef __NetBSD__ /* XXX ALIGN means something else. */ 234 size = round_up(size, PAGE_SIZE); 235 #else 236 size = ALIGN(size, PAGE_SIZE); 237 #endif 238 239 if (kernel) { 240 type = ttm_bo_type_kernel; 241 } else if (sg) { 242 type = ttm_bo_type_sg; 243 } else { 244 type = ttm_bo_type_device; 245 } 246 *bo_ptr = NULL; 247 248 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 249 sizeof(struct amdgpu_bo)); 250 251 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 252 if (bo == NULL) 253 return -ENOMEM; 254 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 255 if (unlikely(r)) { 256 kfree(bo); 257 return r; 258 } 259 bo->adev = adev; 260 INIT_LIST_HEAD(&bo->list); 261 INIT_LIST_HEAD(&bo->va); 262 bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM | 263 AMDGPU_GEM_DOMAIN_GTT | 264 AMDGPU_GEM_DOMAIN_CPU | 265 AMDGPU_GEM_DOMAIN_GDS | 266 AMDGPU_GEM_DOMAIN_GWS | 267 AMDGPU_GEM_DOMAIN_OA); 268 269 bo->flags = flags; 270 271 /* For architectures that don't support WC memory, 272 * mask out the WC flag from the BO 273 */ 274 if (!drm_arch_can_wc_memory()) 275 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 276 277 amdgpu_fill_placement_to_bo(bo, placement); 278 /* Kernel allocation are uninterruptible */ 279 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 280 &bo->placement, page_align, !kernel, NULL, 281 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 282 if (unlikely(r != 0)) { 283 return r; 284 } 285 *bo_ptr = bo; 286 287 trace_amdgpu_bo_create(bo); 288 289 return 0; 290 } 291 292 int amdgpu_bo_create(struct amdgpu_device *adev, 293 unsigned long size, int byte_align, 294 bool kernel, u32 domain, u64 flags, 295 struct sg_table *sg, 296 struct reservation_object *resv, 297 struct amdgpu_bo **bo_ptr) 298 { 299 struct ttm_placement placement = {0}; 300 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 301 302 memset(&placements, 0, 303 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 304 305 amdgpu_ttm_placement_init(adev, &placement, 306 placements, domain, flags); 307 308 return amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 309 domain, flags, sg, &placement, 310 resv, bo_ptr); 311 } 312 313 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 314 { 315 bool is_iomem; 316 int r; 317 318 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 319 return -EPERM; 320 321 if (bo->kptr) { 322 if (ptr) { 323 *ptr = bo->kptr; 324 } 325 return 0; 326 } 327 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 328 if (r) { 329 return r; 330 } 331 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 332 if (ptr) { 333 *ptr = bo->kptr; 334 } 335 return 0; 336 } 337 338 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 339 { 340 if (bo->kptr == NULL) 341 return; 342 bo->kptr = NULL; 343 ttm_bo_kunmap(&bo->kmap); 344 } 345 346 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 347 { 348 if (bo == NULL) 349 return NULL; 350 351 ttm_bo_reference(&bo->tbo); 352 return bo; 353 } 354 355 void amdgpu_bo_unref(struct amdgpu_bo **bo) 356 { 357 struct ttm_buffer_object *tbo; 358 359 if ((*bo) == NULL) 360 return; 361 362 tbo = &((*bo)->tbo); 363 ttm_bo_unref(&tbo); 364 if (tbo == NULL) 365 *bo = NULL; 366 } 367 368 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 369 u64 min_offset, u64 max_offset, 370 u64 *gpu_addr) 371 { 372 int r, i; 373 unsigned fpfn, lpfn; 374 375 if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) 376 return -EPERM; 377 378 if (WARN_ON_ONCE(min_offset > max_offset)) 379 return -EINVAL; 380 381 if (bo->pin_count) { 382 bo->pin_count++; 383 if (gpu_addr) 384 *gpu_addr = amdgpu_bo_gpu_offset(bo); 385 386 if (max_offset != 0) { 387 u64 domain_start; 388 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 389 domain_start = bo->adev->mc.vram_start; 390 else 391 domain_start = bo->adev->mc.gtt_start; 392 WARN_ON_ONCE(max_offset < 393 (amdgpu_bo_gpu_offset(bo) - domain_start)); 394 } 395 396 return 0; 397 } 398 amdgpu_ttm_placement_from_domain(bo, domain); 399 for (i = 0; i < bo->placement.num_placement; i++) { 400 /* force to pin into visible video ram */ 401 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 402 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 403 (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) { 404 if (WARN_ON_ONCE(min_offset > 405 bo->adev->mc.visible_vram_size)) 406 return -EINVAL; 407 fpfn = min_offset >> PAGE_SHIFT; 408 lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; 409 } else { 410 fpfn = min_offset >> PAGE_SHIFT; 411 lpfn = max_offset >> PAGE_SHIFT; 412 } 413 if (fpfn > bo->placements[i].fpfn) 414 bo->placements[i].fpfn = fpfn; 415 if (!bo->placements[i].lpfn || 416 (lpfn && lpfn < bo->placements[i].lpfn)) 417 bo->placements[i].lpfn = lpfn; 418 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 419 } 420 421 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 422 if (likely(r == 0)) { 423 bo->pin_count = 1; 424 if (gpu_addr != NULL) 425 *gpu_addr = amdgpu_bo_gpu_offset(bo); 426 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 427 bo->adev->vram_pin_size += amdgpu_bo_size(bo); 428 else 429 bo->adev->gart_pin_size += amdgpu_bo_size(bo); 430 } else { 431 dev_err(bo->adev->dev, "%p pin failed\n", bo); 432 } 433 return r; 434 } 435 436 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 437 { 438 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 439 } 440 441 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 442 { 443 int r, i; 444 445 if (!bo->pin_count) { 446 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); 447 return 0; 448 } 449 bo->pin_count--; 450 if (bo->pin_count) 451 return 0; 452 for (i = 0; i < bo->placement.num_placement; i++) { 453 bo->placements[i].lpfn = 0; 454 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 455 } 456 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 457 if (likely(r == 0)) { 458 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 459 bo->adev->vram_pin_size -= amdgpu_bo_size(bo); 460 else 461 bo->adev->gart_pin_size -= amdgpu_bo_size(bo); 462 } else { 463 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); 464 } 465 return r; 466 } 467 468 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 469 { 470 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 471 if (0 && (adev->flags & AMD_IS_APU)) { 472 /* Useless to evict on IGP chips */ 473 return 0; 474 } 475 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 476 } 477 478 void amdgpu_bo_force_delete(struct amdgpu_device *adev) 479 { 480 struct amdgpu_bo *bo, *n; 481 482 if (list_empty(&adev->gem.objects)) { 483 return; 484 } 485 dev_err(adev->dev, "Userspace still has active objects !\n"); 486 list_for_each_entry_safe(bo, n, &adev->gem.objects, list) { 487 dev_err(adev->dev, "%p %p %lu %lu force free\n", 488 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 489 *((unsigned long *)&bo->gem_base.refcount)); 490 mutex_lock(&bo->adev->gem.mutex); 491 list_del_init(&bo->list); 492 mutex_unlock(&bo->adev->gem.mutex); 493 /* this should unref the ttm bo */ 494 drm_gem_object_unreference_unlocked(&bo->gem_base); 495 } 496 } 497 498 int amdgpu_bo_init(struct amdgpu_device *adev) 499 { 500 /* Add an MTRR for the VRAM */ 501 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 502 adev->mc.aper_size); 503 DRM_INFO("Detected VRAM RAM=%"PRIu64"M, BAR=%lluM\n", 504 adev->mc.mc_vram_size >> 20, 505 (unsigned long long)adev->mc.aper_size >> 20); 506 DRM_INFO("RAM width %dbits DDR\n", 507 adev->mc.vram_width); 508 return amdgpu_ttm_init(adev); 509 } 510 511 void amdgpu_bo_fini(struct amdgpu_device *adev) 512 { 513 amdgpu_ttm_fini(adev); 514 arch_phys_wc_del(adev->mc.vram_mtrr); 515 } 516 517 #ifndef __NetBSD__ /* XXX unused? */ 518 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 519 struct vm_area_struct *vma) 520 { 521 return ttm_fbdev_mmap(vma, &bo->tbo); 522 } 523 #endif 524 525 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 526 { 527 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 528 return -EINVAL; 529 530 bo->tiling_flags = tiling_flags; 531 return 0; 532 } 533 534 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 535 { 536 lockdep_assert_held(&bo->tbo.resv->lock.base); 537 538 if (tiling_flags) 539 *tiling_flags = bo->tiling_flags; 540 } 541 542 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 543 uint32_t metadata_size, uint64_t flags) 544 { 545 void *buffer; 546 547 if (!metadata_size) { 548 if (bo->metadata_size) { 549 kfree(bo->metadata); 550 bo->metadata = NULL; 551 bo->metadata_size = 0; 552 } 553 return 0; 554 } 555 556 if (metadata == NULL) 557 return -EINVAL; 558 559 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 560 if (buffer == NULL) 561 return -ENOMEM; 562 563 kfree(bo->metadata); 564 bo->metadata_flags = flags; 565 bo->metadata = buffer; 566 bo->metadata_size = metadata_size; 567 568 return 0; 569 } 570 571 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 572 size_t buffer_size, uint32_t *metadata_size, 573 uint64_t *flags) 574 { 575 if (!buffer && !metadata_size) 576 return -EINVAL; 577 578 if (buffer) { 579 if (buffer_size < bo->metadata_size) 580 return -EINVAL; 581 582 if (bo->metadata_size) 583 memcpy(buffer, bo->metadata, bo->metadata_size); 584 } 585 586 if (metadata_size) 587 *metadata_size = bo->metadata_size; 588 if (flags) 589 *flags = bo->metadata_flags; 590 591 return 0; 592 } 593 594 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 595 struct ttm_mem_reg *new_mem) 596 { 597 struct amdgpu_bo *rbo; 598 599 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 600 return; 601 602 rbo = container_of(bo, struct amdgpu_bo, tbo); 603 amdgpu_vm_bo_invalidate(rbo->adev, rbo); 604 605 /* update statistics */ 606 if (!new_mem) 607 return; 608 609 /* move_notify is called before move happens */ 610 amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); 611 } 612 613 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 614 { 615 struct amdgpu_device *adev; 616 struct amdgpu_bo *abo; 617 unsigned long offset, size, lpfn; 618 int i, r; 619 620 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 621 return 0; 622 623 abo = container_of(bo, struct amdgpu_bo, tbo); 624 adev = abo->adev; 625 if (bo->mem.mem_type != TTM_PL_VRAM) 626 return 0; 627 628 size = bo->mem.num_pages << PAGE_SHIFT; 629 offset = bo->mem.start << PAGE_SHIFT; 630 if ((offset + size) <= adev->mc.visible_vram_size) 631 return 0; 632 633 /* hurrah the memory is not visible ! */ 634 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 635 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 636 for (i = 0; i < abo->placement.num_placement; i++) { 637 /* Force into visible VRAM */ 638 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 639 (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn)) 640 abo->placements[i].lpfn = lpfn; 641 } 642 r = ttm_bo_validate(bo, &abo->placement, false, false); 643 if (unlikely(r == -ENOMEM)) { 644 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 645 return ttm_bo_validate(bo, &abo->placement, false, false); 646 } else if (unlikely(r != 0)) { 647 return r; 648 } 649 650 offset = bo->mem.start << PAGE_SHIFT; 651 /* this should never happen */ 652 if ((offset + size) > adev->mc.visible_vram_size) 653 return -EINVAL; 654 655 return 0; 656 } 657 658 /** 659 * amdgpu_bo_fence - add fence to buffer object 660 * 661 * @bo: buffer object in question 662 * @fence: fence to add 663 * @shared: true if fence should be added shared 664 * 665 */ 666 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 667 bool shared) 668 { 669 struct reservation_object *resv = bo->tbo.resv; 670 671 if (shared) 672 reservation_object_add_shared_fence(resv, fence); 673 else 674 reservation_object_add_excl_fence(resv, fence); 675 } 676