1 /* $NetBSD: amdgpu_kms.c,v 1.4 2020/02/14 04:35:19 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: amdgpu_kms.c,v 1.4 2020/02/14 04:35:19 riastradh Exp $"); 32 33 #include <drm/drmP.h> 34 #include "amdgpu.h" 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu_uvd.h" 37 #include "amdgpu_vce.h" 38 39 #include <linux/vga_switcheroo.h> 40 #include <linux/slab.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 44 #include <linux/nbsd-namespace.h> 45 46 #if defined(CONFIG_VGA_SWITCHEROO) 47 bool amdgpu_has_atpx(void); 48 #else 49 static inline bool amdgpu_has_atpx(void) { return false; } 50 #endif 51 52 /** 53 * amdgpu_driver_unload_kms - Main unload function for KMS. 54 * 55 * @dev: drm dev pointer 56 * 57 * This is the main unload function for KMS (all asics). 58 * Returns 0 on success. 59 */ 60 int amdgpu_driver_unload_kms(struct drm_device *dev) 61 { 62 struct amdgpu_device *adev = dev->dev_private; 63 64 if (adev == NULL) 65 return 0; 66 67 if (adev->rmmio_size == 0) 68 goto done_free; 69 70 pm_runtime_get_sync(dev->dev); 71 72 amdgpu_amdkfd_device_fini(adev); 73 74 amdgpu_acpi_fini(adev); 75 76 amdgpu_device_fini(adev); 77 78 done_free: 79 kfree(adev); 80 dev->dev_private = NULL; 81 return 0; 82 } 83 84 /** 85 * amdgpu_driver_load_kms - Main load function for KMS. 86 * 87 * @dev: drm dev pointer 88 * @flags: device flags 89 * 90 * This is the main load function for KMS (all asics). 91 * Returns 0 on success, error on failure. 92 */ 93 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 94 { 95 struct amdgpu_device *adev; 96 int r, acpi_status; 97 98 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 99 if (adev == NULL) { 100 return -ENOMEM; 101 } 102 dev->dev_private = (void *)adev; 103 104 if ((amdgpu_runtime_pm != 0) && 105 amdgpu_has_atpx() && 106 ((flags & AMD_IS_APU) == 0)) 107 flags |= AMD_IS_PX; 108 109 /* amdgpu_device_init should report only fatal error 110 * like memory allocation failure or iomapping failure, 111 * or memory manager initialization failure, it must 112 * properly initialize the GPU MC controller and permit 113 * VRAM allocation 114 */ 115 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 116 if (r) { 117 dev_err(pci_dev_dev(dev->pdev), "Fatal error during GPU init\n"); 118 goto out; 119 } 120 121 /* Call ACPI methods: require modeset init 122 * but failure is not fatal 123 */ 124 if (!r) { 125 acpi_status = amdgpu_acpi_init(adev); 126 if (acpi_status) 127 dev_dbg(pci_dev_dev(dev->pdev), 128 "Error during ACPI methods call\n"); 129 } 130 131 amdgpu_amdkfd_load_interface(adev); 132 amdgpu_amdkfd_device_probe(adev); 133 amdgpu_amdkfd_device_init(adev); 134 135 if (amdgpu_device_is_px(dev)) { 136 pm_runtime_use_autosuspend(dev->dev); 137 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 138 pm_runtime_set_active(dev->dev); 139 pm_runtime_allow(dev->dev); 140 pm_runtime_mark_last_busy(dev->dev); 141 pm_runtime_put_autosuspend(dev->dev); 142 } 143 144 out: 145 if (r) 146 amdgpu_driver_unload_kms(dev); 147 148 149 return r; 150 } 151 152 /* 153 * Userspace get information ioctl 154 */ 155 /** 156 * amdgpu_info_ioctl - answer a device specific request. 157 * 158 * @adev: amdgpu device pointer 159 * @data: request object 160 * @filp: drm filp 161 * 162 * This function is used to pass device specific parameters to the userspace 163 * drivers. Examples include: pci device id, pipeline parms, tiling params, 164 * etc. (all asics). 165 * Returns 0 on success, -EINVAL on failure. 166 */ 167 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 168 { 169 struct amdgpu_device *adev = dev->dev_private; 170 struct drm_amdgpu_info *info = data; 171 struct amdgpu_mode_info *minfo = &adev->mode_info; 172 void __user *out = (void __user *)(long)info->return_pointer; 173 uint32_t size = info->return_size; 174 struct drm_crtc *crtc; 175 uint32_t ui32 = 0; 176 uint64_t ui64 = 0; 177 int i, found; 178 179 if (!info->return_size || !info->return_pointer) 180 return -EINVAL; 181 182 switch (info->query) { 183 case AMDGPU_INFO_ACCEL_WORKING: 184 ui32 = adev->accel_working; 185 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 186 case AMDGPU_INFO_CRTC_FROM_ID: 187 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 188 crtc = (struct drm_crtc *)minfo->crtcs[i]; 189 if (crtc && crtc->base.id == info->mode_crtc.id) { 190 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 191 ui32 = amdgpu_crtc->crtc_id; 192 found = 1; 193 break; 194 } 195 } 196 if (!found) { 197 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 198 return -EINVAL; 199 } 200 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 201 case AMDGPU_INFO_HW_IP_INFO: { 202 struct drm_amdgpu_info_hw_ip ip = {}; 203 enum amd_ip_block_type type; 204 uint32_t ring_mask = 0; 205 uint32_t ib_start_alignment = 0; 206 uint32_t ib_size_alignment = 0; 207 208 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 209 return -EINVAL; 210 211 switch (info->query_hw_ip.type) { 212 case AMDGPU_HW_IP_GFX: 213 type = AMD_IP_BLOCK_TYPE_GFX; 214 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 215 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 216 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 217 ib_size_alignment = 8; 218 break; 219 case AMDGPU_HW_IP_COMPUTE: 220 type = AMD_IP_BLOCK_TYPE_GFX; 221 for (i = 0; i < adev->gfx.num_compute_rings; i++) 222 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 223 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 224 ib_size_alignment = 8; 225 break; 226 case AMDGPU_HW_IP_DMA: 227 type = AMD_IP_BLOCK_TYPE_SDMA; 228 for (i = 0; i < adev->sdma.num_instances; i++) 229 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 230 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 231 ib_size_alignment = 1; 232 break; 233 case AMDGPU_HW_IP_UVD: 234 type = AMD_IP_BLOCK_TYPE_UVD; 235 ring_mask = adev->uvd.ring.ready ? 1 : 0; 236 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 237 ib_size_alignment = 16; 238 break; 239 case AMDGPU_HW_IP_VCE: 240 type = AMD_IP_BLOCK_TYPE_VCE; 241 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) 242 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 243 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 244 ib_size_alignment = 8; 245 break; 246 default: 247 return -EINVAL; 248 } 249 250 for (i = 0; i < adev->num_ip_blocks; i++) { 251 if (adev->ip_blocks[i].type == type && 252 adev->ip_block_status[i].valid) { 253 ip.hw_ip_version_major = adev->ip_blocks[i].major; 254 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 255 ip.capabilities_flags = 0; 256 ip.available_rings = ring_mask; 257 ip.ib_start_alignment = ib_start_alignment; 258 ip.ib_size_alignment = ib_size_alignment; 259 break; 260 } 261 } 262 return copy_to_user(out, &ip, 263 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 264 } 265 case AMDGPU_INFO_HW_IP_COUNT: { 266 enum amd_ip_block_type type; 267 uint32_t count = 0; 268 269 switch (info->query_hw_ip.type) { 270 case AMDGPU_HW_IP_GFX: 271 type = AMD_IP_BLOCK_TYPE_GFX; 272 break; 273 case AMDGPU_HW_IP_COMPUTE: 274 type = AMD_IP_BLOCK_TYPE_GFX; 275 break; 276 case AMDGPU_HW_IP_DMA: 277 type = AMD_IP_BLOCK_TYPE_SDMA; 278 break; 279 case AMDGPU_HW_IP_UVD: 280 type = AMD_IP_BLOCK_TYPE_UVD; 281 break; 282 case AMDGPU_HW_IP_VCE: 283 type = AMD_IP_BLOCK_TYPE_VCE; 284 break; 285 default: 286 return -EINVAL; 287 } 288 289 for (i = 0; i < adev->num_ip_blocks; i++) 290 if (adev->ip_blocks[i].type == type && 291 adev->ip_block_status[i].valid && 292 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 293 count++; 294 295 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 296 } 297 case AMDGPU_INFO_TIMESTAMP: 298 ui64 = amdgpu_asic_get_gpu_clock_counter(adev); 299 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 300 case AMDGPU_INFO_FW_VERSION: { 301 struct drm_amdgpu_info_firmware fw_info; 302 303 /* We only support one instance of each IP block right now. */ 304 if (info->query_fw.ip_instance != 0) 305 return -EINVAL; 306 307 switch (info->query_fw.fw_type) { 308 case AMDGPU_INFO_FW_VCE: 309 fw_info.ver = adev->vce.fw_version; 310 fw_info.feature = adev->vce.fb_version; 311 break; 312 case AMDGPU_INFO_FW_UVD: 313 fw_info.ver = adev->uvd.fw_version; 314 fw_info.feature = 0; 315 break; 316 case AMDGPU_INFO_FW_GMC: 317 fw_info.ver = adev->mc.fw_version; 318 fw_info.feature = 0; 319 break; 320 case AMDGPU_INFO_FW_GFX_ME: 321 fw_info.ver = adev->gfx.me_fw_version; 322 fw_info.feature = adev->gfx.me_feature_version; 323 break; 324 case AMDGPU_INFO_FW_GFX_PFP: 325 fw_info.ver = adev->gfx.pfp_fw_version; 326 fw_info.feature = adev->gfx.pfp_feature_version; 327 break; 328 case AMDGPU_INFO_FW_GFX_CE: 329 fw_info.ver = adev->gfx.ce_fw_version; 330 fw_info.feature = adev->gfx.ce_feature_version; 331 break; 332 case AMDGPU_INFO_FW_GFX_RLC: 333 fw_info.ver = adev->gfx.rlc_fw_version; 334 fw_info.feature = adev->gfx.rlc_feature_version; 335 break; 336 case AMDGPU_INFO_FW_GFX_MEC: 337 if (info->query_fw.index == 0) { 338 fw_info.ver = adev->gfx.mec_fw_version; 339 fw_info.feature = adev->gfx.mec_feature_version; 340 } else if (info->query_fw.index == 1) { 341 fw_info.ver = adev->gfx.mec2_fw_version; 342 fw_info.feature = adev->gfx.mec2_feature_version; 343 } else 344 return -EINVAL; 345 break; 346 case AMDGPU_INFO_FW_SMC: 347 fw_info.ver = adev->pm.fw_version; 348 fw_info.feature = 0; 349 break; 350 case AMDGPU_INFO_FW_SDMA: 351 if (info->query_fw.index >= adev->sdma.num_instances) 352 return -EINVAL; 353 fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version; 354 fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version; 355 break; 356 default: 357 return -EINVAL; 358 } 359 return copy_to_user(out, &fw_info, 360 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 361 } 362 case AMDGPU_INFO_NUM_BYTES_MOVED: 363 ui64 = atomic64_read(&adev->num_bytes_moved); 364 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 365 case AMDGPU_INFO_VRAM_USAGE: 366 ui64 = atomic64_read(&adev->vram_usage); 367 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 368 case AMDGPU_INFO_VIS_VRAM_USAGE: 369 ui64 = atomic64_read(&adev->vram_vis_usage); 370 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 371 case AMDGPU_INFO_GTT_USAGE: 372 ui64 = atomic64_read(&adev->gtt_usage); 373 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 374 case AMDGPU_INFO_GDS_CONFIG: { 375 struct drm_amdgpu_info_gds gds_info; 376 377 memset(&gds_info, 0, sizeof(gds_info)); 378 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 379 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 380 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 381 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 382 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 383 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 384 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 385 return copy_to_user(out, &gds_info, 386 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 387 } 388 case AMDGPU_INFO_VRAM_GTT: { 389 struct drm_amdgpu_info_vram_gtt vram_gtt; 390 391 vram_gtt.vram_size = adev->mc.real_vram_size; 392 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 393 vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; 394 vram_gtt.gtt_size = adev->mc.gtt_size; 395 vram_gtt.gtt_size -= adev->gart_pin_size; 396 return copy_to_user(out, &vram_gtt, 397 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 398 } 399 case AMDGPU_INFO_READ_MMR_REG: { 400 unsigned n, alloc_size; 401 uint32_t *regs; 402 unsigned se_num = (info->read_mmr_reg.instance >> 403 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 404 AMDGPU_INFO_MMR_SE_INDEX_MASK; 405 unsigned sh_num = (info->read_mmr_reg.instance >> 406 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 407 AMDGPU_INFO_MMR_SH_INDEX_MASK; 408 409 /* set full masks if the userspace set all bits 410 * in the bitfields */ 411 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 412 se_num = 0xffffffff; 413 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 414 sh_num = 0xffffffff; 415 416 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 417 if (!regs) 418 return -ENOMEM; 419 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 420 421 for (i = 0; i < info->read_mmr_reg.count; i++) 422 if (amdgpu_asic_read_register(adev, se_num, sh_num, 423 info->read_mmr_reg.dword_offset + i, 424 ®s[i])) { 425 DRM_DEBUG_KMS("unallowed offset %#x\n", 426 info->read_mmr_reg.dword_offset + i); 427 kfree(regs); 428 return -EFAULT; 429 } 430 n = copy_to_user(out, regs, min(size, alloc_size)); 431 kfree(regs); 432 return n ? -EFAULT : 0; 433 } 434 case AMDGPU_INFO_DEV_INFO: { 435 struct drm_amdgpu_info_device dev_info = {}; 436 struct amdgpu_cu_info cu_info; 437 438 dev_info.device_id = dev->pdev->device; 439 dev_info.chip_rev = adev->rev_id; 440 dev_info.external_rev = adev->external_rev_id; 441 dev_info.pci_rev = dev->pdev->revision; 442 dev_info.family = adev->family; 443 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 444 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 445 /* return all clocks in KHz */ 446 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 447 if (adev->pm.dpm_enabled) { 448 dev_info.max_engine_clock = 449 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 450 dev_info.max_memory_clock = 451 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; 452 } else { 453 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 454 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 455 } 456 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 457 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 458 adev->gfx.config.max_shader_engines; 459 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 460 dev_info._pad = 0; 461 dev_info.ids_flags = 0; 462 if (adev->flags & AMD_IS_APU) 463 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 464 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 465 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 466 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 467 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 468 AMDGPU_GPU_PAGE_SIZE; 469 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 470 471 amdgpu_asic_get_cu_info(adev, &cu_info); 472 dev_info.cu_active_number = cu_info.number; 473 dev_info.cu_ao_mask = cu_info.ao_cu_mask; 474 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 475 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); 476 dev_info.vram_type = adev->mc.vram_type; 477 dev_info.vram_bit_width = adev->mc.vram_width; 478 dev_info.vce_harvest_config = adev->vce.harvest_config; 479 480 return copy_to_user(out, &dev_info, 481 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 482 } 483 default: 484 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 485 return -EINVAL; 486 } 487 return 0; 488 } 489 490 491 /* 492 * Outdated mess for old drm with Xorg being in charge (void function now). 493 */ 494 /** 495 * amdgpu_driver_lastclose_kms - drm callback for last close 496 * 497 * @dev: drm dev pointer 498 * 499 * Switch vga_switcheroo state after last close (all asics). 500 */ 501 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 502 { 503 struct amdgpu_device *adev = dev->dev_private; 504 505 amdgpu_fbdev_restore_mode(adev); 506 #ifndef __NetBSD__ /* XXX radeon vga */ 507 vga_switcheroo_process_delayed_switch(); 508 #endif 509 } 510 511 /** 512 * amdgpu_driver_open_kms - drm callback for open 513 * 514 * @dev: drm dev pointer 515 * @file_priv: drm file 516 * 517 * On device open, init vm on cayman+ (all asics). 518 * Returns 0 on success, error on failure. 519 */ 520 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 521 { 522 struct amdgpu_device *adev = dev->dev_private; 523 struct amdgpu_fpriv *fpriv; 524 int r; 525 526 file_priv->driver_priv = NULL; 527 528 r = pm_runtime_get_sync(dev->dev); 529 if (r < 0) 530 return r; 531 532 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 533 if (unlikely(!fpriv)) 534 return -ENOMEM; 535 536 r = amdgpu_vm_init(adev, &fpriv->vm); 537 if (r) 538 goto error_free; 539 540 mutex_init(&fpriv->bo_list_lock); 541 idr_init(&fpriv->bo_list_handles); 542 543 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 544 545 file_priv->driver_priv = fpriv; 546 547 pm_runtime_mark_last_busy(dev->dev); 548 pm_runtime_put_autosuspend(dev->dev); 549 return 0; 550 551 error_free: 552 kfree(fpriv); 553 554 return r; 555 } 556 557 /** 558 * amdgpu_driver_postclose_kms - drm callback for post close 559 * 560 * @dev: drm dev pointer 561 * @file_priv: drm file 562 * 563 * On device post close, tear down vm on cayman+ (all asics). 564 */ 565 void amdgpu_driver_postclose_kms(struct drm_device *dev, 566 struct drm_file *file_priv) 567 { 568 struct amdgpu_device *adev = dev->dev_private; 569 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 570 struct amdgpu_bo_list *list; 571 int handle; 572 573 if (!fpriv) 574 return; 575 576 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 577 578 amdgpu_vm_fini(adev, &fpriv->vm); 579 580 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 581 amdgpu_bo_list_free(list); 582 583 idr_destroy(&fpriv->bo_list_handles); 584 mutex_destroy(&fpriv->bo_list_lock); 585 586 kfree(fpriv); 587 file_priv->driver_priv = NULL; 588 } 589 590 /** 591 * amdgpu_driver_preclose_kms - drm callback for pre close 592 * 593 * @dev: drm dev pointer 594 * @file_priv: drm file 595 * 596 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 597 * (all asics). 598 */ 599 void amdgpu_driver_preclose_kms(struct drm_device *dev, 600 struct drm_file *file_priv) 601 { 602 struct amdgpu_device *adev = dev->dev_private; 603 604 amdgpu_uvd_free_handles(adev, file_priv); 605 amdgpu_vce_free_handles(adev, file_priv); 606 } 607 608 /* 609 * VBlank related functions. 610 */ 611 /** 612 * amdgpu_get_vblank_counter_kms - get frame count 613 * 614 * @dev: drm dev pointer 615 * @pipe: crtc to get the frame count from 616 * 617 * Gets the frame count on the requested crtc (all asics). 618 * Returns frame count on success, -EINVAL on failure. 619 */ 620 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 621 { 622 struct amdgpu_device *adev = dev->dev_private; 623 int vpos, hpos, stat; 624 u32 count; 625 626 if (pipe >= adev->mode_info.num_crtc) { 627 DRM_ERROR("Invalid crtc %u\n", pipe); 628 return -EINVAL; 629 } 630 631 /* The hw increments its frame counter at start of vsync, not at start 632 * of vblank, as is required by DRM core vblank counter handling. 633 * Cook the hw count here to make it appear to the caller as if it 634 * incremented at start of vblank. We measure distance to start of 635 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 636 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 637 * result by 1 to give the proper appearance to caller. 638 */ 639 if (adev->mode_info.crtcs[pipe]) { 640 /* Repeat readout if needed to provide stable result if 641 * we cross start of vsync during the queries. 642 */ 643 do { 644 count = amdgpu_display_vblank_get_counter(adev, pipe); 645 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 646 * distance to start of vblank, instead of regular 647 * vertical scanout pos. 648 */ 649 stat = amdgpu_get_crtc_scanoutpos( 650 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 651 &vpos, &hpos, NULL, NULL, 652 &adev->mode_info.crtcs[pipe]->base.hwmode); 653 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 654 655 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 656 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 657 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 658 } else { 659 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 660 pipe, vpos); 661 662 /* Bump counter if we are at >= leading edge of vblank, 663 * but before vsync where vpos would turn negative and 664 * the hw counter really increments. 665 */ 666 if (vpos >= 0) 667 count++; 668 } 669 } else { 670 /* Fallback to use value as is. */ 671 count = amdgpu_display_vblank_get_counter(adev, pipe); 672 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 673 } 674 675 return count; 676 } 677 678 /** 679 * amdgpu_enable_vblank_kms - enable vblank interrupt 680 * 681 * @dev: drm dev pointer 682 * @pipe: crtc to enable vblank interrupt for 683 * 684 * Enable the interrupt on the requested crtc (all asics). 685 * Returns 0 on success, -EINVAL on failure. 686 */ 687 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 688 { 689 struct amdgpu_device *adev = dev->dev_private; 690 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 691 692 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 693 } 694 695 /** 696 * amdgpu_disable_vblank_kms - disable vblank interrupt 697 * 698 * @dev: drm dev pointer 699 * @pipe: crtc to disable vblank interrupt for 700 * 701 * Disable the interrupt on the requested crtc (all asics). 702 */ 703 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 704 { 705 struct amdgpu_device *adev = dev->dev_private; 706 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 707 708 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 709 } 710 711 /** 712 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp 713 * 714 * @dev: drm dev pointer 715 * @crtc: crtc to get the timestamp for 716 * @max_error: max error 717 * @vblank_time: time value 718 * @flags: flags passed to the driver 719 * 720 * Gets the timestamp on the requested crtc based on the 721 * scanout position. (all asics). 722 * Returns postive status flags on success, negative error on failure. 723 */ 724 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 725 int *max_error, 726 struct timeval *vblank_time, 727 unsigned flags) 728 { 729 struct drm_crtc *crtc; 730 struct amdgpu_device *adev = dev->dev_private; 731 732 if (pipe >= dev->num_crtcs) { 733 DRM_ERROR("Invalid crtc %u\n", pipe); 734 return -EINVAL; 735 } 736 737 /* Get associated drm_crtc: */ 738 crtc = &adev->mode_info.crtcs[pipe]->base; 739 740 /* Helper routine in DRM core does all the work: */ 741 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 742 vblank_time, flags, 743 &crtc->hwmode); 744 } 745 746 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 747 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 748 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 749 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 750 /* KMS */ 751 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 752 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 753 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 754 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 755 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 756 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 757 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 758 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 759 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 760 }; 761 int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 762