1 /* $NetBSD: amdgpu_irq.h,v 1.3 2018/08/27 14:04:50 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __AMDGPU_IRQ_H__ 27 #define __AMDGPU_IRQ_H__ 28 29 #include "amdgpu_ih.h" 30 31 #define AMDGPU_MAX_IRQ_SRC_ID 0x100 32 33 struct amdgpu_device; 34 struct amdgpu_iv_entry; 35 36 enum amdgpu_interrupt_state { 37 AMDGPU_IRQ_STATE_DISABLE, 38 AMDGPU_IRQ_STATE_ENABLE, 39 }; 40 41 struct amdgpu_irq_src { 42 unsigned num_types; 43 atomic_t *enabled_types; 44 const struct amdgpu_irq_src_funcs *funcs; 45 void *data; 46 }; 47 48 /* provided by interrupt generating IP blocks */ 49 struct amdgpu_irq_src_funcs { 50 int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 51 unsigned type, enum amdgpu_interrupt_state state); 52 53 int (*process)(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *source, 55 struct amdgpu_iv_entry *entry); 56 }; 57 58 struct amdgpu_irq { 59 bool installed; 60 spinlock_t lock; 61 /* interrupt sources */ 62 struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID]; 63 64 /* status, etc. */ 65 bool msi_enabled; /* msi enabled */ 66 67 /* interrupt ring */ 68 struct amdgpu_ih_ring ih; 69 const struct amdgpu_ih_funcs *ih_funcs; 70 }; 71 72 void amdgpu_irq_preinstall(struct drm_device *dev); 73 int amdgpu_irq_postinstall(struct drm_device *dev); 74 void amdgpu_irq_uninstall(struct drm_device *dev); 75 irqreturn_t amdgpu_irq_handler(DRM_IRQ_ARGS); 76 77 int amdgpu_irq_init(struct amdgpu_device *adev); 78 void amdgpu_irq_fini(struct amdgpu_device *adev); 79 int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, 80 struct amdgpu_irq_src *source); 81 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 82 struct amdgpu_iv_entry *entry); 83 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 84 unsigned type); 85 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 86 unsigned type); 87 bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, 88 struct amdgpu_irq_src *src, 89 unsigned type); 90 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 91 unsigned type); 92 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 93 unsigned type); 94 95 #endif 96