1*41ec0267Sriastradh /* $NetBSD: amdgpu_ih.h,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2efa246c0Sriastradh 3efa246c0Sriastradh /* 4efa246c0Sriastradh * Copyright 2014 Advanced Micro Devices, Inc. 5efa246c0Sriastradh * 6efa246c0Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7efa246c0Sriastradh * copy of this software and associated documentation files (the "Software"), 8efa246c0Sriastradh * to deal in the Software without restriction, including without limitation 9efa246c0Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10efa246c0Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 11efa246c0Sriastradh * Software is furnished to do so, subject to the following conditions: 12efa246c0Sriastradh * 13efa246c0Sriastradh * The above copyright notice and this permission notice shall be included in 14efa246c0Sriastradh * all copies or substantial portions of the Software. 15efa246c0Sriastradh * 16efa246c0Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17efa246c0Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18efa246c0Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19efa246c0Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20efa246c0Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21efa246c0Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22efa246c0Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 23efa246c0Sriastradh * 24efa246c0Sriastradh */ 25efa246c0Sriastradh 26efa246c0Sriastradh #ifndef __AMDGPU_IH_H__ 27efa246c0Sriastradh #define __AMDGPU_IH_H__ 28efa246c0Sriastradh 29*41ec0267Sriastradh /* Maximum number of IVs processed at once */ 30*41ec0267Sriastradh #define AMDGPU_IH_MAX_NUM_IVS 32 31*41ec0267Sriastradh 32efa246c0Sriastradh struct amdgpu_device; 33*41ec0267Sriastradh struct amdgpu_iv_entry; 34efa246c0Sriastradh 35efa246c0Sriastradh /* 36efa246c0Sriastradh * R6xx+ IH ring 37efa246c0Sriastradh */ 38efa246c0Sriastradh struct amdgpu_ih_ring { 39*41ec0267Sriastradh unsigned ring_size; 40*41ec0267Sriastradh uint32_t ptr_mask; 41*41ec0267Sriastradh u32 doorbell_index; 42*41ec0267Sriastradh bool use_doorbell; 43*41ec0267Sriastradh bool use_bus_addr; 44*41ec0267Sriastradh 45efa246c0Sriastradh struct amdgpu_bo *ring_obj; 460d50c49dSriastradh #ifdef __NetBSD__ 470d50c49dSriastradh bus_dma_segment_t ring_seg; 480d50c49dSriastradh bus_dmamap_t ring_map; 490d50c49dSriastradh #endif 50efa246c0Sriastradh volatile uint32_t *ring; 51efa246c0Sriastradh uint64_t gpu_addr; 52*41ec0267Sriastradh 53*41ec0267Sriastradh uint64_t wptr_addr; 54*41ec0267Sriastradh volatile uint32_t *wptr_cpu; 55*41ec0267Sriastradh 56*41ec0267Sriastradh uint64_t rptr_addr; 57*41ec0267Sriastradh volatile uint32_t *rptr_cpu; 58*41ec0267Sriastradh 59efa246c0Sriastradh bool enabled; 60*41ec0267Sriastradh unsigned rptr; 61*41ec0267Sriastradh atomic_t lock; 62efa246c0Sriastradh }; 63efa246c0Sriastradh 64*41ec0267Sriastradh /* provided by the ih block */ 65*41ec0267Sriastradh struct amdgpu_ih_funcs { 66*41ec0267Sriastradh /* ring read/write ptr handling, called from interrupt context */ 67*41ec0267Sriastradh u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 68*41ec0267Sriastradh void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 69*41ec0267Sriastradh struct amdgpu_iv_entry *entry); 70*41ec0267Sriastradh void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 71efa246c0Sriastradh }; 72efa246c0Sriastradh 73*41ec0267Sriastradh #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) 74*41ec0267Sriastradh #define amdgpu_ih_decode_iv(adev, iv) \ 75*41ec0267Sriastradh (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) 76*41ec0267Sriastradh #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) 77*41ec0267Sriastradh 78*41ec0267Sriastradh int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 79*41ec0267Sriastradh unsigned ring_size, bool use_bus_addr); 80*41ec0267Sriastradh void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 81*41ec0267Sriastradh int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 82efa246c0Sriastradh 83efa246c0Sriastradh #endif 84