1 /* $NetBSD: amdgpu_ih.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.3 2018/08/27 14:04:50 riastradh Exp $"); 28 29 #include <linux/log2.h> 30 #include <drm/drmP.h> 31 #include "amdgpu.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_amdkfd.h" 34 35 /** 36 * amdgpu_ih_ring_alloc - allocate memory for the IH ring 37 * 38 * @adev: amdgpu_device pointer 39 * 40 * Allocate a ring buffer for the interrupt controller. 41 * Returns 0 for success, errors for failure. 42 */ 43 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) 44 { 45 int r; 46 47 /* Allocate ring buffer */ 48 if (adev->irq.ih.ring_obj == NULL) { 49 r = amdgpu_bo_create(adev, adev->irq.ih.ring_size, 50 PAGE_SIZE, true, 51 AMDGPU_GEM_DOMAIN_GTT, 0, 52 NULL, NULL, &adev->irq.ih.ring_obj); 53 if (r) { 54 DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r); 55 return r; 56 } 57 r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); 58 if (unlikely(r != 0)) 59 return r; 60 r = amdgpu_bo_pin(adev->irq.ih.ring_obj, 61 AMDGPU_GEM_DOMAIN_GTT, 62 &adev->irq.ih.gpu_addr); 63 if (r) { 64 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 65 DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r); 66 return r; 67 } 68 r = amdgpu_bo_kmap(adev->irq.ih.ring_obj, 69 (void **)__UNVOLATILE(&adev->irq.ih.ring)); 70 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 71 if (r) { 72 DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r); 73 return r; 74 } 75 } 76 return 0; 77 } 78 79 /** 80 * amdgpu_ih_ring_init - initialize the IH state 81 * 82 * @adev: amdgpu_device pointer 83 * 84 * Initializes the IH state and allocates a buffer 85 * for the IH ring buffer. 86 * Returns 0 for success, errors for failure. 87 */ 88 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, 89 bool use_bus_addr) 90 { 91 u32 rb_bufsz; 92 int r; 93 94 /* Align ring size */ 95 rb_bufsz = order_base_2(ring_size / 4); 96 ring_size = (1 << rb_bufsz) * 4; 97 adev->irq.ih.ring_size = ring_size; 98 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; 99 adev->irq.ih.rptr = 0; 100 adev->irq.ih.use_bus_addr = use_bus_addr; 101 102 if (adev->irq.ih.use_bus_addr) { 103 if (!adev->irq.ih.ring) { 104 /* add 8 bytes for the rptr/wptr shadows and 105 * add them to the end of the ring allocation. 106 */ 107 #ifdef __NetBSD__ 108 const bus_size_t size = adev->irq.ih.ring_size + 8; 109 int rseg __diagused; 110 void *kva; 111 r = -bus_dmamem_alloc(adev->ddev->dmat, size, 112 PAGE_SIZE, 0, &adev->irq.ih.ring_seg, 1, &rseg, 113 BUS_DMA_WAITOK); 114 if (r) { 115 fail0: KASSERT(r); 116 return r; 117 } 118 KASSERT(rseg == 0); 119 r = -bus_dmamap_create(adev->ddev->dmat, size, 1, 120 PAGE_SIZE, 0, BUS_DMA_WAITOK, 121 &adev->irq.ih.ring_map); 122 if (r) { 123 fail1: bus_dmamem_free(adev->ddev->dmat, 124 &adev->irq.ih.ring_seg, 1); 125 goto fail0; 126 } 127 r = -bus_dmamem_map(adev->ddev->dmat, 128 &adev->irq.ih.ring_seg, 1, size, &kva, 129 BUS_DMA_WAITOK); 130 if (r) { 131 fail2: bus_dmamap_destroy(adev->ddev->dmat, 132 adev->irq.ih.ring_map); 133 adev->irq.ih.ring_map = NULL; 134 goto fail1; 135 } 136 r = -bus_dmamap_load(adev->ddev->dmat, 137 adev->irq.ih.ring_map, kva, size, NULL, 138 BUS_DMA_WAITOK); 139 if (r) { 140 fail3: __unused bus_dmamem_unmap(adev->ddev->dmat, kva, size); 141 goto fail2; 142 } 143 adev->irq.ih.ring = kva; 144 adev->irq.ih.rb_dma_addr = 145 adev->irq.ih.ring_map->dm_segs[0].ds_addr; 146 #else 147 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev, 148 adev->irq.ih.ring_size + 8, 149 &adev->irq.ih.rb_dma_addr); 150 if (adev->irq.ih.ring == NULL) 151 return -ENOMEM; 152 #endif 153 memset(__UNVOLATILE(adev->irq.ih.ring), 0, adev->irq.ih.ring_size + 8); 154 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; 155 adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1; 156 } 157 return 0; 158 } else { 159 r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs); 160 if (r) { 161 dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r); 162 return r; 163 } 164 165 r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs); 166 if (r) { 167 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); 168 dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r); 169 return r; 170 } 171 172 return amdgpu_ih_ring_alloc(adev); 173 } 174 } 175 176 /** 177 * amdgpu_ih_ring_fini - tear down the IH state 178 * 179 * @adev: amdgpu_device pointer 180 * 181 * Tears down the IH state and frees buffer 182 * used for the IH ring buffer. 183 */ 184 void amdgpu_ih_ring_fini(struct amdgpu_device *adev) 185 { 186 int r; 187 188 if (adev->irq.ih.use_bus_addr) { 189 if (adev->irq.ih.ring) { 190 /* add 8 bytes for the rptr/wptr shadows and 191 * add them to the end of the ring allocation. 192 */ 193 #ifdef __NetBSD__ 194 const bus_size_t size = adev->irq.ih.ring_size + 8; 195 void *kva = __UNVOLATILE(adev->irq.ih.ring); 196 bus_dmamap_unload(adev->ddev->dmat, 197 adev->irq.ih.ring_map); 198 bus_dmamem_unmap(adev->ddev->dmat, kva, size); 199 bus_dmamap_destroy(adev->ddev->dmat, 200 adev->irq.ih.ring_map); 201 bus_dmamem_free(adev->ddev->dmat, 202 &adev->irq.ih.ring_seg, 1); 203 #else 204 pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8, 205 (void *)adev->irq.ih.ring, 206 adev->irq.ih.rb_dma_addr); 207 #endif 208 adev->irq.ih.ring = NULL; 209 } 210 } else { 211 if (adev->irq.ih.ring_obj) { 212 r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); 213 if (likely(r == 0)) { 214 amdgpu_bo_kunmap(adev->irq.ih.ring_obj); 215 amdgpu_bo_unpin(adev->irq.ih.ring_obj); 216 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 217 } 218 amdgpu_bo_unref(&adev->irq.ih.ring_obj); 219 adev->irq.ih.ring = NULL; 220 adev->irq.ih.ring_obj = NULL; 221 } 222 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); 223 amdgpu_wb_free(adev, adev->irq.ih.rptr_offs); 224 } 225 } 226 227 /** 228 * amdgpu_ih_process - interrupt handler 229 * 230 * @adev: amdgpu_device pointer 231 * 232 * Interrupt hander (VI), walk the IH ring. 233 * Returns irq process return code. 234 */ 235 int amdgpu_ih_process(struct amdgpu_device *adev) 236 { 237 struct amdgpu_iv_entry entry; 238 u32 wptr; 239 240 if (!adev->irq.ih.enabled || adev->shutdown) 241 return IRQ_NONE; 242 243 wptr = amdgpu_ih_get_wptr(adev); 244 245 restart_ih: 246 /* is somebody else already processing irqs? */ 247 if (atomic_xchg(&adev->irq.ih.lock, 1)) 248 return IRQ_NONE; 249 250 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); 251 252 /* Order reading of wptr vs. reading of IH ring data */ 253 rmb(); 254 255 while (adev->irq.ih.rptr != wptr) { 256 u32 ring_index = adev->irq.ih.rptr >> 2; 257 258 /* Before dispatching irq to IP blocks, send it to amdkfd */ 259 amdgpu_amdkfd_interrupt(adev, 260 (const void *)__UNVOLATILE(&adev->irq.ih.ring[ring_index])); 261 262 entry.iv_entry = (const uint32_t *) 263 __UNVOLATILE(&adev->irq.ih.ring[ring_index]); 264 amdgpu_ih_decode_iv(adev, &entry); 265 adev->irq.ih.rptr &= adev->irq.ih.ptr_mask; 266 267 amdgpu_irq_dispatch(adev, &entry); 268 } 269 amdgpu_ih_set_rptr(adev); 270 atomic_set(&adev->irq.ih.lock, 0); 271 272 /* make sure wptr hasn't changed while processing */ 273 wptr = amdgpu_ih_get_wptr(adev); 274 if (wptr != adev->irq.ih.rptr) 275 goto restart_ih; 276 277 return IRQ_HANDLED; 278 } 279