1 /* $NetBSD: amdgpu_ih.c,v 1.4 2020/02/14 14:34:58 maya Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.4 2020/02/14 14:34:58 maya Exp $"); 28 29 #include <drm/drmP.h> 30 #include "amdgpu.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_amdkfd.h" 33 34 /** 35 * amdgpu_ih_ring_alloc - allocate memory for the IH ring 36 * 37 * @adev: amdgpu_device pointer 38 * 39 * Allocate a ring buffer for the interrupt controller. 40 * Returns 0 for success, errors for failure. 41 */ 42 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) 43 { 44 int r; 45 46 /* Allocate ring buffer */ 47 if (adev->irq.ih.ring_obj == NULL) { 48 r = amdgpu_bo_create(adev, adev->irq.ih.ring_size, 49 PAGE_SIZE, true, 50 AMDGPU_GEM_DOMAIN_GTT, 0, 51 NULL, NULL, &adev->irq.ih.ring_obj); 52 if (r) { 53 DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r); 54 return r; 55 } 56 r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); 57 if (unlikely(r != 0)) 58 return r; 59 r = amdgpu_bo_pin(adev->irq.ih.ring_obj, 60 AMDGPU_GEM_DOMAIN_GTT, 61 &adev->irq.ih.gpu_addr); 62 if (r) { 63 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 64 DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r); 65 return r; 66 } 67 r = amdgpu_bo_kmap(adev->irq.ih.ring_obj, 68 (void **)__UNVOLATILE(&adev->irq.ih.ring)); 69 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 70 if (r) { 71 DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r); 72 return r; 73 } 74 } 75 return 0; 76 } 77 78 /** 79 * amdgpu_ih_ring_init - initialize the IH state 80 * 81 * @adev: amdgpu_device pointer 82 * 83 * Initializes the IH state and allocates a buffer 84 * for the IH ring buffer. 85 * Returns 0 for success, errors for failure. 86 */ 87 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, 88 bool use_bus_addr) 89 { 90 u32 rb_bufsz; 91 int r; 92 93 /* Align ring size */ 94 rb_bufsz = order_base_2(ring_size / 4); 95 ring_size = (1 << rb_bufsz) * 4; 96 adev->irq.ih.ring_size = ring_size; 97 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; 98 adev->irq.ih.rptr = 0; 99 adev->irq.ih.use_bus_addr = use_bus_addr; 100 101 if (adev->irq.ih.use_bus_addr) { 102 if (!adev->irq.ih.ring) { 103 /* add 8 bytes for the rptr/wptr shadows and 104 * add them to the end of the ring allocation. 105 */ 106 #ifdef __NetBSD__ 107 const bus_size_t size = adev->irq.ih.ring_size + 8; 108 int rseg __diagused; 109 void *kva; 110 r = -bus_dmamem_alloc(adev->ddev->dmat, size, 111 PAGE_SIZE, 0, &adev->irq.ih.ring_seg, 1, &rseg, 112 BUS_DMA_WAITOK); 113 if (r) { 114 fail0: KASSERT(r); 115 return r; 116 } 117 KASSERT(rseg == 0); 118 r = -bus_dmamap_create(adev->ddev->dmat, size, 1, 119 PAGE_SIZE, 0, BUS_DMA_WAITOK, 120 &adev->irq.ih.ring_map); 121 if (r) { 122 fail1: bus_dmamem_free(adev->ddev->dmat, 123 &adev->irq.ih.ring_seg, 1); 124 goto fail0; 125 } 126 r = -bus_dmamem_map(adev->ddev->dmat, 127 &adev->irq.ih.ring_seg, 1, size, &kva, 128 BUS_DMA_WAITOK); 129 if (r) { 130 fail2: bus_dmamap_destroy(adev->ddev->dmat, 131 adev->irq.ih.ring_map); 132 adev->irq.ih.ring_map = NULL; 133 goto fail1; 134 } 135 r = -bus_dmamap_load(adev->ddev->dmat, 136 adev->irq.ih.ring_map, kva, size, NULL, 137 BUS_DMA_WAITOK); 138 if (r) { 139 fail3: __unused bus_dmamem_unmap(adev->ddev->dmat, kva, size); 140 goto fail2; 141 } 142 adev->irq.ih.ring = kva; 143 adev->irq.ih.rb_dma_addr = 144 adev->irq.ih.ring_map->dm_segs[0].ds_addr; 145 #else 146 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev, 147 adev->irq.ih.ring_size + 8, 148 &adev->irq.ih.rb_dma_addr); 149 if (adev->irq.ih.ring == NULL) 150 return -ENOMEM; 151 #endif 152 memset(__UNVOLATILE(adev->irq.ih.ring), 0, adev->irq.ih.ring_size + 8); 153 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; 154 adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1; 155 } 156 return 0; 157 } else { 158 r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs); 159 if (r) { 160 dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r); 161 return r; 162 } 163 164 r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs); 165 if (r) { 166 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); 167 dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r); 168 return r; 169 } 170 171 return amdgpu_ih_ring_alloc(adev); 172 } 173 } 174 175 /** 176 * amdgpu_ih_ring_fini - tear down the IH state 177 * 178 * @adev: amdgpu_device pointer 179 * 180 * Tears down the IH state and frees buffer 181 * used for the IH ring buffer. 182 */ 183 void amdgpu_ih_ring_fini(struct amdgpu_device *adev) 184 { 185 int r; 186 187 if (adev->irq.ih.use_bus_addr) { 188 if (adev->irq.ih.ring) { 189 /* add 8 bytes for the rptr/wptr shadows and 190 * add them to the end of the ring allocation. 191 */ 192 #ifdef __NetBSD__ 193 const bus_size_t size = adev->irq.ih.ring_size + 8; 194 void *kva = __UNVOLATILE(adev->irq.ih.ring); 195 bus_dmamap_unload(adev->ddev->dmat, 196 adev->irq.ih.ring_map); 197 bus_dmamem_unmap(adev->ddev->dmat, kva, size); 198 bus_dmamap_destroy(adev->ddev->dmat, 199 adev->irq.ih.ring_map); 200 bus_dmamem_free(adev->ddev->dmat, 201 &adev->irq.ih.ring_seg, 1); 202 #else 203 pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8, 204 (void *)adev->irq.ih.ring, 205 adev->irq.ih.rb_dma_addr); 206 #endif 207 adev->irq.ih.ring = NULL; 208 } 209 } else { 210 if (adev->irq.ih.ring_obj) { 211 r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); 212 if (likely(r == 0)) { 213 amdgpu_bo_kunmap(adev->irq.ih.ring_obj); 214 amdgpu_bo_unpin(adev->irq.ih.ring_obj); 215 amdgpu_bo_unreserve(adev->irq.ih.ring_obj); 216 } 217 amdgpu_bo_unref(&adev->irq.ih.ring_obj); 218 adev->irq.ih.ring = NULL; 219 adev->irq.ih.ring_obj = NULL; 220 } 221 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); 222 amdgpu_wb_free(adev, adev->irq.ih.rptr_offs); 223 } 224 } 225 226 /** 227 * amdgpu_ih_process - interrupt handler 228 * 229 * @adev: amdgpu_device pointer 230 * 231 * Interrupt hander (VI), walk the IH ring. 232 * Returns irq process return code. 233 */ 234 int amdgpu_ih_process(struct amdgpu_device *adev) 235 { 236 struct amdgpu_iv_entry entry; 237 u32 wptr; 238 239 if (!adev->irq.ih.enabled || adev->shutdown) 240 return IRQ_NONE; 241 242 wptr = amdgpu_ih_get_wptr(adev); 243 244 restart_ih: 245 /* is somebody else already processing irqs? */ 246 if (atomic_xchg(&adev->irq.ih.lock, 1)) 247 return IRQ_NONE; 248 249 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); 250 251 /* Order reading of wptr vs. reading of IH ring data */ 252 rmb(); 253 254 while (adev->irq.ih.rptr != wptr) { 255 u32 ring_index = adev->irq.ih.rptr >> 2; 256 257 /* Before dispatching irq to IP blocks, send it to amdkfd */ 258 amdgpu_amdkfd_interrupt(adev, 259 (const void *)__UNVOLATILE(&adev->irq.ih.ring[ring_index])); 260 261 entry.iv_entry = (const uint32_t *) 262 __UNVOLATILE(&adev->irq.ih.ring[ring_index]); 263 amdgpu_ih_decode_iv(adev, &entry); 264 adev->irq.ih.rptr &= adev->irq.ih.ptr_mask; 265 266 amdgpu_irq_dispatch(adev, &entry); 267 } 268 amdgpu_ih_set_rptr(adev); 269 atomic_set(&adev->irq.ih.lock, 0); 270 271 /* make sure wptr hasn't changed while processing */ 272 wptr = amdgpu_ih_get_wptr(adev); 273 if (wptr != adev->irq.ih.rptr) 274 goto restart_ih; 275 276 return IRQ_HANDLED; 277 } 278