1 /* $NetBSD: amdgpu_ib.c,v 1.2 2018/08/27 04:58:19 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 * Christian König 30 */ 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ib.c,v 1.2 2018/08/27 04:58:19 riastradh Exp $"); 33 34 #include <linux/seq_file.h> 35 #include <linux/slab.h> 36 #include <drm/drmP.h> 37 #include <drm/amdgpu_drm.h> 38 #include "amdgpu.h" 39 #include "atom.h" 40 41 /* 42 * IB 43 * IBs (Indirect Buffers) and areas of GPU accessible memory where 44 * commands are stored. You can put a pointer to the IB in the 45 * command ring and the hw will fetch the commands from the IB 46 * and execute them. Generally userspace acceleration drivers 47 * produce command buffers which are send to the kernel and 48 * put in IBs for execution by the requested ring. 49 */ 50 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 51 52 /** 53 * amdgpu_ib_get - request an IB (Indirect Buffer) 54 * 55 * @ring: ring index the IB is associated with 56 * @size: requested IB size 57 * @ib: IB object returned 58 * 59 * Request an IB (all asics). IBs are allocated using the 60 * suballocator. 61 * Returns 0 on success, error on failure. 62 */ 63 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 64 unsigned size, struct amdgpu_ib *ib) 65 { 66 struct amdgpu_device *adev = ring->adev; 67 int r; 68 69 if (size) { 70 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 71 &ib->sa_bo, size, 256); 72 if (r) { 73 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); 74 return r; 75 } 76 77 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); 78 79 if (!vm) 80 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 81 } 82 83 amdgpu_sync_create(&ib->sync); 84 85 ib->ring = ring; 86 ib->vm = vm; 87 88 return 0; 89 } 90 91 /** 92 * amdgpu_ib_free - free an IB (Indirect Buffer) 93 * 94 * @adev: amdgpu_device pointer 95 * @ib: IB object to free 96 * 97 * Free an IB (all asics). 98 */ 99 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) 100 { 101 amdgpu_sync_free(adev, &ib->sync, &ib->fence->base); 102 amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); 103 if (ib->fence) 104 fence_put(&ib->fence->base); 105 } 106 107 /** 108 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring 109 * 110 * @adev: amdgpu_device pointer 111 * @num_ibs: number of IBs to schedule 112 * @ibs: IB objects to schedule 113 * @owner: owner for creating the fences 114 * 115 * Schedule an IB on the associated ring (all asics). 116 * Returns 0 on success, error on failure. 117 * 118 * On SI, there are two parallel engines fed from the primary ring, 119 * the CE (Constant Engine) and the DE (Drawing Engine). Since 120 * resource descriptors have moved to memory, the CE allows you to 121 * prime the caches while the DE is updating register state so that 122 * the resource descriptors will be already in cache when the draw is 123 * processed. To accomplish this, the userspace driver submits two 124 * IBs, one for the CE and one for the DE. If there is a CE IB (called 125 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 126 * to SI there was just a DE IB. 127 */ 128 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 129 struct amdgpu_ib *ibs, void *owner) 130 { 131 struct amdgpu_ib *ib = &ibs[0]; 132 struct amdgpu_ring *ring; 133 struct amdgpu_ctx *ctx, *old_ctx; 134 struct amdgpu_vm *vm; 135 unsigned i; 136 int r = 0; 137 138 if (num_ibs == 0) 139 return -EINVAL; 140 141 ring = ibs->ring; 142 ctx = ibs->ctx; 143 vm = ibs->vm; 144 145 if (!ring->ready) { 146 dev_err(adev->dev, "couldn't schedule ib\n"); 147 return -EINVAL; 148 } 149 r = amdgpu_sync_wait(&ibs->sync); 150 if (r) { 151 dev_err(adev->dev, "IB sync failed (%d).\n", r); 152 return r; 153 } 154 r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs); 155 if (r) { 156 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 157 return r; 158 } 159 160 if (vm) { 161 /* grab a vm id if necessary */ 162 r = amdgpu_vm_grab_id(ibs->vm, ibs->ring, &ibs->sync); 163 if (r) { 164 amdgpu_ring_unlock_undo(ring); 165 return r; 166 } 167 } 168 169 r = amdgpu_sync_rings(&ibs->sync, ring); 170 if (r) { 171 amdgpu_ring_unlock_undo(ring); 172 dev_err(adev->dev, "failed to sync rings (%d)\n", r); 173 return r; 174 } 175 176 if (vm) { 177 /* do context switch */ 178 amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); 179 180 if (ring->funcs->emit_gds_switch) 181 amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, 182 ib->gds_base, ib->gds_size, 183 ib->gws_base, ib->gws_size, 184 ib->oa_base, ib->oa_size); 185 186 if (ring->funcs->emit_hdp_flush) 187 amdgpu_ring_emit_hdp_flush(ring); 188 } 189 190 old_ctx = ring->current_ctx; 191 for (i = 0; i < num_ibs; ++i) { 192 ib = &ibs[i]; 193 194 if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) { 195 ring->current_ctx = old_ctx; 196 amdgpu_ring_unlock_undo(ring); 197 return -EINVAL; 198 } 199 amdgpu_ring_emit_ib(ring, ib); 200 ring->current_ctx = ctx; 201 } 202 203 r = amdgpu_fence_emit(ring, owner, &ib->fence); 204 if (r) { 205 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 206 ring->current_ctx = old_ctx; 207 amdgpu_ring_unlock_undo(ring); 208 return r; 209 } 210 211 if (!amdgpu_enable_scheduler && ib->ctx) 212 ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring, 213 &ib->fence->base); 214 215 /* wrap the last IB with fence */ 216 if (ib->user) { 217 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 218 addr += ib->user->offset; 219 amdgpu_ring_emit_fence(ring, addr, ib->sequence, 220 AMDGPU_FENCE_FLAG_64BIT); 221 } 222 223 if (ib->vm) 224 amdgpu_vm_fence(adev, ib->vm, &ib->fence->base); 225 226 amdgpu_ring_unlock_commit(ring); 227 return 0; 228 } 229 230 /** 231 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool 232 * 233 * @adev: amdgpu_device pointer 234 * 235 * Initialize the suballocator to manage a pool of memory 236 * for use as IBs (all asics). 237 * Returns 0 on success, error on failure. 238 */ 239 int amdgpu_ib_pool_init(struct amdgpu_device *adev) 240 { 241 int r; 242 243 if (adev->ib_pool_ready) { 244 return 0; 245 } 246 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, 247 AMDGPU_IB_POOL_SIZE*64*1024, 248 AMDGPU_GPU_PAGE_SIZE, 249 AMDGPU_GEM_DOMAIN_GTT); 250 if (r) { 251 return r; 252 } 253 254 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); 255 if (r) { 256 return r; 257 } 258 259 adev->ib_pool_ready = true; 260 if (amdgpu_debugfs_sa_init(adev)) { 261 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 262 } 263 return 0; 264 } 265 266 /** 267 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool 268 * 269 * @adev: amdgpu_device pointer 270 * 271 * Tear down the suballocator managing the pool of memory 272 * for use as IBs (all asics). 273 */ 274 void amdgpu_ib_pool_fini(struct amdgpu_device *adev) 275 { 276 if (adev->ib_pool_ready) { 277 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); 278 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); 279 adev->ib_pool_ready = false; 280 } 281 } 282 283 /** 284 * amdgpu_ib_ring_tests - test IBs on the rings 285 * 286 * @adev: amdgpu_device pointer 287 * 288 * Test an IB (Indirect Buffer) on each ring. 289 * If the test fails, disable the ring. 290 * Returns 0 on success, error if the primary GFX ring 291 * IB test fails. 292 */ 293 int amdgpu_ib_ring_tests(struct amdgpu_device *adev) 294 { 295 unsigned i; 296 int r, ret = 0; 297 298 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 299 struct amdgpu_ring *ring = adev->rings[i]; 300 301 if (!ring || !ring->ready) 302 continue; 303 304 r = amdgpu_ring_test_ib(ring); 305 if (r) { 306 ring->ready = false; 307 308 if (ring == &adev->gfx.gfx_ring[0]) { 309 /* oh, oh, that's really bad */ 310 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); 311 adev->accel_working = false; 312 return r; 313 314 } else { 315 /* still not good, but we can live with it */ 316 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); 317 ret = r; 318 } 319 } 320 } 321 return ret; 322 } 323 324 /* 325 * Debugfs info 326 */ 327 #if defined(CONFIG_DEBUG_FS) 328 329 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) 330 { 331 struct drm_info_node *node = (struct drm_info_node *) m->private; 332 struct drm_device *dev = node->minor->dev; 333 struct amdgpu_device *adev = dev->dev_private; 334 335 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); 336 337 return 0; 338 339 } 340 341 static struct drm_info_list amdgpu_debugfs_sa_list[] = { 342 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, 343 }; 344 345 #endif 346 347 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) 348 { 349 #if defined(CONFIG_DEBUG_FS) 350 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); 351 #else 352 return 0; 353 #endif 354 } 355