1*41ec0267Sriastradh /* $NetBSD: amdgpu_gds.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2efa246c0Sriastradh 3efa246c0Sriastradh /* 4efa246c0Sriastradh * Copyright 2014 Advanced Micro Devices, Inc. 5efa246c0Sriastradh * 6efa246c0Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7efa246c0Sriastradh * copy of this software and associated documentation files (the "Software"), 8efa246c0Sriastradh * to deal in the Software without restriction, including without limitation 9efa246c0Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10efa246c0Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 11efa246c0Sriastradh * Software is furnished to do so, subject to the following conditions: 12efa246c0Sriastradh * 13efa246c0Sriastradh * The above copyright notice and this permission notice shall be included in 14efa246c0Sriastradh * all copies or substantial portions of the Software. 15efa246c0Sriastradh * 16efa246c0Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17efa246c0Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18efa246c0Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19efa246c0Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20efa246c0Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21efa246c0Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22efa246c0Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 23efa246c0Sriastradh * 24efa246c0Sriastradh */ 25efa246c0Sriastradh 26efa246c0Sriastradh #ifndef __AMDGPU_GDS_H__ 27efa246c0Sriastradh #define __AMDGPU_GDS_H__ 28efa246c0Sriastradh 29efa246c0Sriastradh struct amdgpu_ring; 30efa246c0Sriastradh struct amdgpu_bo; 31efa246c0Sriastradh 32efa246c0Sriastradh struct amdgpu_gds { 33*41ec0267Sriastradh uint32_t gds_size; 34*41ec0267Sriastradh uint32_t gws_size; 35*41ec0267Sriastradh uint32_t oa_size; 36*41ec0267Sriastradh uint32_t gds_compute_max_wave_id; 37efa246c0Sriastradh }; 38efa246c0Sriastradh 39efa246c0Sriastradh struct amdgpu_gds_reg_offset { 40efa246c0Sriastradh uint32_t mem_base; 41efa246c0Sriastradh uint32_t mem_size; 42efa246c0Sriastradh uint32_t gws; 43efa246c0Sriastradh uint32_t oa; 44efa246c0Sriastradh }; 45efa246c0Sriastradh 46efa246c0Sriastradh #endif /* __AMDGPU_GDS_H__ */ 47