1 /* $NetBSD: amdgpu_dpm.h,v 1.2 2018/08/27 04:58:19 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __AMDGPU_DPM_H__ 26 #define __AMDGPU_DPM_H__ 27 28 #define R600_SSTU_DFLT 0 29 #define R600_SST_DFLT 0x00C8 30 31 /* XXX are these ok? */ 32 #define R600_TEMP_RANGE_MIN (90 * 1000) 33 #define R600_TEMP_RANGE_MAX (120 * 1000) 34 35 #define FDO_PWM_MODE_STATIC 1 36 #define FDO_PWM_MODE_STATIC_RPM 5 37 38 enum amdgpu_td { 39 AMDGPU_TD_AUTO, 40 AMDGPU_TD_UP, 41 AMDGPU_TD_DOWN, 42 }; 43 44 enum amdgpu_display_watermark { 45 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 46 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 47 }; 48 49 enum amdgpu_display_gap 50 { 51 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 52 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 53 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 54 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 55 }; 56 57 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 58 void amdgpu_dpm_print_cap_info(u32 caps); 59 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 60 struct amdgpu_ps *rps); 61 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 62 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); 63 bool amdgpu_is_uvd_state(u32 class, u32 class2); 64 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 65 u32 *p, u32 *u); 66 int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th); 67 68 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 69 70 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 71 72 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 73 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 74 75 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 76 77 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, 78 u32 sys_mask, 79 enum amdgpu_pcie_gen asic_gen, 80 enum amdgpu_pcie_gen default_gen); 81 82 u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, 83 u16 asic_lanes, 84 u16 default_lanes); 85 u8 amdgpu_encode_pci_lane_width(u32 lanes); 86 87 #endif 88