1 /* $NetBSD: amdgpu.h,v 1.8 2022/10/08 19:06:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #ifdef _KERNEL_OPT 34 #include "opt_amdgpu_cik.h" 35 #endif 36 37 #ifdef AMDGPU_CIK 38 #define CONFIG_DRM_AMDGPU_CIK 1 39 #endif 40 #include "amdgpu_ctx.h" 41 42 #include <linux/atomic.h> 43 #include <linux/wait.h> 44 #include <linux/list.h> 45 #include <linux/kref.h> 46 #include <linux/rbtree.h> 47 #include <linux/hashtable.h> 48 #include <linux/dma-fence.h> 49 50 #include <drm/ttm/ttm_bo_api.h> 51 #include <drm/ttm/ttm_bo_driver.h> 52 #include <drm/ttm/ttm_placement.h> 53 #include <drm/ttm/ttm_module.h> 54 #include <drm/ttm/ttm_execbuf_util.h> 55 56 #include <drm/amdgpu_drm.h> 57 #include <drm/drm_gem.h> 58 #include <drm/drm_ioctl.h> 59 #include <drm/gpu_scheduler.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_mn.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_nbio.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_gart.h" 91 #include "amdgpu_debugfs.h" 92 #include "amdgpu_job.h" 93 #include "amdgpu_bo_list.h" 94 #include "amdgpu_gem.h" 95 #include "amdgpu_doorbell.h" 96 #include "amdgpu_amdkfd.h" 97 #include "amdgpu_smu.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_mes.h" 100 #include "amdgpu_umc.h" 101 #include "amdgpu_mmhub.h" 102 #include "amdgpu_df.h" 103 104 #define MAX_GPU_INSTANCE 16 105 106 struct amdgpu_gpu_instance 107 { 108 struct amdgpu_device *adev; 109 int mgpu_fan_enabled; 110 }; 111 112 struct amdgpu_mgpu_info 113 { 114 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 115 struct mutex mutex; 116 uint32_t num_gpu; 117 uint32_t num_dgpu; 118 uint32_t num_apu; 119 }; 120 121 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 122 123 /* 124 * Modules parameters. 125 */ 126 extern int amdgpu_modeset; 127 extern int amdgpu_vram_limit; 128 extern int amdgpu_vis_vram_limit; 129 extern int amdgpu_gart_size; 130 extern int amdgpu_gtt_size; 131 extern int amdgpu_moverate; 132 extern int amdgpu_benchmarking; 133 extern int amdgpu_testing; 134 extern int amdgpu_audio; 135 extern int amdgpu_disp_priority; 136 extern int amdgpu_hw_i2c; 137 extern int amdgpu_pcie_gen2; 138 extern int amdgpu_msi; 139 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 140 extern int amdgpu_dpm; 141 extern int amdgpu_fw_load_type; 142 extern int amdgpu_aspm; 143 extern int amdgpu_runtime_pm; 144 extern uint amdgpu_ip_block_mask; 145 extern int amdgpu_bapm; 146 extern int amdgpu_deep_color; 147 extern int amdgpu_vm_size; 148 extern int amdgpu_vm_block_size; 149 extern int amdgpu_vm_fragment_size; 150 extern int amdgpu_vm_fault_stop; 151 extern int amdgpu_vm_debug; 152 extern int amdgpu_vm_update_mode; 153 extern int amdgpu_exp_hw_support; 154 extern int amdgpu_dc; 155 extern int amdgpu_sched_jobs; 156 extern int amdgpu_sched_hw_submission; 157 extern uint amdgpu_pcie_gen_cap; 158 extern uint amdgpu_pcie_lane_cap; 159 extern uint amdgpu_cg_mask; 160 extern uint amdgpu_pg_mask; 161 extern uint amdgpu_sdma_phase_quantum; 162 extern char *amdgpu_disable_cu; 163 extern char *amdgpu_virtual_display; 164 extern uint amdgpu_pp_feature_mask; 165 extern uint amdgpu_force_long_training; 166 extern int amdgpu_job_hang_limit; 167 extern int amdgpu_lbpw; 168 extern int amdgpu_compute_multipipe; 169 extern int amdgpu_gpu_recovery; 170 extern int amdgpu_emu_mode; 171 extern uint amdgpu_smu_memory_pool_size; 172 extern uint amdgpu_dc_feature_mask; 173 extern uint amdgpu_dm_abm_level; 174 extern struct amdgpu_mgpu_info mgpu_info; 175 extern int amdgpu_ras_enable; 176 extern uint amdgpu_ras_mask; 177 extern int amdgpu_async_gfx_ring; 178 extern int amdgpu_mcbp; 179 extern int amdgpu_discovery; 180 extern int amdgpu_mes; 181 extern int amdgpu_noretry; 182 extern int amdgpu_force_asic_type; 183 #ifdef CONFIG_HSA_AMD 184 extern int sched_policy; 185 #else 186 static const int sched_policy = KFD_SCHED_POLICY_HWS; 187 #endif 188 189 #ifdef CONFIG_DRM_AMDGPU_SI 190 extern int amdgpu_si_support; 191 #endif 192 #ifdef CONFIG_DRM_AMDGPU_CIK 193 extern int amdgpu_cik_support; 194 #endif 195 196 #define AMDGPU_VM_MAX_NUM_CTX 4096 197 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 198 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 199 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 200 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 201 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 202 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 203 #define AMDGPU_IB_POOL_SIZE 16 204 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 205 #define AMDGPUFB_CONN_LIMIT 4 206 #define AMDGPU_BIOS_NUM_SCRATCH 16 207 208 /* hard reset data */ 209 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 210 211 /* reset flags */ 212 #define AMDGPU_RESET_GFX (1 << 0) 213 #define AMDGPU_RESET_COMPUTE (1 << 1) 214 #define AMDGPU_RESET_DMA (1 << 2) 215 #define AMDGPU_RESET_CP (1 << 3) 216 #define AMDGPU_RESET_GRBM (1 << 4) 217 #define AMDGPU_RESET_DMA1 (1 << 5) 218 #define AMDGPU_RESET_RLC (1 << 6) 219 #define AMDGPU_RESET_SEM (1 << 7) 220 #define AMDGPU_RESET_IH (1 << 8) 221 #define AMDGPU_RESET_VMC (1 << 9) 222 #define AMDGPU_RESET_MC (1 << 10) 223 #define AMDGPU_RESET_DISPLAY (1 << 11) 224 #define AMDGPU_RESET_UVD (1 << 12) 225 #define AMDGPU_RESET_VCE (1 << 13) 226 #define AMDGPU_RESET_VCE1 (1 << 14) 227 228 /* max cursor sizes (in pixels) */ 229 #define CIK_CURSOR_WIDTH 128 230 #define CIK_CURSOR_HEIGHT 128 231 232 struct amdgpu_device; 233 struct amdgpu_ib; 234 struct amdgpu_cs_parser; 235 struct amdgpu_job; 236 struct amdgpu_irq_src; 237 struct amdgpu_fpriv; 238 struct amdgpu_bo_va_mapping; 239 struct amdgpu_atif; 240 struct kfd_vm_fault_info; 241 242 enum amdgpu_cp_irq { 243 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 244 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 245 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 246 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 247 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 248 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 249 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 250 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 253 254 AMDGPU_CP_IRQ_LAST 255 }; 256 257 enum amdgpu_thermal_irq { 258 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 259 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 260 261 AMDGPU_THERMAL_IRQ_LAST 262 }; 263 264 enum amdgpu_kiq_irq { 265 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 266 AMDGPU_CP_KIQ_IRQ_LAST 267 }; 268 269 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 270 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 271 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 272 273 int amdgpu_device_ip_set_clockgating_state(void *dev, 274 enum amd_ip_block_type block_type, 275 enum amd_clockgating_state state); 276 int amdgpu_device_ip_set_powergating_state(void *dev, 277 enum amd_ip_block_type block_type, 278 enum amd_powergating_state state); 279 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 280 u32 *flags); 281 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 282 enum amd_ip_block_type block_type); 283 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 284 enum amd_ip_block_type block_type); 285 286 #define AMDGPU_MAX_IP_NUM 16 287 288 struct amdgpu_ip_block_status { 289 bool valid; 290 bool sw; 291 bool hw; 292 bool late_initialized; 293 bool hang; 294 }; 295 296 struct amdgpu_ip_block_version { 297 const enum amd_ip_block_type type; 298 const u32 major; 299 const u32 minor; 300 const u32 rev; 301 const struct amd_ip_funcs *funcs; 302 }; 303 304 #define HW_REV(_Major, _Minor, _Rev) \ 305 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 306 307 struct amdgpu_ip_block { 308 struct amdgpu_ip_block_status status; 309 const struct amdgpu_ip_block_version *version; 310 }; 311 312 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 313 enum amd_ip_block_type type, 314 u32 major, u32 minor); 315 316 struct amdgpu_ip_block * 317 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 318 enum amd_ip_block_type type); 319 320 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 321 const struct amdgpu_ip_block_version *ip_block_version); 322 323 /* 324 * BIOS. 325 */ 326 bool amdgpu_get_bios(struct amdgpu_device *adev); 327 bool amdgpu_read_bios(struct amdgpu_device *adev); 328 329 /* 330 * Clocks 331 */ 332 333 #define AMDGPU_MAX_PPLL 3 334 335 struct amdgpu_clock { 336 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 337 struct amdgpu_pll spll; 338 struct amdgpu_pll mpll; 339 /* 10 Khz units */ 340 uint32_t default_mclk; 341 uint32_t default_sclk; 342 uint32_t default_dispclk; 343 uint32_t current_dispclk; 344 uint32_t dp_extclk; 345 uint32_t max_pixel_clock; 346 }; 347 348 /* sub-allocation manager, it has to be protected by another lock. 349 * By conception this is an helper for other part of the driver 350 * like the indirect buffer or semaphore, which both have their 351 * locking. 352 * 353 * Principe is simple, we keep a list of sub allocation in offset 354 * order (first entry has offset == 0, last entry has the highest 355 * offset). 356 * 357 * When allocating new object we first check if there is room at 358 * the end total_size - (last_object_offset + last_object_size) >= 359 * alloc_size. If so we allocate new object there. 360 * 361 * When there is not enough room at the end, we start waiting for 362 * each sub object until we reach object_offset+object_size >= 363 * alloc_size, this object then become the sub object we return. 364 * 365 * Alignment can't be bigger than page size. 366 * 367 * Hole are not considered for allocation to keep things simple. 368 * Assumption is that there won't be hole (all object on same 369 * alignment). 370 */ 371 372 #define AMDGPU_SA_NUM_FENCE_LISTS 32 373 374 struct amdgpu_sa_manager { 375 spinlock_t wq_lock; 376 drm_waitqueue_t wq; 377 struct amdgpu_bo *bo; 378 struct list_head *hole; 379 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 380 struct list_head olist; 381 unsigned size; 382 uint64_t gpu_addr; 383 void *cpu_ptr; 384 uint32_t domain; 385 uint32_t align; 386 }; 387 388 /* sub-allocation buffer */ 389 struct amdgpu_sa_bo { 390 struct list_head olist; 391 struct list_head flist; 392 struct amdgpu_sa_manager *manager; 393 unsigned soffset; 394 unsigned eoffset; 395 struct dma_fence *fence; 396 }; 397 398 int amdgpu_fence_slab_init(void); 399 void amdgpu_fence_slab_fini(void); 400 401 /* 402 * IRQS. 403 */ 404 405 struct amdgpu_flip_work { 406 struct delayed_work flip_work; 407 struct work_struct unpin_work; 408 struct amdgpu_device *adev; 409 int crtc_id; 410 u32 target_vblank; 411 uint64_t base; 412 struct drm_pending_vblank_event *event; 413 struct amdgpu_bo *old_abo; 414 struct dma_fence *excl; 415 unsigned shared_count; 416 struct dma_fence **shared; 417 struct dma_fence_cb cb; 418 bool async; 419 }; 420 421 422 /* 423 * CP & rings. 424 */ 425 426 struct amdgpu_ib { 427 struct amdgpu_sa_bo *sa_bo; 428 uint32_t length_dw; 429 uint64_t gpu_addr; 430 uint32_t *ptr; 431 uint32_t flags; 432 }; 433 434 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 435 436 /* 437 * file private structure 438 */ 439 440 struct amdgpu_fpriv { 441 struct amdgpu_vm vm; 442 struct amdgpu_bo_va *prt_va; 443 struct amdgpu_bo_va *csa_va; 444 struct mutex bo_list_lock; 445 struct idr bo_list_handles; 446 struct amdgpu_ctx_mgr ctx_mgr; 447 }; 448 449 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 450 451 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 452 unsigned size, struct amdgpu_ib *ib); 453 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 454 struct dma_fence *f); 455 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 456 struct amdgpu_ib *ibs, struct amdgpu_job *job, 457 struct dma_fence **f); 458 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 459 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 460 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 461 462 /* 463 * CS. 464 */ 465 struct amdgpu_cs_chunk { 466 uint32_t chunk_id; 467 uint32_t length_dw; 468 void *kdata; 469 }; 470 471 struct amdgpu_cs_post_dep { 472 struct drm_syncobj *syncobj; 473 struct dma_fence_chain *chain; 474 u64 point; 475 }; 476 477 struct amdgpu_cs_parser { 478 struct amdgpu_device *adev; 479 struct drm_file *filp; 480 struct amdgpu_ctx *ctx; 481 482 /* chunks */ 483 unsigned nchunks; 484 struct amdgpu_cs_chunk *chunks; 485 486 /* scheduler job object */ 487 struct amdgpu_job *job; 488 struct drm_sched_entity *entity; 489 490 /* buffer objects */ 491 struct ww_acquire_ctx ticket; 492 struct amdgpu_bo_list *bo_list; 493 struct amdgpu_mn *mn; 494 struct amdgpu_bo_list_entry vm_pd; 495 struct list_head validated; 496 struct dma_fence *fence; 497 uint64_t bytes_moved_threshold; 498 uint64_t bytes_moved_vis_threshold; 499 uint64_t bytes_moved; 500 uint64_t bytes_moved_vis; 501 502 /* user fence */ 503 struct amdgpu_bo_list_entry uf_entry; 504 505 unsigned num_post_deps; 506 struct amdgpu_cs_post_dep *post_deps; 507 }; 508 509 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 510 uint32_t ib_idx, int idx) 511 { 512 return p->job->ibs[ib_idx].ptr[idx]; 513 } 514 515 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 516 uint32_t ib_idx, int idx, 517 uint32_t value) 518 { 519 p->job->ibs[ib_idx].ptr[idx] = value; 520 } 521 522 /* 523 * Writeback 524 */ 525 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 526 527 struct amdgpu_wb { 528 struct amdgpu_bo *wb_obj; 529 volatile uint32_t *wb; 530 uint64_t gpu_addr; 531 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 532 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, NBBY*sizeof(unsigned long))]; 533 }; 534 535 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 536 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 537 538 /* 539 * Benchmarking 540 */ 541 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 542 543 544 /* 545 * Testing 546 */ 547 void amdgpu_test_moves(struct amdgpu_device *adev); 548 549 /* 550 * ASIC specific register table accessible by UMD 551 */ 552 struct amdgpu_allowed_register_entry { 553 uint32_t reg_offset; 554 bool grbm_indexed; 555 }; 556 557 enum amd_reset_method { 558 AMD_RESET_METHOD_LEGACY = 0, 559 AMD_RESET_METHOD_MODE0, 560 AMD_RESET_METHOD_MODE1, 561 AMD_RESET_METHOD_MODE2, 562 AMD_RESET_METHOD_BACO 563 }; 564 565 /* 566 * ASIC specific functions. 567 */ 568 struct amdgpu_asic_funcs { 569 bool (*read_disabled_bios)(struct amdgpu_device *adev); 570 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 571 u8 *bios, u32 length_bytes); 572 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 573 u32 sh_num, u32 reg_offset, u32 *value); 574 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 575 int (*reset)(struct amdgpu_device *adev); 576 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 577 /* get the reference clock */ 578 u32 (*get_xclk)(struct amdgpu_device *adev); 579 /* MM block clocks */ 580 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 581 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 582 /* static power management */ 583 int (*get_pcie_lanes)(struct amdgpu_device *adev); 584 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 585 /* get config memsize register */ 586 u32 (*get_config_memsize)(struct amdgpu_device *adev); 587 /* flush hdp write queue */ 588 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 589 /* invalidate hdp read cache */ 590 void (*invalidate_hdp)(struct amdgpu_device *adev, 591 struct amdgpu_ring *ring); 592 /* check if the asic needs a full reset of if soft reset will work */ 593 bool (*need_full_reset)(struct amdgpu_device *adev); 594 /* initialize doorbell layout for specific asic*/ 595 void (*init_doorbell_index)(struct amdgpu_device *adev); 596 /* PCIe bandwidth usage */ 597 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 598 uint64_t *count1); 599 /* do we need to reset the asic at init time (e.g., kexec) */ 600 bool (*need_reset_on_init)(struct amdgpu_device *adev); 601 /* PCIe replay counter */ 602 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 603 /* device supports BACO */ 604 bool (*supports_baco)(struct amdgpu_device *adev); 605 }; 606 607 /* 608 * IOCTL. 609 */ 610 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 611 struct drm_file *filp); 612 613 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 614 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 615 struct drm_file *filp); 616 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 617 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 618 struct drm_file *filp); 619 620 /* VRAM scratch page for HDP bug, default vram page */ 621 struct amdgpu_vram_scratch { 622 struct amdgpu_bo *robj; 623 volatile uint32_t *ptr; 624 u64 gpu_addr; 625 }; 626 627 /* 628 * ACPI 629 */ 630 struct amdgpu_atcs_functions { 631 bool get_ext_state; 632 bool pcie_perf_req; 633 bool pcie_dev_rdy; 634 bool pcie_bus_width; 635 }; 636 637 struct amdgpu_atcs { 638 struct amdgpu_atcs_functions functions; 639 }; 640 641 /* 642 * Firmware VRAM reservation 643 */ 644 struct amdgpu_fw_vram_usage { 645 u64 start_offset; 646 u64 size; 647 struct amdgpu_bo *reserved_bo; 648 void *va; 649 650 /* GDDR6 training support flag. 651 */ 652 bool mem_train_support; 653 }; 654 655 /* 656 * CGS 657 */ 658 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 659 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 660 661 /* 662 * Core structure, functions and helpers. 663 */ 664 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 665 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 666 667 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 668 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 669 670 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 671 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 672 673 struct amdgpu_mmio_remap { 674 u32 reg_offset; 675 resource_size_t bus_addr; 676 }; 677 678 /* Define the HW IP blocks will be used in driver , add more if necessary */ 679 enum amd_hw_ip_block_type { 680 GC_HWIP = 1, 681 HDP_HWIP, 682 SDMA0_HWIP, 683 SDMA1_HWIP, 684 SDMA2_HWIP, 685 SDMA3_HWIP, 686 SDMA4_HWIP, 687 SDMA5_HWIP, 688 SDMA6_HWIP, 689 SDMA7_HWIP, 690 MMHUB_HWIP, 691 ATHUB_HWIP, 692 NBIO_HWIP, 693 MP0_HWIP, 694 MP1_HWIP, 695 UVD_HWIP, 696 VCN_HWIP = UVD_HWIP, 697 JPEG_HWIP = VCN_HWIP, 698 VCE_HWIP, 699 DF_HWIP, 700 DCE_HWIP, 701 OSSSYS_HWIP, 702 SMUIO_HWIP, 703 PWR_HWIP, 704 NBIF_HWIP, 705 THM_HWIP, 706 CLK_HWIP, 707 UMC_HWIP, 708 RSMU_HWIP, 709 MAX_HWIP 710 }; 711 712 #define HWIP_MAX_INSTANCE 8 713 714 struct amd_powerplay { 715 void *pp_handle; 716 const struct amd_pm_funcs *pp_funcs; 717 }; 718 719 #define AMDGPU_RESET_MAGIC_NUM 64 720 #define AMDGPU_MAX_DF_PERFMONS 4 721 struct amdgpu_device { 722 struct device *dev; 723 struct drm_device *ddev; 724 struct pci_dev *pdev; 725 726 #ifdef CONFIG_DRM_AMD_ACP 727 struct amdgpu_acp acp; 728 #endif 729 730 /* ASIC */ 731 enum amd_asic_type asic_type; 732 uint32_t family; 733 uint32_t rev_id; 734 uint32_t external_rev_id; 735 unsigned long flags; 736 int usec_timeout; 737 const struct amdgpu_asic_funcs *asic_funcs; 738 bool shutdown; 739 bool need_swiotlb; 740 bool accel_working; 741 struct notifier_block acpi_nb; 742 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 743 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 744 unsigned debugfs_count; 745 #if defined(CONFIG_DEBUG_FS) 746 struct dentry *debugfs_preempt; 747 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 748 #endif 749 struct amdgpu_atif *atif; 750 struct amdgpu_atcs atcs; 751 struct mutex srbm_mutex; 752 /* GRBM index mutex. Protects concurrent access to GRBM index */ 753 struct mutex grbm_idx_mutex; 754 struct dev_pm_domain vga_pm_domain; 755 bool have_disp_power_ref; 756 bool have_atomics_support; 757 758 /* BIOS */ 759 bool is_atom_fw; 760 uint8_t *bios; 761 uint32_t bios_size; 762 struct amdgpu_bo *stolen_vga_memory; 763 struct amdgpu_bo *discovery_memory; 764 uint32_t bios_scratch_reg_offset; 765 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 766 767 /* Register/doorbell mmio */ 768 #ifdef __NetBSD__ 769 bus_space_tag_t rmmiot; 770 bus_space_handle_t rmmioh; 771 bus_addr_t rmmio_base; 772 bus_size_t rmmio_size; 773 #else 774 resource_size_t rmmio_base; 775 resource_size_t rmmio_size; 776 void __iomem *rmmio; 777 #endif 778 /* protects concurrent MM_INDEX/DATA based register access */ 779 spinlock_t mmio_idx_lock; 780 struct amdgpu_mmio_remap rmmio_remap; 781 /* protects concurrent SMC based register access */ 782 spinlock_t smc_idx_lock; 783 amdgpu_rreg_t smc_rreg; 784 amdgpu_wreg_t smc_wreg; 785 /* protects concurrent PCIE register access */ 786 spinlock_t pcie_idx_lock; 787 amdgpu_rreg_t pcie_rreg; 788 amdgpu_wreg_t pcie_wreg; 789 amdgpu_rreg_t pciep_rreg; 790 amdgpu_wreg_t pciep_wreg; 791 amdgpu_rreg64_t pcie_rreg64; 792 amdgpu_wreg64_t pcie_wreg64; 793 /* protects concurrent UVD register access */ 794 spinlock_t uvd_ctx_idx_lock; 795 amdgpu_rreg_t uvd_ctx_rreg; 796 amdgpu_wreg_t uvd_ctx_wreg; 797 /* protects concurrent DIDT register access */ 798 spinlock_t didt_idx_lock; 799 amdgpu_rreg_t didt_rreg; 800 amdgpu_wreg_t didt_wreg; 801 /* protects concurrent gc_cac register access */ 802 spinlock_t gc_cac_idx_lock; 803 amdgpu_rreg_t gc_cac_rreg; 804 amdgpu_wreg_t gc_cac_wreg; 805 /* protects concurrent se_cac register access */ 806 spinlock_t se_cac_idx_lock; 807 amdgpu_rreg_t se_cac_rreg; 808 amdgpu_wreg_t se_cac_wreg; 809 /* protects concurrent ENDPOINT (audio) register access */ 810 spinlock_t audio_endpt_idx_lock; 811 amdgpu_block_rreg_t audio_endpt_rreg; 812 amdgpu_block_wreg_t audio_endpt_wreg; 813 #ifdef __NetBSD__ 814 bus_space_tag_t rio_memt; 815 bus_space_handle_t rio_memh; 816 bus_size_t rio_mem_size; 817 #else 818 void __iomem *rio_mem; 819 resource_size_t rio_mem_size; 820 #endif 821 struct amdgpu_doorbell doorbell; 822 823 /* clock/pll info */ 824 struct amdgpu_clock clock; 825 826 /* MC */ 827 struct amdgpu_gmc gmc; 828 struct amdgpu_gart gart; 829 #ifdef __NetBSD__ 830 bus_dma_segment_t dummy_page_seg; 831 bus_dmamap_t dummy_page_map; 832 #endif 833 dma_addr_t dummy_page_addr; 834 struct amdgpu_vm_manager vm_manager; 835 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 836 unsigned num_vmhubs; 837 838 /* memory management */ 839 struct amdgpu_mman mman; 840 struct amdgpu_vram_scratch vram_scratch; 841 struct amdgpu_wb wb; 842 atomic64_t num_bytes_moved; 843 atomic64_t num_evictions; 844 atomic64_t num_vram_cpu_page_faults; 845 atomic_t gpu_reset_counter; 846 atomic_t vram_lost_counter; 847 848 /* data for buffer migration throttling */ 849 struct { 850 spinlock_t lock; 851 s64 last_update_us; 852 s64 accum_us; /* accumulated microseconds */ 853 s64 accum_us_vis; /* for visible VRAM */ 854 u32 log2_max_MBps; 855 } mm_stats; 856 857 /* display */ 858 bool enable_virtual_display; 859 struct amdgpu_mode_info mode_info; 860 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 861 struct work_struct hotplug_work; 862 struct amdgpu_irq_src crtc_irq; 863 struct amdgpu_irq_src vupdate_irq; 864 struct amdgpu_irq_src pageflip_irq; 865 struct amdgpu_irq_src hpd_irq; 866 867 /* rings */ 868 u64 fence_context; 869 unsigned num_rings; 870 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 871 bool ib_pool_ready; 872 struct amdgpu_sa_manager ring_tmp_bo; 873 874 /* interrupts */ 875 struct amdgpu_irq irq; 876 877 /* powerplay */ 878 struct amd_powerplay powerplay; 879 bool pp_force_state_enabled; 880 881 /* smu */ 882 struct smu_context smu; 883 884 /* dpm */ 885 struct amdgpu_pm pm; 886 u32 cg_flags; 887 u32 pg_flags; 888 889 /* nbio */ 890 struct amdgpu_nbio nbio; 891 892 /* mmhub */ 893 struct amdgpu_mmhub mmhub; 894 895 /* gfx */ 896 struct amdgpu_gfx gfx; 897 898 /* sdma */ 899 struct amdgpu_sdma sdma; 900 901 /* uvd */ 902 struct amdgpu_uvd uvd; 903 904 /* vce */ 905 struct amdgpu_vce vce; 906 907 /* vcn */ 908 struct amdgpu_vcn vcn; 909 910 /* jpeg */ 911 struct amdgpu_jpeg jpeg; 912 913 /* firmwares */ 914 struct amdgpu_firmware firmware; 915 916 /* PSP */ 917 struct psp_context psp; 918 919 /* GDS */ 920 struct amdgpu_gds gds; 921 922 /* KFD */ 923 struct amdgpu_kfd_dev kfd; 924 925 /* UMC */ 926 struct amdgpu_umc umc; 927 928 /* display related functionality */ 929 struct amdgpu_display_manager dm; 930 931 /* discovery */ 932 uint8_t *discovery; 933 934 /* mes */ 935 bool enable_mes; 936 struct amdgpu_mes mes; 937 938 /* df */ 939 struct amdgpu_df df; 940 941 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 942 int num_ip_blocks; 943 struct mutex mn_lock; 944 DECLARE_HASHTABLE(mn_hash, 7); 945 946 /* tracking pinned memory */ 947 atomic64_t vram_pin_size; 948 atomic64_t visible_pin_size; 949 atomic64_t gart_pin_size; 950 951 /* soc15 register offset based on ip, instance and segment */ 952 const uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 953 954 /* delayed work_func for deferring clockgating during resume */ 955 struct delayed_work delayed_init_work; 956 957 struct amdgpu_virt virt; 958 /* firmware VRAM reservation */ 959 struct amdgpu_fw_vram_usage fw_vram_usage; 960 961 /* link all shadow bo */ 962 struct list_head shadow_list; 963 struct mutex shadow_list_lock; 964 /* keep an lru list of rings by HW IP */ 965 struct list_head ring_lru_list; 966 spinlock_t ring_lru_list_lock; 967 968 /* record hw reset is performed */ 969 bool has_hw_reset; 970 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 971 972 /* s3/s4 mask */ 973 bool in_suspend; 974 975 /* record last mm index being written through WREG32*/ 976 unsigned long last_mm_index; 977 bool in_gpu_reset; 978 enum pp_mp1_state mp1_state; 979 struct mutex lock_reset; 980 struct amdgpu_doorbell_index doorbell_index; 981 982 struct mutex notifier_lock; 983 984 int asic_reset_res; 985 struct work_struct xgmi_reset_work; 986 987 long gfx_timeout; 988 long sdma_timeout; 989 long video_timeout; 990 long compute_timeout; 991 992 uint64_t unique_id; 993 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 994 995 /* device pstate */ 996 int pstate; 997 /* enable runtime pm on the device */ 998 bool runpm; 999 1000 bool pm_sysfs_en; 1001 bool ucode_sysfs_en; 1002 }; 1003 1004 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1005 { 1006 return container_of(bdev, struct amdgpu_device, mman.bdev); 1007 } 1008 1009 int amdgpu_device_init(struct amdgpu_device *adev, 1010 struct drm_device *ddev, 1011 struct pci_dev *pdev, 1012 uint32_t flags); 1013 void amdgpu_device_fini(struct amdgpu_device *adev); 1014 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1015 1016 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1017 uint32_t *buf, size_t size, bool write); 1018 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1019 uint32_t acc_flags); 1020 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1021 uint32_t acc_flags); 1022 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1023 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1024 1025 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1026 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1027 1028 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1029 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1030 1031 int emu_soc_asic_init(struct amdgpu_device *adev); 1032 1033 /* 1034 * Registers read & write functions. 1035 */ 1036 1037 #define AMDGPU_REGS_IDX (1<<0) 1038 #define AMDGPU_REGS_NO_KIQ (1<<1) 1039 #define AMDGPU_REGS_KIQ (1<<2) 1040 1041 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1042 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1043 1044 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1045 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1046 1047 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1048 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1049 1050 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1051 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1052 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1053 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1054 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1055 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1056 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1057 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1058 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1059 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1060 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1061 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1062 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1063 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1064 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1065 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1066 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1067 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1068 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1069 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1070 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1071 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1072 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1073 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1074 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1075 #define WREG32_P(reg, val, mask) \ 1076 do { \ 1077 uint32_t tmp_ = RREG32(reg); \ 1078 tmp_ &= (mask); \ 1079 tmp_ |= ((val) & ~(mask)); \ 1080 WREG32(reg, tmp_); \ 1081 } while (0) 1082 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1083 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1084 #define WREG32_PLL_P(reg, val, mask) \ 1085 do { \ 1086 uint32_t tmp_ = RREG32_PLL(reg); \ 1087 tmp_ &= (mask); \ 1088 tmp_ |= ((val) & ~(mask)); \ 1089 WREG32_PLL(reg, tmp_); \ 1090 } while (0) 1091 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1092 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1093 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1094 1095 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1096 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1097 1098 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1099 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1100 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1101 1102 #define REG_GET_FIELD(value, reg, field) \ 1103 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1104 1105 #define WREG32_FIELD(reg, field, val) \ 1106 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1107 1108 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1109 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1110 1111 /* 1112 * BIOS helpers. 1113 */ 1114 #define RBIOS8(i) (adev->bios[i]) 1115 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1116 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1117 1118 /* 1119 * ASICs macro. 1120 */ 1121 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1122 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1123 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1124 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1125 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1126 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1127 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1128 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1129 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1130 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1131 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1132 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1133 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1134 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1135 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1136 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1137 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1138 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1139 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1140 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1141 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1142 1143 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1144 1145 /* Common functions */ 1146 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1147 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1148 struct amdgpu_job* job); 1149 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1150 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1151 1152 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1153 u64 num_vis_bytes); 1154 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1155 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1156 const u32 *registers, 1157 const u32 array_size); 1158 int amdgpu_ttm_init(struct amdgpu_device *adev); 1159 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1160 1161 bool amdgpu_device_supports_boco(struct drm_device *dev); 1162 bool amdgpu_device_supports_baco(struct drm_device *dev); 1163 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1164 struct amdgpu_device *peer_adev); 1165 int amdgpu_device_baco_enter(struct drm_device *dev); 1166 int amdgpu_device_baco_exit(struct drm_device *dev); 1167 1168 /* atpx handler */ 1169 #if defined(CONFIG_VGA_SWITCHEROO) 1170 void amdgpu_register_atpx_handler(void); 1171 void amdgpu_unregister_atpx_handler(void); 1172 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1173 bool amdgpu_is_atpx_hybrid(void); 1174 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1175 bool amdgpu_has_atpx(void); 1176 #else 1177 static inline void amdgpu_register_atpx_handler(void) {} 1178 static inline void amdgpu_unregister_atpx_handler(void) {} 1179 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1180 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1181 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1182 static inline bool amdgpu_has_atpx(void) { return false; } 1183 #endif 1184 1185 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1186 void *amdgpu_atpx_get_dhandle(void); 1187 #else 1188 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1189 #endif 1190 1191 /* 1192 * KMS 1193 */ 1194 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1195 extern const int amdgpu_max_kms_ioctl; 1196 1197 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1198 void amdgpu_driver_unload_kms(struct drm_device *dev); 1199 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1200 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1201 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1202 struct drm_file *file_priv); 1203 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1204 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1205 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1206 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1207 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1208 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1209 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1210 unsigned long arg); 1211 1212 /* 1213 * functions used by amdgpu_encoder.c 1214 */ 1215 struct amdgpu_afmt_acr { 1216 u32 clock; 1217 1218 int n_32khz; 1219 int cts_32khz; 1220 1221 int n_44_1khz; 1222 int cts_44_1khz; 1223 1224 int n_48khz; 1225 int cts_48khz; 1226 1227 }; 1228 1229 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1230 1231 /* amdgpu_acpi.c */ 1232 #if defined(CONFIG_ACPI) 1233 int amdgpu_acpi_init(struct amdgpu_device *adev); 1234 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1235 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1236 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1237 u8 perf_req, bool advertise); 1238 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1239 1240 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1241 struct amdgpu_dm_backlight_caps *caps); 1242 #else 1243 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1244 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1245 #endif 1246 1247 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1248 uint64_t addr, struct amdgpu_bo **bo, 1249 struct amdgpu_bo_va_mapping **mapping); 1250 1251 #if defined(CONFIG_DRM_AMD_DC) 1252 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1253 #else 1254 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1255 #endif 1256 1257 1258 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1259 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1260 1261 #include "amdgpu_object.h" 1262 1263 #ifdef __NetBSD__ /* XXX amdgpu sysfs */ 1264 #define AMDGPU_PMU_ATTR(_name, _object) CTASSERT(1) 1265 #else 1266 /* used by df_v3_6.c and amdgpu_pmu.c */ 1267 #define AMDGPU_PMU_ATTR(_name, _object) \ 1268 static ssize_t \ 1269 _name##_show(struct device *dev, \ 1270 struct device_attribute *attr, \ 1271 char *page) \ 1272 { \ 1273 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1274 return sprintf(page, _object "\n"); \ 1275 } \ 1276 \ 1277 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1278 #endif 1279 1280 #endif 1281 1282