1 /* $NetBSD: amdgpu.h,v 1.9 2024/04/16 14:34:01 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #ifdef _KERNEL_OPT 34 #include "opt_amdgpu_cik.h" 35 #endif 36 37 #ifdef AMDGPU_CIK 38 #define CONFIG_DRM_AMDGPU_CIK 1 39 #endif 40 #include "amdgpu_ctx.h" 41 42 #include <linux/atomic.h> 43 #include <linux/wait.h> 44 #include <linux/list.h> 45 #include <linux/kref.h> 46 #include <linux/rbtree.h> 47 #include <linux/hashtable.h> 48 #include <linux/dma-fence.h> 49 #include <linux/acpi.h> 50 51 #include <drm/ttm/ttm_bo_api.h> 52 #include <drm/ttm/ttm_bo_driver.h> 53 #include <drm/ttm/ttm_placement.h> 54 #include <drm/ttm/ttm_module.h> 55 #include <drm/ttm/ttm_execbuf_util.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 #include <drm/gpu_scheduler.h> 61 62 #include <kgd_kfd_interface.h> 63 #include "dm_pp_interface.h" 64 #include "kgd_pp_interface.h" 65 66 #include "amd_shared.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_mn.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_nbio.h" 88 #include "amdgpu_dm.h" 89 #include "amdgpu_virt.h" 90 #include "amdgpu_csa.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_smu.h" 99 #include "amdgpu_discovery.h" 100 #include "amdgpu_mes.h" 101 #include "amdgpu_umc.h" 102 #include "amdgpu_mmhub.h" 103 #include "amdgpu_df.h" 104 105 #define MAX_GPU_INSTANCE 16 106 107 struct amdgpu_gpu_instance 108 { 109 struct amdgpu_device *adev; 110 int mgpu_fan_enabled; 111 }; 112 113 struct amdgpu_mgpu_info 114 { 115 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 116 struct mutex mutex; 117 uint32_t num_gpu; 118 uint32_t num_dgpu; 119 uint32_t num_apu; 120 }; 121 122 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 123 124 /* 125 * Modules parameters. 126 */ 127 extern int amdgpu_modeset; 128 extern int amdgpu_vram_limit; 129 extern int amdgpu_vis_vram_limit; 130 extern int amdgpu_gart_size; 131 extern int amdgpu_gtt_size; 132 extern int amdgpu_moverate; 133 extern int amdgpu_benchmarking; 134 extern int amdgpu_testing; 135 extern int amdgpu_audio; 136 extern int amdgpu_disp_priority; 137 extern int amdgpu_hw_i2c; 138 extern int amdgpu_pcie_gen2; 139 extern int amdgpu_msi; 140 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 141 extern int amdgpu_dpm; 142 extern int amdgpu_fw_load_type; 143 extern int amdgpu_aspm; 144 extern int amdgpu_runtime_pm; 145 extern uint amdgpu_ip_block_mask; 146 extern int amdgpu_bapm; 147 extern int amdgpu_deep_color; 148 extern int amdgpu_vm_size; 149 extern int amdgpu_vm_block_size; 150 extern int amdgpu_vm_fragment_size; 151 extern int amdgpu_vm_fault_stop; 152 extern int amdgpu_vm_debug; 153 extern int amdgpu_vm_update_mode; 154 extern int amdgpu_exp_hw_support; 155 extern int amdgpu_dc; 156 extern int amdgpu_sched_jobs; 157 extern int amdgpu_sched_hw_submission; 158 extern uint amdgpu_pcie_gen_cap; 159 extern uint amdgpu_pcie_lane_cap; 160 extern uint amdgpu_cg_mask; 161 extern uint amdgpu_pg_mask; 162 extern uint amdgpu_sdma_phase_quantum; 163 extern char *amdgpu_disable_cu; 164 extern char *amdgpu_virtual_display; 165 extern uint amdgpu_pp_feature_mask; 166 extern uint amdgpu_force_long_training; 167 extern int amdgpu_job_hang_limit; 168 extern int amdgpu_lbpw; 169 extern int amdgpu_compute_multipipe; 170 extern int amdgpu_gpu_recovery; 171 extern int amdgpu_emu_mode; 172 extern uint amdgpu_smu_memory_pool_size; 173 extern uint amdgpu_dc_feature_mask; 174 extern uint amdgpu_dm_abm_level; 175 extern struct amdgpu_mgpu_info mgpu_info; 176 extern int amdgpu_ras_enable; 177 extern uint amdgpu_ras_mask; 178 extern int amdgpu_async_gfx_ring; 179 extern int amdgpu_mcbp; 180 extern int amdgpu_discovery; 181 extern int amdgpu_mes; 182 extern int amdgpu_noretry; 183 extern int amdgpu_force_asic_type; 184 #ifdef CONFIG_HSA_AMD 185 extern int sched_policy; 186 #else 187 static const int sched_policy = KFD_SCHED_POLICY_HWS; 188 #endif 189 190 #ifdef CONFIG_DRM_AMDGPU_SI 191 extern int amdgpu_si_support; 192 #endif 193 #ifdef CONFIG_DRM_AMDGPU_CIK 194 extern int amdgpu_cik_support; 195 #endif 196 197 #define AMDGPU_VM_MAX_NUM_CTX 4096 198 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 199 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 200 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 201 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 202 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 203 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 204 #define AMDGPU_IB_POOL_SIZE 16 205 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 206 #define AMDGPUFB_CONN_LIMIT 4 207 #define AMDGPU_BIOS_NUM_SCRATCH 16 208 209 /* hard reset data */ 210 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 211 212 /* reset flags */ 213 #define AMDGPU_RESET_GFX (1 << 0) 214 #define AMDGPU_RESET_COMPUTE (1 << 1) 215 #define AMDGPU_RESET_DMA (1 << 2) 216 #define AMDGPU_RESET_CP (1 << 3) 217 #define AMDGPU_RESET_GRBM (1 << 4) 218 #define AMDGPU_RESET_DMA1 (1 << 5) 219 #define AMDGPU_RESET_RLC (1 << 6) 220 #define AMDGPU_RESET_SEM (1 << 7) 221 #define AMDGPU_RESET_IH (1 << 8) 222 #define AMDGPU_RESET_VMC (1 << 9) 223 #define AMDGPU_RESET_MC (1 << 10) 224 #define AMDGPU_RESET_DISPLAY (1 << 11) 225 #define AMDGPU_RESET_UVD (1 << 12) 226 #define AMDGPU_RESET_VCE (1 << 13) 227 #define AMDGPU_RESET_VCE1 (1 << 14) 228 229 /* max cursor sizes (in pixels) */ 230 #define CIK_CURSOR_WIDTH 128 231 #define CIK_CURSOR_HEIGHT 128 232 233 struct amdgpu_device; 234 struct amdgpu_ib; 235 struct amdgpu_cs_parser; 236 struct amdgpu_job; 237 struct amdgpu_irq_src; 238 struct amdgpu_fpriv; 239 struct amdgpu_bo_va_mapping; 240 struct amdgpu_atif; 241 struct kfd_vm_fault_info; 242 243 enum amdgpu_cp_irq { 244 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 245 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 246 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 247 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 248 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 249 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 250 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 253 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 254 255 AMDGPU_CP_IRQ_LAST 256 }; 257 258 enum amdgpu_thermal_irq { 259 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 260 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 261 262 AMDGPU_THERMAL_IRQ_LAST 263 }; 264 265 enum amdgpu_kiq_irq { 266 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 267 AMDGPU_CP_KIQ_IRQ_LAST 268 }; 269 270 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 271 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 272 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 273 274 int amdgpu_device_ip_set_clockgating_state(void *dev, 275 enum amd_ip_block_type block_type, 276 enum amd_clockgating_state state); 277 int amdgpu_device_ip_set_powergating_state(void *dev, 278 enum amd_ip_block_type block_type, 279 enum amd_powergating_state state); 280 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 281 u32 *flags); 282 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 283 enum amd_ip_block_type block_type); 284 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 285 enum amd_ip_block_type block_type); 286 287 #define AMDGPU_MAX_IP_NUM 16 288 289 struct amdgpu_ip_block_status { 290 bool valid; 291 bool sw; 292 bool hw; 293 bool late_initialized; 294 bool hang; 295 }; 296 297 struct amdgpu_ip_block_version { 298 const enum amd_ip_block_type type; 299 const u32 major; 300 const u32 minor; 301 const u32 rev; 302 const struct amd_ip_funcs *funcs; 303 }; 304 305 #define HW_REV(_Major, _Minor, _Rev) \ 306 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 307 308 struct amdgpu_ip_block { 309 struct amdgpu_ip_block_status status; 310 const struct amdgpu_ip_block_version *version; 311 }; 312 313 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 314 enum amd_ip_block_type type, 315 u32 major, u32 minor); 316 317 struct amdgpu_ip_block * 318 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 319 enum amd_ip_block_type type); 320 321 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 322 const struct amdgpu_ip_block_version *ip_block_version); 323 324 /* 325 * BIOS. 326 */ 327 bool amdgpu_get_bios(struct amdgpu_device *adev); 328 bool amdgpu_read_bios(struct amdgpu_device *adev); 329 330 /* 331 * Clocks 332 */ 333 334 #define AMDGPU_MAX_PPLL 3 335 336 struct amdgpu_clock { 337 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 338 struct amdgpu_pll spll; 339 struct amdgpu_pll mpll; 340 /* 10 Khz units */ 341 uint32_t default_mclk; 342 uint32_t default_sclk; 343 uint32_t default_dispclk; 344 uint32_t current_dispclk; 345 uint32_t dp_extclk; 346 uint32_t max_pixel_clock; 347 }; 348 349 /* sub-allocation manager, it has to be protected by another lock. 350 * By conception this is an helper for other part of the driver 351 * like the indirect buffer or semaphore, which both have their 352 * locking. 353 * 354 * Principe is simple, we keep a list of sub allocation in offset 355 * order (first entry has offset == 0, last entry has the highest 356 * offset). 357 * 358 * When allocating new object we first check if there is room at 359 * the end total_size - (last_object_offset + last_object_size) >= 360 * alloc_size. If so we allocate new object there. 361 * 362 * When there is not enough room at the end, we start waiting for 363 * each sub object until we reach object_offset+object_size >= 364 * alloc_size, this object then become the sub object we return. 365 * 366 * Alignment can't be bigger than page size. 367 * 368 * Hole are not considered for allocation to keep things simple. 369 * Assumption is that there won't be hole (all object on same 370 * alignment). 371 */ 372 373 #define AMDGPU_SA_NUM_FENCE_LISTS 32 374 375 struct amdgpu_sa_manager { 376 spinlock_t wq_lock; 377 drm_waitqueue_t wq; 378 struct amdgpu_bo *bo; 379 struct list_head *hole; 380 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 381 struct list_head olist; 382 unsigned size; 383 uint64_t gpu_addr; 384 void *cpu_ptr; 385 uint32_t domain; 386 uint32_t align; 387 }; 388 389 /* sub-allocation buffer */ 390 struct amdgpu_sa_bo { 391 struct list_head olist; 392 struct list_head flist; 393 struct amdgpu_sa_manager *manager; 394 unsigned soffset; 395 unsigned eoffset; 396 struct dma_fence *fence; 397 }; 398 399 int amdgpu_fence_slab_init(void); 400 void amdgpu_fence_slab_fini(void); 401 402 /* 403 * IRQS. 404 */ 405 406 struct amdgpu_flip_work { 407 struct delayed_work flip_work; 408 struct work_struct unpin_work; 409 struct amdgpu_device *adev; 410 int crtc_id; 411 u32 target_vblank; 412 uint64_t base; 413 struct drm_pending_vblank_event *event; 414 struct amdgpu_bo *old_abo; 415 struct dma_fence *excl; 416 unsigned shared_count; 417 struct dma_fence **shared; 418 struct dma_fence_cb cb; 419 bool async; 420 }; 421 422 423 /* 424 * CP & rings. 425 */ 426 427 struct amdgpu_ib { 428 struct amdgpu_sa_bo *sa_bo; 429 uint32_t length_dw; 430 uint64_t gpu_addr; 431 uint32_t *ptr; 432 uint32_t flags; 433 }; 434 435 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 436 437 /* 438 * file private structure 439 */ 440 441 struct amdgpu_fpriv { 442 struct amdgpu_vm vm; 443 struct amdgpu_bo_va *prt_va; 444 struct amdgpu_bo_va *csa_va; 445 struct mutex bo_list_lock; 446 struct idr bo_list_handles; 447 struct amdgpu_ctx_mgr ctx_mgr; 448 }; 449 450 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 451 452 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 453 unsigned size, struct amdgpu_ib *ib); 454 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 455 struct dma_fence *f); 456 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 457 struct amdgpu_ib *ibs, struct amdgpu_job *job, 458 struct dma_fence **f); 459 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 460 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 461 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 462 463 /* 464 * CS. 465 */ 466 struct amdgpu_cs_chunk { 467 uint32_t chunk_id; 468 uint32_t length_dw; 469 void *kdata; 470 }; 471 472 struct amdgpu_cs_post_dep { 473 struct drm_syncobj *syncobj; 474 struct dma_fence_chain *chain; 475 u64 point; 476 }; 477 478 struct amdgpu_cs_parser { 479 struct amdgpu_device *adev; 480 struct drm_file *filp; 481 struct amdgpu_ctx *ctx; 482 483 /* chunks */ 484 unsigned nchunks; 485 struct amdgpu_cs_chunk *chunks; 486 487 /* scheduler job object */ 488 struct amdgpu_job *job; 489 struct drm_sched_entity *entity; 490 491 /* buffer objects */ 492 struct ww_acquire_ctx ticket; 493 struct amdgpu_bo_list *bo_list; 494 struct amdgpu_mn *mn; 495 struct amdgpu_bo_list_entry vm_pd; 496 struct list_head validated; 497 struct dma_fence *fence; 498 uint64_t bytes_moved_threshold; 499 uint64_t bytes_moved_vis_threshold; 500 uint64_t bytes_moved; 501 uint64_t bytes_moved_vis; 502 503 /* user fence */ 504 struct amdgpu_bo_list_entry uf_entry; 505 506 unsigned num_post_deps; 507 struct amdgpu_cs_post_dep *post_deps; 508 }; 509 510 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 511 uint32_t ib_idx, int idx) 512 { 513 return p->job->ibs[ib_idx].ptr[idx]; 514 } 515 516 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 517 uint32_t ib_idx, int idx, 518 uint32_t value) 519 { 520 p->job->ibs[ib_idx].ptr[idx] = value; 521 } 522 523 /* 524 * Writeback 525 */ 526 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 527 528 struct amdgpu_wb { 529 struct amdgpu_bo *wb_obj; 530 volatile uint32_t *wb; 531 uint64_t gpu_addr; 532 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 533 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, NBBY*sizeof(unsigned long))]; 534 }; 535 536 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 537 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 538 539 /* 540 * Benchmarking 541 */ 542 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 543 544 545 /* 546 * Testing 547 */ 548 void amdgpu_test_moves(struct amdgpu_device *adev); 549 550 /* 551 * ASIC specific register table accessible by UMD 552 */ 553 struct amdgpu_allowed_register_entry { 554 uint32_t reg_offset; 555 bool grbm_indexed; 556 }; 557 558 enum amd_reset_method { 559 AMD_RESET_METHOD_LEGACY = 0, 560 AMD_RESET_METHOD_MODE0, 561 AMD_RESET_METHOD_MODE1, 562 AMD_RESET_METHOD_MODE2, 563 AMD_RESET_METHOD_BACO 564 }; 565 566 /* 567 * ASIC specific functions. 568 */ 569 struct amdgpu_asic_funcs { 570 bool (*read_disabled_bios)(struct amdgpu_device *adev); 571 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 572 u8 *bios, u32 length_bytes); 573 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 574 u32 sh_num, u32 reg_offset, u32 *value); 575 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 576 int (*reset)(struct amdgpu_device *adev); 577 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 578 /* get the reference clock */ 579 u32 (*get_xclk)(struct amdgpu_device *adev); 580 /* MM block clocks */ 581 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 582 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 583 /* static power management */ 584 int (*get_pcie_lanes)(struct amdgpu_device *adev); 585 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 586 /* get config memsize register */ 587 u32 (*get_config_memsize)(struct amdgpu_device *adev); 588 /* flush hdp write queue */ 589 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 590 /* invalidate hdp read cache */ 591 void (*invalidate_hdp)(struct amdgpu_device *adev, 592 struct amdgpu_ring *ring); 593 /* check if the asic needs a full reset of if soft reset will work */ 594 bool (*need_full_reset)(struct amdgpu_device *adev); 595 /* initialize doorbell layout for specific asic*/ 596 void (*init_doorbell_index)(struct amdgpu_device *adev); 597 /* PCIe bandwidth usage */ 598 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 599 uint64_t *count1); 600 /* do we need to reset the asic at init time (e.g., kexec) */ 601 bool (*need_reset_on_init)(struct amdgpu_device *adev); 602 /* PCIe replay counter */ 603 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 604 /* device supports BACO */ 605 bool (*supports_baco)(struct amdgpu_device *adev); 606 }; 607 608 /* 609 * IOCTL. 610 */ 611 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 612 struct drm_file *filp); 613 614 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 615 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 616 struct drm_file *filp); 617 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 618 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 619 struct drm_file *filp); 620 621 /* VRAM scratch page for HDP bug, default vram page */ 622 struct amdgpu_vram_scratch { 623 struct amdgpu_bo *robj; 624 volatile uint32_t *ptr; 625 u64 gpu_addr; 626 }; 627 628 /* 629 * ACPI 630 */ 631 struct amdgpu_atcs_functions { 632 bool get_ext_state; 633 bool pcie_perf_req; 634 bool pcie_dev_rdy; 635 bool pcie_bus_width; 636 }; 637 638 struct amdgpu_atcs { 639 struct amdgpu_atcs_functions functions; 640 }; 641 642 /* 643 * Firmware VRAM reservation 644 */ 645 struct amdgpu_fw_vram_usage { 646 u64 start_offset; 647 u64 size; 648 struct amdgpu_bo *reserved_bo; 649 void *va; 650 651 /* GDDR6 training support flag. 652 */ 653 bool mem_train_support; 654 }; 655 656 /* 657 * CGS 658 */ 659 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 660 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 661 662 /* 663 * Core structure, functions and helpers. 664 */ 665 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 666 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 667 668 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 669 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 670 671 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 672 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 673 674 struct amdgpu_mmio_remap { 675 u32 reg_offset; 676 resource_size_t bus_addr; 677 }; 678 679 /* Define the HW IP blocks will be used in driver , add more if necessary */ 680 enum amd_hw_ip_block_type { 681 GC_HWIP = 1, 682 HDP_HWIP, 683 SDMA0_HWIP, 684 SDMA1_HWIP, 685 SDMA2_HWIP, 686 SDMA3_HWIP, 687 SDMA4_HWIP, 688 SDMA5_HWIP, 689 SDMA6_HWIP, 690 SDMA7_HWIP, 691 MMHUB_HWIP, 692 ATHUB_HWIP, 693 NBIO_HWIP, 694 MP0_HWIP, 695 MP1_HWIP, 696 UVD_HWIP, 697 VCN_HWIP = UVD_HWIP, 698 JPEG_HWIP = VCN_HWIP, 699 VCE_HWIP, 700 DF_HWIP, 701 DCE_HWIP, 702 OSSSYS_HWIP, 703 SMUIO_HWIP, 704 PWR_HWIP, 705 NBIF_HWIP, 706 THM_HWIP, 707 CLK_HWIP, 708 UMC_HWIP, 709 RSMU_HWIP, 710 MAX_HWIP 711 }; 712 713 #define HWIP_MAX_INSTANCE 8 714 715 struct amd_powerplay { 716 void *pp_handle; 717 const struct amd_pm_funcs *pp_funcs; 718 }; 719 720 #define AMDGPU_RESET_MAGIC_NUM 64 721 #define AMDGPU_MAX_DF_PERFMONS 4 722 struct amdgpu_device { 723 struct device *dev; 724 struct drm_device *ddev; 725 struct pci_dev *pdev; 726 727 #ifdef CONFIG_DRM_AMD_ACP 728 struct amdgpu_acp acp; 729 #endif 730 731 /* ASIC */ 732 enum amd_asic_type asic_type; 733 uint32_t family; 734 uint32_t rev_id; 735 uint32_t external_rev_id; 736 unsigned long flags; 737 int usec_timeout; 738 const struct amdgpu_asic_funcs *asic_funcs; 739 bool shutdown; 740 bool need_swiotlb; 741 bool accel_working; 742 struct notifier_block acpi_nb; 743 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 744 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 745 unsigned debugfs_count; 746 #if defined(CONFIG_DEBUG_FS) 747 struct dentry *debugfs_preempt; 748 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 749 #endif 750 struct amdgpu_atif *atif; 751 struct amdgpu_atcs atcs; 752 struct mutex srbm_mutex; 753 /* GRBM index mutex. Protects concurrent access to GRBM index */ 754 struct mutex grbm_idx_mutex; 755 struct dev_pm_domain vga_pm_domain; 756 bool have_disp_power_ref; 757 bool have_atomics_support; 758 759 /* BIOS */ 760 bool is_atom_fw; 761 uint8_t *bios; 762 uint32_t bios_size; 763 struct amdgpu_bo *stolen_vga_memory; 764 struct amdgpu_bo *discovery_memory; 765 uint32_t bios_scratch_reg_offset; 766 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 767 768 /* Register/doorbell mmio */ 769 #ifdef __NetBSD__ 770 bus_space_tag_t rmmiot; 771 bus_space_handle_t rmmioh; 772 bus_addr_t rmmio_base; 773 bus_size_t rmmio_size; 774 #else 775 resource_size_t rmmio_base; 776 resource_size_t rmmio_size; 777 void __iomem *rmmio; 778 #endif 779 /* protects concurrent MM_INDEX/DATA based register access */ 780 spinlock_t mmio_idx_lock; 781 struct amdgpu_mmio_remap rmmio_remap; 782 /* protects concurrent SMC based register access */ 783 spinlock_t smc_idx_lock; 784 amdgpu_rreg_t smc_rreg; 785 amdgpu_wreg_t smc_wreg; 786 /* protects concurrent PCIE register access */ 787 spinlock_t pcie_idx_lock; 788 amdgpu_rreg_t pcie_rreg; 789 amdgpu_wreg_t pcie_wreg; 790 amdgpu_rreg_t pciep_rreg; 791 amdgpu_wreg_t pciep_wreg; 792 amdgpu_rreg64_t pcie_rreg64; 793 amdgpu_wreg64_t pcie_wreg64; 794 /* protects concurrent UVD register access */ 795 spinlock_t uvd_ctx_idx_lock; 796 amdgpu_rreg_t uvd_ctx_rreg; 797 amdgpu_wreg_t uvd_ctx_wreg; 798 /* protects concurrent DIDT register access */ 799 spinlock_t didt_idx_lock; 800 amdgpu_rreg_t didt_rreg; 801 amdgpu_wreg_t didt_wreg; 802 /* protects concurrent gc_cac register access */ 803 spinlock_t gc_cac_idx_lock; 804 amdgpu_rreg_t gc_cac_rreg; 805 amdgpu_wreg_t gc_cac_wreg; 806 /* protects concurrent se_cac register access */ 807 spinlock_t se_cac_idx_lock; 808 amdgpu_rreg_t se_cac_rreg; 809 amdgpu_wreg_t se_cac_wreg; 810 /* protects concurrent ENDPOINT (audio) register access */ 811 spinlock_t audio_endpt_idx_lock; 812 amdgpu_block_rreg_t audio_endpt_rreg; 813 amdgpu_block_wreg_t audio_endpt_wreg; 814 #ifdef __NetBSD__ 815 bus_space_tag_t rio_memt; 816 bus_space_handle_t rio_memh; 817 bus_size_t rio_mem_size; 818 #else 819 void __iomem *rio_mem; 820 resource_size_t rio_mem_size; 821 #endif 822 struct amdgpu_doorbell doorbell; 823 824 /* clock/pll info */ 825 struct amdgpu_clock clock; 826 827 /* MC */ 828 struct amdgpu_gmc gmc; 829 struct amdgpu_gart gart; 830 #ifdef __NetBSD__ 831 bus_dma_segment_t dummy_page_seg; 832 bus_dmamap_t dummy_page_map; 833 #endif 834 dma_addr_t dummy_page_addr; 835 struct amdgpu_vm_manager vm_manager; 836 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 837 unsigned num_vmhubs; 838 839 /* memory management */ 840 struct amdgpu_mman mman; 841 struct amdgpu_vram_scratch vram_scratch; 842 struct amdgpu_wb wb; 843 atomic64_t num_bytes_moved; 844 atomic64_t num_evictions; 845 atomic64_t num_vram_cpu_page_faults; 846 atomic_t gpu_reset_counter; 847 atomic_t vram_lost_counter; 848 849 /* data for buffer migration throttling */ 850 struct { 851 spinlock_t lock; 852 s64 last_update_us; 853 s64 accum_us; /* accumulated microseconds */ 854 s64 accum_us_vis; /* for visible VRAM */ 855 u32 log2_max_MBps; 856 } mm_stats; 857 858 /* display */ 859 bool enable_virtual_display; 860 struct amdgpu_mode_info mode_info; 861 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 862 struct work_struct hotplug_work; 863 struct amdgpu_irq_src crtc_irq; 864 struct amdgpu_irq_src vupdate_irq; 865 struct amdgpu_irq_src pageflip_irq; 866 struct amdgpu_irq_src hpd_irq; 867 868 /* rings */ 869 u64 fence_context; 870 unsigned num_rings; 871 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 872 bool ib_pool_ready; 873 struct amdgpu_sa_manager ring_tmp_bo; 874 875 /* interrupts */ 876 struct amdgpu_irq irq; 877 878 /* powerplay */ 879 struct amd_powerplay powerplay; 880 bool pp_force_state_enabled; 881 882 /* smu */ 883 struct smu_context smu; 884 885 /* dpm */ 886 struct amdgpu_pm pm; 887 u32 cg_flags; 888 u32 pg_flags; 889 890 /* nbio */ 891 struct amdgpu_nbio nbio; 892 893 /* mmhub */ 894 struct amdgpu_mmhub mmhub; 895 896 /* gfx */ 897 struct amdgpu_gfx gfx; 898 899 /* sdma */ 900 struct amdgpu_sdma sdma; 901 902 /* uvd */ 903 struct amdgpu_uvd uvd; 904 905 /* vce */ 906 struct amdgpu_vce vce; 907 908 /* vcn */ 909 struct amdgpu_vcn vcn; 910 911 /* jpeg */ 912 struct amdgpu_jpeg jpeg; 913 914 /* firmwares */ 915 struct amdgpu_firmware firmware; 916 917 /* PSP */ 918 struct psp_context psp; 919 920 /* GDS */ 921 struct amdgpu_gds gds; 922 923 /* KFD */ 924 struct amdgpu_kfd_dev kfd; 925 926 /* UMC */ 927 struct amdgpu_umc umc; 928 929 /* display related functionality */ 930 struct amdgpu_display_manager dm; 931 932 /* discovery */ 933 uint8_t *discovery; 934 935 /* mes */ 936 bool enable_mes; 937 struct amdgpu_mes mes; 938 939 /* df */ 940 struct amdgpu_df df; 941 942 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 943 int num_ip_blocks; 944 struct mutex mn_lock; 945 DECLARE_HASHTABLE(mn_hash, 7); 946 947 /* tracking pinned memory */ 948 atomic64_t vram_pin_size; 949 atomic64_t visible_pin_size; 950 atomic64_t gart_pin_size; 951 952 /* soc15 register offset based on ip, instance and segment */ 953 const uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 954 955 /* delayed work_func for deferring clockgating during resume */ 956 struct delayed_work delayed_init_work; 957 958 struct amdgpu_virt virt; 959 /* firmware VRAM reservation */ 960 struct amdgpu_fw_vram_usage fw_vram_usage; 961 962 /* link all shadow bo */ 963 struct list_head shadow_list; 964 struct mutex shadow_list_lock; 965 /* keep an lru list of rings by HW IP */ 966 struct list_head ring_lru_list; 967 spinlock_t ring_lru_list_lock; 968 969 /* record hw reset is performed */ 970 bool has_hw_reset; 971 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 972 973 /* s3/s4 mask */ 974 bool in_suspend; 975 976 /* record last mm index being written through WREG32*/ 977 unsigned long last_mm_index; 978 bool in_gpu_reset; 979 enum pp_mp1_state mp1_state; 980 struct mutex lock_reset; 981 struct amdgpu_doorbell_index doorbell_index; 982 983 struct mutex notifier_lock; 984 985 int asic_reset_res; 986 struct work_struct xgmi_reset_work; 987 988 long gfx_timeout; 989 long sdma_timeout; 990 long video_timeout; 991 long compute_timeout; 992 993 uint64_t unique_id; 994 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 995 996 /* device pstate */ 997 int pstate; 998 /* enable runtime pm on the device */ 999 bool runpm; 1000 1001 bool pm_sysfs_en; 1002 bool ucode_sysfs_en; 1003 }; 1004 1005 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1006 { 1007 return container_of(bdev, struct amdgpu_device, mman.bdev); 1008 } 1009 1010 int amdgpu_device_init(struct amdgpu_device *adev, 1011 struct drm_device *ddev, 1012 struct pci_dev *pdev, 1013 uint32_t flags); 1014 void amdgpu_device_fini(struct amdgpu_device *adev); 1015 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1016 1017 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1018 uint32_t *buf, size_t size, bool write); 1019 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1020 uint32_t acc_flags); 1021 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1022 uint32_t acc_flags); 1023 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1024 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1025 1026 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1027 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1028 1029 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1030 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1031 1032 int emu_soc_asic_init(struct amdgpu_device *adev); 1033 1034 /* 1035 * Registers read & write functions. 1036 */ 1037 1038 #define AMDGPU_REGS_IDX (1<<0) 1039 #define AMDGPU_REGS_NO_KIQ (1<<1) 1040 #define AMDGPU_REGS_KIQ (1<<2) 1041 1042 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1043 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1044 1045 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1046 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1047 1048 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1049 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1050 1051 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1052 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1053 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1054 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1055 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1056 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1057 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1058 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1059 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1060 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1061 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1062 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1063 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1064 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1065 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1066 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1067 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1068 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1069 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1070 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1071 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1072 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1073 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1074 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1075 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1076 #define WREG32_P(reg, val, mask) \ 1077 do { \ 1078 uint32_t tmp_ = RREG32(reg); \ 1079 tmp_ &= (mask); \ 1080 tmp_ |= ((val) & ~(mask)); \ 1081 WREG32(reg, tmp_); \ 1082 } while (0) 1083 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1084 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1085 #define WREG32_PLL_P(reg, val, mask) \ 1086 do { \ 1087 uint32_t tmp_ = RREG32_PLL(reg); \ 1088 tmp_ &= (mask); \ 1089 tmp_ |= ((val) & ~(mask)); \ 1090 WREG32_PLL(reg, tmp_); \ 1091 } while (0) 1092 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1093 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1094 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1095 1096 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1097 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1098 1099 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1100 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1101 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1102 1103 #define REG_GET_FIELD(value, reg, field) \ 1104 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1105 1106 #define WREG32_FIELD(reg, field, val) \ 1107 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1108 1109 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1110 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1111 1112 /* 1113 * BIOS helpers. 1114 */ 1115 #define RBIOS8(i) (adev->bios[i]) 1116 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1117 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1118 1119 /* 1120 * ASICs macro. 1121 */ 1122 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1123 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1124 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1125 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1126 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1127 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1128 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1129 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1130 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1131 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1132 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1133 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1134 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1135 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1136 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1137 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1138 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1139 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1140 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1141 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1142 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1143 1144 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1145 1146 /* Common functions */ 1147 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1148 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1149 struct amdgpu_job* job); 1150 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1151 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1152 1153 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1154 u64 num_vis_bytes); 1155 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1156 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1157 const u32 *registers, 1158 const u32 array_size); 1159 int amdgpu_ttm_init(struct amdgpu_device *adev); 1160 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1161 1162 bool amdgpu_device_supports_boco(struct drm_device *dev); 1163 bool amdgpu_device_supports_baco(struct drm_device *dev); 1164 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1165 struct amdgpu_device *peer_adev); 1166 int amdgpu_device_baco_enter(struct drm_device *dev); 1167 int amdgpu_device_baco_exit(struct drm_device *dev); 1168 1169 /* atpx handler */ 1170 #if defined(CONFIG_VGA_SWITCHEROO) 1171 void amdgpu_register_atpx_handler(void); 1172 void amdgpu_unregister_atpx_handler(void); 1173 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1174 bool amdgpu_is_atpx_hybrid(void); 1175 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1176 bool amdgpu_has_atpx(void); 1177 #else 1178 static inline void amdgpu_register_atpx_handler(void) {} 1179 static inline void amdgpu_unregister_atpx_handler(void) {} 1180 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1181 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1182 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1183 static inline bool amdgpu_has_atpx(void) { return false; } 1184 #endif 1185 1186 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1187 void *amdgpu_atpx_get_dhandle(void); 1188 #else 1189 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1190 #endif 1191 1192 /* 1193 * KMS 1194 */ 1195 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1196 extern const int amdgpu_max_kms_ioctl; 1197 1198 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1199 void amdgpu_driver_unload_kms(struct drm_device *dev); 1200 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1201 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1202 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1203 struct drm_file *file_priv); 1204 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1205 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1206 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1207 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1208 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1209 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1210 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1211 unsigned long arg); 1212 1213 /* 1214 * functions used by amdgpu_encoder.c 1215 */ 1216 struct amdgpu_afmt_acr { 1217 u32 clock; 1218 1219 int n_32khz; 1220 int cts_32khz; 1221 1222 int n_44_1khz; 1223 int cts_44_1khz; 1224 1225 int n_48khz; 1226 int cts_48khz; 1227 1228 }; 1229 1230 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1231 1232 /* amdgpu_acpi.c */ 1233 #if defined(CONFIG_ACPI) 1234 int amdgpu_acpi_init(struct amdgpu_device *adev); 1235 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1236 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1237 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1238 u8 perf_req, bool advertise); 1239 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1240 1241 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1242 struct amdgpu_dm_backlight_caps *caps); 1243 #else 1244 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1245 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1246 #endif 1247 1248 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1249 uint64_t addr, struct amdgpu_bo **bo, 1250 struct amdgpu_bo_va_mapping **mapping); 1251 1252 #if defined(CONFIG_DRM_AMD_DC) 1253 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1254 #else 1255 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1256 #endif 1257 1258 1259 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1260 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1261 1262 #include "amdgpu_object.h" 1263 1264 #ifdef __NetBSD__ /* XXX amdgpu sysfs */ 1265 #define AMDGPU_PMU_ATTR(_name, _object) CTASSERT(1) 1266 #else 1267 /* used by df_v3_6.c and amdgpu_pmu.c */ 1268 #define AMDGPU_PMU_ATTR(_name, _object) \ 1269 static ssize_t \ 1270 _name##_show(struct device *dev, \ 1271 struct device_attribute *attr, \ 1272 char *page) \ 1273 { \ 1274 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1275 return sprintf(page, _object "\n"); \ 1276 } \ 1277 \ 1278 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1279 #endif 1280 1281 #endif 1282 1283