xref: /netbsd-src/sys/external/bsd/compiler_rt/dist/lib/builtins/clear_cache.c (revision 413d532bcc3f62d122e56d92e13ac64825a40baf)
1 /* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
2  *
3  *                     The LLVM Compiler Infrastructure
4  *
5  * This file is dual licensed under the MIT and the University of Illinois Open
6  * Source Licenses. See LICENSE.TXT for details.
7  *
8  * ===----------------------------------------------------------------------===
9  */
10 
11 #include "int_lib.h"
12 
13 #if __APPLE__
14   #include <libkern/OSCacheControl.h>
15 #endif
16 #if defined(__NetBSD__) && defined(__arm__)
17   #include <machine/sysarch.h>
18 #endif
19 
20 /*
21  * The compiler generates calls to __clear_cache() when creating
22  * trampoline functions on the stack for use with nested functions.
23  * It is expected to invalidate the instruction cache for the
24  * specified range.
25  */
26 
27 COMPILER_RT_ABI void
28 __clear_cache(void* start, void* end)
29 {
30 #if __i386__ || __x86_64__
31 /*
32  * Intel processors have a unified instruction and data cache
33  * so there is nothing to do
34  */
35 #elif defined(__NetBSD__) && defined(__arm__)
36   struct arm_sync_icache_args arg;
37 
38   arg.addr = (uintptr_t)start;
39   arg.len = (uintptr_t)end - (uintptr_t)start;
40 
41   sysarch(ARM_SYNC_ICACHE, &arg);
42 #elif defined(__aarch64__) && !defined(__APPLE__)
43   uint64_t xstart = (uint64_t)(uintptr_t) start;
44   uint64_t xend = (uint64_t)(uintptr_t) end;
45 
46   // Get Cache Type Info
47   uint64_t ctr_el0;
48   __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
49 
50   /*
51    * dc & ic instructions must use 64bit registers so we don't use
52    * uintptr_t in case this runs in an IPL32 environment.
53    */
54   const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
55   for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size)
56     __asm __volatile("dc cvau, %0" :: "r"(addr));
57   __asm __volatile("dsb ish");
58 
59   const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
60   for (uint64_t addr = xstart; addr < xend; addr += icache_line_size)
61     __asm __volatile("ic ivau, %0" :: "r"(addr));
62   __asm __volatile("isb sy");
63 #else
64     #if __APPLE__
65         /* On Darwin, sys_icache_invalidate() provides this functionality */
66         sys_icache_invalidate(start, end-start);
67     #else
68         compilerrt_abort();
69     #endif
70 #endif
71 }
72 
73