1*cbab9cadSchs /* $NetBSD: xdvar.h,v 1.13 2012/10/27 17:18:38 chs Exp $ */ 2f00f5d94Spk 3f00f5d94Spk /* 4f00f5d94Spk * Copyright (c) 1995 Charles D. Cranor 5f00f5d94Spk * All rights reserved. 6f00f5d94Spk * 7f00f5d94Spk * Redistribution and use in source and binary forms, with or without 8f00f5d94Spk * modification, are permitted provided that the following conditions 9f00f5d94Spk * are met: 10f00f5d94Spk * 1. Redistributions of source code must retain the above copyright 11f00f5d94Spk * notice, this list of conditions and the following disclaimer. 12f00f5d94Spk * 2. Redistributions in binary form must reproduce the above copyright 13f00f5d94Spk * notice, this list of conditions and the following disclaimer in the 14f00f5d94Spk * documentation and/or other materials provided with the distribution. 15f00f5d94Spk * 16f00f5d94Spk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17f00f5d94Spk * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18f00f5d94Spk * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19f00f5d94Spk * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20f00f5d94Spk * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21f00f5d94Spk * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22f00f5d94Spk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23f00f5d94Spk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24f00f5d94Spk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25f00f5d94Spk * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26f00f5d94Spk */ 27f00f5d94Spk 28f00f5d94Spk /* 29f00f5d94Spk * x d v a r . h 30f00f5d94Spk * 31f00f5d94Spk * this file defines the software structure we use to control the 32f00f5d94Spk * 753/7053. 33f00f5d94Spk * 34e7c4ab00Schuck * author: Chuck Cranor <chuck@netbsd> 35f00f5d94Spk */ 36f00f5d94Spk 37fc96443dSthorpej #include <sys/callout.h> 38fc96443dSthorpej 39f00f5d94Spk /* 40f00f5d94Spk * i/o request: wrapper for hardware's iopb data structure 41f00f5d94Spk */ 42f00f5d94Spk 43f00f5d94Spk struct xd_iorq { 44f00f5d94Spk struct xd_iopb *iopb; /* address of matching iopb */ 455bdabcebSpk struct xd_iopb *dmaiopb; /* DMA address of above */ 46f00f5d94Spk struct xdc_softc *xdc; /* who we are working with */ 47f00f5d94Spk struct xd_softc *xd; /* which disk */ 48f00f5d94Spk int ttl; /* time to live */ 49f00f5d94Spk int mode; /* current mode (state+other data) */ 50f00f5d94Spk int tries; /* number of times we have tried it */ 5106869f0aSchristos int errnum; /* error number if we fail */ 52f00f5d94Spk int lasterror; /* last error we got */ 53f00f5d94Spk int blockno; /* starting block no for this xfer */ 54f00f5d94Spk int sectcnt; /* number of sectors in xfer */ 55f00f5d94Spk char *dbuf; /* KVA of data buffer (advances) */ 56f00f5d94Spk struct buf *buf; /* for NORM */ 57b1f869efSpk bus_dmamap_t dmamap; /* DMA I/O handle */ 58f00f5d94Spk }; 59f00f5d94Spk 60f00f5d94Spk /* 61f00f5d94Spk * state 62f00f5d94Spk */ 63f00f5d94Spk 64f00f5d94Spk #define XD_SUB_MASK 0xf0 /* mask bits for state */ 65f00f5d94Spk #define XD_SUB_FREE 0x00 /* free */ 66f00f5d94Spk #define XD_SUB_NORM 0x10 /* normal I/O request */ 67f00f5d94Spk #define XD_SUB_WAIT 0x20 /* normal I/O request in the 68f00f5d94Spk context of a process */ 69f00f5d94Spk #define XD_SUB_POLL 0x30 /* polled mode */ 70f00f5d94Spk #define XD_SUB_DONE 0x40 /* not active, but can't be free'd yet */ 71f00f5d94Spk #define XD_SUB_NOQ 0x50 /* don't queue, just submit (internal) */ 72f00f5d94Spk 73f00f5d94Spk #define XD_STATE(X) ((X) & XD_SUB_MASK) /* extract state from mode */ 74f00f5d94Spk #define XD_NEWSTATE(OLD, NEW) (((OLD) & ~XD_SUB_MASK) |(NEW)) /* new state */ 75f00f5d94Spk 76f00f5d94Spk 77f00f5d94Spk /* 78f00f5d94Spk * other mode data 79f00f5d94Spk */ 80f00f5d94Spk 81f00f5d94Spk #define XD_MODE_VERBO 0x08 /* print error messages */ 82f00f5d94Spk #define XD_MODE_B144 0x04 /* handling a bad144 sector */ 83f00f5d94Spk 84f00f5d94Spk 85f00f5d94Spk /* 86f00f5d94Spk * software timers and flags 87f00f5d94Spk */ 88f00f5d94Spk 89f00f5d94Spk #define XDC_SUBWAITLIM 4 /* max number of "done" IOPBs there can be 90f00f5d94Spk where we still allow a SUB_WAIT command */ 91f00f5d94Spk #define XDC_TICKCNT (5*hz) /* call xdc_tick on this interval (5 sec) */ 92f00f5d94Spk #define XDC_MAXTTL 2 /* max number of xd ticks to live */ 93f00f5d94Spk #define XDC_NOUNIT (-1) /* for xdcmd: no unit number */ 94f00f5d94Spk 95f00f5d94Spk /* 96f00f5d94Spk * a "xd_softc" structure contains per-disk state info. 97f00f5d94Spk */ 98f00f5d94Spk 99f00f5d94Spk struct xd_softc { 100*cbab9cadSchs device_t sc_dev; /* device struct, reqd by autoconf */ 101f00f5d94Spk struct disk sc_dk; /* generic disk info */ 102f00f5d94Spk struct xdc_softc *parent; /* parent */ 103f00f5d94Spk u_short flags; /* flags */ 104f00f5d94Spk u_short state; /* device state */ 105f00f5d94Spk int xd_drive; /* unit number */ 106f00f5d94Spk /* geometry */ 107f00f5d94Spk u_short ncyl, acyl, pcyl; /* number of cyl's */ 108f00f5d94Spk u_short sectpercyl; /* nhead*nsect */ 109f00f5d94Spk u_char nhead; /* number of heads */ 110f00f5d94Spk u_char nsect; /* number of sectors per track */ 111f00f5d94Spk u_char hw_spt; /* as above, but includes spare sectors */ 112f00f5d94Spk struct dkbad dkb; /* bad144 sectors */ 113f00f5d94Spk }; 114f00f5d94Spk 115f00f5d94Spk /* 116f00f5d94Spk * flags 117f00f5d94Spk */ 118f00f5d94Spk #define XD_WLABEL 0x0001 /* write label */ 119f00f5d94Spk 120f00f5d94Spk /* 121f00f5d94Spk * state 122f00f5d94Spk */ 123f00f5d94Spk #define XD_DRIVE_UNKNOWN 0 /* never talked to it */ 124f00f5d94Spk #define XD_DRIVE_ATTACHING 1 /* attach in progress */ 125f00f5d94Spk #define XD_DRIVE_NOLABEL 2 /* drive on-line, no label */ 126f00f5d94Spk #define XD_DRIVE_ONLINE 3 /* drive is on-line */ 127f00f5d94Spk 128f00f5d94Spk /* 129f00f5d94Spk * a "xdc_softc" structure contains per-disk-controller state info, 130f00f5d94Spk * including a list of active controllers. 131f00f5d94Spk */ 132f00f5d94Spk 133f00f5d94Spk struct xdc_softc { 134*cbab9cadSchs device_t sc_dev; /* device struct, reqd by autoconf */ 135f00f5d94Spk struct evcnt sc_intrcnt; /* event counter (for vmstat -i) */ 136f00f5d94Spk 137fc96443dSthorpej struct callout sc_tick_ch; 138fc96443dSthorpej 139f00f5d94Spk struct xdc *xdc; /* vaddr of vme registers */ 140f00f5d94Spk 141f00f5d94Spk struct xd_softc *sc_drives[XDC_MAXDEV]; /* drives on this controller */ 142f00f5d94Spk int ipl; /* interrupt level */ 143f00f5d94Spk int vector; /* interrupt vector */ 144b1f869efSpk bus_dma_tag_t dmatag; /* Bus DMA tag */ 145f00f5d94Spk 146f00f5d94Spk struct xd_iorq *reqs; /* i/o requests */ 147f00f5d94Spk struct xd_iopb *iopbase; /* iopb base addr (maps iopb->iorq) */ 148f00f5d94Spk struct xd_iopb *dvmaiopb; /* iopb base in DVMA space, not kvm */ 1491bf775b9Spk bus_dmamap_t iopmap; /* IOPB DMA handle */ 1501bf775b9Spk bus_dmamap_t auxmap; /* auxiliary DMA handle */ 151aec75b1cSyamt struct bufq_state *sc_wq; /* queued IOPBs for this controller */ 152f00f5d94Spk char freereq[XDC_MAXIOPB]; /* free list (stack) */ 153f00f5d94Spk char waitq[XDC_MAXIOPB]; /* wait queue */ 154f00f5d94Spk u_char nfree; /* number of iopbs free */ 155f00f5d94Spk u_char nrun; /* number running */ 156f00f5d94Spk u_char nwait; /* number of waiting iopbs */ 157f00f5d94Spk u_char ndone; /* number of done IORQs */ 158f00f5d94Spk u_char waithead; /* head of queue */ 159f00f5d94Spk u_char waitend; /* end of queue */ 160f00f5d94Spk }; 161f00f5d94Spk 162f00f5d94Spk /* 163f00f5d94Spk * reset blast modes 164f00f5d94Spk */ 165f00f5d94Spk 166f00f5d94Spk #define XD_RSET_NONE (-1) /* restart all requests */ 167f00f5d94Spk #define XD_RSET_ALL (-2) /* don't restart anything */ 168