1 /* $NetBSD: si.c,v 1.2 2000/07/04 01:29:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996,2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, Jason R. Thorpe and 9 * Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains VME bus-dependent of the `si' SCSI adapter. 42 * This hardware is frequently found on Sun 3 and Sun 4 machines. 43 * 44 * The SCSI machinery on this adapter is implemented by an NCR5380, 45 * which is taken care of by the chipset driver in /sys/dev/ic/ncr5380sbc.c 46 * 47 * The logic has a bit to enable or disable the DMA engine, 48 * but that bit also gates the interrupt line from the NCR5380! 49 * Therefore, in order to get any interrupt from the 5380, (i.e. 50 * for reselect) one must clear the DMA engine transfer count and 51 * then enable DMA. This has the further complication that you 52 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 53 * we have to turn DMA back off before we even look at the 5380. 54 * 55 * What wonderfully whacky hardware this is! 56 * 57 */ 58 59 /* 60 * This driver originated as an MD implementation for the sun3 and sun4 61 * ports. The notes pertaining to that history are included below. 62 * 63 * David Jones wrote the initial version of this module for NetBSD/sun3, 64 * which included support for the VME adapter only. (no reselection). 65 * 66 * Gordon Ross added support for the Sun 3 OBIO adapter, and re-worked 67 * both the VME and OBIO code to support disconnect/reselect. 68 * (Required figuring out the hardware "features" noted above.) 69 * 70 * The autoconfiguration boilerplate came from Adam Glass. 71 * 72 * Jason R. Thorpe ported the autoconfiguration and VME portions to 73 * NetBSD/sparc, and added initial support for the 4/100 "SCSI Weird", 74 * a wacky OBIO variant of the VME SCSI-3. Many thanks to Chuck Cranor 75 * for lots of helpful tips and suggestions. Thanks also to Paul Kranenburg 76 * and Chris Torek for bits of insight needed along the way. Thanks to 77 * David Gilbert and Andrew Gillham who risked filesystem life-and-limb 78 * for the sake of testing. Andrew Gillham helped work out the bugs 79 * the 4/100 DMA code. 80 */ 81 82 #include "opt_ddb.h" 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/vme/vmereg.h> 97 #include <dev/vme/vmevar.h> 98 99 #include <dev/scsipi/scsi_all.h> 100 #include <dev/scsipi/scsipi_all.h> 101 #include <dev/scsipi/scsipi_debug.h> 102 #include <dev/scsipi/scsiconf.h> 103 104 #ifndef DDB 105 #define Debugger() 106 #endif 107 108 #ifndef DEBUG 109 #define DEBUG XXX 110 #endif 111 112 #include <dev/ic/ncr5380reg.h> 113 #include <dev/ic/ncr5380var.h> 114 115 #include <dev/vme/sireg.h> 116 117 /* 118 * Transfers smaller than this are done using PIO 119 * (on assumption they're not worth DMA overhead) 120 */ 121 #define MIN_DMA_LEN 128 122 123 #ifdef DEBUG 124 int si_debug = 0; 125 static int si_link_flags = 0 /* | SDEV_DB2 */ ; 126 #endif 127 128 /* 129 * This structure is used to keep track of mapped DMA requests. 130 */ 131 struct si_dma_handle { 132 int dh_flags; 133 #define SIDH_BUSY 0x01 /* This DH is in use */ 134 #define SIDH_OUT 0x02 /* DMA does data out (write) */ 135 int dh_maplen; /* Original data length */ 136 bus_dmamap_t dh_dmamap; 137 #define dh_dvma dh_dmamap->dm_segs[0].ds_addr /* VA of buffer in DVMA space */ 138 }; 139 140 /* 141 * The first structure member has to be the ncr5380_softc 142 * so we can just cast to go back and fourth between them. 143 */ 144 struct si_softc { 145 struct ncr5380_softc ncr_sc; 146 bus_space_tag_t sc_bustag; /* bus tags */ 147 bus_dma_tag_t sc_dmatag; 148 vme_chipset_tag_t sc_vctag; 149 150 int sc_adapter_iv_am; /* int. vec + address modifier */ 151 struct si_dma_handle *sc_dma; 152 int sc_xlen; /* length of current DMA segment. */ 153 int sc_options; /* options for this instance. */ 154 }; 155 156 /* 157 * Options. By default, DMA is enabled and DMA completion interrupts 158 * and reselect are disabled. You may enable additional features 159 * the `flags' directive in your kernel's configuration file. 160 * 161 * Alternatively, you can patch your kernel with DDB or some other 162 * mechanism. The sc_options member of the softc is OR'd with 163 * the value in si_options. 164 * 165 * Note, there's a separate sw_options to make life easier. 166 */ 167 #define SI_ENABLE_DMA 0x01 /* Use DMA (maybe polled) */ 168 #define SI_DMA_INTR 0x02 /* DMA completion interrupts */ 169 #define SI_DO_RESELECT 0x04 /* Allow disconnect/reselect */ 170 #define SI_OPTIONS_MASK (SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT) 171 #define SI_OPTIONS_BITS "\10\3RESELECT\2DMA_INTR\1DMA" 172 int si_options = SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT; 173 174 static int si_match __P((struct device *, struct cfdata *, void *)); 175 static void si_attach __P((struct device *, struct device *, void *)); 176 static int si_intr __P((void *)); 177 static void si_reset_adapter __P((struct ncr5380_softc *)); 178 179 void si_dma_alloc __P((struct ncr5380_softc *)); 180 void si_dma_free __P((struct ncr5380_softc *)); 181 void si_dma_poll __P((struct ncr5380_softc *)); 182 183 void si_dma_setup __P((struct ncr5380_softc *)); 184 void si_dma_start __P((struct ncr5380_softc *)); 185 void si_dma_eop __P((struct ncr5380_softc *)); 186 void si_dma_stop __P((struct ncr5380_softc *)); 187 188 void si_intr_on __P((struct ncr5380_softc *)); 189 void si_intr_off __P((struct ncr5380_softc *)); 190 191 /* 192 * Shorthand bus space access 193 * XXX - must look into endian issues here. 194 */ 195 #define SIREG_READ(sc, index) \ 196 bus_space_read_2((sc)->sc_regt, (sc)->sc_regh, index) 197 #define SIREG_WRITE(sc, index, v) \ 198 bus_space_write_2((sc)->sc_regt, (sc)->sc_regh, index, v) 199 200 201 /* Auto-configuration glue. */ 202 struct cfattach si_ca = { 203 sizeof(struct si_softc), si_match, si_attach 204 }; 205 206 static int 207 si_match(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct vme_attach_args *va = aux; 213 vme_chipset_tag_t ct = va->va_vct; 214 vme_am_t mod; 215 vme_addr_t vme_addr; 216 217 /* Make sure there is something there... */ 218 mod = VME_AM_A24 | VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA; 219 vme_addr = va->r[0].offset; 220 221 if (vme_probe(ct, vme_addr, 1, mod, VME_D8, NULL, 0) != 0) 222 return (0); 223 224 /* 225 * If this is a VME SCSI board, we have to determine whether 226 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board. This can 227 * be determined using the fact that the "sc" board occupies 228 * 4K bytes in VME space but the "si" board occupies 2K bytes. 229 */ 230 return (vme_probe(ct, vme_addr + 0x801, 1, mod, VME_D8, NULL, 0) != 0); 231 } 232 233 static void 234 si_attach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct si_softc *sc = (struct si_softc *) self; 239 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 240 struct vme_attach_args *va = aux; 241 vme_chipset_tag_t ct = va->va_vct; 242 bus_space_tag_t bt; 243 bus_space_handle_t bh; 244 vme_mapresc_t resc; 245 vme_intr_handle_t ih; 246 vme_am_t mod; 247 char bits[64]; 248 int i; 249 250 sc->sc_dmatag = va->va_bdt; 251 sc->sc_vctag = ct; 252 253 mod = VME_AM_A24 | VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA; 254 255 if (vme_space_map(ct, va->r[0].offset, SIREG_BANK_SZ, 256 mod, VME_D8, 0, &bt, &bh, &resc) != 0) 257 panic("%s: vme_space_map", ncr_sc->sc_dev.dv_xname); 258 259 ncr_sc->sc_regt = bt; 260 ncr_sc->sc_regh = bh; 261 262 sc->sc_options = si_options; 263 264 ncr_sc->sc_dma_setup = si_dma_setup; 265 ncr_sc->sc_dma_start = si_dma_start; 266 ncr_sc->sc_dma_eop = si_dma_stop; 267 ncr_sc->sc_dma_stop = si_dma_stop; 268 269 vme_intr_map(ct, va->ilevel, va->ivector, &ih); 270 vme_intr_establish(ct, ih, IPL_BIO, si_intr, sc); 271 272 printf("\n"); 273 274 sc->sc_adapter_iv_am = (mod << 8) | (va->ivector & 0xFF); 275 276 /* 277 * Pull in the options flags. Allow the user to completely 278 * override the default values. 279 */ 280 if ((ncr_sc->sc_dev.dv_cfdata->cf_flags & SI_OPTIONS_MASK) != 0) 281 sc->sc_options = 282 (ncr_sc->sc_dev.dv_cfdata->cf_flags & SI_OPTIONS_MASK); 283 284 /* 285 * Initialize fields used by the MI code 286 */ 287 288 /* NCR5380 register bank offsets */ 289 ncr_sc->sci_r0 = 0; 290 ncr_sc->sci_r1 = 1; 291 ncr_sc->sci_r2 = 2; 292 ncr_sc->sci_r3 = 3; 293 ncr_sc->sci_r4 = 4; 294 ncr_sc->sci_r5 = 5; 295 ncr_sc->sci_r6 = 6; 296 ncr_sc->sci_r7 = 7; 297 298 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 299 300 /* 301 * MD function pointers used by the MI code. 302 */ 303 ncr_sc->sc_pio_out = ncr5380_pio_out; 304 ncr_sc->sc_pio_in = ncr5380_pio_in; 305 ncr_sc->sc_dma_alloc = si_dma_alloc; 306 ncr_sc->sc_dma_free = si_dma_free; 307 ncr_sc->sc_dma_poll = si_dma_poll; 308 309 ncr_sc->sc_flags = 0; 310 if ((sc->sc_options & SI_DO_RESELECT) == 0) 311 ncr_sc->sc_no_disconnect = 0xFF; 312 if ((sc->sc_options & SI_DMA_INTR) == 0) 313 ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 314 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 315 316 /* 317 * Allocate DMA handles. 318 */ 319 i = SCI_OPENINGS * sizeof(struct si_dma_handle); 320 sc->sc_dma = (struct si_dma_handle *)malloc(i, M_DEVBUF, M_NOWAIT); 321 if (sc->sc_dma == NULL) 322 panic("si: dma handle malloc failed\n"); 323 324 for (i = 0; i < SCI_OPENINGS; i++) { 325 sc->sc_dma[i].dh_flags = 0; 326 327 /* Allocate a DMA handle */ 328 if (vme_dmamap_create( 329 sc->sc_vctag, /* VME chip tag */ 330 MAXPHYS, /* size */ 331 VME_AM_A24, /* address modifier */ 332 VME_D16, /* data size */ 333 0, /* swap */ 334 1, /* nsegments */ 335 MAXPHYS, /* maxsegsz */ 336 0, /* boundary */ 337 BUS_DMA_NOWAIT, 338 &sc->sc_dma[i].dh_dmamap) != 0) { 339 340 printf("%s: DMA buffer map create error\n", 341 ncr_sc->sc_dev.dv_xname); 342 return; 343 } 344 } 345 346 if (sc->sc_options) { 347 printf("%s: options=%s\n", ncr_sc->sc_dev.dv_xname, 348 bitmask_snprintf(sc->sc_options, SI_OPTIONS_BITS, 349 bits, sizeof(bits))); 350 } 351 #ifdef DEBUG 352 ncr_sc->sc_link.flags |= si_link_flags; 353 #endif 354 355 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 356 ncr_sc->sc_adapter.scsipi_minphys = minphys; 357 358 /* 359 * Initialize si board itself. 360 */ 361 si_reset_adapter(ncr_sc); 362 ncr5380_attach(ncr_sc); 363 364 if (sc->sc_options & SI_DO_RESELECT) { 365 /* 366 * Need to enable interrupts (and DMA!) 367 * on this H/W for reselect to work. 368 */ 369 ncr_sc->sc_intr_on = si_intr_on; 370 ncr_sc->sc_intr_off = si_intr_off; 371 } 372 } 373 374 #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \ 375 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR ) 376 377 static int 378 si_intr(void *arg) 379 { 380 struct si_softc *sc = arg; 381 struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)arg; 382 int dma_error, claimed; 383 u_short csr; 384 385 claimed = 0; 386 dma_error = 0; 387 388 /* SBC interrupt? DMA interrupt? */ 389 csr = SIREG_READ(ncr_sc, SIREG_CSR); 390 391 NCR_TRACE("si_intr: csr=0x%x\n", csr); 392 393 if (csr & SI_CSR_DMA_CONFLICT) { 394 dma_error |= SI_CSR_DMA_CONFLICT; 395 printf("si_intr: DMA conflict\n"); 396 } 397 if (csr & SI_CSR_DMA_BUS_ERR) { 398 dma_error |= SI_CSR_DMA_BUS_ERR; 399 printf("si_intr: DMA bus error\n"); 400 } 401 if (dma_error) { 402 if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 403 sc->ncr_sc.sc_state |= NCR_ABORTING; 404 /* Make sure we will call the main isr. */ 405 csr |= SI_CSR_DMA_IP; 406 } 407 408 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) { 409 claimed = ncr5380_intr(&sc->ncr_sc); 410 #ifdef DEBUG 411 if (!claimed) { 412 printf("si_intr: spurious from SBC\n"); 413 if (si_debug & 4) { 414 Debugger(); /* XXX */ 415 } 416 } 417 #endif 418 } 419 420 return (claimed); 421 } 422 423 424 static void 425 si_reset_adapter(struct ncr5380_softc *ncr_sc) 426 { 427 struct si_softc *sc = (struct si_softc *)ncr_sc; 428 429 #ifdef DEBUG 430 if (si_debug) { 431 printf("si_reset_adapter\n"); 432 } 433 #endif 434 435 /* 436 * The SCSI3 controller has an 8K FIFO to buffer data between the 437 * 5380 and the DMA. Make sure it starts out empty. 438 * 439 * The reset bits in the CSR are active low. 440 */ 441 SIREG_WRITE(ncr_sc, SIREG_CSR, 0); 442 delay(10); 443 SIREG_WRITE(ncr_sc, SIREG_CSR, 444 SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN); 445 delay(10); 446 447 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0); 448 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0); 449 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0); 450 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0); 451 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0); 452 SIREG_WRITE(ncr_sc, SIREG_IV_AM, sc->sc_adapter_iv_am); 453 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0); 454 455 SCI_CLR_INTR(ncr_sc); 456 } 457 458 /***************************************************************** 459 * Common functions for DMA 460 ****************************************************************/ 461 462 /* 463 * Allocate a DMA handle and put it in sc->sc_dma. Prepare 464 * for DMA transfer. 465 */ 466 void 467 si_dma_alloc(ncr_sc) 468 struct ncr5380_softc *ncr_sc; 469 { 470 struct si_softc *sc = (struct si_softc *)ncr_sc; 471 struct sci_req *sr = ncr_sc->sc_current; 472 struct scsipi_xfer *xs = sr->sr_xs; 473 struct si_dma_handle *dh; 474 int i, xlen; 475 u_long addr; 476 477 #ifdef DIAGNOSTIC 478 if (sr->sr_dma_hand != NULL) 479 panic("si_dma_alloc: already have DMA handle"); 480 #endif 481 482 #if 1 /* XXX - Temporary */ 483 /* XXX - In case we think DMA is completely broken... */ 484 if ((sc->sc_options & SI_ENABLE_DMA) == 0) 485 return; 486 #endif 487 488 addr = (u_long) ncr_sc->sc_dataptr; 489 xlen = ncr_sc->sc_datalen; 490 491 /* If the DMA start addr is misaligned then do PIO */ 492 if ((addr & 1) || (xlen & 1)) { 493 printf("si_dma_alloc: misaligned.\n"); 494 return; 495 } 496 497 /* Make sure our caller checked sc_min_dma_len. */ 498 if (xlen < MIN_DMA_LEN) 499 panic("si_dma_alloc: xlen=0x%x\n", xlen); 500 501 /* Find free DMA handle. Guaranteed to find one since we have 502 as many DMA handles as the driver has processes. */ 503 for (i = 0; i < SCI_OPENINGS; i++) { 504 if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 505 goto found; 506 } 507 panic("si: no free DMA handles."); 508 509 found: 510 dh = &sc->sc_dma[i]; 511 dh->dh_flags = SIDH_BUSY; 512 dh->dh_maplen = xlen; 513 514 /* Copy the "write" flag for convenience. */ 515 if ((xs->xs_control & XS_CTL_DATA_OUT) != 0) 516 dh->dh_flags |= SIDH_OUT; 517 518 /* 519 * Double-map the buffer into DVMA space. If we can't re-map 520 * the buffer, we print a warning and fall back to PIO mode. 521 * 522 * NOTE: it is not safe to sleep here! 523 */ 524 if (bus_dmamap_load(sc->sc_dmatag, dh->dh_dmamap, 525 (caddr_t)addr, xlen, NULL, BUS_DMA_NOWAIT) != 0) { 526 /* Can't remap segment */ 527 printf("si_dma_alloc: can't remap 0x%lx/0x%x, doing PIO\n", 528 addr, dh->dh_maplen); 529 dh->dh_flags = 0; 530 return; 531 } 532 bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap, addr, xlen, 533 (dh->dh_flags & SIDH_OUT) 534 ? BUS_DMASYNC_PREWRITE 535 : BUS_DMASYNC_PREREAD); 536 537 /* success */ 538 sr->sr_dma_hand = dh; 539 540 return; 541 } 542 543 544 void 545 si_dma_free(ncr_sc) 546 struct ncr5380_softc *ncr_sc; 547 { 548 struct si_softc *sc = (struct si_softc *)ncr_sc; 549 struct sci_req *sr = ncr_sc->sc_current; 550 struct si_dma_handle *dh = sr->sr_dma_hand; 551 552 #ifdef DIAGNOSTIC 553 if (dh == NULL) 554 panic("si_dma_free: no DMA handle"); 555 #endif 556 557 if (ncr_sc->sc_state & NCR_DOINGDMA) 558 panic("si_dma_free: free while in progress"); 559 560 if (dh->dh_flags & SIDH_BUSY) { 561 /* Give back the DVMA space. */ 562 bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap, 563 dh->dh_dvma, dh->dh_maplen, 564 (dh->dh_flags & SIDH_OUT) 565 ? BUS_DMASYNC_POSTWRITE 566 : BUS_DMASYNC_POSTREAD); 567 bus_dmamap_unload(sc->sc_dmatag, dh->dh_dmamap); 568 dh->dh_flags = 0; 569 } 570 sr->sr_dma_hand = NULL; 571 } 572 573 574 /* 575 * Poll (spin-wait) for DMA completion. 576 * Called right after xx_dma_start(), and 577 * xx_dma_stop() will be called next. 578 * Same for either VME or OBIO. 579 */ 580 void 581 si_dma_poll(ncr_sc) 582 struct ncr5380_softc *ncr_sc; 583 { 584 struct sci_req *sr = ncr_sc->sc_current; 585 int tmo, csr_mask, csr; 586 587 /* Make sure DMA started successfully. */ 588 if (ncr_sc->sc_state & NCR_ABORTING) 589 return; 590 591 csr_mask = SI_CSR_SBC_IP | SI_CSR_DMA_IP | 592 SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR; 593 594 tmo = 50000; /* X100 = 5 sec. */ 595 for (;;) { 596 csr = SIREG_READ(ncr_sc, SIREG_CSR); 597 if (csr & csr_mask) 598 break; 599 if (--tmo <= 0) { 600 printf("%s: DMA timeout (while polling)\n", 601 ncr_sc->sc_dev.dv_xname); 602 /* Indicate timeout as MI code would. */ 603 sr->sr_flags |= SR_OVERDUE; 604 break; 605 } 606 delay(100); 607 } 608 609 #ifdef DEBUG 610 if (si_debug) { 611 printf("si_dma_poll: done, csr=0x%x\n", csr); 612 } 613 #endif 614 } 615 616 617 /***************************************************************** 618 * VME functions for DMA 619 ****************************************************************/ 620 621 622 /* 623 * This is called when the bus is going idle, 624 * so we want to enable the SBC interrupts. 625 * That is controlled by the DMA enable! 626 * Who would have guessed! 627 * What a NASTY trick! 628 */ 629 void 630 si_intr_on(ncr_sc) 631 struct ncr5380_softc *ncr_sc; 632 { 633 u_int16_t csr; 634 635 si_dma_setup(ncr_sc); 636 csr = SIREG_READ(ncr_sc, SIREG_CSR); 637 csr |= SI_CSR_DMA_EN; 638 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 639 } 640 641 /* 642 * This is called when the bus is idle and we are 643 * about to start playing with the SBC chip. 644 */ 645 void 646 si_intr_off(ncr_sc) 647 struct ncr5380_softc *ncr_sc; 648 { 649 u_int16_t csr; 650 651 csr = SIREG_READ(ncr_sc, SIREG_CSR); 652 csr &= ~SI_CSR_DMA_EN; 653 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 654 } 655 656 /* 657 * This function is called during the COMMAND or MSG_IN phase 658 * that preceeds a DATA_IN or DATA_OUT phase, in case we need 659 * to setup the DMA engine before the bus enters a DATA phase. 660 * 661 * XXX: The VME adapter appears to suppress SBC interrupts 662 * when the FIFO is not empty or the FIFO count is non-zero! 663 * 664 * On the VME version we just clear the DMA count and address 665 * here (to make sure it stays idle) and do the real setup 666 * later, in dma_start. 667 */ 668 void 669 si_dma_setup(ncr_sc) 670 struct ncr5380_softc *ncr_sc; 671 { 672 u_int16_t csr; 673 674 csr = SIREG_READ(ncr_sc, SIREG_CSR); 675 676 /* Reset the FIFO */ 677 csr &= ~SI_CSR_FIFO_RES; /* active low */ 678 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 679 csr |= SI_CSR_FIFO_RES; 680 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 681 682 /* Set direction (assume recv here) */ 683 csr &= ~SI_CSR_SEND; 684 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 685 /* Assume worst alignment */ 686 csr |= SI_CSR_BPCON; 687 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 688 689 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0); 690 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0); 691 692 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0); 693 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0); 694 695 /* Clear FIFO counter. (also hits dma_count) */ 696 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0); 697 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0); 698 } 699 700 701 void 702 si_dma_start(ncr_sc) 703 struct ncr5380_softc *ncr_sc; 704 { 705 struct si_softc *sc = (struct si_softc *)ncr_sc; 706 struct sci_req *sr = ncr_sc->sc_current; 707 struct si_dma_handle *dh = sr->sr_dma_hand; 708 u_long dva; 709 int xlen; 710 u_int mode; 711 u_int16_t csr; 712 713 /* 714 * Get the DVMA mapping for this segment. 715 */ 716 dva = (u_long)(dh->dh_dvma); 717 if (dva & 1) 718 panic("si_dma_start: bad dmaaddr=0x%lx", dva); 719 xlen = ncr_sc->sc_datalen; 720 xlen &= ~1; 721 sc->sc_xlen = xlen; /* XXX: or less... */ 722 723 #ifdef DEBUG 724 if (si_debug & 2) { 725 printf("si_dma_start: dh=%p, dmaaddr=0x%lx, xlen=%d\n", 726 dh, dva, xlen); 727 } 728 #endif 729 730 /* 731 * Set up the DMA controller. 732 * Note that (dh->dh_len < sc_datalen) 733 */ 734 735 csr = SIREG_READ(ncr_sc, SIREG_CSR); 736 737 /* Disable DMA while we're setting up the transfer */ 738 csr &= ~SI_CSR_DMA_EN; 739 740 /* Reset FIFO (again?) */ 741 csr &= ~SI_CSR_FIFO_RES; /* active low */ 742 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 743 csr |= SI_CSR_FIFO_RES; 744 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 745 746 /* Set direction (send/recv) */ 747 if (dh->dh_flags & SIDH_OUT) { 748 csr |= SI_CSR_SEND; 749 } else { 750 csr &= ~SI_CSR_SEND; 751 } 752 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 753 754 if (dva & 2) { 755 csr |= SI_CSR_BPCON; 756 } else { 757 csr &= ~SI_CSR_BPCON; 758 } 759 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 760 761 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, (u_int16_t)(dva >> 16)); 762 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, (u_int16_t)(dva & 0xFFFF)); 763 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, (u_int16_t)(xlen >> 16)); 764 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, (u_int16_t)(xlen & 0xFFFF)); 765 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, (u_int16_t)(xlen >> 16)); 766 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, (u_int16_t)(xlen & 0xFFFF)); 767 768 /* 769 * Acknowledge the phase change. (After DMA setup!) 770 * Put the SBIC into DMA mode, and start the transfer. 771 */ 772 if (dh->dh_flags & SIDH_OUT) { 773 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 774 SCI_CLR_INTR(ncr_sc); 775 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 776 777 mode = NCR5380_READ(ncr_sc, sci_mode); 778 mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 779 NCR5380_WRITE(ncr_sc, sci_mode, mode); 780 781 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */ 782 } else { 783 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 784 SCI_CLR_INTR(ncr_sc); 785 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 786 787 mode = NCR5380_READ(ncr_sc, sci_mode); 788 mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 789 NCR5380_WRITE(ncr_sc, sci_mode, mode); 790 791 NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */ 792 } 793 794 /* Enable DMA engine */ 795 csr |= SI_CSR_DMA_EN; 796 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 797 798 ncr_sc->sc_state |= NCR_DOINGDMA; 799 800 #ifdef DEBUG 801 if (si_debug & 2) { 802 printf("si_dma_start: started, flags=0x%x\n", 803 ncr_sc->sc_state); 804 } 805 #endif 806 } 807 808 809 void 810 si_dma_eop(ncr_sc) 811 struct ncr5380_softc *ncr_sc; 812 { 813 814 /* Not needed - DMA was stopped prior to examining sci_csr */ 815 } 816 817 818 void 819 si_dma_stop(ncr_sc) 820 struct ncr5380_softc *ncr_sc; 821 { 822 struct si_softc *sc = (struct si_softc *)ncr_sc; 823 struct sci_req *sr = ncr_sc->sc_current; 824 struct si_dma_handle *dh = sr->sr_dma_hand; 825 int resid, ntrans; 826 u_int16_t csr; 827 u_int mode; 828 829 if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 830 #ifdef DEBUG 831 printf("si_dma_stop: dma not running\n"); 832 #endif 833 return; 834 } 835 836 ncr_sc->sc_state &= ~NCR_DOINGDMA; 837 838 csr = SIREG_READ(ncr_sc, SIREG_CSR); 839 840 /* First, halt the DMA engine. */ 841 csr &= ~SI_CSR_DMA_EN; 842 SIREG_WRITE(ncr_sc, SIREG_CSR, csr); 843 844 if (csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) { 845 printf("si: DMA error, csr=0x%x, reset\n", csr); 846 sr->sr_xs->error = XS_DRIVER_STUFFUP; 847 ncr_sc->sc_state |= NCR_ABORTING; 848 si_reset_adapter(ncr_sc); 849 } 850 851 /* Note that timeout may have set the error flag. */ 852 if (ncr_sc->sc_state & NCR_ABORTING) 853 goto out; 854 855 /* 856 * Now try to figure out how much actually transferred 857 * 858 * The fifo_count does not reflect how many bytes were 859 * actually transferred for VME. 860 * 861 * SCSI-3 VME interface is a little funny on writes: 862 * if we have a disconnect, the dma has overshot by 863 * one byte and the resid needs to be incremented. 864 * Only happens for partial transfers. 865 * (Thanks to Matt Jacob) 866 */ 867 868 resid = SIREG_READ(ncr_sc, SIREG_FIFO_CNTH) << 16; 869 resid |= SIREG_READ(ncr_sc, SIREG_FIFO_CNT) & 0xFFFF; 870 if (dh->dh_flags & SIDH_OUT) 871 if ((resid > 0) && (resid < sc->sc_xlen)) 872 resid++; 873 ntrans = sc->sc_xlen - resid; 874 875 #ifdef DEBUG 876 if (si_debug & 2) { 877 printf("si_dma_stop: resid=0x%x ntrans=0x%x\n", 878 resid, ntrans); 879 } 880 #endif 881 882 if (ntrans > ncr_sc->sc_datalen) 883 panic("si_dma_stop: excess transfer"); 884 885 /* Adjust data pointer */ 886 ncr_sc->sc_dataptr += ntrans; 887 ncr_sc->sc_datalen -= ntrans; 888 889 #ifdef DEBUG 890 if (si_debug & 2) { 891 printf("si_dma_stop: ntrans=0x%x\n", ntrans); 892 } 893 #endif 894 895 /* 896 * After a read, we may need to clean-up 897 * "Left-over bytes" (yuck!) 898 */ 899 if (((dh->dh_flags & SIDH_OUT) == 0) && 900 ((csr & SI_CSR_LOB) != 0)) 901 { 902 char *cp = ncr_sc->sc_dataptr; 903 u_int16_t bprh, bprl; 904 905 bprh = SIREG_READ(ncr_sc, SIREG_BPRH); 906 bprl = SIREG_READ(ncr_sc, SIREG_BPRL); 907 908 #ifdef DEBUG 909 printf("si: got left-over bytes: bprh=%x, bprl=%x, csr=%x\n", 910 bprh, bprl, csr); 911 #endif 912 913 if (csr & SI_CSR_BPCON) { 914 /* have SI_CSR_BPCON */ 915 cp[-1] = (bprl & 0xff00) >> 8; 916 } else { 917 switch (csr & SI_CSR_LOB) { 918 case SI_CSR_LOB_THREE: 919 cp[-3] = (bprh & 0xff00) >> 8; 920 cp[-2] = (bprh & 0x00ff); 921 cp[-1] = (bprl & 0xff00) >> 8; 922 break; 923 case SI_CSR_LOB_TWO: 924 cp[-2] = (bprh & 0xff00) >> 8; 925 cp[-1] = (bprh & 0x00ff); 926 break; 927 case SI_CSR_LOB_ONE: 928 cp[-1] = (bprh & 0xff00) >> 8; 929 break; 930 } 931 } 932 } 933 934 out: 935 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0); 936 SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0); 937 938 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0); 939 SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0); 940 941 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0); 942 SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0); 943 944 mode = NCR5380_READ(ncr_sc, sci_mode); 945 /* Put SBIC back in PIO mode. */ 946 mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 947 NCR5380_WRITE(ncr_sc, sci_mode, mode); 948 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 949 } 950