xref: /netbsd-src/sys/dev/usb/ustirreg.h (revision aaf4ece63a859a04e37cf3a7229b5fab0157cc06)
1 /*	$NetBSD: ustirreg.h,v 1.3 2002/12/28 06:04:18 dsainty Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by David Sainty <David.Sainty@dtsp.co.nz>
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Registers definitions for SigmaTel STIr4200 USB/IrDA Bridge
41  * Controller.  Documentation available at:
42  *  http://www.sigmatel.com/technical_docs.htm
43  *  http://extranet.sigmatel.com/library/infrared/stir4200/stir4200-ds-1-0.pdf
44  */
45 
46 /* Notes:
47  *
48  * The data sheet states that the TX and RX frames are prepended with
49  * BOF characters.  This appears to be incorrect, the standard 0xff
50  * characters behave as expected.
51  *
52  * There does not appear to be any way to get asynchronous
53  * notifications from this device that data is waiting.  You simply do
54  * have to poll continuously looking for a non-zero-length result.
55  *
56  * The SigmaTel drivers provided with the device for other operating
57  * systems poll at full USB speed (1000 per second), which has a
58  * significant impact on the system.
59  */
60 
61 /*
62  * The SigmaTel device is controlled via an array of registers, with
63  * generic register read/write commands.  This is a completely
64  * different approach to that defined in the USB IrDA standard.
65  */
66 #define STIR_REG_MODE		1
67 #define STIR_REG_BRATE		2
68 #define STIR_REG_CONTROL	3
69 #define STIR_REG_SENSITIVITY	4
70 #define STIR_REG_STATUS		5
71 #define STIR_REG_FFCNT_LSB	6
72 #define STIR_REG_FFCNT_MSB	7
73 #define STIR_REG_DPLL		8
74 #define STIR_REG_IRDIG		9
75 
76 /* Register numbers range from zero to STIR_MAX_REG */
77 #define STIR_MAX_REG		15
78 
79 
80 /*
81  * Mode register bits
82  *
83  * The MIR bit was documented in earlier revisions of the data sheet,
84  * but in the current published version (version 1.0, March 2002) the
85  * MIR bit is documented as "reserved".  Possibly the device has a
86  * design flaw affecting the MIR data rates.
87  */
88 #define STIR_RMODE_FIR		0x80
89 #define STIR_RMODE_MIR		0x40
90 #define STIR_RMODE_SIR		0x20
91 #define STIR_RMODE_ASK		0x10
92 
93 /*
94  * FASTRXEN can be set to enable simultaneous reads and writes.  It
95  * isn't clear that this is useful, the RX and TX data is mixed into
96  * the FIFO and the chip appears to get into a funny state.  In the
97  * absence of good documentation about this bit, leave it disabled!
98  */
99 #define STIR_RMODE_FASTRXEN	0x08
100 
101 #define STIR_RMODE_FFRSTEN	0x04
102 
103 /* FFSPRST must be set to enable the FIFO */
104 #define STIR_RMODE_FFSPRST	0x02
105 
106 /*
107  * High bit baud rate generator value, used in conjunction with the
108  * BRATE register.
109  */
110 #define STIR_RMODE_PDCLK8	0x01
111 
112 
113 /* Status register bits */
114 #define STIR_RSTATUS_EOFRAME	0x80
115 #define STIR_RSTATUS_FFUNDER	0x40
116 #define STIR_RSTATUS_FFOVER	0x20
117 
118 /* Set in write direction, cleared in read direction */
119 #define STIR_RSTATUS_FFDIR	0x10
120 
121 /*
122  * FFCLR is write-only, and the only writable bit in the STATUS
123  * register.
124  */
125 #define STIR_RSTATUS_FFCLR	0x08
126 
127 #define STIR_RSTATUS_FFEMPTY	0x04
128 #define STIR_RSTATUS_FFRXERR	0x02
129 #define STIR_RSTATUS_FFTXERR	0x01
130 
131 
132 /* Extract data from portions of registers */
133 #define STIR_GET_SENSITIVITY_CHIPREVISION(x) ((x) & 7)
134 
135 /*
136  * According to the documentation, FFCNT may be off by as much as 3
137  * bytes.
138  */
139 #define STIR_FFCNT_MARGIN	3
140 
141 /*
142  * The FIFO size for the device is a fixed 4k bytes
143  */
144 #define STIR_FIFO_SIZE		0x1000
145 
146 /*
147  * Vendor specific device requests
148  */
149 #define STIR_CMD_WRITEMULTIREG	0x00
150 #define STIR_CMD_READMULTIREG	0x01
151 #define STIR_CMD_READROM	0x02
152 #define STIR_CMD_WRITESINGLEREG	0x03
153 
154 /*
155  * The MSB is the MODE register setting, the LSB is the BRATE register
156  * setting.
157  *
158  * The MIR rates (576000 and 1152000) were documented in earlier
159  * revisions of the data sheet, but in the current published version
160  * these data rates have disappeared.  Possibly the device has a
161  * design flaw affecting the MIR data rates.
162  */
163 #define STIR_BRMODE_4000000	0x8002
164 #define STIR_BRMODE_1152000	0x4001
165 #define STIR_BRMODE_576000	0x4003
166 #define STIR_BRMODE_115200	0x2009
167 #define STIR_BRMODE_57600	0x2013
168 #define STIR_BRMODE_38400	0x201d
169 #define STIR_BRMODE_19200	0x203b
170 #define STIR_BRMODE_9600	0x2077
171 #define STIR_BRMODE_2400	0x21df
172 
173 /*
174  * Extract values from STIR_BRMODE values.
175  */
176 #define STIR_BRMODE_MODEREG(x)	((x) >> 8)
177 #define STIR_BRMODE_BRATEREG(x)	((x) & 0xff)
178 
179 /*
180  * Each transmit frame starts with the sequence:
181  *
182  * 0x55 0xaa LSB(Length) MSB(Length)
183  */
184 #define STIR_OUTPUT_HEADER_SIZE		4
185 #define STIR_OUTPUT_HEADER_BYTE0	0x55
186 #define STIR_OUTPUT_HEADER_BYTE1	0xaa
187