1 /* $NetBSD: uhci.c,v 1.259 2013/09/08 06:37:23 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill@invisible.ca) 10 * and Matthew R. Green (mrg@eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.259 2013/09/08 06:37:23 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 .open_pipe = uhci_open, 285 .soft_intr = uhci_softintr, 286 .do_poll = uhci_poll, 287 .allocm = uhci_allocm, 288 .freem = uhci_freem, 289 .allocx = uhci_allocx, 290 .freex = uhci_freex, 291 .get_lock = uhci_get_lock, 292 }; 293 294 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 295 .transfer = uhci_root_ctrl_transfer, 296 .start = uhci_root_ctrl_start, 297 .abort = uhci_root_ctrl_abort, 298 .close = uhci_root_ctrl_close, 299 .cleartoggle = uhci_noop, 300 .done = uhci_root_ctrl_done, 301 }; 302 303 const struct usbd_pipe_methods uhci_root_intr_methods = { 304 .transfer = uhci_root_intr_transfer, 305 .start = uhci_root_intr_start, 306 .abort = uhci_root_intr_abort, 307 .close = uhci_root_intr_close, 308 .cleartoggle = uhci_noop, 309 .done = uhci_root_intr_done, 310 }; 311 312 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 313 .transfer = uhci_device_ctrl_transfer, 314 .start = uhci_device_ctrl_start, 315 .abort = uhci_device_ctrl_abort, 316 .close = uhci_device_ctrl_close, 317 .cleartoggle = uhci_noop, 318 .done = uhci_device_ctrl_done, 319 }; 320 321 const struct usbd_pipe_methods uhci_device_intr_methods = { 322 .transfer = uhci_device_intr_transfer, 323 .start = uhci_device_intr_start, 324 .abort = uhci_device_intr_abort, 325 .close = uhci_device_intr_close, 326 .cleartoggle = uhci_device_clear_toggle, 327 .done = uhci_device_intr_done, 328 }; 329 330 const struct usbd_pipe_methods uhci_device_bulk_methods = { 331 .transfer = uhci_device_bulk_transfer, 332 .start = uhci_device_bulk_start, 333 .abort = uhci_device_bulk_abort, 334 .close = uhci_device_bulk_close, 335 .cleartoggle = uhci_device_clear_toggle, 336 .done = uhci_device_bulk_done, 337 }; 338 339 const struct usbd_pipe_methods uhci_device_isoc_methods = { 340 .transfer = uhci_device_isoc_transfer, 341 .start = uhci_device_isoc_start, 342 .abort = uhci_device_isoc_abort, 343 .close = uhci_device_isoc_close, 344 .cleartoggle = uhci_noop, 345 .done = uhci_device_isoc_done, 346 }; 347 348 #define uhci_add_intr_info(sc, ii) \ 349 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 350 #define uhci_del_intr_info(ii) \ 351 do { \ 352 LIST_REMOVE((ii), list); \ 353 (ii)->list.le_prev = NULL; \ 354 } while (0) 355 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 356 357 static inline uhci_soft_qh_t * 358 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 359 { 360 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 361 362 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 363 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 364 usb_syncmem(&pqh->dma, 365 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 366 sizeof(pqh->qh.qh_hlink), 367 BUS_DMASYNC_POSTWRITE); 368 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 369 printf("uhci_find_prev_qh: QH not found\n"); 370 return (NULL); 371 } 372 #endif 373 } 374 return (pqh); 375 } 376 377 void 378 uhci_globalreset(uhci_softc_t *sc) 379 { 380 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 381 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 382 UHCICMD(sc, 0); /* do nothing */ 383 } 384 385 usbd_status 386 uhci_init(uhci_softc_t *sc) 387 { 388 usbd_status err; 389 int i, j; 390 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 391 uhci_soft_td_t *std; 392 393 DPRINTFN(1,("uhci_init: start\n")); 394 395 #ifdef UHCI_DEBUG 396 thesc = sc; 397 398 if (uhcidebug > 2) 399 uhci_dumpregs(sc); 400 #endif 401 402 sc->sc_suspend = PWR_RESUME; 403 404 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 405 uhci_globalreset(sc); /* reset the controller */ 406 uhci_reset(sc); 407 408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 409 USB_MEM_RESERVE); 410 411 /* Allocate and initialize real frame array. */ 412 err = usb_allocmem(&sc->sc_bus, 413 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 414 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 415 if (err) 416 return (err); 417 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 418 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 419 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 420 421 /* 422 * Allocate a TD, inactive, that hangs from the last QH. 423 * This is to avoid a bug in the PIIX that makes it run berserk 424 * otherwise. 425 */ 426 std = uhci_alloc_std(sc); 427 if (std == NULL) 428 return (USBD_NOMEM); 429 std->link.std = NULL; 430 std->td.td_link = htole32(UHCI_PTR_T); 431 std->td.td_status = htole32(0); /* inactive */ 432 std->td.td_token = htole32(0); 433 std->td.td_buffer = htole32(0); 434 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 436 437 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 438 lsqh = uhci_alloc_sqh(sc); 439 if (lsqh == NULL) 440 return (USBD_NOMEM); 441 lsqh->hlink = NULL; 442 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 443 lsqh->elink = std; 444 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 445 sc->sc_last_qh = lsqh; 446 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 448 449 /* Allocate the dummy QH where bulk traffic will be queued. */ 450 bsqh = uhci_alloc_sqh(sc); 451 if (bsqh == NULL) 452 return (USBD_NOMEM); 453 bsqh->hlink = lsqh; 454 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 455 bsqh->elink = NULL; 456 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 457 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 458 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 460 461 /* Allocate dummy QH where high speed control traffic will be queued. */ 462 chsqh = uhci_alloc_sqh(sc); 463 if (chsqh == NULL) 464 return (USBD_NOMEM); 465 chsqh->hlink = bsqh; 466 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 467 chsqh->elink = NULL; 468 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 469 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 470 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 472 473 /* Allocate dummy QH where control traffic will be queued. */ 474 clsqh = uhci_alloc_sqh(sc); 475 if (clsqh == NULL) 476 return (USBD_NOMEM); 477 clsqh->hlink = chsqh; 478 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 479 clsqh->elink = NULL; 480 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 481 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 482 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* 486 * Make all (virtual) frame list pointers point to the interrupt 487 * queue heads and the interrupt queue heads at the control 488 * queue head and point the physical frame list to the virtual. 489 */ 490 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 491 std = uhci_alloc_std(sc); 492 sqh = uhci_alloc_sqh(sc); 493 if (std == NULL || sqh == NULL) 494 return (USBD_NOMEM); 495 std->link.sqh = sqh; 496 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 497 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 498 std->td.td_token = htole32(0); 499 std->td.td_buffer = htole32(0); 500 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 sqh->hlink = clsqh; 503 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 504 sqh->elink = NULL; 505 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 506 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 sc->sc_vframes[i].htd = std; 509 sc->sc_vframes[i].etd = std; 510 sc->sc_vframes[i].hqh = sqh; 511 sc->sc_vframes[i].eqh = sqh; 512 for (j = i; 513 j < UHCI_FRAMELIST_COUNT; 514 j += UHCI_VFRAMELIST_COUNT) 515 sc->sc_pframes[j] = htole32(std->physaddr); 516 } 517 usb_syncmem(&sc->sc_dma, 0, 518 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 519 BUS_DMASYNC_PREWRITE); 520 521 522 LIST_INIT(&sc->sc_intrhead); 523 524 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 525 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 526 527 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 528 529 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 530 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 531 cv_init(&sc->sc_softwake_cv, "uhciab"); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.methods = &uhci_bus_methods; 535 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 536 537 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 538 539 DPRINTFN(1,("uhci_init: enabling\n")); 540 541 err = uhci_run(sc, 1, 0); /* and here we go... */ 542 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 543 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 544 return err; 545 } 546 547 int 548 uhci_activate(device_t self, enum devact act) 549 { 550 struct uhci_softc *sc = device_private(self); 551 552 switch (act) { 553 case DVACT_DEACTIVATE: 554 sc->sc_dying = 1; 555 return 0; 556 default: 557 return EOPNOTSUPP; 558 } 559 } 560 561 void 562 uhci_childdet(device_t self, device_t child) 563 { 564 struct uhci_softc *sc = device_private(self); 565 566 KASSERT(sc->sc_child == child); 567 sc->sc_child = NULL; 568 } 569 570 int 571 uhci_detach(struct uhci_softc *sc, int flags) 572 { 573 int rv = 0; 574 575 if (sc->sc_child != NULL) 576 rv = config_detach(sc->sc_child, flags); 577 578 if (rv != 0) 579 return (rv); 580 581 callout_halt(&sc->sc_poll_handle, NULL); 582 callout_destroy(&sc->sc_poll_handle); 583 584 cv_destroy(&sc->sc_softwake_cv); 585 586 mutex_destroy(&sc->sc_lock); 587 mutex_destroy(&sc->sc_intr_lock); 588 589 pool_cache_destroy(sc->sc_xferpool); 590 591 /* XXX free other data structures XXX */ 592 593 return (rv); 594 } 595 596 usbd_status 597 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 598 { 599 struct uhci_softc *sc = bus->hci_private; 600 usbd_status status; 601 u_int32_t n; 602 603 /* 604 * XXX 605 * Since we are allocating a buffer we can assume that we will 606 * need TDs for it. Since we don't want to allocate those from 607 * an interrupt context, we allocate them here and free them again. 608 * This is no guarantee that we'll get the TDs next time... 609 */ 610 n = size / 8; 611 if (n > 16) { 612 u_int32_t i; 613 uhci_soft_td_t **stds; 614 615 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 616 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 617 if (!stds) 618 return USBD_NOMEM; 619 for(i = 0; i < n; i++) 620 stds[i] = uhci_alloc_std(sc); 621 for(i = 0; i < n; i++) 622 if (stds[i] != NULL) 623 uhci_free_std(sc, stds[i]); 624 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 625 } 626 627 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 628 if (status == USBD_NOMEM) 629 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 630 return status; 631 } 632 633 void 634 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 635 { 636 if (dma->block->flags & USB_DMA_RESERVE) { 637 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 638 dma); 639 return; 640 } 641 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 642 } 643 644 usbd_xfer_handle 645 uhci_allocx(struct usbd_bus *bus) 646 { 647 struct uhci_softc *sc = bus->hci_private; 648 usbd_xfer_handle xfer; 649 650 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 651 if (xfer != NULL) { 652 memset(xfer, 0, sizeof(struct uhci_xfer)); 653 UXFER(xfer)->iinfo.sc = sc; 654 #ifdef DIAGNOSTIC 655 UXFER(xfer)->iinfo.isdone = 1; 656 xfer->busy_free = XFER_BUSY; 657 #endif 658 } 659 return (xfer); 660 } 661 662 void 663 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 664 { 665 struct uhci_softc *sc = bus->hci_private; 666 667 #ifdef DIAGNOSTIC 668 if (xfer->busy_free != XFER_BUSY) { 669 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 670 xfer->busy_free); 671 } 672 xfer->busy_free = XFER_FREE; 673 if (!UXFER(xfer)->iinfo.isdone) { 674 printf("uhci_freex: !isdone\n"); 675 } 676 #endif 677 pool_cache_put(sc->sc_xferpool, xfer); 678 } 679 680 Static void 681 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 682 { 683 struct uhci_softc *sc = bus->hci_private; 684 685 *lock = &sc->sc_lock; 686 } 687 688 689 /* 690 * Handle suspend/resume. 691 * 692 * We need to switch to polling mode here, because this routine is 693 * called from an interrupt context. This is all right since we 694 * are almost suspended anyway. 695 */ 696 bool 697 uhci_resume(device_t dv, const pmf_qual_t *qual) 698 { 699 uhci_softc_t *sc = device_private(dv); 700 int cmd; 701 702 mutex_spin_enter(&sc->sc_intr_lock); 703 704 cmd = UREAD2(sc, UHCI_CMD); 705 sc->sc_bus.use_polling++; 706 UWRITE2(sc, UHCI_INTR, 0); 707 uhci_globalreset(sc); 708 uhci_reset(sc); 709 if (cmd & UHCI_CMD_RS) 710 uhci_run(sc, 0, 1); 711 712 /* restore saved state */ 713 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 714 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 715 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 716 717 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 718 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 719 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 720 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 721 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 722 UHCICMD(sc, UHCI_CMD_MAXP); 723 uhci_run(sc, 1, 1); /* and start traffic again */ 724 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 725 sc->sc_bus.use_polling--; 726 if (sc->sc_intr_xfer != NULL) 727 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 728 sc->sc_intr_xfer); 729 #ifdef UHCI_DEBUG 730 if (uhcidebug > 2) 731 uhci_dumpregs(sc); 732 #endif 733 734 sc->sc_suspend = PWR_RESUME; 735 mutex_spin_exit(&sc->sc_intr_lock); 736 737 return true; 738 } 739 740 bool 741 uhci_suspend(device_t dv, const pmf_qual_t *qual) 742 { 743 uhci_softc_t *sc = device_private(dv); 744 int cmd; 745 746 mutex_spin_enter(&sc->sc_intr_lock); 747 748 cmd = UREAD2(sc, UHCI_CMD); 749 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 if (sc->sc_intr_xfer != NULL) 755 callout_stop(&sc->sc_poll_handle); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0, 1); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 770 sc->sc_bus.use_polling--; 771 772 mutex_spin_exit(&sc->sc_intr_lock); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 u_char *p; 995 996 DPRINTFN(20, ("uhci_poll_hub\n")); 997 998 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 999 return; /* device has detached */ 1000 sc = pipe->device->bus->hci_private; 1001 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1002 1003 p = KERNADDR(&xfer->dmabuf, 0); 1004 p[0] = 0; 1005 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1006 p[0] |= 1<<1; 1007 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1008 p[0] |= 1<<2; 1009 if (p[0] == 0) 1010 /* No change, try again in a while */ 1011 return; 1012 1013 xfer->actlen = 1; 1014 xfer->status = USBD_NORMAL_COMPLETION; 1015 mutex_enter(&sc->sc_lock); 1016 usb_transfer_complete(xfer); 1017 mutex_exit(&sc->sc_lock); 1018 } 1019 1020 void 1021 uhci_root_intr_done(usbd_xfer_handle xfer) 1022 { 1023 } 1024 1025 void 1026 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1027 { 1028 } 1029 1030 /* 1031 * Let the last QH loop back to the high speed control transfer QH. 1032 * This is what intel calls "bandwidth reclamation" and improves 1033 * USB performance a lot for some devices. 1034 * If we are already looping, just count it. 1035 */ 1036 void 1037 uhci_add_loop(uhci_softc_t *sc) { 1038 #ifdef UHCI_DEBUG 1039 if (uhcinoloop) 1040 return; 1041 #endif 1042 if (++sc->sc_loops == 1) { 1043 DPRINTFN(5,("uhci_start_loop: add\n")); 1044 /* Note, we don't loop back the soft pointer. */ 1045 sc->sc_last_qh->qh.qh_hlink = 1046 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1047 usb_syncmem(&sc->sc_last_qh->dma, 1048 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1049 sizeof(sc->sc_last_qh->qh.qh_hlink), 1050 BUS_DMASYNC_PREWRITE); 1051 } 1052 } 1053 1054 void 1055 uhci_rem_loop(uhci_softc_t *sc) { 1056 #ifdef UHCI_DEBUG 1057 if (uhcinoloop) 1058 return; 1059 #endif 1060 if (--sc->sc_loops == 0) { 1061 DPRINTFN(5,("uhci_end_loop: remove\n")); 1062 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1063 usb_syncmem(&sc->sc_last_qh->dma, 1064 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1065 sizeof(sc->sc_last_qh->qh.qh_hlink), 1066 BUS_DMASYNC_PREWRITE); 1067 } 1068 } 1069 1070 /* Add high speed control QH, called with lock held. */ 1071 void 1072 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1073 { 1074 uhci_soft_qh_t *eqh; 1075 1076 KASSERT(mutex_owned(&sc->sc_lock)); 1077 1078 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1079 eqh = sc->sc_hctl_end; 1080 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1081 sizeof(eqh->qh.qh_hlink), 1082 BUS_DMASYNC_POSTWRITE); 1083 sqh->hlink = eqh->hlink; 1084 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1085 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1086 BUS_DMASYNC_PREWRITE); 1087 eqh->hlink = sqh; 1088 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1089 sc->sc_hctl_end = sqh; 1090 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1091 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1092 #ifdef UHCI_CTL_LOOP 1093 uhci_add_loop(sc); 1094 #endif 1095 } 1096 1097 /* Remove high speed control QH, called with lock held. */ 1098 void 1099 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1100 { 1101 uhci_soft_qh_t *pqh; 1102 uint32_t elink; 1103 1104 KASSERT(mutex_owned(&sc->sc_lock)); 1105 1106 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1107 #ifdef UHCI_CTL_LOOP 1108 uhci_rem_loop(sc); 1109 #endif 1110 /* 1111 * The T bit should be set in the elink of the QH so that the HC 1112 * doesn't follow the pointer. This condition may fail if the 1113 * the transferred packet was short so that the QH still points 1114 * at the last used TD. 1115 * In this case we set the T bit and wait a little for the HC 1116 * to stop looking at the TD. 1117 * Note that if the TD chain is large enough, the controller 1118 * may still be looking at the chain at the end of this function. 1119 * uhci_free_std_chain() will make sure the controller stops 1120 * looking at it quickly, but until then we should not change 1121 * sqh->hlink. 1122 */ 1123 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1124 sizeof(sqh->qh.qh_elink), 1125 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1126 elink = le32toh(sqh->qh.qh_elink); 1127 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1128 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1129 if (!(elink & UHCI_PTR_T)) { 1130 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1131 usb_syncmem(&sqh->dma, 1132 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), 1134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1135 delay(UHCI_QH_REMOVE_DELAY); 1136 } 1137 1138 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1140 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1141 pqh->hlink = sqh->hlink; 1142 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1143 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1144 sizeof(pqh->qh.qh_hlink), 1145 BUS_DMASYNC_PREWRITE); 1146 delay(UHCI_QH_REMOVE_DELAY); 1147 if (sc->sc_hctl_end == sqh) 1148 sc->sc_hctl_end = pqh; 1149 } 1150 1151 /* Add low speed control QH, called with lock held. */ 1152 void 1153 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1154 { 1155 uhci_soft_qh_t *eqh; 1156 1157 KASSERT(mutex_owned(&sc->sc_lock)); 1158 1159 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1160 eqh = sc->sc_lctl_end; 1161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1162 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1163 sqh->hlink = eqh->hlink; 1164 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1165 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1166 BUS_DMASYNC_PREWRITE); 1167 eqh->hlink = sqh; 1168 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1169 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1170 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1171 sc->sc_lctl_end = sqh; 1172 } 1173 1174 /* Remove low speed control QH, called with lock held. */ 1175 void 1176 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1177 { 1178 uhci_soft_qh_t *pqh; 1179 uint32_t elink; 1180 1181 KASSERT(mutex_owned(&sc->sc_lock)); 1182 1183 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1184 /* See comment in uhci_remove_hs_ctrl() */ 1185 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1186 sizeof(sqh->qh.qh_elink), 1187 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1188 elink = le32toh(sqh->qh.qh_elink); 1189 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1190 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1191 if (!(elink & UHCI_PTR_T)) { 1192 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1193 usb_syncmem(&sqh->dma, 1194 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1197 delay(UHCI_QH_REMOVE_DELAY); 1198 } 1199 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1201 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1202 pqh->hlink = sqh->hlink; 1203 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1204 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1205 sizeof(pqh->qh.qh_hlink), 1206 BUS_DMASYNC_PREWRITE); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 if (sc->sc_lctl_end == sqh) 1209 sc->sc_lctl_end = pqh; 1210 } 1211 1212 /* Add bulk QH, called with lock held. */ 1213 void 1214 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *eqh; 1217 1218 KASSERT(mutex_owned(&sc->sc_lock)); 1219 1220 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1221 eqh = sc->sc_bulk_end; 1222 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1223 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1224 sqh->hlink = eqh->hlink; 1225 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1226 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1227 BUS_DMASYNC_PREWRITE); 1228 eqh->hlink = sqh; 1229 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1230 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1231 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1232 sc->sc_bulk_end = sqh; 1233 uhci_add_loop(sc); 1234 } 1235 1236 /* Remove bulk QH, called with lock held. */ 1237 void 1238 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1239 { 1240 uhci_soft_qh_t *pqh; 1241 1242 KASSERT(mutex_owned(&sc->sc_lock)); 1243 1244 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1245 uhci_rem_loop(sc); 1246 /* See comment in uhci_remove_hs_ctrl() */ 1247 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1248 sizeof(sqh->qh.qh_elink), 1249 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1250 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1251 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1252 usb_syncmem(&sqh->dma, 1253 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1254 sizeof(sqh->qh.qh_elink), 1255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1256 delay(UHCI_QH_REMOVE_DELAY); 1257 } 1258 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1259 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1260 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1261 pqh->hlink = sqh->hlink; 1262 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1263 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1264 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1265 delay(UHCI_QH_REMOVE_DELAY); 1266 if (sc->sc_bulk_end == sqh) 1267 sc->sc_bulk_end = pqh; 1268 } 1269 1270 Static int uhci_intr1(uhci_softc_t *); 1271 1272 int 1273 uhci_intr(void *arg) 1274 { 1275 uhci_softc_t *sc = arg; 1276 int ret = 0; 1277 1278 mutex_spin_enter(&sc->sc_intr_lock); 1279 1280 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1281 goto done; 1282 1283 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1284 #ifdef DIAGNOSTIC 1285 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1286 #endif 1287 goto done; 1288 } 1289 1290 ret = uhci_intr1(sc); 1291 1292 done: 1293 mutex_spin_exit(&sc->sc_intr_lock); 1294 return ret; 1295 } 1296 1297 int 1298 uhci_intr1(uhci_softc_t *sc) 1299 { 1300 int status; 1301 int ack; 1302 1303 #ifdef UHCI_DEBUG 1304 if (uhcidebug > 15) { 1305 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1306 uhci_dumpregs(sc); 1307 } 1308 #endif 1309 1310 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1311 1312 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1313 if (status == 0) /* The interrupt was not for us. */ 1314 return (0); 1315 1316 if (sc->sc_suspend != PWR_RESUME) { 1317 #ifdef DIAGNOSTIC 1318 printf("%s: interrupt while not operating ignored\n", 1319 device_xname(sc->sc_dev)); 1320 #endif 1321 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1322 return (0); 1323 } 1324 1325 ack = 0; 1326 if (status & UHCI_STS_USBINT) 1327 ack |= UHCI_STS_USBINT; 1328 if (status & UHCI_STS_USBEI) 1329 ack |= UHCI_STS_USBEI; 1330 if (status & UHCI_STS_RD) { 1331 ack |= UHCI_STS_RD; 1332 #ifdef UHCI_DEBUG 1333 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1334 #endif 1335 } 1336 if (status & UHCI_STS_HSE) { 1337 ack |= UHCI_STS_HSE; 1338 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1339 } 1340 if (status & UHCI_STS_HCPE) { 1341 ack |= UHCI_STS_HCPE; 1342 printf("%s: host controller process error\n", 1343 device_xname(sc->sc_dev)); 1344 } 1345 1346 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1347 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1348 /* no acknowledge needed */ 1349 if (!sc->sc_dying) { 1350 printf("%s: host controller halted\n", 1351 device_xname(sc->sc_dev)); 1352 #ifdef UHCI_DEBUG 1353 uhci_dump_all(sc); 1354 #endif 1355 } 1356 sc->sc_dying = 1; 1357 } 1358 1359 if (!ack) 1360 return (0); /* nothing to acknowledge */ 1361 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1362 1363 sc->sc_bus.no_intrs++; 1364 usb_schedsoftintr(&sc->sc_bus); 1365 1366 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1367 1368 return (1); 1369 } 1370 1371 void 1372 uhci_softintr(void *v) 1373 { 1374 struct usbd_bus *bus = v; 1375 uhci_softc_t *sc = bus->hci_private; 1376 uhci_intr_info_t *ii, *nextii; 1377 1378 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1379 1380 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1381 1382 /* 1383 * Interrupts on UHCI really suck. When the host controller 1384 * interrupts because a transfer is completed there is no 1385 * way of knowing which transfer it was. You can scan down 1386 * the TDs and QHs of the previous frame to limit the search, 1387 * but that assumes that the interrupt was not delayed by more 1388 * than 1 ms, which may not always be true (e.g. after debug 1389 * output on a slow console). 1390 * We scan all interrupt descriptors to see if any have 1391 * completed. 1392 */ 1393 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1394 nextii = LIST_NEXT(ii, list); 1395 uhci_check_intr(sc, ii); 1396 } 1397 1398 if (sc->sc_softwake) { 1399 sc->sc_softwake = 0; 1400 cv_broadcast(&sc->sc_softwake_cv); 1401 } 1402 } 1403 1404 /* Check for an interrupt. */ 1405 void 1406 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1407 { 1408 uhci_soft_td_t *std, *lstd; 1409 u_int32_t status; 1410 1411 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1412 #ifdef DIAGNOSTIC 1413 if (ii == NULL) { 1414 printf("uhci_check_intr: no ii? %p\n", ii); 1415 return; 1416 } 1417 #endif 1418 if (ii->xfer->status == USBD_CANCELLED || 1419 ii->xfer->status == USBD_TIMEOUT) { 1420 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1421 return; 1422 } 1423 1424 if (ii->stdstart == NULL) 1425 return; 1426 lstd = ii->stdend; 1427 #ifdef DIAGNOSTIC 1428 if (lstd == NULL) { 1429 printf("uhci_check_intr: std==0\n"); 1430 return; 1431 } 1432 #endif 1433 usb_syncmem(&lstd->dma, 1434 lstd->offs + offsetof(uhci_td_t, td_status), 1435 sizeof(lstd->td.td_status), 1436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1437 status = le32toh(lstd->td.td_status); 1438 usb_syncmem(&lstd->dma, 1439 lstd->offs + offsetof(uhci_td_t, td_status), 1440 sizeof(lstd->td.td_status), 1441 BUS_DMASYNC_PREREAD); 1442 1443 /* If the last TD is not marked active we can complete */ 1444 if (!(status & UHCI_TD_ACTIVE)) { 1445 done: 1446 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1447 callout_stop(&ii->xfer->timeout_handle); 1448 uhci_idone(ii); 1449 return; 1450 } 1451 1452 /* 1453 * If the last TD is still active we need to check whether there 1454 * is an error somewhere in the middle, or whether there was a 1455 * short packet (SPD and not ACTIVE). 1456 */ 1457 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1458 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1459 usb_syncmem(&std->dma, 1460 std->offs + offsetof(uhci_td_t, td_status), 1461 sizeof(std->td.td_status), 1462 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1463 status = le32toh(std->td.td_status); 1464 usb_syncmem(&std->dma, 1465 std->offs + offsetof(uhci_td_t, td_status), 1466 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1467 1468 /* If there's an active TD the xfer isn't done. */ 1469 if (status & UHCI_TD_ACTIVE) { 1470 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1471 __func__, ii, std)); 1472 return; 1473 } 1474 1475 /* Any kind of error makes the xfer done. */ 1476 if (status & UHCI_TD_STALLED) 1477 goto done; 1478 1479 /* 1480 * If the data phase of a control transfer is short, we need 1481 * to complete the status stage 1482 */ 1483 usbd_xfer_handle xfer = ii->xfer; 1484 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1485 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1486 1487 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1488 struct uhci_pipe *upipe = 1489 (struct uhci_pipe *)xfer->pipe; 1490 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1491 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1492 1493 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1494 "phase needs completion\n", __func__, ii, 1495 ii->stdstart)); 1496 1497 sqh->qh.qh_elink = 1498 htole32(stat->physaddr | UHCI_PTR_TD); 1499 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1500 BUS_DMASYNC_PREWRITE); 1501 break; 1502 } 1503 1504 /* We want short packets, and it is short: it's done */ 1505 usb_syncmem(&std->dma, 1506 std->offs + offsetof(uhci_td_t, td_token), 1507 sizeof(std->td.td_token), 1508 BUS_DMASYNC_POSTWRITE); 1509 1510 if ((status & UHCI_TD_SPD) && 1511 UHCI_TD_GET_ACTLEN(status) < 1512 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1513 goto done; 1514 } 1515 } 1516 } 1517 1518 /* Called with USB lock held. */ 1519 void 1520 uhci_idone(uhci_intr_info_t *ii) 1521 { 1522 usbd_xfer_handle xfer = ii->xfer; 1523 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1524 #ifdef DIAGNOSTIC 1525 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1526 #endif 1527 uhci_soft_td_t *std; 1528 u_int32_t status = 0, nstatus; 1529 int actlen; 1530 1531 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1532 1533 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1534 #ifdef DIAGNOSTIC 1535 { 1536 /* XXX SMP? */ 1537 int s = splhigh(); 1538 if (ii->isdone) { 1539 splx(s); 1540 #ifdef UHCI_DEBUG 1541 printf("uhci_idone: ii is done!\n "); 1542 uhci_dump_ii(ii); 1543 #else 1544 printf("uhci_idone: ii=%p is done!\n", ii); 1545 #endif 1546 return; 1547 } 1548 ii->isdone = 1; 1549 splx(s); 1550 } 1551 #endif 1552 1553 if (xfer->nframes != 0) { 1554 /* Isoc transfer, do things differently. */ 1555 uhci_soft_td_t **stds = upipe->u.iso.stds; 1556 int i, n, nframes, len; 1557 1558 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1559 1560 nframes = xfer->nframes; 1561 actlen = 0; 1562 n = UXFER(xfer)->curframe; 1563 for (i = 0; i < nframes; i++) { 1564 std = stds[n]; 1565 #ifdef UHCI_DEBUG 1566 if (uhcidebug > 5) { 1567 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1568 uhci_dump_td(std); 1569 } 1570 #endif 1571 if (++n >= UHCI_VFRAMELIST_COUNT) 1572 n = 0; 1573 usb_syncmem(&std->dma, 1574 std->offs + offsetof(uhci_td_t, td_status), 1575 sizeof(std->td.td_status), 1576 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1577 status = le32toh(std->td.td_status); 1578 len = UHCI_TD_GET_ACTLEN(status); 1579 xfer->frlengths[i] = len; 1580 actlen += len; 1581 } 1582 upipe->u.iso.inuse -= nframes; 1583 xfer->actlen = actlen; 1584 xfer->status = USBD_NORMAL_COMPLETION; 1585 goto end; 1586 } 1587 1588 #ifdef UHCI_DEBUG 1589 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1590 ii, xfer, upipe)); 1591 if (uhcidebug > 10) 1592 uhci_dump_tds(ii->stdstart); 1593 #endif 1594 1595 /* The transfer is done, compute actual length and status. */ 1596 actlen = 0; 1597 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1598 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1599 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1600 nstatus = le32toh(std->td.td_status); 1601 if (nstatus & UHCI_TD_ACTIVE) 1602 break; 1603 1604 status = nstatus; 1605 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1606 UHCI_TD_PID_SETUP) 1607 actlen += UHCI_TD_GET_ACTLEN(status); 1608 else { 1609 /* 1610 * UHCI will report CRCTO in addition to a STALL or NAK 1611 * for a SETUP transaction. See section 3.2.2, "TD 1612 * CONTROL AND STATUS". 1613 */ 1614 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1615 status &= ~UHCI_TD_CRCTO; 1616 } 1617 } 1618 /* If there are left over TDs we need to update the toggle. */ 1619 if (std != NULL) 1620 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1621 1622 status &= UHCI_TD_ERROR; 1623 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1624 actlen, status)); 1625 xfer->actlen = actlen; 1626 if (status != 0) { 1627 #ifdef UHCI_DEBUG 1628 char sbuf[128]; 1629 1630 snprintb(sbuf, sizeof(sbuf), 1631 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1632 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1633 1634 DPRINTFN((status == UHCI_TD_STALLED)*10, 1635 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1636 "status 0x%s\n", 1637 xfer->pipe->device->address, 1638 xfer->pipe->endpoint->edesc->bEndpointAddress, 1639 sbuf)); 1640 #endif 1641 1642 if (status == UHCI_TD_STALLED) 1643 xfer->status = USBD_STALLED; 1644 else 1645 xfer->status = USBD_IOERROR; /* more info XXX */ 1646 } else { 1647 xfer->status = USBD_NORMAL_COMPLETION; 1648 } 1649 1650 end: 1651 usb_transfer_complete(xfer); 1652 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1653 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1654 } 1655 1656 /* 1657 * Called when a request does not complete. 1658 */ 1659 void 1660 uhci_timeout(void *addr) 1661 { 1662 uhci_intr_info_t *ii = addr; 1663 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1664 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1665 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1666 1667 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1668 1669 if (sc->sc_dying) { 1670 mutex_enter(&sc->sc_lock); 1671 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1672 mutex_exit(&sc->sc_lock); 1673 return; 1674 } 1675 1676 /* Execute the abort in a process context. */ 1677 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1678 USB_TASKQ_MPSAFE); 1679 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1680 USB_TASKQ_HC); 1681 } 1682 1683 void 1684 uhci_timeout_task(void *addr) 1685 { 1686 usbd_xfer_handle xfer = addr; 1687 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1688 1689 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1690 1691 mutex_enter(&sc->sc_lock); 1692 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1693 mutex_exit(&sc->sc_lock); 1694 } 1695 1696 /* 1697 * Wait here until controller claims to have an interrupt. 1698 * Then call uhci_intr and return. Use timeout to avoid waiting 1699 * too long. 1700 * Only used during boot when interrupts are not enabled yet. 1701 */ 1702 void 1703 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1704 { 1705 int timo = xfer->timeout; 1706 uhci_intr_info_t *ii; 1707 1708 mutex_enter(&sc->sc_lock); 1709 1710 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1711 1712 xfer->status = USBD_IN_PROGRESS; 1713 for (; timo >= 0; timo--) { 1714 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1715 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1716 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1717 mutex_spin_enter(&sc->sc_intr_lock); 1718 uhci_intr1(sc); 1719 mutex_spin_exit(&sc->sc_intr_lock); 1720 if (xfer->status != USBD_IN_PROGRESS) 1721 goto done; 1722 } 1723 } 1724 1725 /* Timeout */ 1726 DPRINTF(("uhci_waitintr: timeout\n")); 1727 for (ii = LIST_FIRST(&sc->sc_intrhead); 1728 ii != NULL && ii->xfer != xfer; 1729 ii = LIST_NEXT(ii, list)) 1730 ; 1731 #ifdef DIAGNOSTIC 1732 if (ii == NULL) 1733 panic("uhci_waitintr: lost intr_info"); 1734 #endif 1735 uhci_idone(ii); 1736 1737 done: 1738 mutex_exit(&sc->sc_lock); 1739 } 1740 1741 void 1742 uhci_poll(struct usbd_bus *bus) 1743 { 1744 uhci_softc_t *sc = bus->hci_private; 1745 1746 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1747 mutex_spin_enter(&sc->sc_intr_lock); 1748 uhci_intr1(sc); 1749 mutex_spin_exit(&sc->sc_intr_lock); 1750 } 1751 } 1752 1753 void 1754 uhci_reset(uhci_softc_t *sc) 1755 { 1756 int n; 1757 1758 UHCICMD(sc, UHCI_CMD_HCRESET); 1759 /* The reset bit goes low when the controller is done. */ 1760 for (n = 0; n < UHCI_RESET_TIMEOUT && 1761 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1762 usb_delay_ms(&sc->sc_bus, 1); 1763 if (n >= UHCI_RESET_TIMEOUT) 1764 printf("%s: controller did not reset\n", 1765 device_xname(sc->sc_dev)); 1766 } 1767 1768 usbd_status 1769 uhci_run(uhci_softc_t *sc, int run, int locked) 1770 { 1771 int n, running; 1772 u_int16_t cmd; 1773 1774 run = run != 0; 1775 if (!locked) 1776 mutex_spin_enter(&sc->sc_intr_lock); 1777 DPRINTF(("uhci_run: setting run=%d\n", run)); 1778 cmd = UREAD2(sc, UHCI_CMD); 1779 if (run) 1780 cmd |= UHCI_CMD_RS; 1781 else 1782 cmd &= ~UHCI_CMD_RS; 1783 UHCICMD(sc, cmd); 1784 for(n = 0; n < 10; n++) { 1785 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1786 /* return when we've entered the state we want */ 1787 if (run == running) { 1788 if (!locked) 1789 mutex_spin_exit(&sc->sc_intr_lock); 1790 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1791 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1792 return (USBD_NORMAL_COMPLETION); 1793 } 1794 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1795 } 1796 if (!locked) 1797 mutex_spin_exit(&sc->sc_intr_lock); 1798 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1799 run ? "start" : "stop"); 1800 return (USBD_IOERROR); 1801 } 1802 1803 /* 1804 * Memory management routines. 1805 * uhci_alloc_std allocates TDs 1806 * uhci_alloc_sqh allocates QHs 1807 * These two routines do their own free list management, 1808 * partly for speed, partly because allocating DMAable memory 1809 * has page size granularaity so much memory would be wasted if 1810 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1811 */ 1812 1813 uhci_soft_td_t * 1814 uhci_alloc_std(uhci_softc_t *sc) 1815 { 1816 uhci_soft_td_t *std; 1817 usbd_status err; 1818 int i, offs; 1819 usb_dma_t dma; 1820 1821 if (sc->sc_freetds == NULL) { 1822 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1823 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1824 UHCI_TD_ALIGN, &dma); 1825 if (err) 1826 return (0); 1827 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1828 offs = i * UHCI_STD_SIZE; 1829 std = KERNADDR(&dma, offs); 1830 std->physaddr = DMAADDR(&dma, offs); 1831 std->dma = dma; 1832 std->offs = offs; 1833 std->link.std = sc->sc_freetds; 1834 sc->sc_freetds = std; 1835 } 1836 } 1837 std = sc->sc_freetds; 1838 sc->sc_freetds = std->link.std; 1839 memset(&std->td, 0, sizeof(uhci_td_t)); 1840 return std; 1841 } 1842 1843 void 1844 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1845 { 1846 #ifdef DIAGNOSTIC 1847 #define TD_IS_FREE 0x12345678 1848 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1849 printf("uhci_free_std: freeing free TD %p\n", std); 1850 return; 1851 } 1852 std->td.td_token = htole32(TD_IS_FREE); 1853 #endif 1854 std->link.std = sc->sc_freetds; 1855 sc->sc_freetds = std; 1856 } 1857 1858 uhci_soft_qh_t * 1859 uhci_alloc_sqh(uhci_softc_t *sc) 1860 { 1861 uhci_soft_qh_t *sqh; 1862 usbd_status err; 1863 int i, offs; 1864 usb_dma_t dma; 1865 1866 if (sc->sc_freeqhs == NULL) { 1867 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1868 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1869 UHCI_QH_ALIGN, &dma); 1870 if (err) 1871 return (0); 1872 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1873 offs = i * UHCI_SQH_SIZE; 1874 sqh = KERNADDR(&dma, offs); 1875 sqh->physaddr = DMAADDR(&dma, offs); 1876 sqh->dma = dma; 1877 sqh->offs = offs; 1878 sqh->hlink = sc->sc_freeqhs; 1879 sc->sc_freeqhs = sqh; 1880 } 1881 } 1882 sqh = sc->sc_freeqhs; 1883 sc->sc_freeqhs = sqh->hlink; 1884 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1885 return (sqh); 1886 } 1887 1888 void 1889 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1890 { 1891 sqh->hlink = sc->sc_freeqhs; 1892 sc->sc_freeqhs = sqh; 1893 } 1894 1895 void 1896 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1897 uhci_soft_td_t *stdend) 1898 { 1899 uhci_soft_td_t *p; 1900 uint32_t td_link; 1901 1902 /* 1903 * to avoid race condition with the controller which may be looking 1904 * at this chain, we need to first invalidate all links, and 1905 * then wait for the controller to move to another queue 1906 */ 1907 for (p = std; p != stdend; p = p->link.std) { 1908 usb_syncmem(&p->dma, 1909 p->offs + offsetof(uhci_td_t, td_link), 1910 sizeof(p->td.td_link), 1911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1912 td_link = le32toh(p->td.td_link); 1913 usb_syncmem(&p->dma, 1914 p->offs + offsetof(uhci_td_t, td_link), 1915 sizeof(p->td.td_link), 1916 BUS_DMASYNC_PREREAD); 1917 if ((td_link & UHCI_PTR_T) == 0) { 1918 p->td.td_link = htole32(UHCI_PTR_T); 1919 usb_syncmem(&p->dma, 1920 p->offs + offsetof(uhci_td_t, td_link), 1921 sizeof(p->td.td_link), 1922 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1923 } 1924 } 1925 delay(UHCI_QH_REMOVE_DELAY); 1926 1927 for (; std != stdend; std = p) { 1928 p = std->link.std; 1929 uhci_free_std(sc, std); 1930 } 1931 } 1932 1933 usbd_status 1934 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1935 int rd, u_int16_t flags, usb_dma_t *dma, 1936 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1937 { 1938 uhci_soft_td_t *p, *lastp; 1939 uhci_physaddr_t lastlink; 1940 int i, ntd, l, tog, maxp; 1941 u_int32_t status; 1942 int addr = upipe->pipe.device->address; 1943 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1944 1945 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1946 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1947 upipe->pipe.device->speed, flags)); 1948 1949 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1950 1951 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1952 if (maxp == 0) { 1953 printf("uhci_alloc_std_chain: maxp=0\n"); 1954 return (USBD_INVAL); 1955 } 1956 ntd = (len + maxp - 1) / maxp; 1957 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1958 ntd++; 1959 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1960 if (ntd == 0) { 1961 *sp = *ep = 0; 1962 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1963 return (USBD_NORMAL_COMPLETION); 1964 } 1965 tog = upipe->nexttoggle; 1966 if (ntd % 2 == 0) 1967 tog ^= 1; 1968 upipe->nexttoggle = tog ^ 1; 1969 lastp = NULL; 1970 lastlink = UHCI_PTR_T; 1971 ntd--; 1972 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1973 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1974 status |= UHCI_TD_LS; 1975 if (flags & USBD_SHORT_XFER_OK) 1976 status |= UHCI_TD_SPD; 1977 usb_syncmem(dma, 0, len, 1978 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1979 for (i = ntd; i >= 0; i--) { 1980 p = uhci_alloc_std(sc); 1981 if (p == NULL) { 1982 KASSERT(lastp != NULL); 1983 uhci_free_std_chain(sc, lastp, NULL); 1984 return (USBD_NOMEM); 1985 } 1986 p->link.std = lastp; 1987 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1988 lastp = p; 1989 lastlink = p->physaddr; 1990 p->td.td_status = htole32(status); 1991 if (i == ntd) { 1992 /* last TD */ 1993 l = len % maxp; 1994 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1995 l = maxp; 1996 *ep = p; 1997 } else 1998 l = maxp; 1999 p->td.td_token = 2000 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 2001 UHCI_TD_OUT(l, endpt, addr, tog)); 2002 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2003 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 2004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005 tog ^= 1; 2006 } 2007 *sp = lastp; 2008 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 2009 upipe->nexttoggle)); 2010 return (USBD_NORMAL_COMPLETION); 2011 } 2012 2013 void 2014 uhci_device_clear_toggle(usbd_pipe_handle pipe) 2015 { 2016 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2017 upipe->nexttoggle = 0; 2018 } 2019 2020 void 2021 uhci_noop(usbd_pipe_handle pipe) 2022 { 2023 } 2024 2025 usbd_status 2026 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2027 { 2028 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2029 usbd_status err; 2030 2031 /* Insert last in queue. */ 2032 mutex_enter(&sc->sc_lock); 2033 err = usb_insert_transfer(xfer); 2034 mutex_exit(&sc->sc_lock); 2035 if (err) 2036 return (err); 2037 2038 /* 2039 * Pipe isn't running (otherwise err would be USBD_INPROG), 2040 * so start it first. 2041 */ 2042 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2043 } 2044 2045 usbd_status 2046 uhci_device_bulk_start(usbd_xfer_handle xfer) 2047 { 2048 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2049 usbd_device_handle dev = upipe->pipe.device; 2050 uhci_softc_t *sc = dev->bus->hci_private; 2051 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2052 uhci_soft_td_t *data, *dataend; 2053 uhci_soft_qh_t *sqh; 2054 usbd_status err; 2055 int len, isread, endpt; 2056 2057 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2058 xfer, xfer->length, xfer->flags, ii)); 2059 2060 if (sc->sc_dying) 2061 return (USBD_IOERROR); 2062 2063 #ifdef DIAGNOSTIC 2064 if (xfer->rqflags & URQ_REQUEST) 2065 panic("uhci_device_bulk_transfer: a request"); 2066 #endif 2067 2068 mutex_enter(&sc->sc_lock); 2069 2070 len = xfer->length; 2071 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2072 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2073 sqh = upipe->u.bulk.sqh; 2074 2075 upipe->u.bulk.isread = isread; 2076 upipe->u.bulk.length = len; 2077 2078 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2079 &xfer->dmabuf, &data, &dataend); 2080 if (err) { 2081 mutex_exit(&sc->sc_lock); 2082 return (err); 2083 } 2084 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2085 usb_syncmem(&dataend->dma, 2086 dataend->offs + offsetof(uhci_td_t, td_status), 2087 sizeof(dataend->td.td_status), 2088 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2089 2090 2091 #ifdef UHCI_DEBUG 2092 if (uhcidebug > 8) { 2093 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2094 uhci_dump_tds(data); 2095 } 2096 #endif 2097 2098 /* Set up interrupt info. */ 2099 ii->xfer = xfer; 2100 ii->stdstart = data; 2101 ii->stdend = dataend; 2102 #ifdef DIAGNOSTIC 2103 if (!ii->isdone) { 2104 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2105 } 2106 ii->isdone = 0; 2107 #endif 2108 2109 sqh->elink = data; 2110 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2111 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2112 2113 uhci_add_bulk(sc, sqh); 2114 uhci_add_intr_info(sc, ii); 2115 2116 if (xfer->timeout && !sc->sc_bus.use_polling) { 2117 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2118 uhci_timeout, ii); 2119 } 2120 xfer->status = USBD_IN_PROGRESS; 2121 2122 #ifdef UHCI_DEBUG 2123 if (uhcidebug > 10) { 2124 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2125 uhci_dump_tds(data); 2126 } 2127 #endif 2128 2129 if (sc->sc_bus.use_polling) 2130 uhci_waitintr(sc, xfer); 2131 2132 mutex_exit(&sc->sc_lock); 2133 return (USBD_IN_PROGRESS); 2134 } 2135 2136 /* Abort a device bulk request. */ 2137 void 2138 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2139 { 2140 #ifdef DIAGNOSTIC 2141 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2142 #endif 2143 2144 KASSERT(mutex_owned(&sc->sc_lock)); 2145 2146 DPRINTF(("uhci_device_bulk_abort:\n")); 2147 uhci_abort_xfer(xfer, USBD_CANCELLED); 2148 } 2149 2150 /* 2151 * Abort a device request. 2152 * If this routine is called at splusb() it guarantees that the request 2153 * will be removed from the hardware scheduling and that the callback 2154 * for it will be called with USBD_CANCELLED status. 2155 * It's impossible to guarantee that the requested transfer will not 2156 * have happened since the hardware runs concurrently. 2157 * If the transaction has already happened we rely on the ordinary 2158 * interrupt processing to process it. 2159 * XXX This is most probably wrong. 2160 * XXXMRG this doesn't make sense anymore. 2161 */ 2162 void 2163 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2164 { 2165 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2166 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2167 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2168 uhci_soft_td_t *std; 2169 int wake; 2170 2171 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2172 2173 KASSERT(mutex_owned(&sc->sc_lock)); 2174 2175 if (sc->sc_dying) { 2176 /* If we're dying, just do the software part. */ 2177 xfer->status = status; /* make software ignore it */ 2178 callout_stop(&xfer->timeout_handle); 2179 usb_transfer_complete(xfer); 2180 return; 2181 } 2182 2183 if (cpu_intr_p() || cpu_softintr_p()) 2184 panic("uhci_abort_xfer: not in process context"); 2185 2186 /* 2187 * If an abort is already in progress then just wait for it to 2188 * complete and return. 2189 */ 2190 if (xfer->hcflags & UXFER_ABORTING) { 2191 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2192 #ifdef DIAGNOSTIC 2193 if (status == USBD_TIMEOUT) 2194 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2195 #endif 2196 /* Override the status which might be USBD_TIMEOUT. */ 2197 xfer->status = status; 2198 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2199 xfer->hcflags |= UXFER_ABORTWAIT; 2200 while (xfer->hcflags & UXFER_ABORTING) 2201 cv_wait(&xfer->hccv, &sc->sc_lock); 2202 goto done; 2203 } 2204 xfer->hcflags |= UXFER_ABORTING; 2205 2206 /* 2207 * Step 1: Make interrupt routine and hardware ignore xfer. 2208 */ 2209 xfer->status = status; /* make software ignore it */ 2210 callout_stop(&xfer->timeout_handle); 2211 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2212 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2213 usb_syncmem(&std->dma, 2214 std->offs + offsetof(uhci_td_t, td_status), 2215 sizeof(std->td.td_status), 2216 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2217 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2218 usb_syncmem(&std->dma, 2219 std->offs + offsetof(uhci_td_t, td_status), 2220 sizeof(std->td.td_status), 2221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2222 } 2223 2224 /* 2225 * Step 2: Wait until we know hardware has finished any possible 2226 * use of the xfer. Also make sure the soft interrupt routine 2227 * has run. 2228 */ 2229 /* Hardware finishes in 1ms */ 2230 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2231 sc->sc_softwake = 1; 2232 usb_schedsoftintr(&sc->sc_bus); 2233 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2234 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2235 2236 /* 2237 * Step 3: Execute callback. 2238 */ 2239 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2240 #ifdef DIAGNOSTIC 2241 ii->isdone = 1; 2242 #endif 2243 wake = xfer->hcflags & UXFER_ABORTWAIT; 2244 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2245 usb_transfer_complete(xfer); 2246 if (wake) 2247 cv_broadcast(&xfer->hccv); 2248 done: 2249 KASSERT(mutex_owned(&sc->sc_lock)); 2250 } 2251 2252 /* Close a device bulk pipe. */ 2253 void 2254 uhci_device_bulk_close(usbd_pipe_handle pipe) 2255 { 2256 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2257 usbd_device_handle dev = upipe->pipe.device; 2258 uhci_softc_t *sc = dev->bus->hci_private; 2259 2260 KASSERT(mutex_owned(&sc->sc_lock)); 2261 2262 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2263 2264 pipe->endpoint->datatoggle = upipe->nexttoggle; 2265 } 2266 2267 usbd_status 2268 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2269 { 2270 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2271 usbd_status err; 2272 2273 /* Insert last in queue. */ 2274 mutex_enter(&sc->sc_lock); 2275 err = usb_insert_transfer(xfer); 2276 mutex_exit(&sc->sc_lock); 2277 if (err) 2278 return (err); 2279 2280 /* 2281 * Pipe isn't running (otherwise err would be USBD_INPROG), 2282 * so start it first. 2283 */ 2284 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2285 } 2286 2287 usbd_status 2288 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2289 { 2290 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2291 usbd_status err; 2292 2293 if (sc->sc_dying) 2294 return (USBD_IOERROR); 2295 2296 #ifdef DIAGNOSTIC 2297 if (!(xfer->rqflags & URQ_REQUEST)) 2298 panic("uhci_device_ctrl_transfer: not a request"); 2299 #endif 2300 2301 mutex_enter(&sc->sc_lock); 2302 err = uhci_device_request(xfer); 2303 mutex_exit(&sc->sc_lock); 2304 if (err) 2305 return (err); 2306 2307 if (sc->sc_bus.use_polling) 2308 uhci_waitintr(sc, xfer); 2309 return (USBD_IN_PROGRESS); 2310 } 2311 2312 usbd_status 2313 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2314 { 2315 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2316 usbd_status err; 2317 2318 /* Insert last in queue. */ 2319 mutex_enter(&sc->sc_lock); 2320 err = usb_insert_transfer(xfer); 2321 mutex_exit(&sc->sc_lock); 2322 if (err) 2323 return (err); 2324 2325 /* 2326 * Pipe isn't running (otherwise err would be USBD_INPROG), 2327 * so start it first. 2328 */ 2329 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2330 } 2331 2332 usbd_status 2333 uhci_device_intr_start(usbd_xfer_handle xfer) 2334 { 2335 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2336 usbd_device_handle dev = upipe->pipe.device; 2337 uhci_softc_t *sc = dev->bus->hci_private; 2338 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2339 uhci_soft_td_t *data, *dataend; 2340 uhci_soft_qh_t *sqh; 2341 usbd_status err; 2342 int isread, endpt; 2343 int i; 2344 2345 if (sc->sc_dying) 2346 return (USBD_IOERROR); 2347 2348 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2349 xfer, xfer->length, xfer->flags)); 2350 2351 #ifdef DIAGNOSTIC 2352 if (xfer->rqflags & URQ_REQUEST) 2353 panic("uhci_device_intr_transfer: a request"); 2354 #endif 2355 2356 mutex_enter(&sc->sc_lock); 2357 2358 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2359 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2360 2361 upipe->u.intr.isread = isread; 2362 2363 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2364 xfer->flags, &xfer->dmabuf, &data, 2365 &dataend); 2366 if (err) { 2367 mutex_exit(&sc->sc_lock); 2368 return (err); 2369 } 2370 2371 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2372 usb_syncmem(&dataend->dma, 2373 dataend->offs + offsetof(uhci_td_t, td_status), 2374 sizeof(dataend->td.td_status), 2375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2376 2377 #ifdef UHCI_DEBUG 2378 if (uhcidebug > 10) { 2379 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2380 uhci_dump_tds(data); 2381 uhci_dump_qh(upipe->u.intr.qhs[0]); 2382 } 2383 #endif 2384 2385 /* Set up interrupt info. */ 2386 ii->xfer = xfer; 2387 ii->stdstart = data; 2388 ii->stdend = dataend; 2389 #ifdef DIAGNOSTIC 2390 if (!ii->isdone) { 2391 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2392 } 2393 ii->isdone = 0; 2394 #endif 2395 2396 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2397 upipe->u.intr.qhs[0])); 2398 for (i = 0; i < upipe->u.intr.npoll; i++) { 2399 sqh = upipe->u.intr.qhs[i]; 2400 sqh->elink = data; 2401 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2402 usb_syncmem(&sqh->dma, 2403 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2404 sizeof(sqh->qh.qh_elink), 2405 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2406 } 2407 uhci_add_intr_info(sc, ii); 2408 xfer->status = USBD_IN_PROGRESS; 2409 mutex_exit(&sc->sc_lock); 2410 2411 #ifdef UHCI_DEBUG 2412 if (uhcidebug > 10) { 2413 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2414 uhci_dump_tds(data); 2415 uhci_dump_qh(upipe->u.intr.qhs[0]); 2416 } 2417 #endif 2418 2419 return (USBD_IN_PROGRESS); 2420 } 2421 2422 /* Abort a device control request. */ 2423 void 2424 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2425 { 2426 #ifdef DIAGNOSTIC 2427 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2428 #endif 2429 2430 KASSERT(mutex_owned(&sc->sc_lock)); 2431 2432 DPRINTF(("uhci_device_ctrl_abort:\n")); 2433 uhci_abort_xfer(xfer, USBD_CANCELLED); 2434 } 2435 2436 /* Close a device control pipe. */ 2437 void 2438 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2439 { 2440 } 2441 2442 /* Abort a device interrupt request. */ 2443 void 2444 uhci_device_intr_abort(usbd_xfer_handle xfer) 2445 { 2446 #ifdef DIAGNOSTIC 2447 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2448 #endif 2449 2450 KASSERT(mutex_owned(&sc->sc_lock)); 2451 2452 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2453 if (xfer->pipe->intrxfer == xfer) { 2454 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2455 xfer->pipe->intrxfer = NULL; 2456 } 2457 uhci_abort_xfer(xfer, USBD_CANCELLED); 2458 } 2459 2460 /* Close a device interrupt pipe. */ 2461 void 2462 uhci_device_intr_close(usbd_pipe_handle pipe) 2463 { 2464 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2465 uhci_softc_t *sc = pipe->device->bus->hci_private; 2466 int i, npoll; 2467 2468 KASSERT(mutex_owned(&sc->sc_lock)); 2469 2470 /* Unlink descriptors from controller data structures. */ 2471 npoll = upipe->u.intr.npoll; 2472 for (i = 0; i < npoll; i++) 2473 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2474 2475 /* 2476 * We now have to wait for any activity on the physical 2477 * descriptors to stop. 2478 */ 2479 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2480 2481 for(i = 0; i < npoll; i++) 2482 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2483 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2484 2485 /* XXX free other resources */ 2486 } 2487 2488 usbd_status 2489 uhci_device_request(usbd_xfer_handle xfer) 2490 { 2491 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2492 usb_device_request_t *req = &xfer->request; 2493 usbd_device_handle dev = upipe->pipe.device; 2494 uhci_softc_t *sc = dev->bus->hci_private; 2495 int addr = dev->address; 2496 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2497 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2498 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2499 uhci_soft_qh_t *sqh; 2500 int len; 2501 u_int32_t ls; 2502 usbd_status err; 2503 int isread; 2504 2505 KASSERT(mutex_owned(&sc->sc_lock)); 2506 2507 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2508 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2509 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2510 UGETW(req->wIndex), UGETW(req->wLength), 2511 addr, endpt)); 2512 2513 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2514 isread = req->bmRequestType & UT_READ; 2515 len = UGETW(req->wLength); 2516 2517 setup = upipe->u.ctl.setup; 2518 stat = upipe->u.ctl.stat; 2519 sqh = upipe->u.ctl.sqh; 2520 2521 /* Set up data transaction */ 2522 if (len != 0) { 2523 upipe->nexttoggle = 1; 2524 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2525 &xfer->dmabuf, &data, &dataend); 2526 if (err) 2527 return (err); 2528 next = data; 2529 dataend->link.std = stat; 2530 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2531 usb_syncmem(&dataend->dma, 2532 dataend->offs + offsetof(uhci_td_t, td_link), 2533 sizeof(dataend->td.td_link), 2534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2535 } else { 2536 next = stat; 2537 } 2538 upipe->u.ctl.length = len; 2539 2540 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2541 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2542 2543 setup->link.std = next; 2544 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2545 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2546 UHCI_TD_ACTIVE); 2547 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2548 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2549 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2551 2552 stat->link.std = NULL; 2553 stat->td.td_link = htole32(UHCI_PTR_T); 2554 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2555 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2556 stat->td.td_token = 2557 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2558 UHCI_TD_IN (0, endpt, addr, 1)); 2559 stat->td.td_buffer = htole32(0); 2560 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2562 2563 #ifdef UHCI_DEBUG 2564 if (uhcidebug > 10) { 2565 DPRINTF(("uhci_device_request: before transfer\n")); 2566 uhci_dump_tds(setup); 2567 } 2568 #endif 2569 2570 /* Set up interrupt info. */ 2571 ii->xfer = xfer; 2572 ii->stdstart = setup; 2573 ii->stdend = stat; 2574 #ifdef DIAGNOSTIC 2575 if (!ii->isdone) { 2576 printf("uhci_device_request: not done, ii=%p\n", ii); 2577 } 2578 ii->isdone = 0; 2579 #endif 2580 2581 sqh->elink = setup; 2582 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2583 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2584 2585 if (dev->speed == USB_SPEED_LOW) 2586 uhci_add_ls_ctrl(sc, sqh); 2587 else 2588 uhci_add_hs_ctrl(sc, sqh); 2589 uhci_add_intr_info(sc, ii); 2590 #ifdef UHCI_DEBUG 2591 if (uhcidebug > 12) { 2592 uhci_soft_td_t *std; 2593 uhci_soft_qh_t *xqh; 2594 uhci_soft_qh_t *sxqh; 2595 int maxqh = 0; 2596 uhci_physaddr_t link; 2597 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2598 for (std = sc->sc_vframes[0].htd, link = 0; 2599 (link & UHCI_PTR_QH) == 0; 2600 std = std->link.std) { 2601 link = le32toh(std->td.td_link); 2602 uhci_dump_td(std); 2603 } 2604 sxqh = (uhci_soft_qh_t *)std; 2605 uhci_dump_qh(sxqh); 2606 for (xqh = sxqh; 2607 xqh != NULL; 2608 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2609 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2610 uhci_dump_qh(xqh); 2611 } 2612 DPRINTF(("Enqueued QH:\n")); 2613 uhci_dump_qh(sqh); 2614 uhci_dump_tds(sqh->elink); 2615 } 2616 #endif 2617 if (xfer->timeout && !sc->sc_bus.use_polling) { 2618 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2619 uhci_timeout, ii); 2620 } 2621 xfer->status = USBD_IN_PROGRESS; 2622 2623 return (USBD_NORMAL_COMPLETION); 2624 } 2625 2626 usbd_status 2627 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2628 { 2629 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2630 usbd_status err; 2631 2632 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2633 2634 /* Put it on our queue, */ 2635 mutex_enter(&sc->sc_lock); 2636 err = usb_insert_transfer(xfer); 2637 mutex_exit(&sc->sc_lock); 2638 2639 /* bail out on error, */ 2640 if (err && err != USBD_IN_PROGRESS) 2641 return (err); 2642 2643 /* XXX should check inuse here */ 2644 2645 /* insert into schedule, */ 2646 uhci_device_isoc_enter(xfer); 2647 2648 /* and start if the pipe wasn't running */ 2649 if (!err) 2650 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2651 2652 return (err); 2653 } 2654 2655 void 2656 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2657 { 2658 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2659 usbd_device_handle dev = upipe->pipe.device; 2660 uhci_softc_t *sc = dev->bus->hci_private; 2661 struct iso *iso = &upipe->u.iso; 2662 uhci_soft_td_t *std; 2663 u_int32_t buf, len, status, offs; 2664 int i, next, nframes; 2665 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2666 2667 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2668 "nframes=%d\n", 2669 iso->inuse, iso->next, xfer, xfer->nframes)); 2670 2671 if (sc->sc_dying) 2672 return; 2673 2674 if (xfer->status == USBD_IN_PROGRESS) { 2675 /* This request has already been entered into the frame list */ 2676 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2677 /* XXX */ 2678 } 2679 2680 #ifdef DIAGNOSTIC 2681 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2682 printf("uhci_device_isoc_enter: overflow!\n"); 2683 #endif 2684 2685 next = iso->next; 2686 if (next == -1) { 2687 /* Not in use yet, schedule it a few frames ahead. */ 2688 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2689 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2690 } 2691 2692 xfer->status = USBD_IN_PROGRESS; 2693 UXFER(xfer)->curframe = next; 2694 2695 buf = DMAADDR(&xfer->dmabuf, 0); 2696 offs = 0; 2697 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2698 UHCI_TD_ACTIVE | 2699 UHCI_TD_IOS); 2700 nframes = xfer->nframes; 2701 mutex_enter(&sc->sc_lock); 2702 for (i = 0; i < nframes; i++) { 2703 std = iso->stds[next]; 2704 if (++next >= UHCI_VFRAMELIST_COUNT) 2705 next = 0; 2706 len = xfer->frlengths[i]; 2707 std->td.td_buffer = htole32(buf); 2708 usb_syncmem(&xfer->dmabuf, offs, len, 2709 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2710 if (i == nframes - 1) 2711 status |= UHCI_TD_IOC; 2712 std->td.td_status = htole32(status); 2713 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2714 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2715 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2716 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2717 #ifdef UHCI_DEBUG 2718 if (uhcidebug > 5) { 2719 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2720 uhci_dump_td(std); 2721 } 2722 #endif 2723 buf += len; 2724 offs += len; 2725 } 2726 iso->next = next; 2727 iso->inuse += xfer->nframes; 2728 2729 mutex_exit(&sc->sc_lock); 2730 } 2731 2732 usbd_status 2733 uhci_device_isoc_start(usbd_xfer_handle xfer) 2734 { 2735 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2736 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2737 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2738 uhci_soft_td_t *end; 2739 int i; 2740 2741 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2742 2743 mutex_enter(&sc->sc_lock); 2744 2745 if (sc->sc_dying) { 2746 mutex_exit(&sc->sc_lock); 2747 return (USBD_IOERROR); 2748 } 2749 2750 #ifdef DIAGNOSTIC 2751 if (xfer->status != USBD_IN_PROGRESS) 2752 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2753 #endif 2754 2755 /* Find the last TD */ 2756 i = UXFER(xfer)->curframe + xfer->nframes; 2757 if (i >= UHCI_VFRAMELIST_COUNT) 2758 i -= UHCI_VFRAMELIST_COUNT; 2759 end = upipe->u.iso.stds[i]; 2760 2761 #ifdef DIAGNOSTIC 2762 if (end == NULL) { 2763 printf("uhci_device_isoc_start: end == NULL\n"); 2764 return (USBD_INVAL); 2765 } 2766 #endif 2767 2768 /* Set up interrupt info. */ 2769 ii->xfer = xfer; 2770 ii->stdstart = end; 2771 ii->stdend = end; 2772 #ifdef DIAGNOSTIC 2773 if (!ii->isdone) 2774 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2775 ii->isdone = 0; 2776 #endif 2777 uhci_add_intr_info(sc, ii); 2778 2779 mutex_exit(&sc->sc_lock); 2780 2781 return (USBD_IN_PROGRESS); 2782 } 2783 2784 void 2785 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2786 { 2787 #ifdef DIAGNOSTIC 2788 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2789 #endif 2790 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2791 uhci_soft_td_t **stds = upipe->u.iso.stds; 2792 uhci_soft_td_t *std; 2793 int i, n, nframes, maxlen, len; 2794 2795 KASSERT(mutex_owned(&sc->sc_lock)); 2796 2797 /* Transfer is already done. */ 2798 if (xfer->status != USBD_NOT_STARTED && 2799 xfer->status != USBD_IN_PROGRESS) { 2800 return; 2801 } 2802 2803 /* Give xfer the requested abort code. */ 2804 xfer->status = USBD_CANCELLED; 2805 2806 /* make hardware ignore it, */ 2807 nframes = xfer->nframes; 2808 n = UXFER(xfer)->curframe; 2809 maxlen = 0; 2810 for (i = 0; i < nframes; i++) { 2811 std = stds[n]; 2812 usb_syncmem(&std->dma, 2813 std->offs + offsetof(uhci_td_t, td_status), 2814 sizeof(std->td.td_status), 2815 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2816 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2817 usb_syncmem(&std->dma, 2818 std->offs + offsetof(uhci_td_t, td_status), 2819 sizeof(std->td.td_status), 2820 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2821 usb_syncmem(&std->dma, 2822 std->offs + offsetof(uhci_td_t, td_token), 2823 sizeof(std->td.td_token), 2824 BUS_DMASYNC_POSTWRITE); 2825 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2826 if (len > maxlen) 2827 maxlen = len; 2828 if (++n >= UHCI_VFRAMELIST_COUNT) 2829 n = 0; 2830 } 2831 2832 /* and wait until we are sure the hardware has finished. */ 2833 delay(maxlen); 2834 2835 #ifdef DIAGNOSTIC 2836 UXFER(xfer)->iinfo.isdone = 1; 2837 #endif 2838 /* Run callback and remove from interrupt list. */ 2839 usb_transfer_complete(xfer); 2840 2841 KASSERT(mutex_owned(&sc->sc_lock)); 2842 } 2843 2844 void 2845 uhci_device_isoc_close(usbd_pipe_handle pipe) 2846 { 2847 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2848 usbd_device_handle dev = upipe->pipe.device; 2849 uhci_softc_t *sc = dev->bus->hci_private; 2850 uhci_soft_td_t *std, *vstd; 2851 struct iso *iso; 2852 int i; 2853 2854 KASSERT(mutex_owned(&sc->sc_lock)); 2855 2856 /* 2857 * Make sure all TDs are marked as inactive. 2858 * Wait for completion. 2859 * Unschedule. 2860 * Deallocate. 2861 */ 2862 iso = &upipe->u.iso; 2863 2864 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2865 std = iso->stds[i]; 2866 usb_syncmem(&std->dma, 2867 std->offs + offsetof(uhci_td_t, td_status), 2868 sizeof(std->td.td_status), 2869 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2870 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2871 usb_syncmem(&std->dma, 2872 std->offs + offsetof(uhci_td_t, td_status), 2873 sizeof(std->td.td_status), 2874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2875 } 2876 /* wait for completion */ 2877 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2878 2879 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2880 std = iso->stds[i]; 2881 for (vstd = sc->sc_vframes[i].htd; 2882 vstd != NULL && vstd->link.std != std; 2883 vstd = vstd->link.std) 2884 ; 2885 if (vstd == NULL) { 2886 /*panic*/ 2887 printf("uhci_device_isoc_close: %p not found\n", std); 2888 mutex_exit(&sc->sc_lock); 2889 return; 2890 } 2891 vstd->link = std->link; 2892 usb_syncmem(&std->dma, 2893 std->offs + offsetof(uhci_td_t, td_link), 2894 sizeof(std->td.td_link), 2895 BUS_DMASYNC_POSTWRITE); 2896 vstd->td.td_link = std->td.td_link; 2897 usb_syncmem(&vstd->dma, 2898 vstd->offs + offsetof(uhci_td_t, td_link), 2899 sizeof(vstd->td.td_link), 2900 BUS_DMASYNC_PREWRITE); 2901 uhci_free_std(sc, std); 2902 } 2903 2904 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2905 } 2906 2907 usbd_status 2908 uhci_setup_isoc(usbd_pipe_handle pipe) 2909 { 2910 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2911 usbd_device_handle dev = upipe->pipe.device; 2912 uhci_softc_t *sc = dev->bus->hci_private; 2913 int addr = upipe->pipe.device->address; 2914 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2915 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2916 uhci_soft_td_t *std, *vstd; 2917 u_int32_t token; 2918 struct iso *iso; 2919 int i; 2920 2921 iso = &upipe->u.iso; 2922 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2923 sizeof (uhci_soft_td_t *), 2924 KM_SLEEP); 2925 if (iso->stds == NULL) 2926 return USBD_NOMEM; 2927 2928 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2929 UHCI_TD_OUT(0, endpt, addr, 0); 2930 2931 mutex_enter(&sc->sc_lock); 2932 2933 /* Allocate the TDs and mark as inactive; */ 2934 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2935 std = uhci_alloc_std(sc); 2936 if (std == 0) 2937 goto bad; 2938 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2939 std->td.td_token = htole32(token); 2940 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2942 iso->stds[i] = std; 2943 } 2944 2945 /* Insert TDs into schedule. */ 2946 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2947 std = iso->stds[i]; 2948 vstd = sc->sc_vframes[i].htd; 2949 usb_syncmem(&vstd->dma, 2950 vstd->offs + offsetof(uhci_td_t, td_link), 2951 sizeof(vstd->td.td_link), 2952 BUS_DMASYNC_POSTWRITE); 2953 std->link = vstd->link; 2954 std->td.td_link = vstd->td.td_link; 2955 usb_syncmem(&std->dma, 2956 std->offs + offsetof(uhci_td_t, td_link), 2957 sizeof(std->td.td_link), 2958 BUS_DMASYNC_PREWRITE); 2959 vstd->link.std = std; 2960 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2961 usb_syncmem(&vstd->dma, 2962 vstd->offs + offsetof(uhci_td_t, td_link), 2963 sizeof(vstd->td.td_link), 2964 BUS_DMASYNC_PREWRITE); 2965 } 2966 mutex_exit(&sc->sc_lock); 2967 2968 iso->next = -1; 2969 iso->inuse = 0; 2970 2971 return (USBD_NORMAL_COMPLETION); 2972 2973 bad: 2974 while (--i >= 0) 2975 uhci_free_std(sc, iso->stds[i]); 2976 mutex_exit(&sc->sc_lock); 2977 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2978 return (USBD_NOMEM); 2979 } 2980 2981 void 2982 uhci_device_isoc_done(usbd_xfer_handle xfer) 2983 { 2984 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2985 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2986 int i, offs; 2987 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2988 2989 2990 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2991 xfer->actlen, xfer->busy_free)); 2992 2993 if (ii->xfer != xfer) 2994 /* Not on interrupt list, ignore it. */ 2995 return; 2996 2997 if (!uhci_active_intr_info(ii)) 2998 return; 2999 3000 #ifdef DIAGNOSTIC 3001 if (ii->stdend == NULL) { 3002 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 3003 #ifdef UHCI_DEBUG 3004 uhci_dump_ii(ii); 3005 #endif 3006 return; 3007 } 3008 #endif 3009 3010 /* Turn off the interrupt since it is active even if the TD is not. */ 3011 usb_syncmem(&ii->stdend->dma, 3012 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3013 sizeof(ii->stdend->td.td_status), 3014 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3015 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3016 usb_syncmem(&ii->stdend->dma, 3017 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3018 sizeof(ii->stdend->td.td_status), 3019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3020 3021 uhci_del_intr_info(ii); /* remove from active list */ 3022 3023 offs = 0; 3024 for (i = 0; i < xfer->nframes; i++) { 3025 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 3026 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3027 offs += xfer->frlengths[i]; 3028 } 3029 } 3030 3031 void 3032 uhci_device_intr_done(usbd_xfer_handle xfer) 3033 { 3034 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3035 uhci_softc_t *sc = ii->sc; 3036 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3037 uhci_soft_qh_t *sqh; 3038 int i, npoll, isread; 3039 3040 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3041 3042 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3043 3044 npoll = upipe->u.intr.npoll; 3045 for(i = 0; i < npoll; i++) { 3046 sqh = upipe->u.intr.qhs[i]; 3047 sqh->elink = NULL; 3048 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3049 usb_syncmem(&sqh->dma, 3050 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3051 sizeof(sqh->qh.qh_elink), 3052 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3053 } 3054 uhci_free_std_chain(sc, ii->stdstart, NULL); 3055 3056 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3057 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3058 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3059 3060 /* XXX Wasteful. */ 3061 if (xfer->pipe->repeat) { 3062 uhci_soft_td_t *data, *dataend; 3063 3064 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3065 3066 /* This alloc cannot fail since we freed the chain above. */ 3067 uhci_alloc_std_chain(upipe, sc, xfer->length, 3068 upipe->u.intr.isread, xfer->flags, 3069 &xfer->dmabuf, &data, &dataend); 3070 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3071 usb_syncmem(&dataend->dma, 3072 dataend->offs + offsetof(uhci_td_t, td_status), 3073 sizeof(dataend->td.td_status), 3074 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3075 3076 #ifdef UHCI_DEBUG 3077 if (uhcidebug > 10) { 3078 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3079 uhci_dump_tds(data); 3080 uhci_dump_qh(upipe->u.intr.qhs[0]); 3081 } 3082 #endif 3083 3084 ii->stdstart = data; 3085 ii->stdend = dataend; 3086 #ifdef DIAGNOSTIC 3087 if (!ii->isdone) { 3088 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3089 } 3090 ii->isdone = 0; 3091 #endif 3092 for (i = 0; i < npoll; i++) { 3093 sqh = upipe->u.intr.qhs[i]; 3094 sqh->elink = data; 3095 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3096 usb_syncmem(&sqh->dma, 3097 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3098 sizeof(sqh->qh.qh_elink), 3099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3100 } 3101 xfer->status = USBD_IN_PROGRESS; 3102 /* The ii is already on the examined list, just leave it. */ 3103 } else { 3104 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3105 if (uhci_active_intr_info(ii)) 3106 uhci_del_intr_info(ii); 3107 } 3108 } 3109 3110 /* Deallocate request data structures */ 3111 void 3112 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3113 { 3114 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3115 uhci_softc_t *sc = ii->sc; 3116 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3117 int len = UGETW(xfer->request.wLength); 3118 int isread = (xfer->request.bmRequestType & UT_READ); 3119 3120 KASSERT(mutex_owned(&sc->sc_lock)); 3121 3122 #ifdef DIAGNOSTIC 3123 if (!(xfer->rqflags & URQ_REQUEST)) 3124 panic("uhci_device_ctrl_done: not a request"); 3125 #endif 3126 3127 if (!uhci_active_intr_info(ii)) 3128 return; 3129 3130 uhci_del_intr_info(ii); /* remove from active list */ 3131 3132 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3133 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3134 else 3135 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3136 3137 if (upipe->u.ctl.length != 0) 3138 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3139 3140 if (len) { 3141 usb_syncmem(&xfer->dmabuf, 0, len, 3142 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3143 } 3144 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3145 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3146 3147 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3148 } 3149 3150 /* Deallocate request data structures */ 3151 void 3152 uhci_device_bulk_done(usbd_xfer_handle xfer) 3153 { 3154 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3155 uhci_softc_t *sc = ii->sc; 3156 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3157 3158 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3159 xfer, ii, sc, upipe)); 3160 3161 KASSERT(mutex_owned(&sc->sc_lock)); 3162 3163 if (!uhci_active_intr_info(ii)) 3164 return; 3165 3166 uhci_del_intr_info(ii); /* remove from active list */ 3167 3168 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3169 3170 uhci_free_std_chain(sc, ii->stdstart, NULL); 3171 3172 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3173 } 3174 3175 /* Add interrupt QH, called with vflock. */ 3176 void 3177 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3178 { 3179 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3180 uhci_soft_qh_t *eqh; 3181 3182 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3183 3184 eqh = vf->eqh; 3185 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3186 sizeof(eqh->qh.qh_hlink), 3187 BUS_DMASYNC_POSTWRITE); 3188 sqh->hlink = eqh->hlink; 3189 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3190 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3191 sizeof(sqh->qh.qh_hlink), 3192 BUS_DMASYNC_PREWRITE); 3193 eqh->hlink = sqh; 3194 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3195 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3196 sizeof(eqh->qh.qh_hlink), 3197 BUS_DMASYNC_PREWRITE); 3198 vf->eqh = sqh; 3199 vf->bandwidth++; 3200 } 3201 3202 /* Remove interrupt QH. */ 3203 void 3204 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3205 { 3206 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3207 uhci_soft_qh_t *pqh; 3208 3209 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3210 3211 /* See comment in uhci_remove_ctrl() */ 3212 3213 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3214 sizeof(sqh->qh.qh_elink), 3215 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3216 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3217 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3218 usb_syncmem(&sqh->dma, 3219 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3220 sizeof(sqh->qh.qh_elink), 3221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3222 delay(UHCI_QH_REMOVE_DELAY); 3223 } 3224 3225 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3226 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3227 sizeof(sqh->qh.qh_hlink), 3228 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3229 pqh->hlink = sqh->hlink; 3230 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3231 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3232 sizeof(pqh->qh.qh_hlink), 3233 BUS_DMASYNC_PREWRITE); 3234 delay(UHCI_QH_REMOVE_DELAY); 3235 if (vf->eqh == sqh) 3236 vf->eqh = pqh; 3237 vf->bandwidth--; 3238 } 3239 3240 usbd_status 3241 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3242 { 3243 uhci_soft_qh_t *sqh; 3244 int i, npoll; 3245 u_int bestbw, bw, bestoffs, offs; 3246 3247 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3248 if (ival == 0) { 3249 printf("uhci_device_setintr: 0 interval\n"); 3250 return (USBD_INVAL); 3251 } 3252 3253 if (ival > UHCI_VFRAMELIST_COUNT) 3254 ival = UHCI_VFRAMELIST_COUNT; 3255 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3256 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3257 3258 upipe->u.intr.npoll = npoll; 3259 upipe->u.intr.qhs = 3260 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3261 if (upipe->u.intr.qhs == NULL) 3262 return USBD_NOMEM; 3263 3264 /* 3265 * Figure out which offset in the schedule that has most 3266 * bandwidth left over. 3267 */ 3268 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3269 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3270 for (bw = i = 0; i < npoll; i++) 3271 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3272 if (bw < bestbw) { 3273 bestbw = bw; 3274 bestoffs = offs; 3275 } 3276 } 3277 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3278 3279 mutex_enter(&sc->sc_lock); 3280 for(i = 0; i < npoll; i++) { 3281 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3282 sqh->elink = NULL; 3283 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3284 usb_syncmem(&sqh->dma, 3285 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3286 sizeof(sqh->qh.qh_elink), 3287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3288 sqh->pos = MOD(i * ival + bestoffs); 3289 } 3290 #undef MOD 3291 3292 /* Enter QHs into the controller data structures. */ 3293 for(i = 0; i < npoll; i++) 3294 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3295 mutex_exit(&sc->sc_lock); 3296 3297 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3298 return (USBD_NORMAL_COMPLETION); 3299 } 3300 3301 /* Open a new pipe. */ 3302 usbd_status 3303 uhci_open(usbd_pipe_handle pipe) 3304 { 3305 uhci_softc_t *sc = pipe->device->bus->hci_private; 3306 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3307 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3308 usbd_status err = USBD_NOMEM; 3309 int ival; 3310 3311 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3312 pipe, pipe->device->address, 3313 ed->bEndpointAddress, sc->sc_addr)); 3314 3315 if (sc->sc_dying) 3316 return USBD_IOERROR; 3317 3318 upipe->aborting = 0; 3319 /* toggle state needed for bulk endpoints */ 3320 upipe->nexttoggle = pipe->endpoint->datatoggle; 3321 3322 if (pipe->device->address == sc->sc_addr) { 3323 switch (ed->bEndpointAddress) { 3324 case USB_CONTROL_ENDPOINT: 3325 pipe->methods = &uhci_root_ctrl_methods; 3326 break; 3327 case UE_DIR_IN | UHCI_INTR_ENDPT: 3328 pipe->methods = &uhci_root_intr_methods; 3329 break; 3330 default: 3331 return (USBD_INVAL); 3332 } 3333 } else { 3334 switch (ed->bmAttributes & UE_XFERTYPE) { 3335 case UE_CONTROL: 3336 pipe->methods = &uhci_device_ctrl_methods; 3337 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3338 if (upipe->u.ctl.sqh == NULL) 3339 goto bad; 3340 upipe->u.ctl.setup = uhci_alloc_std(sc); 3341 if (upipe->u.ctl.setup == NULL) { 3342 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3343 goto bad; 3344 } 3345 upipe->u.ctl.stat = uhci_alloc_std(sc); 3346 if (upipe->u.ctl.stat == NULL) { 3347 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3348 uhci_free_std(sc, upipe->u.ctl.setup); 3349 goto bad; 3350 } 3351 err = usb_allocmem(&sc->sc_bus, 3352 sizeof(usb_device_request_t), 3353 0, &upipe->u.ctl.reqdma); 3354 if (err) { 3355 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3356 uhci_free_std(sc, upipe->u.ctl.setup); 3357 uhci_free_std(sc, upipe->u.ctl.stat); 3358 goto bad; 3359 } 3360 break; 3361 case UE_INTERRUPT: 3362 pipe->methods = &uhci_device_intr_methods; 3363 ival = pipe->interval; 3364 if (ival == USBD_DEFAULT_INTERVAL) 3365 ival = ed->bInterval; 3366 return (uhci_device_setintr(sc, upipe, ival)); 3367 case UE_ISOCHRONOUS: 3368 pipe->methods = &uhci_device_isoc_methods; 3369 return (uhci_setup_isoc(pipe)); 3370 case UE_BULK: 3371 pipe->methods = &uhci_device_bulk_methods; 3372 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3373 if (upipe->u.bulk.sqh == NULL) 3374 goto bad; 3375 break; 3376 } 3377 } 3378 return (USBD_NORMAL_COMPLETION); 3379 3380 bad: 3381 return USBD_NOMEM; 3382 } 3383 3384 /* 3385 * Data structures and routines to emulate the root hub. 3386 */ 3387 usb_device_descriptor_t uhci_devd = { 3388 USB_DEVICE_DESCRIPTOR_SIZE, 3389 UDESC_DEVICE, /* type */ 3390 {0x00, 0x01}, /* USB version */ 3391 UDCLASS_HUB, /* class */ 3392 UDSUBCLASS_HUB, /* subclass */ 3393 UDPROTO_FSHUB, /* protocol */ 3394 64, /* max packet */ 3395 {0},{0},{0x00,0x01}, /* device id */ 3396 1,2,0, /* string indicies */ 3397 1 /* # of configurations */ 3398 }; 3399 3400 const usb_config_descriptor_t uhci_confd = { 3401 USB_CONFIG_DESCRIPTOR_SIZE, 3402 UDESC_CONFIG, 3403 {USB_CONFIG_DESCRIPTOR_SIZE + 3404 USB_INTERFACE_DESCRIPTOR_SIZE + 3405 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3406 1, 3407 1, 3408 0, 3409 UC_ATTR_MBO | UC_SELF_POWERED, 3410 0 /* max power */ 3411 }; 3412 3413 const usb_interface_descriptor_t uhci_ifcd = { 3414 USB_INTERFACE_DESCRIPTOR_SIZE, 3415 UDESC_INTERFACE, 3416 0, 3417 0, 3418 1, 3419 UICLASS_HUB, 3420 UISUBCLASS_HUB, 3421 UIPROTO_FSHUB, 3422 0 3423 }; 3424 3425 const usb_endpoint_descriptor_t uhci_endpd = { 3426 USB_ENDPOINT_DESCRIPTOR_SIZE, 3427 UDESC_ENDPOINT, 3428 UE_DIR_IN | UHCI_INTR_ENDPT, 3429 UE_INTERRUPT, 3430 {8}, 3431 255 3432 }; 3433 3434 const usb_hub_descriptor_t uhci_hubd_piix = { 3435 USB_HUB_DESCRIPTOR_SIZE, 3436 UDESC_HUB, 3437 2, 3438 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3439 50, /* power on to power good */ 3440 0, 3441 { 0x00 }, /* both ports are removable */ 3442 { 0 }, 3443 }; 3444 3445 /* 3446 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3447 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3448 * should not be used by the USB subsystem. As we cannot issue a 3449 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3450 * will be enabled as part of the reset. 3451 * 3452 * On the VT83C572, the port cannot be successfully enabled until the 3453 * outstanding "port enable change" and "connection status change" 3454 * events have been reset. 3455 */ 3456 Static usbd_status 3457 uhci_portreset(uhci_softc_t *sc, int index) 3458 { 3459 int lim, port, x; 3460 3461 if (index == 1) 3462 port = UHCI_PORTSC1; 3463 else if (index == 2) 3464 port = UHCI_PORTSC2; 3465 else 3466 return (USBD_IOERROR); 3467 3468 x = URWMASK(UREAD2(sc, port)); 3469 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3470 3471 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3472 3473 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3474 index, UREAD2(sc, port))); 3475 3476 x = URWMASK(UREAD2(sc, port)); 3477 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3478 3479 delay(100); 3480 3481 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3482 index, UREAD2(sc, port))); 3483 3484 x = URWMASK(UREAD2(sc, port)); 3485 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3486 3487 for (lim = 10; --lim > 0;) { 3488 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3489 3490 x = UREAD2(sc, port); 3491 3492 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3493 index, lim, x)); 3494 3495 if (!(x & UHCI_PORTSC_CCS)) { 3496 /* 3497 * No device is connected (or was disconnected 3498 * during reset). Consider the port reset. 3499 * The delay must be long enough to ensure on 3500 * the initial iteration that the device 3501 * connection will have been registered. 50ms 3502 * appears to be sufficient, but 20ms is not. 3503 */ 3504 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3505 index, lim)); 3506 break; 3507 } 3508 3509 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3510 /* 3511 * Port enabled changed and/or connection 3512 * status changed were set. Reset either or 3513 * both raised flags (by writing a 1 to that 3514 * bit), and wait again for state to settle. 3515 */ 3516 UWRITE2(sc, port, URWMASK(x) | 3517 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3518 continue; 3519 } 3520 3521 if (x & UHCI_PORTSC_PE) 3522 /* Port is enabled */ 3523 break; 3524 3525 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3526 } 3527 3528 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3529 index, UREAD2(sc, port))); 3530 3531 if (lim <= 0) { 3532 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3533 return (USBD_TIMEOUT); 3534 } 3535 3536 sc->sc_isreset = 1; 3537 return (USBD_NORMAL_COMPLETION); 3538 } 3539 3540 /* 3541 * Simulate a hardware hub by handling all the necessary requests. 3542 */ 3543 usbd_status 3544 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3545 { 3546 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3547 usbd_status err; 3548 3549 /* Insert last in queue. */ 3550 mutex_enter(&sc->sc_lock); 3551 err = usb_insert_transfer(xfer); 3552 mutex_exit(&sc->sc_lock); 3553 if (err) 3554 return (err); 3555 3556 /* 3557 * Pipe isn't running (otherwise err would be USBD_INPROG), 3558 * so start it first. 3559 */ 3560 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3561 } 3562 3563 usbd_status 3564 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3565 { 3566 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3567 usb_device_request_t *req; 3568 void *buf = NULL; 3569 int port, x; 3570 int len, value, index, status, change, l, totlen = 0; 3571 usb_port_status_t ps; 3572 usbd_status err; 3573 3574 if (sc->sc_dying) 3575 return (USBD_IOERROR); 3576 3577 #ifdef DIAGNOSTIC 3578 if (!(xfer->rqflags & URQ_REQUEST)) 3579 panic("uhci_root_ctrl_start: not a request"); 3580 #endif 3581 req = &xfer->request; 3582 3583 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3584 req->bmRequestType, req->bRequest)); 3585 3586 len = UGETW(req->wLength); 3587 value = UGETW(req->wValue); 3588 index = UGETW(req->wIndex); 3589 3590 if (len != 0) 3591 buf = KERNADDR(&xfer->dmabuf, 0); 3592 3593 #define C(x,y) ((x) | ((y) << 8)) 3594 switch(C(req->bRequest, req->bmRequestType)) { 3595 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3596 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3597 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3598 /* 3599 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3600 * for the integrated root hub. 3601 */ 3602 break; 3603 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3604 if (len > 0) { 3605 *(u_int8_t *)buf = sc->sc_conf; 3606 totlen = 1; 3607 } 3608 break; 3609 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3610 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3611 if (len == 0) 3612 break; 3613 switch(value >> 8) { 3614 case UDESC_DEVICE: 3615 if ((value & 0xff) != 0) { 3616 err = USBD_IOERROR; 3617 goto ret; 3618 } 3619 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3620 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3621 memcpy(buf, &uhci_devd, l); 3622 break; 3623 case UDESC_CONFIG: 3624 if ((value & 0xff) != 0) { 3625 err = USBD_IOERROR; 3626 goto ret; 3627 } 3628 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3629 memcpy(buf, &uhci_confd, l); 3630 buf = (char *)buf + l; 3631 len -= l; 3632 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3633 totlen += l; 3634 memcpy(buf, &uhci_ifcd, l); 3635 buf = (char *)buf + l; 3636 len -= l; 3637 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3638 totlen += l; 3639 memcpy(buf, &uhci_endpd, l); 3640 break; 3641 case UDESC_STRING: 3642 #define sd ((usb_string_descriptor_t *)buf) 3643 switch (value & 0xff) { 3644 case 0: /* Language table */ 3645 totlen = usb_makelangtbl(sd, len); 3646 break; 3647 case 1: /* Vendor */ 3648 totlen = usb_makestrdesc(sd, len, 3649 sc->sc_vendor); 3650 break; 3651 case 2: /* Product */ 3652 totlen = usb_makestrdesc(sd, len, 3653 "UHCI root hub"); 3654 break; 3655 } 3656 #undef sd 3657 break; 3658 default: 3659 err = USBD_IOERROR; 3660 goto ret; 3661 } 3662 break; 3663 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3664 if (len > 0) { 3665 *(u_int8_t *)buf = 0; 3666 totlen = 1; 3667 } 3668 break; 3669 case C(UR_GET_STATUS, UT_READ_DEVICE): 3670 if (len > 1) { 3671 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3672 totlen = 2; 3673 } 3674 break; 3675 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3676 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3677 if (len > 1) { 3678 USETW(((usb_status_t *)buf)->wStatus, 0); 3679 totlen = 2; 3680 } 3681 break; 3682 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3683 if (value >= USB_MAX_DEVICES) { 3684 err = USBD_IOERROR; 3685 goto ret; 3686 } 3687 sc->sc_addr = value; 3688 break; 3689 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3690 if (value != 0 && value != 1) { 3691 err = USBD_IOERROR; 3692 goto ret; 3693 } 3694 sc->sc_conf = value; 3695 break; 3696 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3697 break; 3698 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3699 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3700 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3701 err = USBD_IOERROR; 3702 goto ret; 3703 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3704 break; 3705 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3706 break; 3707 /* Hub requests */ 3708 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3709 break; 3710 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3711 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3712 "port=%d feature=%d\n", 3713 index, value)); 3714 if (index == 1) 3715 port = UHCI_PORTSC1; 3716 else if (index == 2) 3717 port = UHCI_PORTSC2; 3718 else { 3719 err = USBD_IOERROR; 3720 goto ret; 3721 } 3722 switch(value) { 3723 case UHF_PORT_ENABLE: 3724 x = URWMASK(UREAD2(sc, port)); 3725 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3726 break; 3727 case UHF_PORT_SUSPEND: 3728 x = URWMASK(UREAD2(sc, port)); 3729 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3730 break; 3731 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3732 /* see USB2 spec ch. 7.1.7.7 */ 3733 usb_delay_ms(&sc->sc_bus, 20); 3734 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3735 /* 10ms resume delay must be provided by caller */ 3736 break; 3737 case UHF_PORT_RESET: 3738 x = URWMASK(UREAD2(sc, port)); 3739 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3740 break; 3741 case UHF_C_PORT_CONNECTION: 3742 x = URWMASK(UREAD2(sc, port)); 3743 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3744 break; 3745 case UHF_C_PORT_ENABLE: 3746 x = URWMASK(UREAD2(sc, port)); 3747 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3748 break; 3749 case UHF_C_PORT_OVER_CURRENT: 3750 x = URWMASK(UREAD2(sc, port)); 3751 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3752 break; 3753 case UHF_C_PORT_RESET: 3754 sc->sc_isreset = 0; 3755 err = USBD_NORMAL_COMPLETION; 3756 goto ret; 3757 case UHF_PORT_CONNECTION: 3758 case UHF_PORT_OVER_CURRENT: 3759 case UHF_PORT_POWER: 3760 case UHF_PORT_LOW_SPEED: 3761 case UHF_C_PORT_SUSPEND: 3762 default: 3763 err = USBD_IOERROR; 3764 goto ret; 3765 } 3766 break; 3767 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3768 if (index == 1) 3769 port = UHCI_PORTSC1; 3770 else if (index == 2) 3771 port = UHCI_PORTSC2; 3772 else { 3773 err = USBD_IOERROR; 3774 goto ret; 3775 } 3776 if (len > 0) { 3777 *(u_int8_t *)buf = 3778 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3779 UHCI_PORTSC_LS_SHIFT; 3780 totlen = 1; 3781 } 3782 break; 3783 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3784 if (len == 0) 3785 break; 3786 if ((value & 0xff) != 0) { 3787 err = USBD_IOERROR; 3788 goto ret; 3789 } 3790 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3791 totlen = l; 3792 memcpy(buf, &uhci_hubd_piix, l); 3793 break; 3794 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3795 if (len != 4) { 3796 err = USBD_IOERROR; 3797 goto ret; 3798 } 3799 memset(buf, 0, len); 3800 totlen = len; 3801 break; 3802 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3803 if (index == 1) 3804 port = UHCI_PORTSC1; 3805 else if (index == 2) 3806 port = UHCI_PORTSC2; 3807 else { 3808 err = USBD_IOERROR; 3809 goto ret; 3810 } 3811 if (len != 4) { 3812 err = USBD_IOERROR; 3813 goto ret; 3814 } 3815 x = UREAD2(sc, port); 3816 status = change = 0; 3817 if (x & UHCI_PORTSC_CCS) 3818 status |= UPS_CURRENT_CONNECT_STATUS; 3819 if (x & UHCI_PORTSC_CSC) 3820 change |= UPS_C_CONNECT_STATUS; 3821 if (x & UHCI_PORTSC_PE) 3822 status |= UPS_PORT_ENABLED; 3823 if (x & UHCI_PORTSC_POEDC) 3824 change |= UPS_C_PORT_ENABLED; 3825 if (x & UHCI_PORTSC_OCI) 3826 status |= UPS_OVERCURRENT_INDICATOR; 3827 if (x & UHCI_PORTSC_OCIC) 3828 change |= UPS_C_OVERCURRENT_INDICATOR; 3829 if (x & UHCI_PORTSC_SUSP) 3830 status |= UPS_SUSPEND; 3831 if (x & UHCI_PORTSC_LSDA) 3832 status |= UPS_LOW_SPEED; 3833 status |= UPS_PORT_POWER; 3834 if (sc->sc_isreset) 3835 change |= UPS_C_PORT_RESET; 3836 USETW(ps.wPortStatus, status); 3837 USETW(ps.wPortChange, change); 3838 l = min(len, sizeof ps); 3839 memcpy(buf, &ps, l); 3840 totlen = l; 3841 break; 3842 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3843 err = USBD_IOERROR; 3844 goto ret; 3845 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3846 break; 3847 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3848 if (index == 1) 3849 port = UHCI_PORTSC1; 3850 else if (index == 2) 3851 port = UHCI_PORTSC2; 3852 else { 3853 err = USBD_IOERROR; 3854 goto ret; 3855 } 3856 switch(value) { 3857 case UHF_PORT_ENABLE: 3858 x = URWMASK(UREAD2(sc, port)); 3859 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3860 break; 3861 case UHF_PORT_SUSPEND: 3862 x = URWMASK(UREAD2(sc, port)); 3863 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3864 break; 3865 case UHF_PORT_RESET: 3866 err = uhci_portreset(sc, index); 3867 goto ret; 3868 case UHF_PORT_POWER: 3869 /* Pretend we turned on power */ 3870 err = USBD_NORMAL_COMPLETION; 3871 goto ret; 3872 case UHF_C_PORT_CONNECTION: 3873 case UHF_C_PORT_ENABLE: 3874 case UHF_C_PORT_OVER_CURRENT: 3875 case UHF_PORT_CONNECTION: 3876 case UHF_PORT_OVER_CURRENT: 3877 case UHF_PORT_LOW_SPEED: 3878 case UHF_C_PORT_SUSPEND: 3879 case UHF_C_PORT_RESET: 3880 default: 3881 err = USBD_IOERROR; 3882 goto ret; 3883 } 3884 break; 3885 default: 3886 err = USBD_IOERROR; 3887 goto ret; 3888 } 3889 xfer->actlen = totlen; 3890 err = USBD_NORMAL_COMPLETION; 3891 ret: 3892 xfer->status = err; 3893 mutex_enter(&sc->sc_lock); 3894 usb_transfer_complete(xfer); 3895 mutex_exit(&sc->sc_lock); 3896 return (USBD_IN_PROGRESS); 3897 } 3898 3899 /* Abort a root control request. */ 3900 void 3901 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3902 { 3903 /* Nothing to do, all transfers are synchronous. */ 3904 } 3905 3906 /* Close the root pipe. */ 3907 void 3908 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3909 { 3910 DPRINTF(("uhci_root_ctrl_close\n")); 3911 } 3912 3913 /* Abort a root interrupt request. */ 3914 void 3915 uhci_root_intr_abort(usbd_xfer_handle xfer) 3916 { 3917 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3918 3919 KASSERT(mutex_owned(&sc->sc_lock)); 3920 3921 callout_stop(&sc->sc_poll_handle); 3922 sc->sc_intr_xfer = NULL; 3923 3924 if (xfer->pipe->intrxfer == xfer) { 3925 DPRINTF(("uhci_root_intr_abort: remove\n")); 3926 xfer->pipe->intrxfer = 0; 3927 } 3928 xfer->status = USBD_CANCELLED; 3929 #ifdef DIAGNOSTIC 3930 UXFER(xfer)->iinfo.isdone = 1; 3931 #endif 3932 usb_transfer_complete(xfer); 3933 } 3934 3935 usbd_status 3936 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3937 { 3938 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3939 usbd_status err; 3940 3941 /* Insert last in queue. */ 3942 mutex_enter(&sc->sc_lock); 3943 err = usb_insert_transfer(xfer); 3944 mutex_exit(&sc->sc_lock); 3945 if (err) 3946 return (err); 3947 3948 /* 3949 * Pipe isn't running (otherwise err would be USBD_INPROG), 3950 * start first 3951 */ 3952 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3953 } 3954 3955 /* Start a transfer on the root interrupt pipe */ 3956 usbd_status 3957 uhci_root_intr_start(usbd_xfer_handle xfer) 3958 { 3959 usbd_pipe_handle pipe = xfer->pipe; 3960 uhci_softc_t *sc = pipe->device->bus->hci_private; 3961 unsigned int ival; 3962 3963 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3964 xfer, xfer->length, xfer->flags)); 3965 3966 if (sc->sc_dying) 3967 return (USBD_IOERROR); 3968 3969 /* XXX temporary variable needed to avoid gcc3 warning */ 3970 ival = xfer->pipe->endpoint->edesc->bInterval; 3971 sc->sc_ival = mstohz(ival); 3972 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3973 sc->sc_intr_xfer = xfer; 3974 return (USBD_IN_PROGRESS); 3975 } 3976 3977 /* Close the root interrupt pipe. */ 3978 void 3979 uhci_root_intr_close(usbd_pipe_handle pipe) 3980 { 3981 uhci_softc_t *sc = pipe->device->bus->hci_private; 3982 3983 KASSERT(mutex_owned(&sc->sc_lock)); 3984 3985 callout_stop(&sc->sc_poll_handle); 3986 sc->sc_intr_xfer = NULL; 3987 DPRINTF(("uhci_root_intr_close\n")); 3988 } 3989