1 /* $NetBSD: ohci.c,v 1.310 2020/06/03 15:38:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill@invisible.ca), 10 * Matthew R. Green (mrg@eterna.com.au), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.310 2020/06/03 15:38:02 skrll Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 10; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 int 372 ohci_detach(struct ohci_softc *sc, int flags) 373 { 374 int rv = 0; 375 376 if (sc->sc_child != NULL) 377 rv = config_detach(sc->sc_child, flags); 378 379 if (rv != 0) 380 return rv; 381 382 softint_disestablish(sc->sc_rhsc_si); 383 384 callout_halt(&sc->sc_tmo_rhsc, NULL); 385 callout_destroy(&sc->sc_tmo_rhsc); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 394 return rv; 395 } 396 397 ohci_soft_ed_t * 398 ohci_alloc_sed(ohci_softc_t *sc) 399 { 400 ohci_soft_ed_t *sed; 401 usbd_status err; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, USBMALLOC_COHERENT, &dma); 414 if (err) 415 return NULL; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 usbd_status err; 461 int i, offs; 462 usb_dma_t dma; 463 464 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 465 466 mutex_enter(&sc->sc_lock); 467 if (sc->sc_freetds == NULL) { 468 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 469 mutex_exit(&sc->sc_lock); 470 471 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 472 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 473 if (err) 474 return NULL; 475 476 mutex_enter(&sc->sc_lock); 477 for (i = 0; i < OHCI_STD_CHUNK; i++) { 478 offs = i * OHCI_STD_SIZE; 479 std = KERNADDR(&dma, offs); 480 std->physaddr = DMAADDR(&dma, offs); 481 std->dma = dma; 482 std->offs = offs; 483 std->nexttd = sc->sc_freetds; 484 sc->sc_freetds = std; 485 } 486 } 487 488 std = sc->sc_freetds; 489 sc->sc_freetds = std->nexttd; 490 mutex_exit(&sc->sc_lock); 491 492 memset(&std->td, 0, sizeof(ohci_td_t)); 493 std->nexttd = NULL; 494 std->xfer = NULL; 495 496 return std; 497 } 498 499 void 500 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 501 { 502 503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 504 505 std->nexttd = sc->sc_freetds; 506 sc->sc_freetds = std; 507 } 508 509 void 510 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 511 { 512 513 mutex_enter(&sc->sc_lock); 514 ohci_free_std_locked(sc, std); 515 mutex_exit(&sc->sc_lock); 516 } 517 518 Static int 519 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 520 { 521 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 522 uint16_t flags = xfer->ux_flags; 523 524 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 525 526 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 527 xfer->ux_pipe->up_dev->ud_addr, 528 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 529 length, xfer->ux_pipe->up_dev->ud_speed); 530 531 ASSERT_SLEEPABLE(); 532 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 533 534 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 535 nstd += howmany(length, OHCI_PAGE_SIZE); 536 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 537 KM_SLEEP); 538 ox->ox_nstd = nstd; 539 540 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 541 542 for (size_t j = 0; j < ox->ox_nstd;) { 543 ohci_soft_td_t *cur = ohci_alloc_std(sc); 544 if (cur == NULL) 545 goto nomem; 546 547 ox->ox_stds[j++] = cur; 548 cur->xfer = xfer; 549 cur->flags = 0; 550 } 551 552 return 0; 553 554 nomem: 555 ohci_free_stds(sc, ox); 556 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 557 558 return ENOMEM; 559 } 560 561 Static void 562 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 563 { 564 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 565 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 566 567 mutex_enter(&sc->sc_lock); 568 for (size_t i = 0; i < ox->ox_nstd; i++) { 569 ohci_soft_td_t *std = ox->ox_stds[i]; 570 if (std == NULL) 571 break; 572 ohci_free_std_locked(sc, std); 573 } 574 mutex_exit(&sc->sc_lock); 575 } 576 577 void 578 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 579 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 580 { 581 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 582 ohci_soft_td_t *next, *cur; 583 int len, curlen; 584 usb_dma_t *dma = &xfer->ux_dmabuf; 585 uint16_t flags = xfer->ux_flags; 586 587 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 588 DPRINTF("start len=%jd", alen, 0, 0, 0); 589 590 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 591 592 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 593 xfer->ux_pipe->up_dev->ud_addr, 594 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 595 alen, xfer->ux_pipe->up_dev->ud_speed); 596 597 KASSERT(sp); 598 599 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 600 601 /* 602 * Assign next for the len == 0 case where we don't go through the 603 * main loop. 604 */ 605 len = alen; 606 cur = next = sp; 607 608 usb_syncmem(dma, 0, len, 609 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 610 const uint32_t tdflags = HTOO32( 611 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 612 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 613 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 614 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 615 ); 616 617 size_t curoffs = 0; 618 for (size_t j = 1; len != 0;) { 619 if (j == ox->ox_nstd) 620 next = NULL; 621 else 622 next = ox->ox_stds[j++]; 623 KASSERT(next != cur); 624 625 curlen = len; 626 /* 627 * The OHCI hardware can handle at most one page crossing per 628 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 629 * length in this TD accordingly. 630 */ 631 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 632 633 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 634 if (curlen > maxlen) { 635 curlen = maxlen; 636 637 /* 638 * the length must be a multiple of 639 * the max size 640 */ 641 curlen -= curlen % mps; 642 } 643 644 const int edataoffs = curoffs + curlen - 1; 645 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 646 647 KASSERT(curlen != 0); 648 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 649 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 650 651 cur->td.td_flags = tdflags; 652 cur->td.td_cbp = HTOO32(sdataphys); 653 cur->td.td_be = HTOO32(edataphys); 654 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 655 cur->nexttd = next; 656 cur->len = curlen; 657 cur->flags = OHCI_ADD_LEN; 658 cur->xfer = xfer; 659 ohci_hash_add_td(sc, cur); 660 661 curoffs += curlen; 662 len -= curlen; 663 664 if (len != 0) { 665 KASSERT(next != NULL); 666 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 667 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 668 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 669 670 cur = next; 671 } 672 } 673 cur->td.td_flags |= 674 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 675 676 if (!rd && 677 (flags & USBD_FORCE_SHORT_XFER) && 678 alen % mps == 0) { 679 /* We're adding a ZLP so sync the previous TD */ 680 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 681 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 682 683 /* Force a 0 length transfer at the end. */ 684 685 KASSERT(next != NULL); 686 cur = next; 687 688 cur->td.td_flags = tdflags; 689 cur->td.td_cbp = 0; /* indicate 0 length packet */ 690 cur->td.td_nexttd = 0; 691 cur->td.td_be = ~0; 692 cur->nexttd = NULL; 693 cur->len = 0; 694 cur->flags = 0; 695 cur->xfer = xfer; 696 ohci_hash_add_td(sc, cur); 697 698 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 699 } 700 701 /* Last TD gets usb_syncmem'ed by caller */ 702 *ep = cur; 703 } 704 705 ohci_soft_itd_t * 706 ohci_alloc_sitd(ohci_softc_t *sc) 707 { 708 ohci_soft_itd_t *sitd; 709 usbd_status err; 710 int i, offs; 711 usb_dma_t dma; 712 713 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 714 715 mutex_enter(&sc->sc_lock); 716 if (sc->sc_freeitds == NULL) { 717 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 718 mutex_exit(&sc->sc_lock); 719 720 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 721 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 722 if (err) 723 return NULL; 724 mutex_enter(&sc->sc_lock); 725 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 726 offs = i * OHCI_SITD_SIZE; 727 sitd = KERNADDR(&dma, offs); 728 sitd->physaddr = DMAADDR(&dma, offs); 729 sitd->dma = dma; 730 sitd->offs = offs; 731 sitd->nextitd = sc->sc_freeitds; 732 sc->sc_freeitds = sitd; 733 } 734 } 735 736 sitd = sc->sc_freeitds; 737 sc->sc_freeitds = sitd->nextitd; 738 mutex_exit(&sc->sc_lock); 739 740 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 741 sitd->nextitd = NULL; 742 sitd->xfer = NULL; 743 744 #ifdef DIAGNOSTIC 745 sitd->isdone = true; 746 #endif 747 748 return sitd; 749 } 750 751 Static void 752 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 753 { 754 755 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 756 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 757 758 KASSERT(sitd->isdone); 759 #ifdef DIAGNOSTIC 760 /* Warn double free */ 761 sitd->isdone = false; 762 #endif 763 764 sitd->nextitd = sc->sc_freeitds; 765 sc->sc_freeitds = sitd; 766 } 767 768 void 769 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 770 { 771 772 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 773 774 mutex_enter(&sc->sc_lock); 775 ohci_free_sitd_locked(sc, sitd); 776 mutex_exit(&sc->sc_lock); 777 } 778 779 int 780 ohci_init(ohci_softc_t *sc) 781 { 782 ohci_soft_ed_t *sed, *psed; 783 usbd_status err; 784 int i; 785 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 786 787 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 788 789 aprint_normal_dev(sc->sc_dev, ""); 790 791 sc->sc_hcca = NULL; 792 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 793 794 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 795 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 796 797 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 798 ohci_rhsc_softint, sc); 799 800 for (i = 0; i < OHCI_HASH_SIZE; i++) 801 LIST_INIT(&sc->sc_hash_tds[i]); 802 for (i = 0; i < OHCI_HASH_SIZE; i++) 803 LIST_INIT(&sc->sc_hash_itds[i]); 804 805 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 806 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 807 808 rev = OREAD4(sc, OHCI_REVISION); 809 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 810 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 811 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 812 813 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 814 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 815 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 816 return -1; 817 } 818 sc->sc_bus.ub_revision = USBREV_1_0; 819 sc->sc_bus.ub_usedma = true; 820 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 821 822 /* XXX determine alignment by R/W */ 823 /* Allocate the HCCA area. */ 824 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 825 OHCI_HCCA_ALIGN, USBMALLOC_COHERENT, &sc->sc_hccadma); 826 if (err) { 827 sc->sc_hcca = NULL; 828 return err; 829 } 830 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 831 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 832 833 sc->sc_eintrs = OHCI_NORMAL_INTRS; 834 835 /* Allocate dummy ED that starts the control list. */ 836 sc->sc_ctrl_head = ohci_alloc_sed(sc); 837 if (sc->sc_ctrl_head == NULL) { 838 err = ENOMEM; 839 goto bad1; 840 } 841 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 842 843 /* Allocate dummy ED that starts the bulk list. */ 844 sc->sc_bulk_head = ohci_alloc_sed(sc); 845 if (sc->sc_bulk_head == NULL) { 846 err = ENOMEM; 847 goto bad2; 848 } 849 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 850 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 851 sizeof(sc->sc_bulk_head->ed), 852 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 853 854 /* Allocate dummy ED that starts the isochronous list. */ 855 sc->sc_isoc_head = ohci_alloc_sed(sc); 856 if (sc->sc_isoc_head == NULL) { 857 err = ENOMEM; 858 goto bad3; 859 } 860 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 861 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 862 sizeof(sc->sc_isoc_head->ed), 863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 864 865 /* Allocate all the dummy EDs that make up the interrupt tree. */ 866 for (i = 0; i < OHCI_NO_EDS; i++) { 867 sed = ohci_alloc_sed(sc); 868 if (sed == NULL) { 869 while (--i >= 0) 870 ohci_free_sed(sc, sc->sc_eds[i]); 871 err = ENOMEM; 872 goto bad4; 873 } 874 /* All ED fields are set to 0. */ 875 sc->sc_eds[i] = sed; 876 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 877 if (i != 0) 878 psed = sc->sc_eds[(i-1) / 2]; 879 else 880 psed= sc->sc_isoc_head; 881 sed->next = psed; 882 sed->ed.ed_nexted = HTOO32(psed->physaddr); 883 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 885 } 886 /* 887 * Fill HCCA interrupt table. The bit reversal is to get 888 * the tree set up properly to spread the interrupts. 889 */ 890 for (i = 0; i < OHCI_NO_INTRS; i++) 891 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 892 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 893 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 894 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 895 896 #ifdef OHCI_DEBUG 897 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 898 if (ohcidebug >= 15) { 899 for (i = 0; i < OHCI_NO_EDS; i++) { 900 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 901 ohci_dump_ed(sc, sc->sc_eds[i]); 902 } 903 DPRINTFN(15, "iso", 0, 0, 0 ,0); 904 ohci_dump_ed(sc, sc->sc_isoc_head); 905 } 906 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 907 #endif 908 909 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 910 ctl = OREAD4(sc, OHCI_CONTROL); 911 rwc = ctl & OHCI_RWC; 912 fm = OREAD4(sc, OHCI_FM_INTERVAL); 913 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 914 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 915 916 /* Determine in what context we are running. */ 917 if (ctl & OHCI_IR) { 918 /* SMM active, request change */ 919 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 920 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 921 (OHCI_OC | OHCI_MIE)) 922 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 923 s = OREAD4(sc, OHCI_COMMAND_STATUS); 924 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 925 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 926 usb_delay_ms(&sc->sc_bus, 1); 927 ctl = OREAD4(sc, OHCI_CONTROL); 928 } 929 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 930 if ((ctl & OHCI_IR) == 0) { 931 aprint_error_dev(sc->sc_dev, 932 "SMM does not respond, resetting\n"); 933 OWRITE4(sc, OHCI_CONTROL, 934 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 935 goto reset; 936 } 937 #if 0 938 /* 939 * Don't bother trying to reuse the BIOS init, we'll reset it 940 * anyway. 941 */ 942 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 943 /* BIOS started controller. */ 944 DPRINTF("BIOS active", 0, 0, 0, 0); 945 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 946 OWRITE4(sc, OHCI_CONTROL, 947 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 948 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 949 } 950 #endif 951 } else { 952 DPRINTF("cold started", 0 ,0 ,0 ,0); 953 reset: 954 /* Controller was cold started. */ 955 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 956 } 957 958 /* 959 * This reset should not be necessary according to the OHCI spec, but 960 * without it some controllers do not start. 961 */ 962 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 963 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 964 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 965 966 /* We now own the host controller and the bus has been reset. */ 967 968 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 969 /* Nominal time for a reset is 10 us. */ 970 for (i = 0; i < 10; i++) { 971 delay(10); 972 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 973 if (!hcr) 974 break; 975 } 976 if (hcr) { 977 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 978 err = EIO; 979 goto bad5; 980 } 981 #ifdef OHCI_DEBUG 982 if (ohcidebug >= 15) 983 ohci_dumpregs(sc); 984 #endif 985 986 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 987 988 /* Set up HC registers. */ 989 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 990 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 991 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 992 /* disable all interrupts and then switch on all desired interrupts */ 993 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 994 /* switch on desired functional features */ 995 ctl = OREAD4(sc, OHCI_CONTROL); 996 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 997 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 998 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 999 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1000 /* And finally start it! */ 1001 OWRITE4(sc, OHCI_CONTROL, ctl); 1002 1003 /* 1004 * The controller is now OPERATIONAL. Set a some final 1005 * registers that should be set earlier, but that the 1006 * controller ignores when in the SUSPEND state. 1007 */ 1008 ival = OHCI_FM_GET_IVAL(fm); 1009 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1010 fm |= OHCI_FSMPS(ival) | ival; 1011 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1012 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1013 OWRITE4(sc, OHCI_PERIODIC_START, per); 1014 1015 if (sc->sc_flags & OHCIF_SUPERIO) { 1016 /* no overcurrent protection */ 1017 desca |= OHCI_RHD_NOCP; 1018 /* 1019 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1020 * that 1021 * - ports are always power switched 1022 * - don't wait for powered root hub port 1023 */ 1024 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1025 } 1026 1027 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1028 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1029 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1030 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1031 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1032 1033 /* 1034 * The AMD756 requires a delay before re-reading the register, 1035 * otherwise it will occasionally report 0 ports. 1036 */ 1037 sc->sc_noport = 0; 1038 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1039 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1040 sc->sc_noport = 1041 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1042 } 1043 1044 #ifdef OHCI_DEBUG 1045 if (ohcidebug >= 5) 1046 ohci_dumpregs(sc); 1047 #endif 1048 1049 /* Set up the bus struct. */ 1050 sc->sc_bus.ub_methods = &ohci_bus_methods; 1051 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1052 1053 sc->sc_control = sc->sc_intre = 0; 1054 1055 /* Finally, turn on interrupts. */ 1056 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1057 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1058 1059 return 0; 1060 1061 bad5: 1062 for (i = 0; i < OHCI_NO_EDS; i++) 1063 ohci_free_sed(sc, sc->sc_eds[i]); 1064 bad4: 1065 ohci_free_sed(sc, sc->sc_isoc_head); 1066 bad3: 1067 ohci_free_sed(sc, sc->sc_bulk_head); 1068 bad2: 1069 ohci_free_sed(sc, sc->sc_ctrl_head); 1070 bad1: 1071 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1072 sc->sc_hcca = NULL; 1073 return err; 1074 } 1075 1076 struct usbd_xfer * 1077 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1078 { 1079 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1080 struct usbd_xfer *xfer; 1081 1082 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1083 if (xfer != NULL) { 1084 memset(xfer, 0, sizeof(struct ohci_xfer)); 1085 1086 #ifdef DIAGNOSTIC 1087 xfer->ux_state = XFER_BUSY; 1088 #endif 1089 } 1090 return xfer; 1091 } 1092 1093 void 1094 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1095 { 1096 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1097 1098 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1099 xfer->ux_status == USBD_NOT_STARTED, 1100 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1101 #ifdef DIAGNOSTIC 1102 xfer->ux_state = XFER_FREE; 1103 #endif 1104 pool_cache_put(sc->sc_xferpool, xfer); 1105 } 1106 1107 Static bool 1108 ohci_dying(struct usbd_bus *bus) 1109 { 1110 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1111 1112 return sc->sc_dying; 1113 } 1114 1115 Static void 1116 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1117 { 1118 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1119 1120 *lock = &sc->sc_lock; 1121 } 1122 1123 /* 1124 * Shut down the controller when the system is going down. 1125 */ 1126 bool 1127 ohci_shutdown(device_t self, int flags) 1128 { 1129 ohci_softc_t *sc = device_private(self); 1130 1131 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1132 1133 DPRINTF("stopping the HC", 0, 0, 0, 0); 1134 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1135 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1136 return true; 1137 } 1138 1139 bool 1140 ohci_resume(device_t dv, const pmf_qual_t *qual) 1141 { 1142 ohci_softc_t *sc = device_private(dv); 1143 uint32_t ctl; 1144 1145 mutex_spin_enter(&sc->sc_intr_lock); 1146 sc->sc_bus.ub_usepolling++; 1147 mutex_spin_exit(&sc->sc_intr_lock); 1148 1149 /* Some broken BIOSes do not recover these values */ 1150 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1151 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1152 sc->sc_ctrl_head->physaddr); 1153 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1154 sc->sc_bulk_head->physaddr); 1155 if (sc->sc_intre) 1156 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1157 (OHCI_ALL_INTRS | OHCI_MIE)); 1158 if (sc->sc_control) 1159 ctl = sc->sc_control; 1160 else 1161 ctl = OREAD4(sc, OHCI_CONTROL); 1162 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1163 OWRITE4(sc, OHCI_CONTROL, ctl); 1164 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1165 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1166 OWRITE4(sc, OHCI_CONTROL, ctl); 1167 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1168 sc->sc_control = sc->sc_intre = 0; 1169 1170 mutex_spin_enter(&sc->sc_intr_lock); 1171 sc->sc_bus.ub_usepolling--; 1172 mutex_spin_exit(&sc->sc_intr_lock); 1173 1174 return true; 1175 } 1176 1177 bool 1178 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1179 { 1180 ohci_softc_t *sc = device_private(dv); 1181 uint32_t ctl; 1182 1183 mutex_spin_enter(&sc->sc_intr_lock); 1184 sc->sc_bus.ub_usepolling++; 1185 mutex_spin_exit(&sc->sc_intr_lock); 1186 1187 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1188 if (sc->sc_control == 0) { 1189 /* 1190 * Preserve register values, in case that BIOS 1191 * does not recover them. 1192 */ 1193 sc->sc_control = ctl; 1194 sc->sc_intre = OREAD4(sc, 1195 OHCI_INTERRUPT_ENABLE); 1196 } 1197 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1198 OWRITE4(sc, OHCI_CONTROL, ctl); 1199 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1200 1201 mutex_spin_enter(&sc->sc_intr_lock); 1202 sc->sc_bus.ub_usepolling--; 1203 mutex_spin_exit(&sc->sc_intr_lock); 1204 1205 return true; 1206 } 1207 1208 #ifdef OHCI_DEBUG 1209 void 1210 ohci_dumpregs(ohci_softc_t *sc) 1211 { 1212 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1213 1214 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1215 OREAD4(sc, OHCI_REVISION), 1216 OREAD4(sc, OHCI_CONTROL), 1217 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1218 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1219 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1220 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1221 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1222 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1223 OREAD4(sc, OHCI_HCCA), 1224 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1225 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1226 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1227 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1228 OREAD4(sc, OHCI_BULK_HEAD_ED), 1229 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1230 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1231 OREAD4(sc, OHCI_DONE_HEAD), 1232 OREAD4(sc, OHCI_FM_INTERVAL), 1233 OREAD4(sc, OHCI_FM_REMAINING), 0); 1234 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1235 OREAD4(sc, OHCI_FM_NUMBER), 1236 OREAD4(sc, OHCI_PERIODIC_START), 1237 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1238 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1239 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1240 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1241 OREAD4(sc, OHCI_RH_STATUS), 0); 1242 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1243 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1244 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1245 usb_syncmem(&sc->sc_hccadma, 1246 offsetof(struct ohci_hcca, hcca_frame_number), 1247 sizeof(sc->sc_hcca->hcca_frame_number) + 1248 sizeof(sc->sc_hcca->hcca_done_head), 1249 BUS_DMASYNC_POSTREAD); 1250 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1251 O32TOH(sc->sc_hcca->hcca_frame_number), 1252 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1253 } 1254 #endif 1255 1256 Static int ohci_intr1(ohci_softc_t *); 1257 1258 int 1259 ohci_intr(void *p) 1260 { 1261 ohci_softc_t *sc = p; 1262 int ret = 0; 1263 1264 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1265 1266 if (sc == NULL) 1267 return 0; 1268 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 1271 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1272 goto done; 1273 1274 /* If we get an interrupt while polling, then just ignore it. */ 1275 if (sc->sc_bus.ub_usepolling) { 1276 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1277 /* for level triggered intrs, should do something to ack */ 1278 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1279 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1280 1281 goto done; 1282 } 1283 1284 ret = ohci_intr1(sc); 1285 1286 done: 1287 mutex_spin_exit(&sc->sc_intr_lock); 1288 return ret; 1289 } 1290 1291 Static int 1292 ohci_intr1(ohci_softc_t *sc) 1293 { 1294 uint32_t intrs, eintrs; 1295 1296 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1297 1298 /* In case the interrupt occurs before initialization has completed. */ 1299 if (sc == NULL || sc->sc_hcca == NULL) { 1300 #ifdef DIAGNOSTIC 1301 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1302 #endif 1303 return 0; 1304 } 1305 1306 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1307 1308 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1309 if (!intrs) 1310 return 0; 1311 1312 /* Acknowledge */ 1313 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1314 eintrs = intrs & sc->sc_eintrs; 1315 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1316 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1317 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1318 sc->sc_eintrs); 1319 1320 if (!eintrs) { 1321 return 0; 1322 } 1323 1324 if (eintrs & OHCI_SO) { 1325 sc->sc_overrun_cnt++; 1326 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1327 printf("%s: %u scheduling overruns\n", 1328 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1329 sc->sc_overrun_cnt = 0; 1330 } 1331 /* XXX do what */ 1332 eintrs &= ~OHCI_SO; 1333 } 1334 if (eintrs & OHCI_WDH) { 1335 /* 1336 * We block the interrupt below, and reenable it later from 1337 * ohci_softintr(). 1338 */ 1339 usb_schedsoftintr(&sc->sc_bus); 1340 } 1341 if (eintrs & OHCI_RD) { 1342 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1343 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1344 /* XXX process resume detect */ 1345 } 1346 if (eintrs & OHCI_UE) { 1347 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1348 printf("%s: unrecoverable error, controller halted\n", 1349 device_xname(sc->sc_dev)); 1350 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1351 /* XXX what else */ 1352 } 1353 if (eintrs & OHCI_RHSC) { 1354 /* 1355 * We block the interrupt below, and reenable it later from 1356 * a timeout. 1357 */ 1358 softint_schedule(sc->sc_rhsc_si); 1359 } 1360 1361 if (eintrs != 0) { 1362 /* Block unprocessed interrupts. */ 1363 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1364 sc->sc_eintrs &= ~eintrs; 1365 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1366 eintrs, 0, 0); 1367 } 1368 1369 return 1; 1370 } 1371 1372 void 1373 ohci_rhsc_enable(void *v_sc) 1374 { 1375 ohci_softc_t *sc = v_sc; 1376 1377 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1378 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1379 mutex_spin_enter(&sc->sc_intr_lock); 1380 sc->sc_eintrs |= OHCI_RHSC; 1381 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1382 mutex_spin_exit(&sc->sc_intr_lock); 1383 } 1384 1385 #ifdef OHCI_DEBUG 1386 const char *ohci_cc_strs[] = { 1387 "NO_ERROR", 1388 "CRC", 1389 "BIT_STUFFING", 1390 "DATA_TOGGLE_MISMATCH", 1391 "STALL", 1392 "DEVICE_NOT_RESPONDING", 1393 "PID_CHECK_FAILURE", 1394 "UNEXPECTED_PID", 1395 "DATA_OVERRUN", 1396 "DATA_UNDERRUN", 1397 "BUFFER_OVERRUN", 1398 "BUFFER_UNDERRUN", 1399 "reserved", 1400 "reserved", 1401 "NOT_ACCESSED", 1402 "NOT_ACCESSED", 1403 }; 1404 #endif 1405 1406 void 1407 ohci_softintr(void *v) 1408 { 1409 struct usbd_bus *bus = v; 1410 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1411 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1412 ohci_soft_td_t *std, *sdone, *stdnext; 1413 struct usbd_xfer *xfer; 1414 struct ohci_pipe *opipe; 1415 int len, cc; 1416 int i, j, actlen, iframes, uedir; 1417 ohci_physaddr_t done; 1418 1419 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1420 1421 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1422 1423 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1424 sizeof(sc->sc_hcca->hcca_done_head), 1425 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1426 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1427 sc->sc_hcca->hcca_done_head = 0; 1428 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1429 sizeof(sc->sc_hcca->hcca_done_head), 1430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1431 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1432 sc->sc_eintrs |= OHCI_WDH; 1433 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1434 1435 /* Reverse the done list. */ 1436 for (sdone = NULL, sidone = NULL; done != 0; ) { 1437 std = ohci_hash_find_td(sc, done); 1438 if (std != NULL) { 1439 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1440 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1441 std->dnext = sdone; 1442 done = O32TOH(std->td.td_nexttd); 1443 sdone = std; 1444 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1445 continue; 1446 } 1447 sitd = ohci_hash_find_itd(sc, done); 1448 if (sitd != NULL) { 1449 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1450 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1451 sitd->dnext = sidone; 1452 done = O32TOH(sitd->itd.itd_nextitd); 1453 sidone = sitd; 1454 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1455 continue; 1456 } 1457 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1458 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1459 (u_long)done); 1460 break; 1461 } 1462 1463 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1464 (uintptr_t)sidone, 0, 0); 1465 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1466 #ifdef OHCI_DEBUG 1467 if (ohcidebug >= 10) { 1468 for (std = sdone; std; std = std->dnext) 1469 ohci_dump_td(sc, std); 1470 } 1471 #endif 1472 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1473 1474 for (std = sdone; std; std = stdnext) { 1475 xfer = std->xfer; 1476 stdnext = std->dnext; 1477 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1478 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1479 0); 1480 if (xfer == NULL) { 1481 /* 1482 * xfer == NULL: There seems to be no xfer associated 1483 * with this TD. It is tailp that happened to end up on 1484 * the done queue. 1485 * Shouldn't happen, but some chips are broken(?). 1486 */ 1487 continue; 1488 } 1489 1490 /* 1491 * Try to claim this xfer for completion. If it has 1492 * already completed or aborted, drop it on the floor. 1493 */ 1494 if (!usbd_xfer_trycomplete(xfer)) 1495 continue; 1496 1497 len = std->len; 1498 if (std->td.td_cbp != 0) 1499 len -= O32TOH(std->td.td_be) - 1500 O32TOH(std->td.td_cbp) + 1; 1501 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1502 if (std->flags & OHCI_ADD_LEN) 1503 xfer->ux_actlen += len; 1504 1505 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1506 if (cc == OHCI_CC_NO_ERROR) { 1507 ohci_hash_rem_td(sc, std); 1508 if (std->flags & OHCI_CALL_DONE) { 1509 xfer->ux_status = USBD_NORMAL_COMPLETION; 1510 usb_transfer_complete(xfer); 1511 } 1512 } else { 1513 /* 1514 * Endpoint is halted. First unlink all the TDs 1515 * belonging to the failed transfer, and then restart 1516 * the endpoint. 1517 */ 1518 ohci_soft_td_t *p, *n; 1519 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1520 1521 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1522 1523 /* remove xfer's TDs from the hash */ 1524 for (p = std; p->xfer == xfer; p = n) { 1525 n = p->nexttd; 1526 ohci_hash_rem_td(sc, p); 1527 } 1528 1529 ohci_soft_ed_t *sed = opipe->sed; 1530 1531 /* clear halt and TD chain, preserving toggle carry */ 1532 sed->ed.ed_headp = HTOO32(p->physaddr | 1533 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1534 usb_syncmem(&sed->dma, 1535 sed->offs + offsetof(ohci_ed_t, ed_headp), 1536 sizeof(sed->ed.ed_headp), 1537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1538 1539 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1540 1541 if (cc == OHCI_CC_DATA_UNDERRUN) 1542 xfer->ux_status = USBD_NORMAL_COMPLETION; 1543 else if (cc == OHCI_CC_STALL) 1544 xfer->ux_status = USBD_STALLED; 1545 else 1546 xfer->ux_status = USBD_IOERROR; 1547 usb_transfer_complete(xfer); 1548 } 1549 } 1550 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1551 #ifdef OHCI_DEBUG 1552 if (ohcidebug >= 10) { 1553 for (sitd = sidone; sitd; sitd = sitd->dnext) 1554 ohci_dump_itd(sc, sitd); 1555 } 1556 #endif 1557 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1558 1559 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1560 xfer = sitd->xfer; 1561 sitdnext = sitd->dnext; 1562 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1563 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1564 0); 1565 if (xfer == NULL) 1566 continue; 1567 1568 /* 1569 * Try to claim this xfer for completion. If it has 1570 * already completed or aborted, drop it on the floor. 1571 */ 1572 if (!usbd_xfer_trycomplete(xfer)) 1573 continue; 1574 1575 KASSERT(!sitd->isdone); 1576 #ifdef DIAGNOSTIC 1577 sitd->isdone = true; 1578 #endif 1579 if (sitd->flags & OHCI_CALL_DONE) { 1580 ohci_soft_itd_t *next; 1581 1582 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1583 opipe->isoc.inuse -= xfer->ux_nframes; 1584 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1585 bEndpointAddress); 1586 xfer->ux_status = USBD_NORMAL_COMPLETION; 1587 actlen = 0; 1588 for (i = 0, sitd = xfer->ux_hcpriv;; 1589 sitd = next) { 1590 next = sitd->nextitd; 1591 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1592 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1593 xfer->ux_status = USBD_IOERROR; 1594 /* For input, update frlengths with actual */ 1595 /* XXX anything necessary for output? */ 1596 if (uedir == UE_DIR_IN && 1597 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1598 iframes = OHCI_ITD_GET_FC(O32TOH( 1599 sitd->itd.itd_flags)); 1600 for (j = 0; j < iframes; i++, j++) { 1601 len = O16TOH(sitd-> 1602 itd.itd_offset[j]); 1603 if ((OHCI_ITD_PSW_GET_CC(len) & 1604 OHCI_CC_NOT_ACCESSED_MASK) 1605 == OHCI_CC_NOT_ACCESSED) 1606 len = 0; 1607 else 1608 len = OHCI_ITD_PSW_SIZE(len); 1609 xfer->ux_frlengths[i] = len; 1610 actlen += len; 1611 } 1612 } 1613 if (sitd->flags & OHCI_CALL_DONE) 1614 break; 1615 ohci_hash_rem_itd(sc, sitd); 1616 1617 } 1618 ohci_hash_rem_itd(sc, sitd); 1619 if (uedir == UE_DIR_IN && 1620 xfer->ux_status == USBD_NORMAL_COMPLETION) 1621 xfer->ux_actlen = actlen; 1622 xfer->ux_hcpriv = NULL; 1623 1624 usb_transfer_complete(xfer); 1625 } 1626 } 1627 1628 DPRINTFN(10, "done", 0, 0, 0, 0); 1629 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1630 } 1631 1632 void 1633 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1634 { 1635 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1636 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1637 int len = UGETW(xfer->ux_request.wLength); 1638 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1639 1640 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1641 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1642 1643 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1644 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1645 1646 if (len) 1647 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1648 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1649 usb_syncmem(&opipe->ctrl.reqdma, 0, 1650 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1651 } 1652 1653 void 1654 ohci_device_intr_done(struct usbd_xfer *xfer) 1655 { 1656 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1657 int isread = 1658 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1659 1660 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1661 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1662 xfer->ux_actlen, 0, 0); 1663 1664 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1665 1666 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1667 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1668 } 1669 1670 void 1671 ohci_device_bulk_done(struct usbd_xfer *xfer) 1672 { 1673 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1674 1675 int isread = 1676 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1677 1678 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1679 1680 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1681 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1682 0, 0); 1683 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1684 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1685 } 1686 1687 Static void 1688 ohci_rhsc_softint(void *arg) 1689 { 1690 ohci_softc_t *sc = arg; 1691 1692 mutex_enter(&sc->sc_lock); 1693 1694 ohci_rhsc(sc, sc->sc_intrxfer); 1695 1696 /* Do not allow RHSC interrupts > 1 per second */ 1697 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1698 1699 mutex_exit(&sc->sc_lock); 1700 } 1701 1702 void 1703 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1704 { 1705 u_char *p; 1706 int i, m; 1707 int hstatus __unused; 1708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1709 1710 KASSERT(mutex_owned(&sc->sc_lock)); 1711 1712 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1713 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1714 (uintptr_t)xfer, hstatus, 0); 1715 1716 if (xfer == NULL) { 1717 /* Just ignore the change. */ 1718 return; 1719 } 1720 KASSERT(xfer == sc->sc_intrxfer); 1721 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1722 1723 p = xfer->ux_buf; 1724 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1725 memset(p, 0, xfer->ux_length); 1726 for (i = 1; i <= m; i++) { 1727 /* Pick out CHANGE bits from the status reg. */ 1728 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1729 p[i/8] |= 1 << (i%8); 1730 } 1731 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1732 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1733 xfer->ux_actlen = xfer->ux_length; 1734 xfer->ux_status = USBD_NORMAL_COMPLETION; 1735 1736 usb_transfer_complete(xfer); 1737 } 1738 1739 void 1740 ohci_root_intr_done(struct usbd_xfer *xfer) 1741 { 1742 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1743 1744 KASSERT(mutex_owned(&sc->sc_lock)); 1745 1746 /* Claim the xfer so it doesn't get completed again. */ 1747 KASSERT(sc->sc_intrxfer == xfer); 1748 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1749 sc->sc_intrxfer = NULL; 1750 } 1751 1752 void 1753 ohci_poll(struct usbd_bus *bus) 1754 { 1755 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1756 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1757 1758 #ifdef OHCI_DEBUG 1759 static int last; 1760 int new; 1761 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1762 if (new != last) { 1763 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1764 last = new; 1765 } 1766 #endif 1767 sc->sc_eintrs |= OHCI_WDH; 1768 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1769 mutex_spin_enter(&sc->sc_intr_lock); 1770 ohci_intr1(sc); 1771 mutex_spin_exit(&sc->sc_intr_lock); 1772 } 1773 } 1774 1775 /* 1776 * Add an ED to the schedule. Called with USB lock held. 1777 */ 1778 Static void 1779 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1780 { 1781 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1782 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1783 0); 1784 1785 KASSERT(mutex_owned(&sc->sc_lock)); 1786 1787 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1788 sizeof(head->ed.ed_nexted), 1789 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1790 sed->next = head->next; 1791 sed->ed.ed_nexted = head->ed.ed_nexted; 1792 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1793 sizeof(sed->ed.ed_nexted), 1794 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1795 head->next = sed; 1796 head->ed.ed_nexted = HTOO32(sed->physaddr); 1797 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1798 sizeof(head->ed.ed_nexted), 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 } 1801 1802 /* 1803 * Remove an ED from the schedule. Called with USB lock held. 1804 */ 1805 Static void 1806 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1807 { 1808 ohci_soft_ed_t *p; 1809 1810 KASSERT(mutex_owned(&sc->sc_lock)); 1811 1812 /* XXX */ 1813 for (p = head; p != NULL && p->next != sed; p = p->next) 1814 ; 1815 KASSERT(p != NULL); 1816 1817 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1818 sizeof(sed->ed.ed_nexted), 1819 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1820 p->next = sed->next; 1821 p->ed.ed_nexted = sed->ed.ed_nexted; 1822 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1823 sizeof(p->ed.ed_nexted), 1824 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1825 } 1826 1827 /* 1828 * When a transfer is completed the TD is added to the done queue by 1829 * the host controller. This queue is the processed by software. 1830 * Unfortunately the queue contains the physical address of the TD 1831 * and we have no simple way to translate this back to a kernel address. 1832 * To make the translation possible (and fast) we use a hash table of 1833 * TDs currently in the schedule. The physical address is used as the 1834 * hash value. 1835 */ 1836 1837 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1838 /* Called with USB lock held. */ 1839 void 1840 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1841 { 1842 int h = HASH(std->physaddr); 1843 1844 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1845 1846 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1847 } 1848 1849 /* Called with USB lock held. */ 1850 void 1851 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1852 { 1853 1854 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1855 1856 LIST_REMOVE(std, hnext); 1857 } 1858 1859 ohci_soft_td_t * 1860 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1861 { 1862 int h = HASH(a); 1863 ohci_soft_td_t *std; 1864 1865 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1866 std != NULL; 1867 std = LIST_NEXT(std, hnext)) 1868 if (std->physaddr == a) 1869 return std; 1870 return NULL; 1871 } 1872 1873 /* Called with USB lock held. */ 1874 void 1875 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1876 { 1877 int h = HASH(sitd->physaddr); 1878 1879 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1880 1881 KASSERT(mutex_owned(&sc->sc_lock)); 1882 1883 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1884 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1885 1886 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1887 } 1888 1889 /* Called with USB lock held. */ 1890 void 1891 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1892 { 1893 1894 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1895 1896 KASSERT(mutex_owned(&sc->sc_lock)); 1897 1898 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1899 sitd->physaddr, 0, 0); 1900 1901 LIST_REMOVE(sitd, hnext); 1902 } 1903 1904 ohci_soft_itd_t * 1905 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1906 { 1907 int h = HASH(a); 1908 ohci_soft_itd_t *sitd; 1909 1910 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1911 sitd != NULL; 1912 sitd = LIST_NEXT(sitd, hnext)) 1913 if (sitd->physaddr == a) 1914 return sitd; 1915 return NULL; 1916 } 1917 1918 #ifdef OHCI_DEBUG 1919 void 1920 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1921 { 1922 for (; std; std = std->nexttd) { 1923 ohci_dump_td(sc, std); 1924 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1925 "std %p next %p", std, std->nexttd); 1926 } 1927 } 1928 1929 void 1930 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1931 { 1932 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1933 1934 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1935 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1936 1937 uint32_t flags = O32TOH(std->td.td_flags); 1938 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1939 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1940 !!(flags & OHCI_TD_R), 1941 OHCI_TD_GET_DP(flags), 1942 OHCI_TD_GET_DI(flags), 1943 OHCI_TD_GET_TOGGLE(flags)); 1944 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1945 OHCI_TD_GET_CC(flags), 0, 0); 1946 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1947 (u_long)O32TOH(std->td.td_cbp), 1948 (u_long)O32TOH(std->td.td_nexttd), 1949 (u_long)O32TOH(std->td.td_be), 0); 1950 } 1951 1952 void 1953 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1954 { 1955 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1956 1957 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1958 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1959 1960 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1961 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1962 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1963 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1964 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1965 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1966 O32TOH(sitd->itd.itd_bp0), 1967 O32TOH(sitd->itd.itd_nextitd), 1968 O32TOH(sitd->itd.itd_be), 0); 1969 CTASSERT(OHCI_ITD_NOFFSET == 8); 1970 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1971 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1972 O16TOH(sitd->itd.itd_offset[0]), 1973 O16TOH(sitd->itd.itd_offset[1]), 1974 O16TOH(sitd->itd.itd_offset[2]), 1975 O16TOH(sitd->itd.itd_offset[3])); 1976 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1977 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1978 O16TOH(sitd->itd.itd_offset[4]), 1979 O16TOH(sitd->itd.itd_offset[5]), 1980 O16TOH(sitd->itd.itd_offset[6]), 1981 O16TOH(sitd->itd.itd_offset[7])); 1982 } 1983 1984 void 1985 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1986 { 1987 for (; sitd; sitd = sitd->nextitd) 1988 ohci_dump_itd(sc, sitd); 1989 } 1990 1991 void 1992 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1993 { 1994 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1995 1996 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1997 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1998 1999 uint32_t flags = O32TOH(sed->ed.ed_flags); 2000 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2001 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2002 OHCI_ED_GET_FA(flags), 2003 OHCI_ED_GET_EN(flags), 2004 OHCI_ED_GET_MAXP(flags), 2005 0); 2006 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2007 OHCI_ED_GET_DIR(flags), 2008 __SHIFTOUT(flags, OHCI_ED_SPEED), 2009 __SHIFTOUT(flags, OHCI_ED_SKIP), 2010 OHCI_ED_GET_FORMAT(flags)); 2011 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2012 0, 0, 0); 2013 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2014 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2015 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2016 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2017 } 2018 #endif 2019 2020 usbd_status 2021 ohci_open(struct usbd_pipe *pipe) 2022 { 2023 struct usbd_device *dev = pipe->up_dev; 2024 struct usbd_bus *bus = dev->ud_bus; 2025 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2026 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2027 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2028 uint8_t addr = dev->ud_addr; 2029 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2030 ohci_soft_ed_t *sed; 2031 ohci_soft_td_t *std; 2032 ohci_soft_itd_t *sitd; 2033 ohci_physaddr_t tdphys; 2034 uint32_t fmt; 2035 usbd_status err = USBD_NOMEM; 2036 int ival; 2037 2038 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2039 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2040 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2041 2042 if (sc->sc_dying) { 2043 return USBD_IOERROR; 2044 } 2045 2046 std = NULL; 2047 sed = NULL; 2048 2049 if (addr == bus->ub_rhaddr) { 2050 switch (ed->bEndpointAddress) { 2051 case USB_CONTROL_ENDPOINT: 2052 pipe->up_methods = &roothub_ctrl_methods; 2053 break; 2054 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2055 pipe->up_methods = &ohci_root_intr_methods; 2056 break; 2057 default: 2058 err = USBD_INVAL; 2059 goto bad; 2060 } 2061 } else { 2062 sed = ohci_alloc_sed(sc); 2063 if (sed == NULL) 2064 goto bad; 2065 opipe->sed = sed; 2066 if (xfertype == UE_ISOCHRONOUS) { 2067 sitd = ohci_alloc_sitd(sc); 2068 if (sitd == NULL) 2069 goto bad; 2070 2071 opipe->tail.itd = sitd; 2072 tdphys = sitd->physaddr; 2073 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2074 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2075 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2076 else 2077 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2078 } else { 2079 std = ohci_alloc_std(sc); 2080 if (std == NULL) 2081 goto bad; 2082 2083 opipe->tail.td = std; 2084 tdphys = std->physaddr; 2085 fmt = 2086 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2087 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2088 } 2089 sed->ed.ed_flags = HTOO32( 2090 OHCI_ED_SET_FA(addr) | 2091 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2092 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2093 fmt | 2094 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2095 sed->ed.ed_headp = HTOO32(tdphys | 2096 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2097 sed->ed.ed_tailp = HTOO32(tdphys); 2098 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2100 2101 switch (xfertype) { 2102 case UE_CONTROL: 2103 pipe->up_methods = &ohci_device_ctrl_methods; 2104 err = usb_allocmem(&sc->sc_bus, 2105 sizeof(usb_device_request_t), 0, 2106 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2107 if (err) 2108 goto bad; 2109 mutex_enter(&sc->sc_lock); 2110 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2111 mutex_exit(&sc->sc_lock); 2112 break; 2113 case UE_INTERRUPT: 2114 pipe->up_methods = &ohci_device_intr_methods; 2115 ival = pipe->up_interval; 2116 if (ival == USBD_DEFAULT_INTERVAL) 2117 ival = ed->bInterval; 2118 err = ohci_device_setintr(sc, opipe, ival); 2119 if (err) 2120 goto bad; 2121 break; 2122 case UE_ISOCHRONOUS: 2123 pipe->up_serialise = false; 2124 pipe->up_methods = &ohci_device_isoc_methods; 2125 return ohci_setup_isoc(pipe); 2126 case UE_BULK: 2127 pipe->up_methods = &ohci_device_bulk_methods; 2128 mutex_enter(&sc->sc_lock); 2129 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2130 mutex_exit(&sc->sc_lock); 2131 break; 2132 } 2133 } 2134 2135 return USBD_NORMAL_COMPLETION; 2136 2137 bad: 2138 if (std != NULL) { 2139 ohci_free_std(sc, std); 2140 } 2141 if (sed != NULL) 2142 ohci_free_sed(sc, sed); 2143 return err; 2144 2145 } 2146 2147 /* 2148 * Close a reqular pipe. 2149 * Assumes that there are no pending transactions. 2150 */ 2151 void 2152 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2153 { 2154 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2155 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2156 ohci_soft_ed_t *sed = opipe->sed; 2157 2158 KASSERT(mutex_owned(&sc->sc_lock)); 2159 2160 #ifdef DIAGNOSTIC 2161 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2162 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2163 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2164 ohci_soft_td_t *std; 2165 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2166 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2167 "tl=%#x pipe=%p, std=%p\n", sed, 2168 (int)O32TOH(sed->ed.ed_headp), 2169 (int)O32TOH(sed->ed.ed_tailp), 2170 pipe, std); 2171 #ifdef OHCI_DEBUG 2172 usbd_dump_pipe(&opipe->pipe); 2173 ohci_dump_ed(sc, sed); 2174 if (std) 2175 ohci_dump_td(sc, std); 2176 #endif 2177 usb_delay_ms(&sc->sc_bus, 2); 2178 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2179 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2180 printf("ohci_close_pipe: pipe still not empty\n"); 2181 } 2182 #endif 2183 ohci_rem_ed(sc, sed, head); 2184 /* Make sure the host controller is not touching this ED */ 2185 usb_delay_ms(&sc->sc_bus, 1); 2186 pipe->up_endpoint->ue_toggle = 2187 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2188 ohci_free_sed_locked(sc, opipe->sed); 2189 } 2190 2191 /* 2192 * Arrange for the hardware to tells us that it is not still processing 2193 * the TDs by setting the sKip bit and requesting a SOF interrupt 2194 * 2195 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2196 * they've been processed and either 2197 * a) if they're unused recover them for later use, or 2198 * b) if they've been used allocate new TD/iTDs to replace those 2199 * used. The softint handler will free the old ones. 2200 */ 2201 void 2202 ohci_abortx(struct usbd_xfer *xfer) 2203 { 2204 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2205 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2206 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2207 ohci_soft_ed_t *sed = opipe->sed; 2208 ohci_soft_td_t *p, *n; 2209 ohci_physaddr_t headp; 2210 int hit; 2211 2212 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2213 (uintptr_t)opipe, (uintptr_t)sed, 0); 2214 2215 KASSERT(mutex_owned(&sc->sc_lock)); 2216 ASSERT_SLEEPABLE(); 2217 2218 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2219 xfer->ux_status == USBD_TIMEOUT), 2220 "bad abort status: %d", xfer->ux_status); 2221 2222 /* 2223 * If we're dying, skip the hardware action and just notify the 2224 * software that we're done. 2225 */ 2226 if (sc->sc_dying) { 2227 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2228 xfer->ux_status, 0, 0); 2229 goto dying; 2230 } 2231 2232 /* 2233 * HC Step 1: Unless the endpoint is already halted, we set the endpoint 2234 * descriptor sKip bit and wait for hardware to complete processing. 2235 * 2236 * This includes ensuring that any TDs of the transfer that got onto 2237 * the done list are also removed. We ensure this by waiting for 2238 * both a WDH and SOF interrupt. 2239 */ 2240 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2241 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2242 sizeof(sed->ed.ed_flags), 2243 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2244 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2245 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2246 sizeof(sed->ed.ed_flags), 2247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2248 2249 /* 2250 * HC Step 2: Wait until we know hardware has finished any possible 2251 * use of the xfer. 2252 */ 2253 /* Hardware finishes in 1ms */ 2254 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2255 2256 /* 2257 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2258 * The complication here is that the hardware may have executed 2259 * beyond the xfer we're trying to abort. So as we're scanning 2260 * the TDs of this xfer we check if the hardware points to 2261 * any of them. 2262 */ 2263 p = xfer->ux_hcpriv; 2264 KASSERT(p); 2265 2266 #ifdef OHCI_DEBUG 2267 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2268 2269 if (ohcidebug >= 2) { 2270 DPRINTF("sed:", 0, 0, 0, 0); 2271 ohci_dump_ed(sc, sed); 2272 ohci_dump_tds(sc, p); 2273 } 2274 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2275 #endif 2276 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2277 hit = 0; 2278 for (; p->xfer == xfer; p = n) { 2279 hit |= headp == p->physaddr; 2280 n = p->nexttd; 2281 ohci_hash_rem_td(sc, p); 2282 } 2283 /* Zap headp register if hardware pointed inside the xfer. */ 2284 if (hit) { 2285 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2286 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2287 /* unlink TDs, preserving toggle carry */ 2288 sed->ed.ed_headp = HTOO32(p->physaddr | 2289 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2290 usb_syncmem(&sed->dma, 2291 sed->offs + offsetof(ohci_ed_t, ed_headp), 2292 sizeof(sed->ed.ed_headp), 2293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2294 } else { 2295 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2296 } 2297 2298 /* 2299 * HC Step 4: Turn on hardware again. 2300 */ 2301 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2302 sizeof(sed->ed.ed_flags), 2303 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2304 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2305 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2306 sizeof(sed->ed.ed_flags), 2307 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2308 2309 /* 2310 * Final step: Notify completion to waiting xfers. 2311 */ 2312 dying: 2313 usb_transfer_complete(xfer); 2314 DPRINTFN(14, "end", 0, 0, 0, 0); 2315 2316 KASSERT(mutex_owned(&sc->sc_lock)); 2317 } 2318 2319 /* 2320 * Data structures and routines to emulate the root hub. 2321 */ 2322 Static int 2323 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2324 void *buf, int buflen) 2325 { 2326 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2327 usb_port_status_t ps; 2328 uint16_t len, value, index; 2329 int l, totlen = 0; 2330 int port, i; 2331 uint32_t v; 2332 2333 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2334 2335 if (sc->sc_dying) 2336 return -1; 2337 2338 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2339 req->bRequest, 0, 0); 2340 2341 len = UGETW(req->wLength); 2342 value = UGETW(req->wValue); 2343 index = UGETW(req->wIndex); 2344 2345 #define C(x,y) ((x) | ((y) << 8)) 2346 switch (C(req->bRequest, req->bmRequestType)) { 2347 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2348 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2349 if (len == 0) 2350 break; 2351 switch (value) { 2352 #define sd ((usb_string_descriptor_t *)buf) 2353 case C(2, UDESC_STRING): 2354 /* Product */ 2355 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2356 break; 2357 #undef sd 2358 default: 2359 /* default from usbroothub */ 2360 return buflen; 2361 } 2362 break; 2363 2364 /* Hub requests */ 2365 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2366 break; 2367 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2368 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2369 index, value, 0, 0); 2370 if (index < 1 || index > sc->sc_noport) { 2371 return -1; 2372 } 2373 port = OHCI_RH_PORT_STATUS(index); 2374 switch(value) { 2375 case UHF_PORT_ENABLE: 2376 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2377 break; 2378 case UHF_PORT_SUSPEND: 2379 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2380 break; 2381 case UHF_PORT_POWER: 2382 /* Yes, writing to the LOW_SPEED bit clears power. */ 2383 OWRITE4(sc, port, UPS_LOW_SPEED); 2384 break; 2385 case UHF_C_PORT_CONNECTION: 2386 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2387 break; 2388 case UHF_C_PORT_ENABLE: 2389 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2390 break; 2391 case UHF_C_PORT_SUSPEND: 2392 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2393 break; 2394 case UHF_C_PORT_OVER_CURRENT: 2395 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2396 break; 2397 case UHF_C_PORT_RESET: 2398 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2399 break; 2400 default: 2401 return -1; 2402 } 2403 switch(value) { 2404 case UHF_C_PORT_CONNECTION: 2405 case UHF_C_PORT_ENABLE: 2406 case UHF_C_PORT_SUSPEND: 2407 case UHF_C_PORT_OVER_CURRENT: 2408 case UHF_C_PORT_RESET: 2409 /* Enable RHSC interrupt if condition is cleared. */ 2410 if ((OREAD4(sc, port) >> 16) == 0) 2411 ohci_rhsc_enable(sc); 2412 break; 2413 default: 2414 break; 2415 } 2416 break; 2417 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2418 if (len == 0) 2419 break; 2420 if ((value & 0xff) != 0) { 2421 return -1; 2422 } 2423 usb_hub_descriptor_t hubd; 2424 2425 totlen = uimin(buflen, sizeof(hubd)); 2426 memcpy(&hubd, buf, totlen); 2427 2428 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2429 hubd.bNbrPorts = sc->sc_noport; 2430 USETW(hubd.wHubCharacteristics, 2431 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2432 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2433 /* XXX overcurrent */ 2434 ); 2435 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2436 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2437 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2438 hubd.DeviceRemovable[i++] = (uint8_t)v; 2439 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2440 totlen = uimin(totlen, hubd.bDescLength); 2441 memcpy(buf, &hubd, totlen); 2442 break; 2443 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2444 if (len != 4) { 2445 return -1; 2446 } 2447 memset(buf, 0, len); /* ? XXX */ 2448 totlen = len; 2449 break; 2450 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2451 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2452 if (index < 1 || index > sc->sc_noport) { 2453 return -1; 2454 } 2455 if (len != 4) { 2456 return -1; 2457 } 2458 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2459 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2460 USETW(ps.wPortStatus, v); 2461 USETW(ps.wPortChange, v >> 16); 2462 totlen = uimin(len, sizeof(ps)); 2463 memcpy(buf, &ps, totlen); 2464 break; 2465 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2466 return -1; 2467 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2468 break; 2469 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2470 if (index < 1 || index > sc->sc_noport) { 2471 return -1; 2472 } 2473 port = OHCI_RH_PORT_STATUS(index); 2474 switch(value) { 2475 case UHF_PORT_ENABLE: 2476 OWRITE4(sc, port, UPS_PORT_ENABLED); 2477 break; 2478 case UHF_PORT_SUSPEND: 2479 OWRITE4(sc, port, UPS_SUSPEND); 2480 break; 2481 case UHF_PORT_RESET: 2482 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2483 OWRITE4(sc, port, UPS_RESET); 2484 for (i = 0; i < 5; i++) { 2485 usb_delay_ms(&sc->sc_bus, 2486 USB_PORT_ROOT_RESET_DELAY); 2487 if (sc->sc_dying) { 2488 return -1; 2489 } 2490 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2491 break; 2492 } 2493 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2494 OREAD4(sc, port), 0, 0); 2495 break; 2496 case UHF_PORT_POWER: 2497 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2498 OWRITE4(sc, port, UPS_PORT_POWER); 2499 break; 2500 default: 2501 return -1; 2502 } 2503 break; 2504 default: 2505 /* default from usbroothub */ 2506 return buflen; 2507 } 2508 2509 return totlen; 2510 } 2511 2512 Static usbd_status 2513 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2514 { 2515 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2516 usbd_status err; 2517 2518 /* Insert last in queue. */ 2519 mutex_enter(&sc->sc_lock); 2520 err = usb_insert_transfer(xfer); 2521 mutex_exit(&sc->sc_lock); 2522 if (err) 2523 return err; 2524 2525 /* Pipe isn't running, start first */ 2526 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2527 } 2528 2529 Static usbd_status 2530 ohci_root_intr_start(struct usbd_xfer *xfer) 2531 { 2532 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2533 const bool polling = sc->sc_bus.ub_usepolling; 2534 2535 if (sc->sc_dying) 2536 return USBD_IOERROR; 2537 2538 if (!polling) 2539 mutex_enter(&sc->sc_lock); 2540 KASSERT(sc->sc_intrxfer == NULL); 2541 sc->sc_intrxfer = xfer; 2542 xfer->ux_status = USBD_IN_PROGRESS; 2543 if (!polling) 2544 mutex_exit(&sc->sc_lock); 2545 2546 return USBD_IN_PROGRESS; 2547 } 2548 2549 /* Abort a root interrupt request. */ 2550 Static void 2551 ohci_root_intr_abort(struct usbd_xfer *xfer) 2552 { 2553 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2554 2555 KASSERT(mutex_owned(&sc->sc_lock)); 2556 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2557 2558 /* If xfer has already completed, nothing to do here. */ 2559 if (sc->sc_intrxfer == NULL) 2560 return; 2561 2562 /* 2563 * Otherwise, sc->sc_intrxfer had better be this transfer. 2564 * Cancel it. 2565 */ 2566 KASSERT(sc->sc_intrxfer == xfer); 2567 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2568 xfer->ux_status = USBD_CANCELLED; 2569 usb_transfer_complete(xfer); 2570 } 2571 2572 /* Close the root pipe. */ 2573 Static void 2574 ohci_root_intr_close(struct usbd_pipe *pipe) 2575 { 2576 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2577 2578 KASSERT(mutex_owned(&sc->sc_lock)); 2579 2580 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2581 2582 /* 2583 * Caller must guarantee the xfer has completed first, by 2584 * closing the pipe only after normal completion or an abort. 2585 */ 2586 KASSERT(sc->sc_intrxfer == NULL); 2587 } 2588 2589 /************************/ 2590 2591 int 2592 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2593 { 2594 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2595 usb_device_request_t *req = &xfer->ux_request; 2596 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2597 ohci_soft_td_t *stat, *setup; 2598 int isread = req->bmRequestType & UT_READ; 2599 int len = xfer->ux_bufsize; 2600 int err = ENOMEM; 2601 2602 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2603 2604 setup = ohci_alloc_std(sc); 2605 if (setup == NULL) { 2606 goto bad1; 2607 } 2608 stat = ohci_alloc_std(sc); 2609 if (stat == NULL) { 2610 goto bad2; 2611 } 2612 2613 ox->ox_setup = setup; 2614 ox->ox_stat = stat; 2615 ox->ox_nstd = 0; 2616 2617 /* Set up data transaction */ 2618 if (len != 0) { 2619 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2620 if (err) { 2621 goto bad3; 2622 } 2623 } 2624 return 0; 2625 2626 bad3: 2627 ohci_free_std(sc, stat); 2628 bad2: 2629 ohci_free_std(sc, setup); 2630 bad1: 2631 return err; 2632 } 2633 2634 void 2635 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2636 { 2637 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2638 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2639 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2640 2641 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2642 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2643 2644 mutex_enter(&sc->sc_lock); 2645 if (ox->ox_setup != opipe->tail.td) { 2646 ohci_free_std_locked(sc, ox->ox_setup); 2647 } 2648 for (size_t i = 0; i < ox->ox_nstd; i++) { 2649 ohci_soft_td_t *std = ox->ox_stds[i]; 2650 if (std == NULL) 2651 break; 2652 ohci_free_std_locked(sc, std); 2653 } 2654 ohci_free_std_locked(sc, ox->ox_stat); 2655 mutex_exit(&sc->sc_lock); 2656 2657 if (ox->ox_nstd) { 2658 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2659 kmem_free(ox->ox_stds, sz); 2660 } 2661 } 2662 2663 Static usbd_status 2664 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2665 { 2666 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2667 usbd_status err; 2668 2669 /* Insert last in queue. */ 2670 mutex_enter(&sc->sc_lock); 2671 err = usb_insert_transfer(xfer); 2672 mutex_exit(&sc->sc_lock); 2673 if (err) 2674 return err; 2675 2676 /* Pipe isn't running, start first */ 2677 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2678 } 2679 2680 Static usbd_status 2681 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2682 { 2683 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2684 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2685 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2686 usb_device_request_t *req = &xfer->ux_request; 2687 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2688 ohci_soft_td_t *setup, *stat, *next, *tail; 2689 ohci_soft_ed_t *sed; 2690 int isread; 2691 int len; 2692 const bool polling = sc->sc_bus.ub_usepolling; 2693 2694 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2695 2696 if (sc->sc_dying) 2697 return USBD_IOERROR; 2698 2699 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2700 2701 isread = req->bmRequestType & UT_READ; 2702 len = UGETW(req->wLength); 2703 2704 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2705 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2706 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2707 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2708 UGETW(req->wIndex)); 2709 2710 /* Need to take lock here for pipe->tail.td */ 2711 if (!polling) 2712 mutex_enter(&sc->sc_lock); 2713 2714 /* 2715 * Use the pipe "tail" TD as our first and loan our first TD to the 2716 * next transfer 2717 */ 2718 setup = opipe->tail.td; 2719 opipe->tail.td = ox->ox_setup; 2720 ox->ox_setup = setup; 2721 2722 stat = ox->ox_stat; 2723 2724 /* point at sentinel */ 2725 tail = opipe->tail.td; 2726 sed = opipe->sed; 2727 2728 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2729 "address ED %" __PRIuBITS " pipe %d\n", 2730 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2731 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2732 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2733 "MPL ED %" __PRIuBITS " pipe %d\n", 2734 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2735 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2736 2737 /* next will point to data if len != 0 */ 2738 next = stat; 2739 2740 /* Set up data transaction */ 2741 if (len != 0) { 2742 ohci_soft_td_t *std; 2743 ohci_soft_td_t *end; 2744 2745 next = ox->ox_stds[0]; 2746 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2747 2748 end->td.td_nexttd = HTOO32(stat->physaddr); 2749 end->nexttd = stat; 2750 2751 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2753 2754 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2755 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2756 std = ox->ox_stds[0]; 2757 /* Start toggle at 1 and then use the carried toggle. */ 2758 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2759 std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2760 usb_syncmem(&std->dma, 2761 std->offs + offsetof(ohci_td_t, td_flags), 2762 sizeof(std->td.td_flags), 2763 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2764 } 2765 2766 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2767 (uintptr_t)setup, 2768 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2769 (uintptr_t)tail); 2770 KASSERT(opipe->tail.td == tail); 2771 2772 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2773 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2774 2775 setup->td.td_flags = HTOO32( 2776 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2777 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2778 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2779 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2780 ); 2781 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2782 setup->td.td_nexttd = HTOO32(next->physaddr); 2783 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2784 setup->nexttd = next; 2785 setup->len = 0; 2786 setup->xfer = xfer; 2787 setup->flags = 0; 2788 ohci_hash_add_td(sc, setup); 2789 2790 xfer->ux_hcpriv = setup; 2791 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2793 2794 stat->td.td_flags = HTOO32( 2795 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2796 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2797 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2798 OHCI_TD_SET_DI(1) 2799 ); 2800 stat->td.td_cbp = 0; 2801 stat->td.td_nexttd = HTOO32(tail->physaddr); 2802 stat->td.td_be = 0; 2803 stat->nexttd = tail; 2804 stat->flags = OHCI_CALL_DONE; 2805 stat->len = 0; 2806 stat->xfer = xfer; 2807 ohci_hash_add_td(sc, stat); 2808 2809 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2811 2812 memset(&tail->td, 0, sizeof(tail->td)); 2813 tail->nexttd = NULL; 2814 tail->xfer = NULL; 2815 2816 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2818 2819 #ifdef OHCI_DEBUG 2820 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2821 if (ohcidebug >= 5) { 2822 ohci_dump_ed(sc, sed); 2823 ohci_dump_tds(sc, setup); 2824 } 2825 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2826 #endif 2827 2828 /* Insert ED in schedule */ 2829 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2830 usb_syncmem(&sed->dma, 2831 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2832 sizeof(sed->ed.ed_tailp), 2833 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2834 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2835 usbd_xfer_schedule_timeout(xfer); 2836 2837 DPRINTF("done", 0, 0, 0, 0); 2838 2839 xfer->ux_status = USBD_IN_PROGRESS; 2840 if (!polling) 2841 mutex_exit(&sc->sc_lock); 2842 2843 return USBD_IN_PROGRESS; 2844 } 2845 2846 /* Abort a device control request. */ 2847 Static void 2848 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2849 { 2850 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2851 2852 KASSERT(mutex_owned(&sc->sc_lock)); 2853 2854 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2855 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2856 usbd_xfer_abort(xfer); 2857 } 2858 2859 /* Close a device control pipe. */ 2860 Static void 2861 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2862 { 2863 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2864 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2865 2866 KASSERT(mutex_owned(&sc->sc_lock)); 2867 2868 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2869 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2870 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2871 ohci_free_std_locked(sc, opipe->tail.td); 2872 2873 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2874 } 2875 2876 /************************/ 2877 2878 Static void 2879 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2880 { 2881 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2882 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2883 2884 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2885 } 2886 2887 Static void 2888 ohci_noop(struct usbd_pipe *pipe) 2889 { 2890 } 2891 2892 Static int 2893 ohci_device_bulk_init(struct usbd_xfer *xfer) 2894 { 2895 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2896 int len = xfer->ux_bufsize; 2897 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2898 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2899 int err; 2900 2901 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2902 2903 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2904 2905 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2906 len, isread, xfer->ux_flags); 2907 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2908 2909 /* Allocate a chain of new TDs (including a new tail). */ 2910 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2911 if (err) 2912 return err; 2913 2914 return 0; 2915 } 2916 2917 Static void 2918 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2919 { 2920 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2921 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2922 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2923 2924 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2925 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2926 2927 mutex_enter(&sc->sc_lock); 2928 for (size_t i = 0; i < ox->ox_nstd; i++) { 2929 ohci_soft_td_t *std = ox->ox_stds[i]; 2930 if (std == NULL) 2931 break; 2932 if (std != opipe->tail.td) 2933 ohci_free_std_locked(sc, std); 2934 } 2935 mutex_exit(&sc->sc_lock); 2936 2937 if (ox->ox_nstd) { 2938 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2939 kmem_free(ox->ox_stds, sz); 2940 } 2941 } 2942 2943 Static usbd_status 2944 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2945 { 2946 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2947 usbd_status err; 2948 2949 /* Insert last in queue. */ 2950 mutex_enter(&sc->sc_lock); 2951 err = usb_insert_transfer(xfer); 2952 mutex_exit(&sc->sc_lock); 2953 if (err) 2954 return err; 2955 2956 /* Pipe isn't running, start first */ 2957 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2958 } 2959 2960 Static usbd_status 2961 ohci_device_bulk_start(struct usbd_xfer *xfer) 2962 { 2963 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2964 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2965 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2966 ohci_soft_td_t *last; 2967 ohci_soft_td_t *data, *tail, *tdp; 2968 ohci_soft_ed_t *sed; 2969 int len, isread, endpt; 2970 const bool polling = sc->sc_bus.ub_usepolling; 2971 2972 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2973 2974 if (sc->sc_dying) 2975 return USBD_IOERROR; 2976 2977 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2978 2979 len = xfer->ux_length; 2980 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2981 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2982 sed = opipe->sed; 2983 2984 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2985 len, isread, xfer->ux_flags); 2986 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2987 2988 if (!polling) 2989 mutex_enter(&sc->sc_lock); 2990 2991 /* 2992 * Use the pipe "tail" TD as our first and loan our first TD to the 2993 * next transfer 2994 */ 2995 data = opipe->tail.td; 2996 opipe->tail.td = ox->ox_stds[0]; 2997 ox->ox_stds[0] = data; 2998 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 2999 3000 /* point at sentinel */ 3001 tail = opipe->tail.td; 3002 memset(&tail->td, 0, sizeof(tail->td)); 3003 tail->nexttd = NULL; 3004 tail->xfer = NULL; 3005 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3006 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3007 xfer->ux_hcpriv = data; 3008 3009 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3010 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3011 KASSERT(opipe->tail.td == tail); 3012 3013 /* We want interrupt at the end of the transfer. */ 3014 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3015 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3016 last->td.td_nexttd = HTOO32(tail->physaddr); 3017 last->nexttd = tail; 3018 last->flags |= OHCI_CALL_DONE; 3019 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3020 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3021 3022 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3023 "td_cbp=0x%08jx td_be=0x%08jx", 3024 (int)O32TOH(sed->ed.ed_flags), 3025 (int)O32TOH(data->td.td_flags), 3026 (int)O32TOH(data->td.td_cbp), 3027 (int)O32TOH(data->td.td_be)); 3028 3029 #ifdef OHCI_DEBUG 3030 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3031 if (ohcidebug >= 5) { 3032 ohci_dump_ed(sc, sed); 3033 ohci_dump_tds(sc, data); 3034 } 3035 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3036 #endif 3037 3038 /* Insert ED in schedule */ 3039 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3040 KASSERT(tdp->xfer == xfer); 3041 } 3042 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3043 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3044 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3045 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3046 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3048 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3049 usbd_xfer_schedule_timeout(xfer); 3050 xfer->ux_status = USBD_IN_PROGRESS; 3051 if (!polling) 3052 mutex_exit(&sc->sc_lock); 3053 3054 return USBD_IN_PROGRESS; 3055 } 3056 3057 Static void 3058 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3059 { 3060 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3061 3062 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3063 3064 KASSERT(mutex_owned(&sc->sc_lock)); 3065 3066 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3067 usbd_xfer_abort(xfer); 3068 } 3069 3070 /* 3071 * Close a device bulk pipe. 3072 */ 3073 Static void 3074 ohci_device_bulk_close(struct usbd_pipe *pipe) 3075 { 3076 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3077 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3078 3079 KASSERT(mutex_owned(&sc->sc_lock)); 3080 3081 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3082 3083 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3084 ohci_close_pipe(pipe, sc->sc_bulk_head); 3085 ohci_free_std_locked(sc, opipe->tail.td); 3086 } 3087 3088 /************************/ 3089 3090 Static int 3091 ohci_device_intr_init(struct usbd_xfer *xfer) 3092 { 3093 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3094 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3095 int len = xfer->ux_bufsize; 3096 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3097 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3098 int err; 3099 3100 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3101 3102 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3103 KASSERT(len != 0); 3104 3105 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3106 len, isread, xfer->ux_flags); 3107 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3108 3109 ox->ox_nstd = 0; 3110 3111 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3112 if (err) { 3113 return err; 3114 } 3115 3116 return 0; 3117 } 3118 3119 Static void 3120 ohci_device_intr_fini(struct usbd_xfer *xfer) 3121 { 3122 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3123 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3124 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3125 3126 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3127 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3128 3129 mutex_enter(&sc->sc_lock); 3130 for (size_t i = 0; i < ox->ox_nstd; i++) { 3131 ohci_soft_td_t *std = ox->ox_stds[i]; 3132 if (std != NULL) 3133 break; 3134 if (std != opipe->tail.td) 3135 ohci_free_std_locked(sc, std); 3136 } 3137 mutex_exit(&sc->sc_lock); 3138 3139 if (ox->ox_nstd) { 3140 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3141 kmem_free(ox->ox_stds, sz); 3142 } 3143 } 3144 3145 Static usbd_status 3146 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3147 { 3148 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3149 usbd_status err; 3150 3151 /* Insert last in queue. */ 3152 mutex_enter(&sc->sc_lock); 3153 err = usb_insert_transfer(xfer); 3154 mutex_exit(&sc->sc_lock); 3155 if (err) 3156 return err; 3157 3158 /* Pipe isn't running, start first */ 3159 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3160 } 3161 3162 Static usbd_status 3163 ohci_device_intr_start(struct usbd_xfer *xfer) 3164 { 3165 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3166 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3167 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3168 ohci_soft_ed_t *sed = opipe->sed; 3169 ohci_soft_td_t *data, *last, *tail; 3170 int len, isread, endpt; 3171 const bool polling = sc->sc_bus.ub_usepolling; 3172 3173 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3174 3175 if (sc->sc_dying) 3176 return USBD_IOERROR; 3177 3178 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3179 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3180 3181 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3182 3183 len = xfer->ux_length; 3184 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3185 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3186 3187 if (!polling) 3188 mutex_enter(&sc->sc_lock); 3189 3190 /* 3191 * Use the pipe "tail" TD as our first and loan our first TD to the 3192 * next transfer. 3193 */ 3194 data = opipe->tail.td; 3195 opipe->tail.td = ox->ox_stds[0]; 3196 ox->ox_stds[0] = data; 3197 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3198 3199 /* point at sentinel */ 3200 tail = opipe->tail.td; 3201 memset(&tail->td, 0, sizeof(tail->td)); 3202 tail->nexttd = NULL; 3203 tail->xfer = NULL; 3204 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 xfer->ux_hcpriv = data; 3207 3208 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3209 (uintptr_t)tail, 0, 0); 3210 KASSERT(opipe->tail.td == tail); 3211 3212 /* We want interrupt at the end of the transfer. */ 3213 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3214 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3215 3216 last->td.td_nexttd = HTOO32(tail->physaddr); 3217 last->nexttd = tail; 3218 last->flags |= OHCI_CALL_DONE; 3219 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 3222 #ifdef OHCI_DEBUG 3223 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3224 if (ohcidebug >= 5) { 3225 ohci_dump_ed(sc, sed); 3226 ohci_dump_tds(sc, data); 3227 } 3228 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3229 #endif 3230 3231 /* Insert ED in schedule */ 3232 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3233 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3234 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3235 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3236 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3237 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3238 3239 xfer->ux_status = USBD_IN_PROGRESS; 3240 if (!polling) 3241 mutex_exit(&sc->sc_lock); 3242 3243 return USBD_IN_PROGRESS; 3244 } 3245 3246 /* Abort a device interrupt request. */ 3247 Static void 3248 ohci_device_intr_abort(struct usbd_xfer *xfer) 3249 { 3250 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3251 3252 KASSERT(mutex_owned(&sc->sc_lock)); 3253 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3254 3255 usbd_xfer_abort(xfer); 3256 } 3257 3258 /* Close a device interrupt pipe. */ 3259 Static void 3260 ohci_device_intr_close(struct usbd_pipe *pipe) 3261 { 3262 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3263 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3264 int nslots = opipe->intr.nslots; 3265 int pos = opipe->intr.pos; 3266 int j; 3267 ohci_soft_ed_t *p, *sed = opipe->sed; 3268 3269 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3270 3271 KASSERT(mutex_owned(&sc->sc_lock)); 3272 3273 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3274 pos, 0); 3275 usb_syncmem(&sed->dma, sed->offs, 3276 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3277 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3278 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3279 sizeof(sed->ed.ed_flags), 3280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3281 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3282 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3283 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3284 3285 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3286 continue; 3287 KASSERT(p); 3288 p->next = sed->next; 3289 p->ed.ed_nexted = sed->ed.ed_nexted; 3290 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3291 sizeof(p->ed.ed_nexted), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 3294 for (j = 0; j < nslots; j++) 3295 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3296 3297 ohci_free_std_locked(sc, opipe->tail.td); 3298 ohci_free_sed_locked(sc, opipe->sed); 3299 } 3300 3301 Static usbd_status 3302 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3303 { 3304 int i, j, best; 3305 u_int npoll, slow, shigh, nslots; 3306 u_int bestbw, bw; 3307 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3308 3309 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3310 3311 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3312 if (ival == 0) { 3313 printf("ohci_setintr: 0 interval\n"); 3314 return USBD_INVAL; 3315 } 3316 3317 npoll = OHCI_NO_INTRS; 3318 while (npoll > ival) 3319 npoll /= 2; 3320 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3321 3322 /* 3323 * We now know which level in the tree the ED must go into. 3324 * Figure out which slot has most bandwidth left over. 3325 * Slots to examine: 3326 * npoll 3327 * 1 0 3328 * 2 1 2 3329 * 4 3 4 5 6 3330 * 8 7 8 9 10 11 12 13 14 3331 * N (N-1) .. (N-1+N-1) 3332 */ 3333 slow = npoll-1; 3334 shigh = slow + npoll; 3335 nslots = OHCI_NO_INTRS / npoll; 3336 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3337 bw = 0; 3338 for (j = 0; j < nslots; j++) 3339 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3340 if (bw < bestbw) { 3341 best = i; 3342 bestbw = bw; 3343 } 3344 } 3345 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3346 3347 mutex_enter(&sc->sc_lock); 3348 hsed = sc->sc_eds[best]; 3349 sed->next = hsed->next; 3350 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3351 sizeof(hsed->ed.ed_flags), 3352 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3353 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3355 sizeof(sed->ed.ed_flags), 3356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3357 hsed->next = sed; 3358 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3359 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3360 sizeof(hsed->ed.ed_flags), 3361 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3362 mutex_exit(&sc->sc_lock); 3363 3364 for (j = 0; j < nslots; j++) 3365 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3366 opipe->intr.nslots = nslots; 3367 opipe->intr.pos = best; 3368 3369 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3370 return USBD_NORMAL_COMPLETION; 3371 } 3372 3373 /***********************/ 3374 3375 Static int 3376 ohci_device_isoc_init(struct usbd_xfer *xfer) 3377 { 3378 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3379 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3380 ohci_soft_itd_t *sitd; 3381 size_t i; 3382 int err; 3383 3384 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3385 3386 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3387 xfer->ux_length, xfer->ux_flags, 0); 3388 3389 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3390 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3391 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3392 3393 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3394 KM_SLEEP); 3395 ox->ox_nsitd = nsitd; 3396 3397 for (i = 0; i < nsitd; i++) { 3398 /* Allocate next ITD */ 3399 sitd = ohci_alloc_sitd(sc); 3400 if (sitd == NULL) { 3401 err = ENOMEM; 3402 goto fail; 3403 } 3404 ox->ox_sitds[i] = sitd; 3405 sitd->xfer = xfer; 3406 sitd->flags = 0; 3407 } 3408 3409 return 0; 3410 fail: 3411 for (; i > 0;) { 3412 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3413 } 3414 return err; 3415 } 3416 3417 Static void 3418 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3419 { 3420 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3421 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3422 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3423 3424 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3425 3426 mutex_enter(&sc->sc_lock); 3427 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3428 if (ox->ox_sitds[i] != opipe->tail.itd) { 3429 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3430 } 3431 } 3432 mutex_exit(&sc->sc_lock); 3433 3434 if (ox->ox_nsitd) { 3435 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3436 kmem_free(ox->ox_sitds, sz); 3437 } 3438 } 3439 3440 3441 usbd_status 3442 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3443 { 3444 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3445 usbd_status __diagused err; 3446 3447 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3448 3449 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3450 3451 /* Put it on our queue, */ 3452 mutex_enter(&sc->sc_lock); 3453 err = usb_insert_transfer(xfer); 3454 mutex_exit(&sc->sc_lock); 3455 3456 KASSERT(err == USBD_NORMAL_COMPLETION); 3457 3458 /* insert into schedule, */ 3459 ohci_device_isoc_enter(xfer); 3460 3461 /* and start if the pipe wasn't running */ 3462 return USBD_IN_PROGRESS; 3463 } 3464 3465 void 3466 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3467 { 3468 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3469 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3470 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3471 ohci_soft_ed_t *sed = opipe->sed; 3472 ohci_soft_itd_t *sitd, *nsitd, *tail; 3473 ohci_physaddr_t buf, offs, bp0, bp1; 3474 int i, ncur, nframes; 3475 size_t boff, frlen; 3476 3477 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3478 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3479 3480 mutex_enter(&sc->sc_lock); 3481 3482 if (sc->sc_dying) { 3483 mutex_exit(&sc->sc_lock); 3484 return; 3485 } 3486 3487 struct isoc *isoc = &opipe->isoc; 3488 3489 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3490 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3491 3492 int isread = 3493 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3494 3495 if (xfer->ux_length) 3496 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3497 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3498 3499 if (isoc->next == -1) { 3500 /* Not in use yet, schedule it a few frames ahead. */ 3501 usb_syncmem(&sc->sc_hccadma, 3502 offsetof(struct ohci_hcca, hcca_frame_number), 3503 sizeof(sc->sc_hcca->hcca_frame_number), 3504 BUS_DMASYNC_POSTREAD); 3505 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3506 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3507 } 3508 3509 sitd = opipe->tail.itd; 3510 opipe->tail.itd = ox->ox_sitds[0]; 3511 ox->ox_sitds[0] = sitd; 3512 3513 boff = 0; 3514 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3515 bp0 = bp1 = OHCI_PAGE(buf); 3516 offs = OHCI_PAGE_OFFSET(buf); 3517 3518 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3519 3520 nframes = xfer->ux_nframes; 3521 xfer->ux_hcpriv = sitd; 3522 size_t j = 1; 3523 for (i = ncur = 0; i < nframes; i++, ncur++) { 3524 frlen = xfer->ux_frlengths[i]; 3525 3526 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3527 xfer->ux_frlengths[i], 0); 3528 /* 3529 * XXXNH: The loop assumes this is never true, because 3530 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3531 */ 3532 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3533 frlen = 2 * OHCI_PAGE_SIZE - offs; 3534 3535 boff += frlen; 3536 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3537 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3538 3539 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3540 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3541 3542 /* Note the first page crossing in bp1 */ 3543 if (bp0 == bp1 && bp1 != nep) 3544 bp1 = nep; 3545 3546 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3547 ncur, bp0, bp1, nend); 3548 3549 /* all offsets used or too many page crossings */ 3550 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3551 /* Allocate next ITD */ 3552 nsitd = ox->ox_sitds[j++]; 3553 KASSERT(nsitd != NULL); 3554 KASSERT(j < ox->ox_nsitd); 3555 3556 /* Fill current ITD */ 3557 sitd->itd.itd_flags = HTOO32( 3558 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3559 OHCI_ITD_SET_SF(isoc->next) | 3560 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3561 OHCI_ITD_SET_FC(ncur) 3562 ); 3563 sitd->itd.itd_bp0 = HTOO32(bp0); 3564 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3565 sitd->itd.itd_be = HTOO32(end); 3566 sitd->nextitd = nsitd; 3567 sitd->xfer = xfer; 3568 sitd->flags = 0; 3569 #ifdef DIAGNOSTIC 3570 sitd->isdone = false; 3571 #endif 3572 ohci_hash_add_itd(sc, sitd); 3573 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3574 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3575 3576 sitd = nsitd; 3577 isoc->next = isoc->next + ncur; 3578 bp0 = bp1 = OHCI_PAGE(buf); 3579 ncur = 0; 3580 } 3581 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3582 end = nend; 3583 offs = noffs; 3584 } 3585 KASSERT(j <= ox->ox_nsitd); 3586 3587 /* point at sentinel */ 3588 tail = opipe->tail.itd; 3589 memset(&tail->itd, 0, sizeof(tail->itd)); 3590 tail->nextitd = NULL; 3591 tail->xfer = NULL; 3592 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3593 BUS_DMASYNC_PREWRITE); 3594 3595 /* Fixup last used ITD */ 3596 sitd->itd.itd_flags = HTOO32( 3597 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3598 OHCI_ITD_SET_SF(isoc->next) | 3599 OHCI_ITD_SET_DI(0) | 3600 OHCI_ITD_SET_FC(ncur) 3601 ); 3602 sitd->itd.itd_bp0 = HTOO32(bp0); 3603 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3604 sitd->itd.itd_be = HTOO32(end); 3605 sitd->nextitd = tail; 3606 sitd->xfer = xfer; 3607 sitd->flags = OHCI_CALL_DONE; 3608 #ifdef DIAGNOSTIC 3609 sitd->isdone = false; 3610 #endif 3611 ohci_hash_add_itd(sc, sitd); 3612 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3613 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3614 3615 isoc->next = isoc->next + ncur; 3616 isoc->inuse += nframes; 3617 3618 /* XXX pretend we did it all */ 3619 xfer->ux_actlen = offs; 3620 xfer->ux_status = USBD_IN_PROGRESS; 3621 3622 #ifdef OHCI_DEBUG 3623 if (ohcidebug >= 5) { 3624 usb_syncmem(&sc->sc_hccadma, 3625 offsetof(struct ohci_hcca, hcca_frame_number), 3626 sizeof(sc->sc_hcca->hcca_frame_number), 3627 BUS_DMASYNC_POSTREAD); 3628 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3629 0, 0, 0); 3630 ohci_dump_itds(sc, xfer->ux_hcpriv); 3631 ohci_dump_ed(sc, sed); 3632 } 3633 #endif 3634 3635 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3636 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3637 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3638 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3639 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3640 sizeof(sed->ed.ed_flags), 3641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3642 mutex_exit(&sc->sc_lock); 3643 } 3644 3645 void 3646 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3647 { 3648 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3649 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3650 ohci_soft_ed_t *sed; 3651 ohci_soft_itd_t *sitd; 3652 3653 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3654 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 3658 /* Transfer is already done. */ 3659 if (xfer->ux_status != USBD_NOT_STARTED && 3660 xfer->ux_status != USBD_IN_PROGRESS) { 3661 printf("ohci_device_isoc_abort: early return\n"); 3662 goto done; 3663 } 3664 3665 /* Give xfer the requested abort code. */ 3666 xfer->ux_status = USBD_CANCELLED; 3667 3668 sed = opipe->sed; 3669 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3670 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3671 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3672 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3673 sizeof(sed->ed.ed_flags), 3674 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3675 3676 sitd = xfer->ux_hcpriv; 3677 KASSERT(sitd); 3678 3679 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3680 3681 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3682 ohci_hash_rem_itd(sc, sitd); 3683 #ifdef DIAGNOSTIC 3684 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3685 0, 0, 0); 3686 sitd->isdone = true; 3687 #endif 3688 } 3689 3690 /* Run callback. */ 3691 usb_transfer_complete(xfer); 3692 3693 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3694 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3695 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3697 3698 done: 3699 KASSERT(mutex_owned(&sc->sc_lock)); 3700 } 3701 3702 void 3703 ohci_device_isoc_done(struct usbd_xfer *xfer) 3704 { 3705 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3706 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3707 3708 int isread = 3709 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3710 3711 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3712 0, 0); 3713 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3714 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3715 } 3716 3717 usbd_status 3718 ohci_setup_isoc(struct usbd_pipe *pipe) 3719 { 3720 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3721 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3722 struct isoc *isoc = &opipe->isoc; 3723 3724 isoc->next = -1; 3725 isoc->inuse = 0; 3726 3727 mutex_enter(&sc->sc_lock); 3728 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3729 mutex_exit(&sc->sc_lock); 3730 3731 return USBD_NORMAL_COMPLETION; 3732 } 3733 3734 void 3735 ohci_device_isoc_close(struct usbd_pipe *pipe) 3736 { 3737 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3738 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3739 3740 KASSERT(mutex_owned(&sc->sc_lock)); 3741 3742 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3743 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3744 ohci_close_pipe(pipe, sc->sc_isoc_head); 3745 #ifdef DIAGNOSTIC 3746 opipe->tail.itd->isdone = true; 3747 #endif 3748 ohci_free_sitd_locked(sc, opipe->tail.itd); 3749 } 3750