1 /* $NetBSD: if_urtwn.c,v 1.73 2019/10/10 23:30:02 bad Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.73 2019/10/10 23:30:02 bad Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 77 #include <dev/ic/rtwnreg.h> 78 #include <dev/ic/rtwn_data.h> 79 #include <dev/usb/if_urtwnreg.h> 80 #include <dev/usb/if_urtwnvar.h> 81 82 /* 83 * The sc_write_mtx locking is to prevent sequences of writes from 84 * being intermingled with each other. I don't know if this is really 85 * needed. I have added it just to be on the safe side. 86 */ 87 88 #ifdef URTWN_DEBUG 89 #define DBG_INIT __BIT(0) 90 #define DBG_FN __BIT(1) 91 #define DBG_TX __BIT(2) 92 #define DBG_RX __BIT(3) 93 #define DBG_STM __BIT(4) 94 #define DBG_RF __BIT(5) 95 #define DBG_REG __BIT(6) 96 #define DBG_ALL 0xffffffffU 97 u_int urtwn_debug = 0; 98 #define DPRINTFN(n, s) \ 99 do { if (urtwn_debug & (n)) printf s; } while (/*CONSTCOND*/0) 100 #else 101 #define DPRINTFN(n, s) 102 #endif 103 104 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 105 #define URTWN_RTL8188E_DEV(v,p) \ 106 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 107 #define URTWN_RTL8192EU_DEV(v,p) \ 108 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 109 static const struct urtwn_dev { 110 struct usb_devno dev; 111 uint32_t flags; 112 #define FLAG_RTL8188E __BIT(0) 113 #define FLAG_RTL8192E __BIT(1) 114 } urtwn_devs[] = { 115 URTWN_DEV(ABOCOM, RTL8188CU_1), 116 URTWN_DEV(ABOCOM, RTL8188CU_2), 117 URTWN_DEV(ABOCOM, RTL8192CU), 118 URTWN_DEV(ASUSTEK, RTL8192CU), 119 URTWN_DEV(ASUSTEK, RTL8192CU_3), 120 URTWN_DEV(ASUSTEK, USBN10NANO), 121 URTWN_DEV(ASUSTEK, RTL8192CU_3), 122 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 124 URTWN_DEV(AZUREWAVE, RTL8188CU), 125 URTWN_DEV(BELKIN, F7D2102), 126 URTWN_DEV(BELKIN, RTL8188CU), 127 URTWN_DEV(BELKIN, RTL8188CUS), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(BELKIN, RTL8192CU_1), 130 URTWN_DEV(BELKIN, RTL8192CU_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_1), 132 URTWN_DEV(CHICONY, RTL8188CUS_2), 133 URTWN_DEV(CHICONY, RTL8188CUS_3), 134 URTWN_DEV(CHICONY, RTL8188CUS_4), 135 URTWN_DEV(CHICONY, RTL8188CUS_5), 136 URTWN_DEV(CHICONY, RTL8188CUS_6), 137 URTWN_DEV(COMPARE, RTL8192CU), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(DLINK, RTL8188CU), 141 URTWN_DEV(DLINK, RTL8192CU_1), 142 URTWN_DEV(DLINK, RTL8192CU_2), 143 URTWN_DEV(DLINK, RTL8192CU_3), 144 URTWN_DEV(DLINK, RTL8192CU_4), 145 URTWN_DEV(EDIMAX, RTL8188CU), 146 URTWN_DEV(EDIMAX, RTL8192CU), 147 URTWN_DEV(FEIXUN, RTL8188CU), 148 URTWN_DEV(FEIXUN, RTL8192CU), 149 URTWN_DEV(GUILLEMOT, HWNUP150), 150 URTWN_DEV(GUILLEMOT, RTL8192CU), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HAWKING, RTL8192CU_2), 153 URTWN_DEV(HP3, RTL8188CU), 154 URTWN_DEV(IODATA, WNG150UM), 155 URTWN_DEV(IODATA, RTL8192CU), 156 URTWN_DEV(NETGEAR, WNA1000M), 157 URTWN_DEV(NETGEAR, RTL8192CU), 158 URTWN_DEV(NETGEAR4, RTL8188CU), 159 URTWN_DEV(NOVATECH, RTL8188CU), 160 URTWN_DEV(PLANEX2, RTL8188CU_1), 161 URTWN_DEV(PLANEX2, RTL8188CU_2), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(PLANEX2, RTL8188CU_3), 164 URTWN_DEV(PLANEX2, RTL8188CU_4), 165 URTWN_DEV(PLANEX2, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188CE_0), 167 URTWN_DEV(REALTEK, RTL8188CE_1), 168 URTWN_DEV(REALTEK, RTL8188CTV), 169 URTWN_DEV(REALTEK, RTL8188CU_0), 170 URTWN_DEV(REALTEK, RTL8188CU_1), 171 URTWN_DEV(REALTEK, RTL8188CU_2), 172 URTWN_DEV(REALTEK, RTL8188CU_3), 173 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 174 URTWN_DEV(REALTEK, RTL8188CUS), 175 URTWN_DEV(REALTEK, RTL8188RU), 176 URTWN_DEV(REALTEK, RTL8188RU_2), 177 URTWN_DEV(REALTEK, RTL8188RU_3), 178 URTWN_DEV(REALTEK, RTL8191CU), 179 URTWN_DEV(REALTEK, RTL8192CE), 180 URTWN_DEV(REALTEK, RTL8192CU), 181 URTWN_DEV(SITECOMEU, RTL8188CU), 182 URTWN_DEV(SITECOMEU, RTL8188CU_2), 183 URTWN_DEV(SITECOMEU, RTL8192CU), 184 URTWN_DEV(SITECOMEU, RTL8192CUR2), 185 URTWN_DEV(TPLINK, RTL8192CU), 186 URTWN_DEV(TRENDNET, RTL8188CU), 187 URTWN_DEV(TRENDNET, RTL8192CU), 188 URTWN_DEV(ZYXEL, RTL8192CU), 189 190 /* URTWN_RTL8188E */ 191 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 192 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 193 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 194 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 195 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 196 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 197 198 /* URTWN_RTL8192EU */ 199 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 200 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 201 URTWN_RTL8192EU_DEV(TPLINK, RTL8192EU), 202 }; 203 #undef URTWN_DEV 204 #undef URTWN_RTL8188E_DEV 205 #undef URTWN_RTL8192EU_DEV 206 207 static int urtwn_match(device_t, cfdata_t, void *); 208 static void urtwn_attach(device_t, device_t, void *); 209 static int urtwn_detach(device_t, int); 210 static int urtwn_activate(device_t, enum devact); 211 212 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 213 urtwn_attach, urtwn_detach, urtwn_activate); 214 215 static int urtwn_open_pipes(struct urtwn_softc *); 216 static void urtwn_close_pipes(struct urtwn_softc *); 217 static int urtwn_alloc_rx_list(struct urtwn_softc *); 218 static void urtwn_free_rx_list(struct urtwn_softc *); 219 static int urtwn_alloc_tx_list(struct urtwn_softc *); 220 static void urtwn_free_tx_list(struct urtwn_softc *); 221 static void urtwn_task(void *); 222 static void urtwn_do_async(struct urtwn_softc *, 223 void (*)(struct urtwn_softc *, void *), void *, int); 224 static void urtwn_wait_async(struct urtwn_softc *); 225 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 226 int); 227 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 228 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 229 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 230 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 231 int); 232 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 233 int); 234 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 235 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 236 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 237 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 238 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 239 uint32_t); 240 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 241 uint32_t); 242 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 243 uint32_t); 244 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 245 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 246 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 247 static void urtwn_efuse_read(struct urtwn_softc *); 248 static void urtwn_efuse_switch_power(struct urtwn_softc *); 249 static int urtwn_read_chipid(struct urtwn_softc *); 250 #ifdef URTWN_DEBUG 251 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 252 #endif 253 static void urtwn_read_rom(struct urtwn_softc *); 254 static void urtwn_r88e_read_rom(struct urtwn_softc *); 255 static int urtwn_media_change(struct ifnet *); 256 static int urtwn_ra_init(struct urtwn_softc *); 257 static int urtwn_get_nettype(struct urtwn_softc *); 258 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 259 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 260 static void urtwn_set_led(struct urtwn_softc *, int, int); 261 static void urtwn_calib_to(void *); 262 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 263 static void urtwn_next_scan(void *); 264 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 265 int); 266 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 267 static int urtwn_wme_update(struct ieee80211com *); 268 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 269 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 270 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 271 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 272 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 273 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 274 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 275 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 276 struct ieee80211_node *, struct urtwn_tx_data *); 277 static struct urtwn_tx_data * 278 urtwn_get_tx_data(struct urtwn_softc *, size_t); 279 static void urtwn_start(struct ifnet *); 280 static void urtwn_watchdog(struct ifnet *); 281 static int urtwn_ioctl(struct ifnet *, u_long, void *); 282 static int urtwn_r92c_power_on(struct urtwn_softc *); 283 static int urtwn_r92e_power_on(struct urtwn_softc *); 284 static int urtwn_r88e_power_on(struct urtwn_softc *); 285 static int urtwn_llt_init(struct urtwn_softc *); 286 static void urtwn_fw_reset(struct urtwn_softc *); 287 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 288 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 289 static int urtwn_load_firmware(struct urtwn_softc *); 290 static int urtwn_r92c_dma_init(struct urtwn_softc *); 291 static int urtwn_r88e_dma_init(struct urtwn_softc *); 292 static void urtwn_mac_init(struct urtwn_softc *); 293 static void urtwn_bb_init(struct urtwn_softc *); 294 static void urtwn_rf_init(struct urtwn_softc *); 295 static void urtwn_cam_init(struct urtwn_softc *); 296 static void urtwn_pa_bias_init(struct urtwn_softc *); 297 static void urtwn_rxfilter_init(struct urtwn_softc *); 298 static void urtwn_edca_init(struct urtwn_softc *); 299 static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); 300 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 301 uint16_t[]); 302 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 303 u_int, uint16_t[]); 304 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 305 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 306 u_int); 307 static void urtwn_iq_calib(struct urtwn_softc *, bool); 308 static void urtwn_lc_calib(struct urtwn_softc *); 309 static void urtwn_temp_calib(struct urtwn_softc *); 310 static int urtwn_init(struct ifnet *); 311 static void urtwn_stop(struct ifnet *, int); 312 static int urtwn_reset(struct ifnet *); 313 static void urtwn_chip_stop(struct urtwn_softc *); 314 static void urtwn_newassoc(struct ieee80211_node *, int); 315 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 316 317 /* Aliases. */ 318 #define urtwn_bb_write urtwn_write_4 319 #define urtwn_bb_read urtwn_read_4 320 321 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 322 323 static const uint16_t addaReg[] = { 324 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 325 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 326 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 327 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 328 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 329 }; 330 331 static int 332 urtwn_match(device_t parent, cfdata_t match, void *aux) 333 { 334 struct usb_attach_arg *uaa = aux; 335 336 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 337 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 338 } 339 340 static void 341 urtwn_attach(device_t parent, device_t self, void *aux) 342 { 343 struct urtwn_softc *sc = device_private(self); 344 struct ieee80211com *ic = &sc->sc_ic; 345 struct ifnet *ifp = &sc->sc_if; 346 struct usb_attach_arg *uaa = aux; 347 char *devinfop; 348 const struct urtwn_dev *dev; 349 usb_device_request_t req; 350 size_t i; 351 int error; 352 353 sc->sc_dev = self; 354 sc->sc_udev = uaa->uaa_device; 355 356 sc->chip = 0; 357 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 358 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 359 SET(sc->chip, URTWN_CHIP_88E); 360 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 361 SET(sc->chip, URTWN_CHIP_92EU); 362 363 aprint_naive("\n"); 364 aprint_normal("\n"); 365 366 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 367 368 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 369 aprint_normal_dev(self, "%s\n", devinfop); 370 usbd_devinfo_free(devinfop); 371 372 req.bmRequestType = UT_WRITE_DEVICE; 373 req.bRequest = UR_SET_FEATURE; 374 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 375 USETW(req.wIndex, UHF_PORT_SUSPEND); 376 USETW(req.wLength, 0); 377 378 (void) usbd_do_request(sc->sc_udev, &req, 0); 379 380 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 381 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 382 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 383 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 384 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 385 386 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 387 388 callout_init(&sc->sc_scan_to, 0); 389 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 390 callout_init(&sc->sc_calib_to, 0); 391 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 392 393 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 394 RND_TYPE_NET, RND_FLAG_DEFAULT); 395 396 error = usbd_set_config_no(sc->sc_udev, 1, 0); 397 if (error != 0) { 398 aprint_error_dev(self, "failed to set configuration" 399 ", err=%s\n", usbd_errstr(error)); 400 goto fail; 401 } 402 403 /* Get the first interface handle. */ 404 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 405 if (error != 0) { 406 aprint_error_dev(self, "could not get interface handle\n"); 407 goto fail; 408 } 409 410 error = urtwn_read_chipid(sc); 411 if (error != 0) { 412 aprint_error_dev(self, "unsupported test chip\n"); 413 goto fail; 414 } 415 416 /* Determine number of Tx/Rx chains. */ 417 if (sc->chip & URTWN_CHIP_92C) { 418 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 419 sc->nrxchains = 2; 420 } else if (sc->chip & URTWN_CHIP_92EU) { 421 sc->ntxchains = 2; 422 sc->nrxchains = 2; 423 } else { 424 sc->ntxchains = 1; 425 sc->nrxchains = 1; 426 } 427 428 if (ISSET(sc->chip, URTWN_CHIP_88E) || 429 ISSET(sc->chip, URTWN_CHIP_92EU)) 430 urtwn_r88e_read_rom(sc); 431 else 432 urtwn_read_rom(sc); 433 434 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 435 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 436 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 437 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 438 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 439 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 440 "8188CUS", sc->ntxchains, sc->nrxchains, 441 ether_sprintf(ic->ic_myaddr)); 442 443 error = urtwn_open_pipes(sc); 444 if (error != 0) { 445 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 446 goto fail; 447 } 448 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 449 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 450 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 451 452 /* 453 * Setup the 802.11 device. 454 */ 455 ic->ic_ifp = ifp; 456 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 457 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 458 ic->ic_state = IEEE80211_S_INIT; 459 460 /* Set device capabilities. */ 461 ic->ic_caps = 462 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 463 IEEE80211_C_IBSS | /* IBSS mode supported */ 464 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 465 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 466 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 467 IEEE80211_C_WME | /* 802.11e */ 468 IEEE80211_C_WPA; /* 802.11i */ 469 470 /* Set supported .11b and .11g rates. */ 471 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 472 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 473 474 /* Set supported .11b and .11g channels (1 through 14). */ 475 for (i = 1; i <= 14; i++) { 476 ic->ic_channels[i].ic_freq = 477 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 478 ic->ic_channels[i].ic_flags = 479 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 480 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 481 } 482 483 ifp->if_softc = sc; 484 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 485 ifp->if_init = urtwn_init; 486 ifp->if_ioctl = urtwn_ioctl; 487 ifp->if_start = urtwn_start; 488 ifp->if_watchdog = urtwn_watchdog; 489 IFQ_SET_READY(&ifp->if_snd); 490 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 491 492 if_initialize(ifp); 493 ieee80211_ifattach(ic); 494 495 /* override default methods */ 496 ic->ic_newassoc = urtwn_newassoc; 497 ic->ic_reset = urtwn_reset; 498 ic->ic_wme.wme_update = urtwn_wme_update; 499 500 /* Override state transition machine. */ 501 sc->sc_newstate = ic->ic_newstate; 502 ic->ic_newstate = urtwn_newstate; 503 ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); 504 505 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 506 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 507 &sc->sc_drvbpf); 508 509 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 510 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 511 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 512 513 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 514 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 515 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 516 517 ifp->if_percpuq = if_percpuq_create(ifp); 518 if_register(ifp); 519 520 ieee80211_announce(ic); 521 522 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 523 524 if (!pmf_device_register(self, NULL, NULL)) 525 aprint_error_dev(self, "couldn't establish power handler\n"); 526 527 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 528 return; 529 530 fail: 531 sc->sc_dying = 1; 532 aprint_error_dev(self, "attach failed\n"); 533 } 534 535 static int 536 urtwn_detach(device_t self, int flags) 537 { 538 struct urtwn_softc *sc = device_private(self); 539 struct ifnet *ifp = &sc->sc_if; 540 int s; 541 542 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 543 544 pmf_device_deregister(self); 545 546 s = splusb(); 547 548 sc->sc_dying = 1; 549 550 callout_halt(&sc->sc_scan_to, NULL); 551 callout_halt(&sc->sc_calib_to, NULL); 552 553 pmf_device_deregister(self); 554 555 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 556 urtwn_stop(ifp, 0); 557 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 558 NULL); 559 560 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 561 bpf_detach(ifp); 562 ieee80211_ifdetach(&sc->sc_ic); 563 if_detach(ifp); 564 565 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 566 urtwn_close_pipes(sc); 567 } 568 569 splx(s); 570 571 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 572 573 rnd_detach_source(&sc->rnd_source); 574 575 callout_destroy(&sc->sc_scan_to); 576 callout_destroy(&sc->sc_calib_to); 577 578 mutex_destroy(&sc->sc_write_mtx); 579 mutex_destroy(&sc->sc_fwcmd_mtx); 580 mutex_destroy(&sc->sc_tx_mtx); 581 mutex_destroy(&sc->sc_rx_mtx); 582 mutex_destroy(&sc->sc_task_mtx); 583 584 return 0; 585 } 586 587 static int 588 urtwn_activate(device_t self, enum devact act) 589 { 590 struct urtwn_softc *sc = device_private(self); 591 592 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 593 594 switch (act) { 595 case DVACT_DEACTIVATE: 596 if_deactivate(sc->sc_ic.ic_ifp); 597 return 0; 598 default: 599 return EOPNOTSUPP; 600 } 601 } 602 603 static int 604 urtwn_open_pipes(struct urtwn_softc *sc) 605 { 606 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 607 static uint8_t epaddr[R92C_MAX_EPOUT]; 608 static uint8_t rxepaddr[R92C_MAX_EPIN]; 609 usb_interface_descriptor_t *id; 610 usb_endpoint_descriptor_t *ed; 611 size_t i, ntx = 0, nrx = 0; 612 int error; 613 614 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 615 616 /* Determine the number of bulk-out pipes. */ 617 id = usbd_get_interface_descriptor(sc->sc_iface); 618 for (i = 0; i < id->bNumEndpoints; i++) { 619 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 620 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 621 continue; 622 } 623 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 624 if (ntx < sizeof(epaddr)) 625 epaddr[ntx] = ed->bEndpointAddress; 626 ntx++; 627 } 628 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 629 if (nrx < sizeof(rxepaddr)) 630 rxepaddr[nrx] = ed->bEndpointAddress; 631 nrx++; 632 } 633 } 634 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 635 aprint_error_dev(sc->sc_dev, 636 "%zd: invalid number of Rx bulk pipes\n", nrx); 637 return EIO; 638 } 639 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 640 aprint_error_dev(sc->sc_dev, 641 "%zd: invalid number of Tx bulk pipes\n", ntx); 642 return EIO; 643 } 644 DPRINTFN(DBG_INIT, ("%s: %s: found %zd/%zd bulk-in/out pipes\n", 645 device_xname(sc->sc_dev), __func__, nrx, ntx)); 646 sc->rx_npipe = nrx; 647 sc->tx_npipe = ntx; 648 649 /* Open bulk-in pipe at address 0x81. */ 650 for (i = 0; i < nrx; i++) { 651 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 652 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 653 if (error != 0) { 654 aprint_error_dev(sc->sc_dev, 655 "could not open Rx bulk pipe 0x%02x: %d\n", 656 rxepaddr[i], error); 657 goto fail; 658 } 659 } 660 661 /* Open bulk-out pipes (up to 3). */ 662 for (i = 0; i < ntx; i++) { 663 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 664 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 665 if (error != 0) { 666 aprint_error_dev(sc->sc_dev, 667 "could not open Tx bulk pipe 0x%02x: %d\n", 668 epaddr[i], error); 669 goto fail; 670 } 671 } 672 673 /* Map 802.11 access categories to USB pipes. */ 674 sc->ac2idx[WME_AC_BK] = 675 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 676 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 677 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 678 679 fail: 680 if (error != 0) 681 urtwn_close_pipes(sc); 682 return error; 683 } 684 685 static void 686 urtwn_close_pipes(struct urtwn_softc *sc) 687 { 688 struct usbd_pipe *pipe; 689 size_t i; 690 691 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 692 693 /* Close Rx pipes. */ 694 CTASSERT(sizeof(pipe) == sizeof(void *)); 695 for (i = 0; i < sc->rx_npipe; i++) { 696 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 697 if (pipe != NULL) { 698 usbd_close_pipe(pipe); 699 } 700 } 701 702 /* Close Tx pipes. */ 703 for (i = 0; i < sc->tx_npipe; i++) { 704 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 705 if (pipe != NULL) { 706 usbd_close_pipe(pipe); 707 } 708 } 709 } 710 711 static int 712 urtwn_alloc_rx_list(struct urtwn_softc *sc) 713 { 714 struct urtwn_rx_data *data; 715 size_t i; 716 int error = 0; 717 718 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 719 720 for (size_t j = 0; j < sc->rx_npipe; j++) { 721 TAILQ_INIT(&sc->rx_free_list[j]); 722 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 723 data = &sc->rx_data[j][i]; 724 725 data->sc = sc; /* Backpointer for callbacks. */ 726 727 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 728 0, 0, &data->xfer); 729 if (error) { 730 aprint_error_dev(sc->sc_dev, 731 "could not allocate xfer\n"); 732 break; 733 } 734 735 data->buf = usbd_get_buffer(data->xfer); 736 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 737 } 738 } 739 if (error != 0) 740 urtwn_free_rx_list(sc); 741 return error; 742 } 743 744 static void 745 urtwn_free_rx_list(struct urtwn_softc *sc) 746 { 747 struct usbd_xfer *xfer; 748 size_t i; 749 750 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 751 752 /* NB: Caller must abort pipe first. */ 753 for (size_t j = 0; j < sc->rx_npipe; j++) { 754 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 755 CTASSERT(sizeof(xfer) == sizeof(void *)); 756 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 757 if (xfer != NULL) 758 usbd_destroy_xfer(xfer); 759 } 760 } 761 } 762 763 static int 764 urtwn_alloc_tx_list(struct urtwn_softc *sc) 765 { 766 struct urtwn_tx_data *data; 767 size_t i; 768 int error = 0; 769 770 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 771 772 mutex_enter(&sc->sc_tx_mtx); 773 for (size_t j = 0; j < sc->tx_npipe; j++) { 774 TAILQ_INIT(&sc->tx_free_list[j]); 775 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 776 data = &sc->tx_data[j][i]; 777 778 data->sc = sc; /* Backpointer for callbacks. */ 779 data->pidx = j; 780 781 error = usbd_create_xfer(sc->tx_pipe[j], 782 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 783 &data->xfer); 784 if (error) { 785 aprint_error_dev(sc->sc_dev, 786 "could not allocate xfer\n"); 787 goto fail; 788 } 789 790 data->buf = usbd_get_buffer(data->xfer); 791 792 /* Append this Tx buffer to our free list. */ 793 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 794 } 795 } 796 mutex_exit(&sc->sc_tx_mtx); 797 return 0; 798 799 fail: 800 urtwn_free_tx_list(sc); 801 mutex_exit(&sc->sc_tx_mtx); 802 return error; 803 } 804 805 static void 806 urtwn_free_tx_list(struct urtwn_softc *sc) 807 { 808 struct usbd_xfer *xfer; 809 size_t i; 810 811 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 812 813 /* NB: Caller must abort pipe first. */ 814 for (size_t j = 0; j < sc->tx_npipe; j++) { 815 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 816 CTASSERT(sizeof(xfer) == sizeof(void *)); 817 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 818 if (xfer != NULL) 819 usbd_destroy_xfer(xfer); 820 } 821 } 822 } 823 824 static int 825 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 826 struct ieee80211_node *ni) 827 { 828 struct urtwn_tx_data *data = 829 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 830 return urtwn_tx(sc, m, ni, data); 831 } 832 833 static void 834 urtwn_task(void *arg) 835 { 836 struct urtwn_softc *sc = arg; 837 struct ieee80211com *ic = &sc->sc_ic; 838 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 839 struct urtwn_host_cmd *cmd; 840 int s; 841 842 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 843 if (ic->ic_state == IEEE80211_S_RUN && 844 (ic->ic_opmode == IEEE80211_M_HOSTAP || 845 ic->ic_opmode == IEEE80211_M_IBSS)) { 846 847 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 848 &sc->sc_bo); 849 if (m == NULL) { 850 aprint_error_dev(sc->sc_dev, 851 "could not allocate beacon"); 852 } 853 854 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 855 m_freem(m); 856 aprint_error_dev(sc->sc_dev, "could not send beacon"); 857 } 858 859 /* beacon is no longer needed */ 860 m_freem(m); 861 } 862 863 /* Process host commands. */ 864 s = splusb(); 865 mutex_spin_enter(&sc->sc_task_mtx); 866 while (ring->next != ring->cur) { 867 cmd = &ring->cmd[ring->next]; 868 mutex_spin_exit(&sc->sc_task_mtx); 869 splx(s); 870 /* Invoke callback with kernel lock held. */ 871 cmd->cb(sc, cmd->data); 872 s = splusb(); 873 mutex_spin_enter(&sc->sc_task_mtx); 874 ring->queued--; 875 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 876 } 877 mutex_spin_exit(&sc->sc_task_mtx); 878 wakeup(&sc->cmdq); 879 splx(s); 880 } 881 882 static void 883 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 884 void *arg, int len) 885 { 886 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 887 struct urtwn_host_cmd *cmd; 888 int s; 889 890 DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", 891 device_xname(sc->sc_dev), __func__, cb, arg, len)); 892 893 s = splusb(); 894 mutex_spin_enter(&sc->sc_task_mtx); 895 cmd = &ring->cmd[ring->cur]; 896 cmd->cb = cb; 897 KASSERT(len <= sizeof(cmd->data)); 898 memcpy(cmd->data, arg, len); 899 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 900 901 /* If there is no pending command already, schedule a task. */ 902 if (!sc->sc_dying && ++ring->queued == 1) { 903 mutex_spin_exit(&sc->sc_task_mtx); 904 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 905 } else 906 mutex_spin_exit(&sc->sc_task_mtx); 907 splx(s); 908 } 909 910 static void 911 urtwn_wait_async(struct urtwn_softc *sc) 912 { 913 914 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 915 916 /* Wait for all queued asynchronous commands to complete. */ 917 while (sc->cmdq.queued > 0) 918 tsleep(&sc->cmdq, 0, "endtask", 0); 919 } 920 921 static int 922 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 923 int len) 924 { 925 usb_device_request_t req; 926 usbd_status error; 927 928 KASSERT(mutex_owned(&sc->sc_write_mtx)); 929 930 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 931 req.bRequest = R92C_REQ_REGS; 932 USETW(req.wValue, addr); 933 USETW(req.wIndex, 0); 934 USETW(req.wLength, len); 935 error = usbd_do_request(sc->sc_udev, &req, buf); 936 if (error != USBD_NORMAL_COMPLETION) { 937 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 938 device_xname(sc->sc_dev), __func__, error, addr, len)); 939 } 940 return error; 941 } 942 943 static void 944 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 945 { 946 947 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 948 device_xname(sc->sc_dev), __func__, addr, val)); 949 950 urtwn_write_region_1(sc, addr, &val, 1); 951 } 952 953 static void 954 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 955 { 956 uint8_t buf[2]; 957 958 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 959 device_xname(sc->sc_dev), __func__, addr, val)); 960 961 buf[0] = (uint8_t)val; 962 buf[1] = (uint8_t)(val >> 8); 963 urtwn_write_region_1(sc, addr, buf, 2); 964 } 965 966 static void 967 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 968 { 969 uint8_t buf[4]; 970 971 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 972 device_xname(sc->sc_dev), __func__, addr, val)); 973 974 buf[0] = (uint8_t)val; 975 buf[1] = (uint8_t)(val >> 8); 976 buf[2] = (uint8_t)(val >> 16); 977 buf[3] = (uint8_t)(val >> 24); 978 urtwn_write_region_1(sc, addr, buf, 4); 979 } 980 981 static int 982 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 983 { 984 985 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, len=0x%x\n", 986 device_xname(sc->sc_dev), __func__, addr, len)); 987 988 return urtwn_write_region_1(sc, addr, buf, len); 989 } 990 991 static int 992 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 993 int len) 994 { 995 usb_device_request_t req; 996 usbd_status error; 997 998 req.bmRequestType = UT_READ_VENDOR_DEVICE; 999 req.bRequest = R92C_REQ_REGS; 1000 USETW(req.wValue, addr); 1001 USETW(req.wIndex, 0); 1002 USETW(req.wLength, len); 1003 error = usbd_do_request(sc->sc_udev, &req, buf); 1004 if (error != USBD_NORMAL_COMPLETION) { 1005 DPRINTFN(DBG_REG, ("%s: %s: error=%d: addr=0x%x, len=%d\n", 1006 device_xname(sc->sc_dev), __func__, error, addr, len)); 1007 } 1008 return error; 1009 } 1010 1011 static uint8_t 1012 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1013 { 1014 uint8_t val; 1015 1016 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1017 return 0xff; 1018 1019 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1020 device_xname(sc->sc_dev), __func__, addr, val)); 1021 return val; 1022 } 1023 1024 static uint16_t 1025 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1026 { 1027 uint8_t buf[2]; 1028 uint16_t val; 1029 1030 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1031 return 0xffff; 1032 1033 val = LE_READ_2(&buf[0]); 1034 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1035 device_xname(sc->sc_dev), __func__, addr, val)); 1036 return val; 1037 } 1038 1039 static uint32_t 1040 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1041 { 1042 uint8_t buf[4]; 1043 uint32_t val; 1044 1045 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1046 return 0xffffffff; 1047 1048 val = LE_READ_4(&buf[0]); 1049 DPRINTFN(DBG_REG, ("%s: %s: addr=0x%x, val=0x%x\n", 1050 device_xname(sc->sc_dev), __func__, addr, val)); 1051 return val; 1052 } 1053 1054 static int 1055 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1056 { 1057 struct r92c_fw_cmd cmd; 1058 uint8_t *cp; 1059 int fwcur; 1060 int ntries; 1061 1062 DPRINTFN(DBG_REG, ("%s: %s: id=%d, buf=%p, len=%d\n", 1063 device_xname(sc->sc_dev), __func__, id, buf, len)); 1064 1065 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1066 1067 mutex_enter(&sc->sc_fwcmd_mtx); 1068 fwcur = sc->fwcur; 1069 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1070 mutex_exit(&sc->sc_fwcmd_mtx); 1071 1072 /* Wait for current FW box to be empty. */ 1073 for (ntries = 0; ntries < 100; ntries++) { 1074 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1075 break; 1076 DELAY(2000); 1077 } 1078 if (ntries == 100) { 1079 aprint_error_dev(sc->sc_dev, 1080 "could not send firmware command %d\n", id); 1081 return ETIMEDOUT; 1082 } 1083 1084 memset(&cmd, 0, sizeof(cmd)); 1085 KASSERT(len <= sizeof(cmd.msg)); 1086 memcpy(cmd.msg, buf, len); 1087 1088 /* Write the first word last since that will trigger the FW. */ 1089 cp = (uint8_t *)&cmd; 1090 cmd.id = id; 1091 if (len >= 4) { 1092 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1093 cmd.id |= R92C_CMD_FLAG_EXT; 1094 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1095 &cp[1], 2); 1096 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1097 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1098 ((uint32_t)cp[5] << 24)); 1099 } else { 1100 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1101 &cp[4], 2); 1102 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1103 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1104 ((uint32_t)cp[3] << 24)); 1105 } 1106 } else { 1107 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1108 } 1109 1110 return 0; 1111 } 1112 1113 static __inline void 1114 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1115 { 1116 1117 sc->sc_rf_write(sc, chain, addr, val); 1118 } 1119 1120 static void 1121 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1122 uint32_t val) 1123 { 1124 1125 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1126 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1127 } 1128 1129 static void 1130 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1131 uint32_t val) 1132 { 1133 1134 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1135 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1136 } 1137 1138 static void 1139 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1140 uint32_t val) 1141 { 1142 1143 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1144 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1145 } 1146 1147 static uint32_t 1148 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1149 { 1150 uint32_t reg[R92C_MAX_CHAINS], val; 1151 1152 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1153 if (chain != 0) { 1154 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1155 } 1156 1157 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1158 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1159 DELAY(1000); 1160 1161 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1162 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1163 R92C_HSSI_PARAM2_READ_EDGE); 1164 DELAY(1000); 1165 1166 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1167 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1168 DELAY(1000); 1169 1170 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1171 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1172 } else { 1173 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1174 } 1175 return MS(val, R92C_LSSI_READBACK_DATA); 1176 } 1177 1178 static int 1179 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1180 { 1181 int ntries; 1182 1183 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1184 1185 urtwn_write_4(sc, R92C_LLT_INIT, 1186 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1187 SM(R92C_LLT_INIT_ADDR, addr) | 1188 SM(R92C_LLT_INIT_DATA, data)); 1189 /* Wait for write operation to complete. */ 1190 for (ntries = 0; ntries < 20; ntries++) { 1191 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1192 R92C_LLT_INIT_OP_NO_ACTIVE) { 1193 /* Done */ 1194 return 0; 1195 } 1196 DELAY(5); 1197 } 1198 return ETIMEDOUT; 1199 } 1200 1201 static uint8_t 1202 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1203 { 1204 uint32_t reg; 1205 int ntries; 1206 1207 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1208 1209 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1210 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1211 reg &= ~R92C_EFUSE_CTRL_VALID; 1212 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1213 1214 /* Wait for read operation to complete. */ 1215 for (ntries = 0; ntries < 100; ntries++) { 1216 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1217 if (reg & R92C_EFUSE_CTRL_VALID) { 1218 /* Done */ 1219 return MS(reg, R92C_EFUSE_CTRL_DATA); 1220 } 1221 DELAY(5); 1222 } 1223 aprint_error_dev(sc->sc_dev, 1224 "could not read efuse byte at address 0x%04x\n", addr); 1225 return 0xff; 1226 } 1227 1228 static void 1229 urtwn_efuse_read(struct urtwn_softc *sc) 1230 { 1231 uint8_t *rom = (uint8_t *)&sc->rom; 1232 uint32_t reg; 1233 uint16_t addr = 0; 1234 uint8_t off, msk; 1235 size_t i; 1236 1237 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1238 1239 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1240 1241 urtwn_efuse_switch_power(sc); 1242 1243 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1244 while (addr < 512) { 1245 reg = urtwn_efuse_read_1(sc, addr); 1246 if (reg == 0xff) 1247 break; 1248 addr++; 1249 off = reg >> 4; 1250 msk = reg & 0xf; 1251 for (i = 0; i < 4; i++) { 1252 if (msk & (1U << i)) 1253 continue; 1254 1255 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1256 addr++; 1257 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1258 addr++; 1259 } 1260 } 1261 #ifdef URTWN_DEBUG 1262 if (urtwn_debug & DBG_INIT) { 1263 /* Dump ROM content. */ 1264 printf("%s: %s", device_xname(sc->sc_dev), __func__); 1265 for (i = 0; i < (int)sizeof(sc->rom); i++) 1266 printf(":%02x", rom[i]); 1267 printf("\n"); 1268 } 1269 #endif 1270 } 1271 1272 static void 1273 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1274 { 1275 uint32_t reg; 1276 1277 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1278 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1279 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1280 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1281 } 1282 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1283 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1284 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1285 reg | R92C_SYS_FUNC_EN_ELDR); 1286 } 1287 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1288 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1289 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1290 urtwn_write_2(sc, R92C_SYS_CLKR, 1291 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1292 } 1293 } 1294 1295 static int 1296 urtwn_read_chipid(struct urtwn_softc *sc) 1297 { 1298 uint32_t reg; 1299 1300 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1301 1302 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1303 ISSET(sc->chip, URTWN_CHIP_92EU)) 1304 return 0; 1305 1306 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1307 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1308 /* test chip, not supported */ 1309 return EIO; 1310 } 1311 if (reg & R92C_SYS_CFG_TYPE_92C) { 1312 sc->chip |= URTWN_CHIP_92C; 1313 /* Check if it is a castrated 8192C. */ 1314 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1315 R92C_HPON_FSM_CHIP_BONDING_ID) == 1316 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1317 sc->chip |= URTWN_CHIP_92C_1T2R; 1318 } 1319 } 1320 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1321 sc->chip |= URTWN_CHIP_UMC; 1322 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1323 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1324 } 1325 } 1326 return 0; 1327 } 1328 1329 #ifdef URTWN_DEBUG 1330 static void 1331 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1332 { 1333 1334 aprint_normal_dev(sc->sc_dev, 1335 "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", 1336 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1337 1338 aprint_normal_dev(sc->sc_dev, 1339 "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", 1340 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1341 1342 aprint_normal_dev(sc->sc_dev, 1343 "macaddr %s\n", 1344 ether_sprintf(rp->macaddr)); 1345 1346 aprint_normal_dev(sc->sc_dev, 1347 "string %s, subcustomer_id 0x%x\n", 1348 rp->string, rp->subcustomer_id); 1349 1350 aprint_normal_dev(sc->sc_dev, 1351 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1352 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1353 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1354 1355 aprint_normal_dev(sc->sc_dev, 1356 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1357 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1358 rp->ht40_1s_tx_pwr[0][2], 1359 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1360 rp->ht40_1s_tx_pwr[1][2]); 1361 1362 aprint_normal_dev(sc->sc_dev, 1363 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1364 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1365 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1366 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1367 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1368 1369 aprint_normal_dev(sc->sc_dev, 1370 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1371 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1372 rp->ht20_tx_pwr_diff[2] & 0xf, 1373 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1374 rp->ht20_tx_pwr_diff[2] >> 4); 1375 1376 aprint_normal_dev(sc->sc_dev, 1377 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1378 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1379 rp->ofdm_tx_pwr_diff[2] & 0xf, 1380 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1381 rp->ofdm_tx_pwr_diff[2] >> 4); 1382 1383 aprint_normal_dev(sc->sc_dev, 1384 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1385 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1386 rp->ht40_max_pwr[2] & 0xf, 1387 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1388 rp->ht40_max_pwr[2] >> 4); 1389 1390 aprint_normal_dev(sc->sc_dev, 1391 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1392 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1393 rp->ht20_max_pwr[2] & 0xf, 1394 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1395 rp->ht20_max_pwr[2] >> 4); 1396 1397 aprint_normal_dev(sc->sc_dev, 1398 "xtal_calib %d, tssi %d %d, thermal %d\n", 1399 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1400 1401 aprint_normal_dev(sc->sc_dev, 1402 "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", 1403 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1404 1405 aprint_normal_dev(sc->sc_dev, 1406 "channnel_plan %d, version %d customer_id 0x%x\n", 1407 rp->channel_plan, rp->version, rp->curstomer_id); 1408 } 1409 #endif 1410 1411 static void 1412 urtwn_read_rom(struct urtwn_softc *sc) 1413 { 1414 struct ieee80211com *ic = &sc->sc_ic; 1415 struct r92c_rom *rom = &sc->rom; 1416 1417 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1418 1419 mutex_enter(&sc->sc_write_mtx); 1420 1421 /* Read full ROM image. */ 1422 urtwn_efuse_read(sc); 1423 #ifdef URTWN_DEBUG 1424 if (urtwn_debug & DBG_REG) 1425 urtwn_dump_rom(sc, rom); 1426 #endif 1427 1428 /* XXX Weird but this is what the vendor driver does. */ 1429 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1430 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1431 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1432 1433 DPRINTFN(DBG_INIT, 1434 ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", 1435 device_xname(sc->sc_dev), __func__, sc->pa_setting, 1436 sc->board_type, sc->regulatory)); 1437 1438 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1439 1440 sc->sc_rf_write = urtwn_r92c_rf_write; 1441 sc->sc_power_on = urtwn_r92c_power_on; 1442 sc->sc_dma_init = urtwn_r92c_dma_init; 1443 1444 mutex_exit(&sc->sc_write_mtx); 1445 } 1446 1447 static void 1448 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1449 { 1450 struct ieee80211com *ic = &sc->sc_ic; 1451 uint8_t *rom = sc->r88e_rom; 1452 uint32_t reg; 1453 uint16_t addr = 0; 1454 uint8_t off, msk, tmp; 1455 int i; 1456 1457 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1458 1459 mutex_enter(&sc->sc_write_mtx); 1460 1461 off = 0; 1462 urtwn_efuse_switch_power(sc); 1463 1464 /* Read full ROM image. */ 1465 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1466 while (addr < 4096) { 1467 reg = urtwn_efuse_read_1(sc, addr); 1468 if (reg == 0xff) 1469 break; 1470 addr++; 1471 if ((reg & 0x1f) == 0x0f) { 1472 tmp = (reg & 0xe0) >> 5; 1473 reg = urtwn_efuse_read_1(sc, addr); 1474 if ((reg & 0x0f) != 0x0f) 1475 off = ((reg & 0xf0) >> 1) | tmp; 1476 addr++; 1477 } else 1478 off = reg >> 4; 1479 msk = reg & 0xf; 1480 for (i = 0; i < 4; i++) { 1481 if (msk & (1 << i)) 1482 continue; 1483 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1484 addr++; 1485 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1486 addr++; 1487 } 1488 } 1489 #ifdef URTWN_DEBUG 1490 if (urtwn_debug & DBG_REG) { 1491 } 1492 #endif 1493 1494 addr = 0x10; 1495 for (i = 0; i < 6; i++) 1496 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1497 for (i = 0; i < 5; i++) 1498 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1499 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1500 if (sc->bw20_tx_pwr_diff & 0x08) 1501 sc->bw20_tx_pwr_diff |= 0xf0; 1502 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1503 if (sc->ofdm_tx_pwr_diff & 0x08) 1504 sc->ofdm_tx_pwr_diff |= 0xf0; 1505 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1506 1507 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1508 1509 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1510 sc->sc_power_on = urtwn_r92e_power_on; 1511 sc->sc_rf_write = urtwn_r92e_rf_write; 1512 } else { 1513 sc->sc_power_on = urtwn_r88e_power_on; 1514 sc->sc_rf_write = urtwn_r88e_rf_write; 1515 } 1516 sc->sc_dma_init = urtwn_r88e_dma_init; 1517 1518 mutex_exit(&sc->sc_write_mtx); 1519 } 1520 1521 static int 1522 urtwn_media_change(struct ifnet *ifp) 1523 { 1524 #ifdef URTWN_DEBUG 1525 struct urtwn_softc *sc = ifp->if_softc; 1526 #endif 1527 int error; 1528 1529 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1530 1531 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1532 return error; 1533 1534 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1535 (IFF_UP | IFF_RUNNING)) { 1536 urtwn_init(ifp); 1537 } 1538 return 0; 1539 } 1540 1541 /* 1542 * Initialize rate adaptation in firmware. 1543 */ 1544 static int 1545 urtwn_ra_init(struct urtwn_softc *sc) 1546 { 1547 static const uint8_t map[] = { 1548 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1549 }; 1550 struct ieee80211com *ic = &sc->sc_ic; 1551 struct ieee80211_node *ni = ic->ic_bss; 1552 struct ieee80211_rateset *rs = &ni->ni_rates; 1553 struct r92c_fw_cmd_macid_cfg cmd; 1554 uint32_t rates, basicrates; 1555 uint32_t rrsr_mask, rrsr_rate; 1556 uint8_t mode; 1557 size_t maxrate, maxbasicrate, i, j; 1558 int error; 1559 1560 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1561 1562 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1563 1564 /* Get normal and basic rates mask. */ 1565 rates = basicrates = 1; 1566 maxrate = maxbasicrate = 0; 1567 for (i = 0; i < rs->rs_nrates; i++) { 1568 /* Convert 802.11 rate to HW rate index. */ 1569 for (j = 0; j < __arraycount(map); j++) { 1570 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1571 break; 1572 } 1573 } 1574 if (j == __arraycount(map)) { 1575 /* Unknown rate, skip. */ 1576 continue; 1577 } 1578 1579 rates |= 1U << j; 1580 if (j > maxrate) { 1581 maxrate = j; 1582 } 1583 1584 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1585 basicrates |= 1U << j; 1586 if (j > maxbasicrate) { 1587 maxbasicrate = j; 1588 } 1589 } 1590 } 1591 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1592 mode = R92C_RAID_11B; 1593 } else { 1594 mode = R92C_RAID_11BG; 1595 } 1596 DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x, " 1597 "maxrate=%zx, maxbasicrate=%zx\n", 1598 device_xname(sc->sc_dev), __func__, mode, rates, basicrates, 1599 maxrate, maxbasicrate)); 1600 1601 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1602 maxbasicrate |= R92C_RATE_SHORTGI; 1603 maxrate |= R92C_RATE_SHORTGI; 1604 } 1605 1606 /* Set rates mask for group addressed frames. */ 1607 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1608 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1609 cmd.macid |= RTWN_MACID_SHORTGI; 1610 cmd.mask = htole32((mode << 28) | basicrates); 1611 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1612 if (error != 0) { 1613 aprint_error_dev(sc->sc_dev, 1614 "could not add broadcast station\n"); 1615 return error; 1616 } 1617 /* Set initial MRR rate. */ 1618 DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%zd\n", 1619 device_xname(sc->sc_dev), __func__, maxbasicrate)); 1620 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1621 1622 /* Set rates mask for unicast frames. */ 1623 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1624 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1625 cmd.macid |= RTWN_MACID_SHORTGI; 1626 cmd.mask = htole32((mode << 28) | rates); 1627 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1628 if (error != 0) { 1629 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1630 return error; 1631 } 1632 /* Set initial MRR rate. */ 1633 DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%zd\n", device_xname(sc->sc_dev), 1634 __func__, maxrate)); 1635 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1636 1637 rrsr_rate = ic->ic_fixed_rate; 1638 if (rrsr_rate == -1) 1639 rrsr_rate = 11; 1640 1641 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1642 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1643 1644 /* Indicate highest supported rate. */ 1645 ni->ni_txrate = rs->rs_nrates - 1; 1646 1647 return 0; 1648 } 1649 1650 static int 1651 urtwn_get_nettype(struct urtwn_softc *sc) 1652 { 1653 struct ieee80211com *ic = &sc->sc_ic; 1654 int type; 1655 1656 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1657 1658 switch (ic->ic_opmode) { 1659 case IEEE80211_M_STA: 1660 type = R92C_CR_NETTYPE_INFRA; 1661 break; 1662 1663 case IEEE80211_M_IBSS: 1664 type = R92C_CR_NETTYPE_ADHOC; 1665 break; 1666 1667 default: 1668 type = R92C_CR_NETTYPE_NOLINK; 1669 break; 1670 } 1671 1672 return type; 1673 } 1674 1675 static void 1676 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1677 { 1678 uint8_t reg; 1679 1680 DPRINTFN(DBG_FN, ("%s: %s: type=%d\n", device_xname(sc->sc_dev), 1681 __func__, type)); 1682 1683 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1684 1685 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1686 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1687 } 1688 1689 static void 1690 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1691 { 1692 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1693 uint64_t tsf; 1694 1695 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1696 1697 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1698 1699 /* Enable TSF synchronization. */ 1700 urtwn_write_1(sc, R92C_BCN_CTRL, 1701 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1702 1703 /* Correct TSF */ 1704 urtwn_write_1(sc, R92C_BCN_CTRL, 1705 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1706 1707 /* Set initial TSF. */ 1708 tsf = ni->ni_tstamp.tsf; 1709 tsf = le64toh(tsf); 1710 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1711 tsf -= IEEE80211_DUR_TU; 1712 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1713 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1714 1715 urtwn_write_1(sc, R92C_BCN_CTRL, 1716 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1717 } 1718 1719 static void 1720 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1721 { 1722 uint8_t reg; 1723 1724 DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), 1725 __func__, led, on)); 1726 1727 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1728 1729 if (led == URTWN_LED_LINK) { 1730 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1731 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1732 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1733 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1734 (R92C_LEDCFG0_DIS << 1)); 1735 if (on) { 1736 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1737 R92E_LEDSON; 1738 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1739 } 1740 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1741 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1742 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1743 if (!on) { 1744 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1745 urtwn_write_1(sc, R92C_LEDCFG2, 1746 reg | R92C_LEDCFG0_DIS); 1747 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1748 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1749 reg & 0xfe); 1750 } 1751 } else { 1752 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1753 if (!on) { 1754 reg |= R92C_LEDCFG0_DIS; 1755 } 1756 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1757 } 1758 sc->ledlink = on; /* Save LED state. */ 1759 } 1760 } 1761 1762 static void 1763 urtwn_calib_to(void *arg) 1764 { 1765 struct urtwn_softc *sc = arg; 1766 1767 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1768 1769 if (sc->sc_dying) 1770 return; 1771 1772 /* Do it in a process context. */ 1773 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1774 } 1775 1776 /* ARGSUSED */ 1777 static void 1778 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1779 { 1780 struct r92c_fw_cmd_rssi cmd; 1781 struct r92e_fw_cmd_rssi cmde; 1782 1783 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1784 1785 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1786 goto restart_timer; 1787 1788 mutex_enter(&sc->sc_write_mtx); 1789 if (sc->avg_pwdb != -1) { 1790 /* Indicate Rx signal strength to FW for rate adaptation. */ 1791 memset(&cmd, 0, sizeof(cmd)); 1792 memset(&cmde, 0, sizeof(cmde)); 1793 cmd.macid = 0; /* BSS. */ 1794 cmde.macid = 0; /* BSS. */ 1795 cmd.pwdb = sc->avg_pwdb; 1796 cmde.pwdb = sc->avg_pwdb; 1797 DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", 1798 device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); 1799 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1800 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1801 sizeof(cmd)); 1802 } else { 1803 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1804 sizeof(cmde)); 1805 } 1806 } 1807 1808 /* Do temperature compensation. */ 1809 urtwn_temp_calib(sc); 1810 mutex_exit(&sc->sc_write_mtx); 1811 1812 restart_timer: 1813 if (!sc->sc_dying) { 1814 /* Restart calibration timer. */ 1815 callout_schedule(&sc->sc_calib_to, hz); 1816 } 1817 } 1818 1819 static void 1820 urtwn_next_scan(void *arg) 1821 { 1822 struct urtwn_softc *sc = arg; 1823 int s; 1824 1825 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1826 1827 if (sc->sc_dying) 1828 return; 1829 1830 s = splnet(); 1831 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1832 ieee80211_next_scan(&sc->sc_ic); 1833 splx(s); 1834 } 1835 1836 static void 1837 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1838 { 1839 DPRINTFN(DBG_FN, ("%s: new node %s\n", __func__, 1840 ether_sprintf(ni->ni_macaddr))); 1841 /* start with lowest Tx rate */ 1842 ni->ni_txrate = 0; 1843 } 1844 1845 static int 1846 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1847 { 1848 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1849 struct urtwn_cmd_newstate cmd; 1850 1851 DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", 1852 device_xname(sc->sc_dev), __func__, 1853 ieee80211_state_name[nstate], nstate, arg)); 1854 1855 callout_stop(&sc->sc_scan_to); 1856 callout_stop(&sc->sc_calib_to); 1857 1858 /* Do it in a process context. */ 1859 cmd.state = nstate; 1860 cmd.arg = arg; 1861 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1862 return 0; 1863 } 1864 1865 static void 1866 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1867 { 1868 struct urtwn_cmd_newstate *cmd = arg; 1869 struct ieee80211com *ic = &sc->sc_ic; 1870 struct ieee80211_node *ni; 1871 enum ieee80211_state ostate = ic->ic_state; 1872 enum ieee80211_state nstate = cmd->state; 1873 uint32_t reg; 1874 uint8_t sifs_time, msr; 1875 int s; 1876 1877 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", 1878 device_xname(sc->sc_dev), __func__, 1879 ieee80211_state_name[ostate], ostate, 1880 ieee80211_state_name[nstate], nstate)); 1881 1882 s = splnet(); 1883 mutex_enter(&sc->sc_write_mtx); 1884 1885 callout_stop(&sc->sc_scan_to); 1886 callout_stop(&sc->sc_calib_to); 1887 1888 switch (ostate) { 1889 case IEEE80211_S_INIT: 1890 break; 1891 1892 case IEEE80211_S_SCAN: 1893 if (nstate != IEEE80211_S_SCAN) { 1894 /* 1895 * End of scanning 1896 */ 1897 /* flush 4-AC Queue after site_survey */ 1898 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1899 1900 /* Allow Rx from our BSSID only. */ 1901 urtwn_write_4(sc, R92C_RCR, 1902 urtwn_read_4(sc, R92C_RCR) | 1903 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1904 } 1905 break; 1906 1907 case IEEE80211_S_AUTH: 1908 case IEEE80211_S_ASSOC: 1909 break; 1910 1911 case IEEE80211_S_RUN: 1912 /* Turn link LED off. */ 1913 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1914 1915 /* Set media status to 'No Link'. */ 1916 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1917 1918 /* Stop Rx of data frames. */ 1919 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1920 1921 /* Reset TSF. */ 1922 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1923 1924 /* Disable TSF synchronization. */ 1925 urtwn_write_1(sc, R92C_BCN_CTRL, 1926 urtwn_read_1(sc, R92C_BCN_CTRL) | 1927 R92C_BCN_CTRL_DIS_TSF_UDT0); 1928 1929 /* Back to 20MHz mode */ 1930 urtwn_set_chan(sc, ic->ic_curchan, 1931 IEEE80211_HTINFO_2NDCHAN_NONE); 1932 1933 if (ic->ic_opmode == IEEE80211_M_IBSS || 1934 ic->ic_opmode == IEEE80211_M_HOSTAP) { 1935 /* Stop BCN */ 1936 urtwn_write_1(sc, R92C_BCN_CTRL, 1937 urtwn_read_1(sc, R92C_BCN_CTRL) & 1938 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 1939 } 1940 1941 /* Reset EDCA parameters. */ 1942 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1943 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1944 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1945 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1946 1947 /* flush all cam entries */ 1948 urtwn_cam_init(sc); 1949 break; 1950 } 1951 1952 switch (nstate) { 1953 case IEEE80211_S_INIT: 1954 /* Turn link LED off. */ 1955 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1956 break; 1957 1958 case IEEE80211_S_SCAN: 1959 if (ostate != IEEE80211_S_SCAN) { 1960 /* 1961 * Begin of scanning 1962 */ 1963 1964 /* Set gain for scanning. */ 1965 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1966 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1967 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1968 1969 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 1970 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1971 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1972 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1973 } 1974 1975 /* Set media status to 'No Link'. */ 1976 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1977 1978 /* Allow Rx from any BSSID. */ 1979 urtwn_write_4(sc, R92C_RCR, 1980 urtwn_read_4(sc, R92C_RCR) & 1981 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1982 1983 /* Stop Rx of data frames. */ 1984 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1985 1986 /* Disable update TSF */ 1987 urtwn_write_1(sc, R92C_BCN_CTRL, 1988 urtwn_read_1(sc, R92C_BCN_CTRL) | 1989 R92C_BCN_CTRL_DIS_TSF_UDT0); 1990 } 1991 1992 /* Make link LED blink during scan. */ 1993 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1994 1995 /* Pause AC Tx queues. */ 1996 urtwn_write_1(sc, R92C_TXPAUSE, 1997 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1998 1999 urtwn_set_chan(sc, ic->ic_curchan, 2000 IEEE80211_HTINFO_2NDCHAN_NONE); 2001 2002 /* Start periodic scan. */ 2003 if (!sc->sc_dying) 2004 callout_schedule(&sc->sc_scan_to, hz / 5); 2005 break; 2006 2007 case IEEE80211_S_AUTH: 2008 /* Set initial gain under link. */ 2009 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2010 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2011 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2012 2013 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2014 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2015 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2016 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2017 } 2018 2019 /* Set media status to 'No Link'. */ 2020 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2021 2022 /* Allow Rx from any BSSID. */ 2023 urtwn_write_4(sc, R92C_RCR, 2024 urtwn_read_4(sc, R92C_RCR) & 2025 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2026 2027 urtwn_set_chan(sc, ic->ic_curchan, 2028 IEEE80211_HTINFO_2NDCHAN_NONE); 2029 break; 2030 2031 case IEEE80211_S_ASSOC: 2032 break; 2033 2034 case IEEE80211_S_RUN: 2035 ni = ic->ic_bss; 2036 2037 /* XXX: Set 20MHz mode */ 2038 urtwn_set_chan(sc, ic->ic_curchan, 2039 IEEE80211_HTINFO_2NDCHAN_NONE); 2040 2041 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2042 /* Back to 20MHz mode */ 2043 urtwn_set_chan(sc, ic->ic_curchan, 2044 IEEE80211_HTINFO_2NDCHAN_NONE); 2045 2046 /* Set media status to 'No Link'. */ 2047 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2048 2049 /* Enable Rx of data frames. */ 2050 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2051 2052 /* Allow Rx from any BSSID. */ 2053 urtwn_write_4(sc, R92C_RCR, 2054 urtwn_read_4(sc, R92C_RCR) & 2055 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2056 2057 /* Accept Rx data/control/management frames */ 2058 urtwn_write_4(sc, R92C_RCR, 2059 urtwn_read_4(sc, R92C_RCR) | 2060 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2061 2062 /* Turn link LED on. */ 2063 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2064 break; 2065 } 2066 2067 /* Set media status to 'Associated'. */ 2068 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2069 2070 /* Set BSSID. */ 2071 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2072 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2073 2074 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2075 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2076 } else { 2077 /* 802.11b/g */ 2078 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2079 } 2080 2081 /* Enable Rx of data frames. */ 2082 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2083 2084 /* Set beacon interval. */ 2085 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2086 2087 msr = urtwn_read_1(sc, R92C_MSR); 2088 msr &= R92C_MSR_MASK; 2089 switch (ic->ic_opmode) { 2090 case IEEE80211_M_STA: 2091 /* Allow Rx from our BSSID only. */ 2092 urtwn_write_4(sc, R92C_RCR, 2093 urtwn_read_4(sc, R92C_RCR) | 2094 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2095 2096 /* Enable TSF synchronization. */ 2097 urtwn_tsf_sync_enable(sc); 2098 2099 msr |= R92C_MSR_INFRA; 2100 break; 2101 case IEEE80211_M_HOSTAP: 2102 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2103 2104 /* Allow Rx from any BSSID. */ 2105 urtwn_write_4(sc, R92C_RCR, 2106 urtwn_read_4(sc, R92C_RCR) & 2107 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2108 2109 /* Reset TSF timer to zero. */ 2110 reg = urtwn_read_4(sc, R92C_TCR); 2111 reg &= ~0x01; 2112 urtwn_write_4(sc, R92C_TCR, reg); 2113 reg |= 0x01; 2114 urtwn_write_4(sc, R92C_TCR, reg); 2115 2116 msr |= R92C_MSR_AP; 2117 break; 2118 default: 2119 msr |= R92C_MSR_ADHOC; 2120 break; 2121 } 2122 urtwn_write_1(sc, R92C_MSR, msr); 2123 2124 sifs_time = 10; 2125 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2126 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2127 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2128 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2129 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2130 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2131 2132 /* Initialize rate adaptation. */ 2133 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2134 ISSET(sc->chip, URTWN_CHIP_92EU)) 2135 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2136 else 2137 urtwn_ra_init(sc); 2138 2139 /* Turn link LED on. */ 2140 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2141 2142 /* Reset average RSSI. */ 2143 sc->avg_pwdb = -1; 2144 2145 /* Reset temperature calibration state machine. */ 2146 sc->thcal_state = 0; 2147 sc->thcal_lctemp = 0; 2148 2149 /* Start periodic calibration. */ 2150 if (!sc->sc_dying) 2151 callout_schedule(&sc->sc_calib_to, hz); 2152 break; 2153 } 2154 2155 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2156 2157 mutex_exit(&sc->sc_write_mtx); 2158 splx(s); 2159 } 2160 2161 static int 2162 urtwn_wme_update(struct ieee80211com *ic) 2163 { 2164 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2165 2166 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2167 2168 /* don't override default WME values if WME is not actually enabled */ 2169 if (!(ic->ic_flags & IEEE80211_F_WME)) 2170 return 0; 2171 2172 /* Do it in a process context. */ 2173 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2174 return 0; 2175 } 2176 2177 static void 2178 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2179 { 2180 static const uint16_t ac2reg[WME_NUM_AC] = { 2181 R92C_EDCA_BE_PARAM, 2182 R92C_EDCA_BK_PARAM, 2183 R92C_EDCA_VI_PARAM, 2184 R92C_EDCA_VO_PARAM 2185 }; 2186 struct ieee80211com *ic = &sc->sc_ic; 2187 const struct wmeParams *wmep; 2188 int ac, aifs, slottime; 2189 int s; 2190 2191 DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), 2192 __func__)); 2193 2194 s = splnet(); 2195 mutex_enter(&sc->sc_write_mtx); 2196 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2197 for (ac = 0; ac < WME_NUM_AC; ac++) { 2198 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2199 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2200 aifs = wmep->wmep_aifsn * slottime + 10; 2201 urtwn_write_4(sc, ac2reg[ac], 2202 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2203 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2204 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2205 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2206 } 2207 mutex_exit(&sc->sc_write_mtx); 2208 splx(s); 2209 } 2210 2211 static void 2212 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2213 { 2214 int pwdb; 2215 2216 DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", 2217 device_xname(sc->sc_dev), __func__, rate, rssi)); 2218 2219 /* Convert antenna signal to percentage. */ 2220 if (rssi <= -100 || rssi >= 20) 2221 pwdb = 0; 2222 else if (rssi >= 0) 2223 pwdb = 100; 2224 else 2225 pwdb = 100 + rssi; 2226 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2227 if (rate <= 3) { 2228 /* CCK gain is smaller than OFDM/MCS gain. */ 2229 pwdb += 6; 2230 if (pwdb > 100) 2231 pwdb = 100; 2232 if (pwdb <= 14) 2233 pwdb -= 4; 2234 else if (pwdb <= 26) 2235 pwdb -= 8; 2236 else if (pwdb <= 34) 2237 pwdb -= 6; 2238 else if (pwdb <= 42) 2239 pwdb -= 2; 2240 } 2241 } 2242 if (sc->avg_pwdb == -1) /* Init. */ 2243 sc->avg_pwdb = pwdb; 2244 else if (sc->avg_pwdb < pwdb) 2245 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2246 else 2247 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2248 2249 DPRINTFN(DBG_RF, ("%s: %s: rate=%d rssi=%d PWDB=%d EMA=%d\n", 2250 device_xname(sc->sc_dev), __func__, 2251 rate, rssi, pwdb, sc->avg_pwdb)); 2252 } 2253 2254 static int8_t 2255 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2256 { 2257 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2258 struct r92c_rx_phystat *phy; 2259 struct r92c_rx_cck *cck; 2260 uint8_t rpt; 2261 int8_t rssi; 2262 2263 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2264 __func__, rate)); 2265 2266 if (rate <= 3) { 2267 cck = (struct r92c_rx_cck *)physt; 2268 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2269 rpt = (cck->agc_rpt >> 5) & 0x3; 2270 rssi = (cck->agc_rpt & 0x1f) << 1; 2271 } else { 2272 rpt = (cck->agc_rpt >> 6) & 0x3; 2273 rssi = cck->agc_rpt & 0x3e; 2274 } 2275 rssi = cckoff[rpt] - rssi; 2276 } else { /* OFDM/HT. */ 2277 phy = (struct r92c_rx_phystat *)physt; 2278 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2279 } 2280 return rssi; 2281 } 2282 2283 static int8_t 2284 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2285 { 2286 struct r92c_rx_phystat *phy; 2287 struct r88e_rx_cck *cck; 2288 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2289 int8_t rssi; 2290 2291 DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), 2292 __func__, rate)); 2293 2294 rssi = 0; 2295 if (rate <= 3) { 2296 cck = (struct r88e_rx_cck *)physt; 2297 cck_agc_rpt = cck->agc_rpt; 2298 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2299 vga_idx = cck_agc_rpt & 0x1f; 2300 switch (lna_idx) { 2301 case 7: 2302 if (vga_idx <= 27) 2303 rssi = -100 + 2* (27 - vga_idx); 2304 else 2305 rssi = -100; 2306 break; 2307 case 6: 2308 rssi = -48 + 2 * (2 - vga_idx); 2309 break; 2310 case 5: 2311 rssi = -42 + 2 * (7 - vga_idx); 2312 break; 2313 case 4: 2314 rssi = -36 + 2 * (7 - vga_idx); 2315 break; 2316 case 3: 2317 rssi = -24 + 2 * (7 - vga_idx); 2318 break; 2319 case 2: 2320 rssi = -12 + 2 * (5 - vga_idx); 2321 break; 2322 case 1: 2323 rssi = 8 - (2 * vga_idx); 2324 break; 2325 case 0: 2326 rssi = 14 - (2 * vga_idx); 2327 break; 2328 } 2329 rssi += 6; 2330 } else { /* OFDM/HT. */ 2331 phy = (struct r92c_rx_phystat *)physt; 2332 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2333 } 2334 return rssi; 2335 } 2336 2337 static void 2338 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2339 { 2340 struct ieee80211com *ic = &sc->sc_ic; 2341 struct ifnet *ifp = ic->ic_ifp; 2342 struct ieee80211_frame *wh; 2343 struct ieee80211_node *ni; 2344 struct r92c_rx_desc_usb *stat; 2345 uint32_t rxdw0, rxdw3; 2346 struct mbuf *m; 2347 uint8_t rate; 2348 int8_t rssi = 0; 2349 int s, infosz; 2350 2351 DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", 2352 device_xname(sc->sc_dev), __func__, buf, pktlen)); 2353 2354 stat = (struct r92c_rx_desc_usb *)buf; 2355 rxdw0 = le32toh(stat->rxdw0); 2356 rxdw3 = le32toh(stat->rxdw3); 2357 2358 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2359 /* 2360 * This should not happen since we setup our Rx filter 2361 * to not receive these frames. 2362 */ 2363 DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", 2364 device_xname(sc->sc_dev), __func__)); 2365 ifp->if_ierrors++; 2366 return; 2367 } 2368 /* 2369 * XXX: This will drop most control packets. Do we really 2370 * want this in IEEE80211_M_MONITOR mode? 2371 */ 2372 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2373 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2374 DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", 2375 device_xname(sc->sc_dev), __func__, pktlen)); 2376 ic->ic_stats.is_rx_tooshort++; 2377 ifp->if_ierrors++; 2378 return; 2379 } 2380 if (__predict_false(pktlen > MCLBYTES)) { 2381 DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", 2382 device_xname(sc->sc_dev), __func__, pktlen)); 2383 ifp->if_ierrors++; 2384 return; 2385 } 2386 2387 rate = MS(rxdw3, R92C_RXDW3_RATE); 2388 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2389 2390 /* Get RSSI from PHY status descriptor if present. */ 2391 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2392 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2393 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2394 else 2395 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2396 /* Update our average RSSI. */ 2397 urtwn_update_avgrssi(sc, rate, rssi); 2398 } 2399 2400 DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 2401 device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); 2402 2403 MGETHDR(m, M_DONTWAIT, MT_DATA); 2404 if (__predict_false(m == NULL)) { 2405 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2406 ic->ic_stats.is_rx_nobuf++; 2407 ifp->if_ierrors++; 2408 return; 2409 } 2410 if (pktlen > (int)MHLEN) { 2411 MCLGET(m, M_DONTWAIT); 2412 if (__predict_false(!(m->m_flags & M_EXT))) { 2413 aprint_error_dev(sc->sc_dev, 2414 "couldn't allocate rx mbuf cluster\n"); 2415 m_freem(m); 2416 ic->ic_stats.is_rx_nobuf++; 2417 ifp->if_ierrors++; 2418 return; 2419 } 2420 } 2421 2422 /* Finalize mbuf. */ 2423 m_set_rcvif(m, ifp); 2424 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2425 memcpy(mtod(m, uint8_t *), wh, pktlen); 2426 m->m_pkthdr.len = m->m_len = pktlen; 2427 2428 s = splnet(); 2429 if (__predict_false(sc->sc_drvbpf != NULL)) { 2430 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2431 2432 tap->wr_flags = 0; 2433 if (!(rxdw3 & R92C_RXDW3_HT)) { 2434 switch (rate) { 2435 /* CCK. */ 2436 case 0: tap->wr_rate = 2; break; 2437 case 1: tap->wr_rate = 4; break; 2438 case 2: tap->wr_rate = 11; break; 2439 case 3: tap->wr_rate = 22; break; 2440 /* OFDM. */ 2441 case 4: tap->wr_rate = 12; break; 2442 case 5: tap->wr_rate = 18; break; 2443 case 6: tap->wr_rate = 24; break; 2444 case 7: tap->wr_rate = 36; break; 2445 case 8: tap->wr_rate = 48; break; 2446 case 9: tap->wr_rate = 72; break; 2447 case 10: tap->wr_rate = 96; break; 2448 case 11: tap->wr_rate = 108; break; 2449 } 2450 } else if (rate >= 12) { /* MCS0~15. */ 2451 /* Bit 7 set means HT MCS instead of rate. */ 2452 tap->wr_rate = 0x80 | (rate - 12); 2453 } 2454 tap->wr_dbm_antsignal = rssi; 2455 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2456 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2457 2458 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2459 } 2460 2461 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2462 2463 /* push the frame up to the 802.11 stack */ 2464 ieee80211_input(ic, m, ni, rssi, 0); 2465 2466 /* Node is no longer needed. */ 2467 ieee80211_free_node(ni); 2468 2469 splx(s); 2470 } 2471 2472 static void 2473 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2474 { 2475 struct urtwn_rx_data *data = priv; 2476 struct urtwn_softc *sc = data->sc; 2477 struct r92c_rx_desc_usb *stat; 2478 size_t pidx = data->pidx; 2479 uint32_t rxdw0; 2480 uint8_t *buf; 2481 int len, totlen, pktlen, infosz, npkts; 2482 2483 DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", 2484 device_xname(sc->sc_dev), __func__, status)); 2485 2486 mutex_enter(&sc->sc_rx_mtx); 2487 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2488 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2489 /* Put this Rx buffer back to our free list. */ 2490 mutex_exit(&sc->sc_rx_mtx); 2491 2492 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2493 if (status == USBD_STALLED) 2494 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2495 else if (status != USBD_CANCELLED) 2496 goto resubmit; 2497 return; 2498 } 2499 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2500 2501 if (__predict_false(len < (int)sizeof(*stat))) { 2502 DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", 2503 device_xname(sc->sc_dev), __func__, len)); 2504 goto resubmit; 2505 } 2506 buf = data->buf; 2507 2508 /* Get the number of encapsulated frames. */ 2509 stat = (struct r92c_rx_desc_usb *)buf; 2510 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2511 DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", 2512 device_xname(sc->sc_dev), __func__, npkts)); 2513 2514 if (npkts != 0) 2515 rnd_add_uint32(&sc->rnd_source, npkts); 2516 2517 /* Process all of them. */ 2518 while (npkts-- > 0) { 2519 if (__predict_false(len < (int)sizeof(*stat))) { 2520 DPRINTFN(DBG_RX, 2521 ("%s: %s: len(%d) is short than header\n", 2522 device_xname(sc->sc_dev), __func__, len)); 2523 break; 2524 } 2525 stat = (struct r92c_rx_desc_usb *)buf; 2526 rxdw0 = le32toh(stat->rxdw0); 2527 2528 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2529 if (__predict_false(pktlen == 0)) { 2530 DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", 2531 device_xname(sc->sc_dev), __func__)); 2532 break; 2533 } 2534 2535 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2536 2537 /* Make sure everything fits in xfer. */ 2538 totlen = sizeof(*stat) + infosz + pktlen; 2539 if (__predict_false(totlen > len)) { 2540 DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", 2541 device_xname(sc->sc_dev), __func__, totlen, 2542 (int)sizeof(*stat), infosz, pktlen, len)); 2543 break; 2544 } 2545 2546 /* Process 802.11 frame. */ 2547 urtwn_rx_frame(sc, buf, pktlen); 2548 2549 /* Next chunk is 128-byte aligned. */ 2550 totlen = roundup2(totlen, 128); 2551 buf += totlen; 2552 len -= totlen; 2553 } 2554 2555 resubmit: 2556 /* Setup a new transfer. */ 2557 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2558 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2559 (void)usbd_transfer(xfer); 2560 } 2561 2562 static void 2563 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2564 { 2565 struct urtwn_tx_data *data = priv; 2566 struct urtwn_softc *sc = data->sc; 2567 struct ifnet *ifp = &sc->sc_if; 2568 size_t pidx = data->pidx; 2569 int s; 2570 2571 DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", 2572 device_xname(sc->sc_dev), __func__, status)); 2573 2574 mutex_enter(&sc->sc_tx_mtx); 2575 /* Put this Tx buffer back to our free list. */ 2576 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2577 mutex_exit(&sc->sc_tx_mtx); 2578 2579 s = splnet(); 2580 sc->tx_timer = 0; 2581 ifp->if_flags &= ~IFF_OACTIVE; 2582 2583 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2584 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2585 if (status == USBD_STALLED) { 2586 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2587 usbd_clear_endpoint_stall_async(pipe); 2588 } 2589 printf("ERROR1\n"); 2590 ifp->if_oerrors++; 2591 } 2592 splx(s); 2593 return; 2594 } 2595 2596 ifp->if_opackets++; 2597 urtwn_start(ifp); 2598 splx(s); 2599 2600 } 2601 2602 static int 2603 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2604 struct urtwn_tx_data *data) 2605 { 2606 struct ieee80211com *ic = &sc->sc_ic; 2607 struct ieee80211_frame *wh; 2608 struct ieee80211_key *k = NULL; 2609 struct r92c_tx_desc_usb *txd; 2610 size_t i, padsize, xferlen, txd_len; 2611 uint16_t seq, sum; 2612 uint8_t raid, type, tid; 2613 int s, hasqos, error; 2614 2615 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2616 2617 wh = mtod(m, struct ieee80211_frame *); 2618 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2619 txd_len = sizeof(*txd); 2620 2621 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2622 txd_len = 32; 2623 2624 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2625 k = ieee80211_crypto_encap(ic, ni, m); 2626 if (k == NULL) 2627 return ENOBUFS; 2628 2629 /* packet header may have moved, reset our local pointer */ 2630 wh = mtod(m, struct ieee80211_frame *); 2631 } 2632 2633 if (__predict_false(sc->sc_drvbpf != NULL)) { 2634 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2635 2636 tap->wt_flags = 0; 2637 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2638 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2639 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2640 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2641 2642 /* XXX: set tap->wt_rate? */ 2643 2644 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2645 } 2646 2647 /* non-qos data frames */ 2648 tid = R92C_TXDW1_QSEL_BE; 2649 if ((hasqos = ieee80211_has_qos(wh))) { 2650 /* data frames in 11n mode */ 2651 struct ieee80211_qosframe *qwh = (void *)wh; 2652 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2653 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2654 tid = R92C_TXDW1_QSEL_MGNT; 2655 } 2656 2657 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2658 padsize = 8; 2659 else 2660 padsize = 0; 2661 2662 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2663 padsize = 0; 2664 2665 /* Fill Tx descriptor. */ 2666 txd = (struct r92c_tx_desc_usb *)data->buf; 2667 memset(txd, 0, txd_len + padsize); 2668 2669 txd->txdw0 |= htole32( 2670 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2671 SM(R92C_TXDW0_OFFSET, txd_len)); 2672 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2673 txd->txdw0 |= htole32( 2674 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2675 } 2676 2677 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2678 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2679 2680 /* fix pad field */ 2681 if (padsize > 0) { 2682 DPRINTFN(DBG_TX, ("%s: %s: padding: size=%zd\n", 2683 device_xname(sc->sc_dev), __func__, padsize)); 2684 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2685 } 2686 2687 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2688 type == IEEE80211_FC0_TYPE_DATA) { 2689 if (ic->ic_curmode == IEEE80211_MODE_11B) 2690 raid = R92C_RAID_11B; 2691 else 2692 raid = R92C_RAID_11BG; 2693 DPRINTFN(DBG_TX, 2694 ("%s: %s: data packet: tid=%d, raid=%d\n", 2695 device_xname(sc->sc_dev), __func__, tid, raid)); 2696 2697 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2698 txd->txdw1 |= htole32( 2699 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2700 SM(R92C_TXDW1_QSEL, tid) | 2701 SM(R92C_TXDW1_RAID, raid) | 2702 R92C_TXDW1_AGGBK); 2703 } else 2704 txd->txdw1 |= htole32( 2705 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2706 SM(R92C_TXDW1_QSEL, tid) | 2707 SM(R92C_TXDW1_RAID, raid) | 2708 R92C_TXDW1_AGGBK); 2709 2710 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2711 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2712 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2713 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2714 2715 if (hasqos) { 2716 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2717 } 2718 2719 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2720 /* for 11g */ 2721 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2722 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2723 R92C_TXDW4_HWRTSEN); 2724 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2725 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2726 R92C_TXDW4_HWRTSEN); 2727 } 2728 } 2729 /* Send RTS at OFDM24. */ 2730 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2731 txd->txdw5 |= htole32(0x0001ff00); 2732 /* Send data at OFDM54. */ 2733 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2734 txd->txdw5 |= htole32(0x13 & 0x3f); 2735 else 2736 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2737 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2738 DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", 2739 device_xname(sc->sc_dev), __func__)); 2740 txd->txdw1 |= htole32( 2741 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2742 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2743 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2744 2745 /* Force CCK1. */ 2746 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2747 /* Use 1Mbps */ 2748 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2749 } else { 2750 /* broadcast or multicast packets */ 2751 DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", 2752 device_xname(sc->sc_dev), __func__)); 2753 txd->txdw1 |= htole32( 2754 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2755 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2756 2757 /* Force CCK1. */ 2758 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2759 /* Use 1Mbps */ 2760 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2761 } 2762 /* Set sequence number */ 2763 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2764 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2765 txd->txdseq |= htole16(seq); 2766 2767 if (!hasqos) { 2768 /* Use HW sequence numbering for non-QoS frames. */ 2769 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2770 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2771 } 2772 } else { 2773 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2774 R92E_HWSEQ_SHIFT); 2775 if (!hasqos) { 2776 /* Use HW sequence numbering for non-QoS frames. */ 2777 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2778 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2779 } 2780 } 2781 2782 /* Compute Tx descriptor checksum. */ 2783 sum = 0; 2784 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2785 sum ^= ((uint16_t *)txd)[i]; 2786 txd->txdsum = sum; /* NB: already little endian. */ 2787 2788 xferlen = txd_len + m->m_pkthdr.len + padsize; 2789 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2790 2791 s = splnet(); 2792 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2793 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2794 urtwn_txeof); 2795 error = usbd_transfer(data->xfer); 2796 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2797 error != USBD_IN_PROGRESS)) { 2798 splx(s); 2799 DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", 2800 device_xname(sc->sc_dev), __func__, error)); 2801 return error; 2802 } 2803 splx(s); 2804 return 0; 2805 } 2806 2807 struct urtwn_tx_data * 2808 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2809 { 2810 struct urtwn_tx_data *data = NULL; 2811 2812 mutex_enter(&sc->sc_tx_mtx); 2813 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2814 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2815 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2816 } 2817 mutex_exit(&sc->sc_tx_mtx); 2818 2819 return data; 2820 } 2821 2822 static void 2823 urtwn_start(struct ifnet *ifp) 2824 { 2825 struct urtwn_softc *sc = ifp->if_softc; 2826 struct ieee80211com *ic = &sc->sc_ic; 2827 struct urtwn_tx_data *data; 2828 struct ether_header *eh; 2829 struct ieee80211_node *ni; 2830 struct mbuf *m; 2831 2832 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2833 2834 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2835 return; 2836 2837 data = NULL; 2838 for (;;) { 2839 /* Send pending management frames first. */ 2840 IF_POLL(&ic->ic_mgtq, m); 2841 if (m != NULL) { 2842 /* Use AC_VO for management frames. */ 2843 2844 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2845 2846 if (data == NULL) { 2847 ifp->if_flags |= IFF_OACTIVE; 2848 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2849 device_xname(sc->sc_dev))); 2850 return; 2851 } 2852 IF_DEQUEUE(&ic->ic_mgtq, m); 2853 ni = M_GETCTX(m, struct ieee80211_node *); 2854 M_CLEARCTX(m); 2855 goto sendit; 2856 } 2857 if (ic->ic_state != IEEE80211_S_RUN) 2858 break; 2859 2860 /* Encapsulate and send data frames. */ 2861 IFQ_POLL(&ifp->if_snd, m); 2862 if (m == NULL) 2863 break; 2864 2865 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2866 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2867 uint8_t qid = WME_AC_BE; 2868 if (ieee80211_has_qos(wh)) { 2869 /* data frames in 11n mode */ 2870 struct ieee80211_qosframe *qwh = (void *)wh; 2871 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2872 qid = TID_TO_WME_AC(tid); 2873 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2874 qid = WME_AC_VO; 2875 } 2876 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2877 2878 if (data == NULL) { 2879 ifp->if_flags |= IFF_OACTIVE; 2880 DPRINTFN(DBG_TX, ("%s: empty tx_free_list\n", 2881 device_xname(sc->sc_dev))); 2882 return; 2883 } 2884 IFQ_DEQUEUE(&ifp->if_snd, m); 2885 2886 if (m->m_len < (int)sizeof(*eh) && 2887 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2888 printf("ERROR6\n"); 2889 ifp->if_oerrors++; 2890 continue; 2891 } 2892 eh = mtod(m, struct ether_header *); 2893 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2894 if (ni == NULL) { 2895 m_freem(m); 2896 printf("ERROR5\n"); 2897 ifp->if_oerrors++; 2898 continue; 2899 } 2900 2901 bpf_mtap(ifp, m, BPF_D_OUT); 2902 2903 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2904 ieee80211_free_node(ni); 2905 printf("ERROR4\n"); 2906 ifp->if_oerrors++; 2907 continue; 2908 } 2909 sendit: 2910 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2911 2912 if (urtwn_tx(sc, m, ni, data) != 0) { 2913 m_freem(m); 2914 ieee80211_free_node(ni); 2915 printf("ERROR3\n"); 2916 ifp->if_oerrors++; 2917 continue; 2918 } 2919 m_freem(m); 2920 ieee80211_free_node(ni); 2921 sc->tx_timer = 5; 2922 ifp->if_timer = 1; 2923 } 2924 } 2925 2926 static void 2927 urtwn_watchdog(struct ifnet *ifp) 2928 { 2929 struct urtwn_softc *sc = ifp->if_softc; 2930 2931 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2932 2933 ifp->if_timer = 0; 2934 2935 if (sc->tx_timer > 0) { 2936 if (--sc->tx_timer == 0) { 2937 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2938 /* urtwn_init(ifp); XXX needs a process context! */ 2939 printf("ERROR2\n"); 2940 ifp->if_oerrors++; 2941 return; 2942 } 2943 ifp->if_timer = 1; 2944 } 2945 ieee80211_watchdog(&sc->sc_ic); 2946 } 2947 2948 static int 2949 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2950 { 2951 struct urtwn_softc *sc = ifp->if_softc; 2952 struct ieee80211com *ic = &sc->sc_ic; 2953 int s, error = 0; 2954 2955 DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", 2956 device_xname(sc->sc_dev), __func__, cmd, data)); 2957 2958 s = splnet(); 2959 2960 switch (cmd) { 2961 case SIOCSIFFLAGS: 2962 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2963 break; 2964 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2965 case IFF_UP | IFF_RUNNING: 2966 break; 2967 case IFF_UP: 2968 urtwn_init(ifp); 2969 break; 2970 case IFF_RUNNING: 2971 urtwn_stop(ifp, 1); 2972 break; 2973 case 0: 2974 break; 2975 } 2976 break; 2977 2978 case SIOCADDMULTI: 2979 case SIOCDELMULTI: 2980 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2981 /* setup multicast filter, etc */ 2982 error = 0; 2983 } 2984 break; 2985 2986 case SIOCS80211CHANNEL: 2987 /* 2988 * This allows for fast channel switching in monitor mode 2989 * (used by kismet). In IBSS mode, we must explicitly reset 2990 * the interface to generate a new beacon frame. 2991 */ 2992 error = ieee80211_ioctl(ic, cmd, data); 2993 if (error == ENETRESET && 2994 ic->ic_opmode == IEEE80211_M_MONITOR) { 2995 urtwn_set_chan(sc, ic->ic_curchan, 2996 IEEE80211_HTINFO_2NDCHAN_NONE); 2997 error = 0; 2998 } 2999 break; 3000 3001 default: 3002 error = ieee80211_ioctl(ic, cmd, data); 3003 break; 3004 } 3005 if (error == ENETRESET) { 3006 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3007 (IFF_UP | IFF_RUNNING) && 3008 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3009 urtwn_init(ifp); 3010 } 3011 error = 0; 3012 } 3013 3014 splx(s); 3015 3016 return error; 3017 } 3018 3019 static __inline int 3020 urtwn_power_on(struct urtwn_softc *sc) 3021 { 3022 3023 return sc->sc_power_on(sc); 3024 } 3025 3026 static int 3027 urtwn_r92c_power_on(struct urtwn_softc *sc) 3028 { 3029 uint32_t reg; 3030 int ntries; 3031 3032 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3033 3034 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3035 3036 /* Wait for autoload done bit. */ 3037 for (ntries = 0; ntries < 1000; ntries++) { 3038 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3039 break; 3040 DELAY(5); 3041 } 3042 if (ntries == 1000) { 3043 aprint_error_dev(sc->sc_dev, 3044 "timeout waiting for chip autoload\n"); 3045 return ETIMEDOUT; 3046 } 3047 3048 /* Unlock ISO/CLK/Power control register. */ 3049 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3050 /* Move SPS into PWM mode. */ 3051 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3052 DELAY(5); 3053 3054 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3055 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3056 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3057 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3058 DELAY(100); 3059 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3060 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3061 ~R92C_SYS_ISO_CTRL_MD2PP); 3062 } 3063 3064 /* Auto enable WLAN. */ 3065 urtwn_write_2(sc, R92C_APS_FSMCO, 3066 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3067 for (ntries = 0; ntries < 1000; ntries++) { 3068 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3069 R92C_APS_FSMCO_APFM_ONMAC)) 3070 break; 3071 DELAY(100); 3072 } 3073 if (ntries == 1000) { 3074 aprint_error_dev(sc->sc_dev, 3075 "timeout waiting for MAC auto ON\n"); 3076 return ETIMEDOUT; 3077 } 3078 3079 /* Enable radio, GPIO and LED functions. */ 3080 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3081 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3082 urtwn_write_2(sc, R92C_APS_FSMCO, 3083 R92C_APS_FSMCO_AFSM_HSUS | 3084 R92C_APS_FSMCO_PDN_EN | 3085 R92C_APS_FSMCO_PFM_ALDN); 3086 3087 /* Release RF digital isolation. */ 3088 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3089 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3090 3091 /* Initialize MAC. */ 3092 urtwn_write_1(sc, R92C_APSD_CTRL, 3093 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3094 for (ntries = 0; ntries < 200; ntries++) { 3095 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3096 R92C_APSD_CTRL_OFF_STATUS)) 3097 break; 3098 DELAY(5); 3099 } 3100 if (ntries == 200) { 3101 aprint_error_dev(sc->sc_dev, 3102 "timeout waiting for MAC initialization\n"); 3103 return ETIMEDOUT; 3104 } 3105 3106 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3107 reg = urtwn_read_2(sc, R92C_CR); 3108 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3109 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3110 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3111 R92C_CR_ENSEC; 3112 urtwn_write_2(sc, R92C_CR, reg); 3113 3114 urtwn_write_1(sc, 0xfe10, 0x19); 3115 return 0; 3116 } 3117 3118 static int 3119 urtwn_r92e_power_on(struct urtwn_softc *sc) 3120 { 3121 uint32_t reg; 3122 uint32_t val; 3123 int ntries; 3124 3125 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3126 3127 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3128 3129 /* Enable radio, GPIO and LED functions. */ 3130 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3131 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3132 urtwn_write_2(sc, R92C_APS_FSMCO, 3133 R92C_APS_FSMCO_AFSM_HSUS | 3134 R92C_APS_FSMCO_PDN_EN | 3135 R92C_APS_FSMCO_PFM_ALDN); 3136 3137 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3138 /* LDO. */ 3139 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3140 } 3141 else { 3142 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3143 R92C_SYS_SWR_CTRL2) & 0xffff); 3144 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3145 } 3146 3147 for (ntries = 0; ntries < 2; ntries++) { 3148 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3149 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3150 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3151 R92C_AFE_CTRL4)); 3152 } 3153 3154 /* Reset BB. */ 3155 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3156 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3157 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3158 3159 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3160 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3161 3162 /* Disable HWPDN. */ 3163 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3164 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3165 3166 /* Disable WL suspend. */ 3167 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3168 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3169 R92C_APS_FSMCO_AFSM_HSUS)); 3170 3171 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3172 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3173 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3174 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3175 for (ntries = 0; ntries < 10000; ntries++) { 3176 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3177 R92C_APS_FSMCO_APFM_ONMAC; 3178 if (val == 0x0) 3179 break; 3180 DELAY(10); 3181 } 3182 if (ntries == 10000) { 3183 aprint_error_dev(sc->sc_dev, 3184 "timeout waiting for chip power up\n"); 3185 return ETIMEDOUT; 3186 } 3187 3188 urtwn_write_2(sc, R92C_CR, 0x00); 3189 reg = urtwn_read_2(sc, R92C_CR); 3190 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3191 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3192 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3193 urtwn_write_2(sc, R92C_CR, reg); 3194 3195 return 0; 3196 } 3197 3198 static int 3199 urtwn_r88e_power_on(struct urtwn_softc *sc) 3200 { 3201 uint32_t reg; 3202 uint8_t val; 3203 int ntries; 3204 3205 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3206 3207 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3208 3209 /* Wait for power ready bit. */ 3210 for (ntries = 0; ntries < 5000; ntries++) { 3211 val = urtwn_read_1(sc, 0x6) & 0x2; 3212 if (val == 0x2) 3213 break; 3214 DELAY(10); 3215 } 3216 if (ntries == 5000) { 3217 aprint_error_dev(sc->sc_dev, 3218 "timeout waiting for chip power up\n"); 3219 return ETIMEDOUT; 3220 } 3221 3222 /* Reset BB. */ 3223 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3224 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3225 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3226 3227 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3228 3229 /* Disable HWPDN. */ 3230 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3231 3232 /* Disable WL suspend. */ 3233 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3234 3235 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3236 for (ntries = 0; ntries < 5000; ntries++) { 3237 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3238 break; 3239 DELAY(10); 3240 } 3241 if (ntries == 5000) 3242 return ETIMEDOUT; 3243 3244 /* Enable LDO normal mode. */ 3245 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3246 3247 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3248 urtwn_write_2(sc, R92C_CR, 0); 3249 reg = urtwn_read_2(sc, R92C_CR); 3250 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3251 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3252 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3253 urtwn_write_2(sc, R92C_CR, reg); 3254 3255 return 0; 3256 } 3257 3258 static int 3259 urtwn_llt_init(struct urtwn_softc *sc) 3260 { 3261 size_t i, page_count, pktbuf_count; 3262 uint32_t val; 3263 int error; 3264 3265 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3266 3267 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3268 3269 if (sc->chip & URTWN_CHIP_88E) 3270 page_count = R88E_TX_PAGE_COUNT; 3271 else if (sc->chip & URTWN_CHIP_92EU) 3272 page_count = R92E_TX_PAGE_COUNT; 3273 else 3274 page_count = R92C_TX_PAGE_COUNT; 3275 if (sc->chip & URTWN_CHIP_88E) 3276 pktbuf_count = R88E_TXPKTBUF_COUNT; 3277 else if (sc->chip & URTWN_CHIP_92EU) 3278 pktbuf_count = R88E_TXPKTBUF_COUNT; 3279 else 3280 pktbuf_count = R92C_TXPKTBUF_COUNT; 3281 3282 if (sc->chip & URTWN_CHIP_92EU) { 3283 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3284 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3285 DELAY(100); 3286 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3287 if (val & R92E_AUTO_LLT_EN) 3288 return EIO; 3289 return 0; 3290 } 3291 3292 /* Reserve pages [0; page_count]. */ 3293 for (i = 0; i < page_count; i++) { 3294 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3295 return error; 3296 } 3297 /* NB: 0xff indicates end-of-list. */ 3298 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3299 return error; 3300 /* 3301 * Use pages [page_count + 1; pktbuf_count - 1] 3302 * as ring buffer. 3303 */ 3304 for (++i; i < pktbuf_count - 1; i++) { 3305 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3306 return error; 3307 } 3308 /* Make the last page point to the beginning of the ring buffer. */ 3309 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3310 return error; 3311 } 3312 3313 static void 3314 urtwn_fw_reset(struct urtwn_softc *sc) 3315 { 3316 uint16_t reg; 3317 int ntries; 3318 3319 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3320 3321 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3322 3323 /* Tell 8051 to reset itself. */ 3324 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3325 3326 /* Wait until 8051 resets by itself. */ 3327 for (ntries = 0; ntries < 100; ntries++) { 3328 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3329 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3330 return; 3331 DELAY(50); 3332 } 3333 /* Force 8051 reset. */ 3334 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3335 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3336 } 3337 3338 static void 3339 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3340 { 3341 uint16_t reg; 3342 3343 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3344 3345 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3346 3347 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3348 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3349 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3350 } 3351 DELAY(50); 3352 3353 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3354 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3355 DELAY(50); 3356 3357 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3358 DELAY(50); 3359 3360 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3361 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3362 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3363 } 3364 DELAY(50); 3365 3366 } 3367 3368 static int 3369 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3370 { 3371 uint32_t reg; 3372 int off, mlen, error = 0; 3373 3374 DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", 3375 device_xname(sc->sc_dev), __func__, page, buf, len)); 3376 3377 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3378 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3379 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3380 3381 off = R92C_FW_START_ADDR; 3382 while (len > 0) { 3383 if (len > 196) 3384 mlen = 196; 3385 else if (len > 4) 3386 mlen = 4; 3387 else 3388 mlen = 1; 3389 error = urtwn_write_region(sc, off, buf, mlen); 3390 if (error != 0) 3391 break; 3392 off += mlen; 3393 buf += mlen; 3394 len -= mlen; 3395 } 3396 return error; 3397 } 3398 3399 static int 3400 urtwn_load_firmware(struct urtwn_softc *sc) 3401 { 3402 firmware_handle_t fwh; 3403 const struct r92c_fw_hdr *hdr; 3404 const char *name; 3405 u_char *fw, *ptr; 3406 size_t len; 3407 uint32_t reg; 3408 int mlen, ntries, page, error; 3409 3410 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3411 3412 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3413 3414 /* Read firmware image from the filesystem. */ 3415 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3416 name = "rtl8188eufw.bin"; 3417 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3418 name = "rtl8192eefw.bin"; 3419 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3420 URTWN_CHIP_UMC_A_CUT) 3421 name = "rtl8192cfwU.bin"; 3422 else 3423 name = "rtl8192cfw.bin"; 3424 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3425 aprint_error_dev(sc->sc_dev, 3426 "failed load firmware of file %s (error %d)\n", name, 3427 error); 3428 return error; 3429 } 3430 const size_t fwlen = len = firmware_get_size(fwh); 3431 fw = firmware_malloc(len); 3432 if (fw == NULL) { 3433 aprint_error_dev(sc->sc_dev, 3434 "failed to allocate firmware memory\n"); 3435 firmware_close(fwh); 3436 return ENOMEM; 3437 } 3438 error = firmware_read(fwh, 0, fw, len); 3439 firmware_close(fwh); 3440 if (error != 0) { 3441 aprint_error_dev(sc->sc_dev, 3442 "failed to read firmware (error %d)\n", error); 3443 firmware_free(fw, fwlen); 3444 return error; 3445 } 3446 3447 len = fwlen; 3448 ptr = fw; 3449 hdr = (const struct r92c_fw_hdr *)ptr; 3450 /* Check if there is a valid FW header and skip it. */ 3451 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3452 (le16toh(hdr->signature) >> 4) == 0x88e || 3453 (le16toh(hdr->signature) >> 4) == 0x92e || 3454 (le16toh(hdr->signature) >> 4) == 0x92c) { 3455 DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", 3456 device_xname(sc->sc_dev), __func__, 3457 le16toh(hdr->version), le16toh(hdr->subversion), 3458 hdr->month, hdr->date, hdr->hour, hdr->minute)); 3459 ptr += sizeof(*hdr); 3460 len -= sizeof(*hdr); 3461 } 3462 3463 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3464 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3465 ISSET(sc->chip, URTWN_CHIP_92EU)) 3466 urtwn_r88e_fw_reset(sc); 3467 else 3468 urtwn_fw_reset(sc); 3469 } 3470 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3471 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3472 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3473 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3474 R92C_SYS_FUNC_EN_CPUEN); 3475 } 3476 3477 /* download enabled */ 3478 urtwn_write_1(sc, R92C_MCUFWDL, 3479 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3480 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3481 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3482 3483 /* Reset the FWDL checksum. */ 3484 urtwn_write_1(sc, R92C_MCUFWDL, 3485 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3486 3487 DELAY(50); 3488 /* download firmware */ 3489 for (page = 0; len > 0; page++) { 3490 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3491 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3492 if (error != 0) { 3493 aprint_error_dev(sc->sc_dev, 3494 "could not load firmware page %d\n", page); 3495 goto fail; 3496 } 3497 ptr += mlen; 3498 len -= mlen; 3499 } 3500 3501 /* download disable */ 3502 urtwn_write_1(sc, R92C_MCUFWDL, 3503 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3504 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3505 3506 /* Wait for checksum report. */ 3507 for (ntries = 0; ntries < 1000; ntries++) { 3508 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3509 break; 3510 DELAY(5); 3511 } 3512 if (ntries == 1000) { 3513 aprint_error_dev(sc->sc_dev, 3514 "timeout waiting for checksum report\n"); 3515 error = ETIMEDOUT; 3516 goto fail; 3517 } 3518 3519 /* Wait for firmware readiness. */ 3520 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3521 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3522 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3523 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3524 ISSET(sc->chip, URTWN_CHIP_92EU)) 3525 urtwn_r88e_fw_reset(sc); 3526 for (ntries = 0; ntries < 6000; ntries++) { 3527 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3528 break; 3529 DELAY(5); 3530 } 3531 if (ntries == 6000) { 3532 aprint_error_dev(sc->sc_dev, 3533 "timeout waiting for firmware readiness\n"); 3534 error = ETIMEDOUT; 3535 goto fail; 3536 } 3537 fail: 3538 firmware_free(fw, fwlen); 3539 return error; 3540 } 3541 3542 static __inline int 3543 urtwn_dma_init(struct urtwn_softc *sc) 3544 { 3545 3546 return sc->sc_dma_init(sc); 3547 } 3548 3549 static int 3550 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3551 { 3552 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3553 uint32_t reg; 3554 int error; 3555 3556 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3557 3558 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3559 3560 /* Initialize LLT table. */ 3561 error = urtwn_llt_init(sc); 3562 if (error != 0) 3563 return error; 3564 3565 /* Get Tx queues to USB endpoints mapping. */ 3566 hashq = hasnq = haslq = 0; 3567 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3568 DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", 3569 device_xname(sc->sc_dev), __func__, reg)); 3570 if (MS(reg, R92C_USB_EP_HQ) != 0) 3571 hashq = 1; 3572 if (MS(reg, R92C_USB_EP_NQ) != 0) 3573 hasnq = 1; 3574 if (MS(reg, R92C_USB_EP_LQ) != 0) 3575 haslq = 1; 3576 nqueues = hashq + hasnq + haslq; 3577 if (nqueues == 0) 3578 return EIO; 3579 /* Get the number of pages for each queue. */ 3580 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3581 /* The remaining pages are assigned to the high priority queue. */ 3582 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3583 3584 /* Set number of pages for normal priority queue. */ 3585 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3586 urtwn_write_4(sc, R92C_RQPN, 3587 /* Set number of pages for public queue. */ 3588 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3589 /* Set number of pages for high priority queue. */ 3590 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3591 /* Set number of pages for low priority queue. */ 3592 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3593 /* Load values. */ 3594 R92C_RQPN_LD); 3595 3596 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3597 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3598 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3599 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3600 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3601 3602 /* Set queue to USB pipe mapping. */ 3603 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3604 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3605 if (nqueues == 1) { 3606 if (hashq) { 3607 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3608 } else if (hasnq) { 3609 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3610 } else { 3611 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3612 } 3613 } else if (nqueues == 2) { 3614 /* All 2-endpoints configs have a high priority queue. */ 3615 if (!hashq) { 3616 return EIO; 3617 } 3618 if (hasnq) { 3619 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3620 } else { 3621 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3622 } 3623 } else { 3624 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3625 } 3626 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3627 3628 /* Set Tx/Rx transfer page boundary. */ 3629 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3630 3631 /* Set Tx/Rx transfer page size. */ 3632 urtwn_write_1(sc, R92C_PBP, 3633 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3634 return 0; 3635 } 3636 3637 static int 3638 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3639 { 3640 usb_interface_descriptor_t *id; 3641 uint32_t reg; 3642 int nqueues; 3643 int error; 3644 3645 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3646 3647 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3648 3649 /* Initialize LLT table. */ 3650 error = urtwn_llt_init(sc); 3651 if (error != 0) 3652 return error; 3653 3654 /* Get Tx queues to USB endpoints mapping. */ 3655 id = usbd_get_interface_descriptor(sc->sc_iface); 3656 nqueues = id->bNumEndpoints - 1; 3657 if (nqueues == 0) 3658 return EIO; 3659 3660 /* Set number of pages for normal priority queue. */ 3661 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3662 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3663 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3664 3665 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3666 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3667 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3668 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3669 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3670 3671 /* Set queue to USB pipe mapping. */ 3672 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3673 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3674 if (nqueues == 1) 3675 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3676 else if (nqueues == 2) 3677 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3678 else 3679 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3680 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3681 3682 /* Set Tx/Rx transfer page boundary. */ 3683 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3684 3685 /* Set Tx/Rx transfer page size. */ 3686 urtwn_write_1(sc, R92C_PBP, 3687 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3688 3689 return 0; 3690 } 3691 3692 static void 3693 urtwn_mac_init(struct urtwn_softc *sc) 3694 { 3695 size_t i; 3696 3697 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3698 3699 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3700 3701 /* Write MAC initialization values. */ 3702 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3703 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3704 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3705 rtl8188eu_mac[i].val); 3706 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3707 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3708 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3709 rtl8192eu_mac[i].val); 3710 } else { 3711 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3712 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3713 rtl8192cu_mac[i].val); 3714 } 3715 } 3716 3717 static void 3718 urtwn_bb_init(struct urtwn_softc *sc) 3719 { 3720 const struct rtwn_bb_prog *prog; 3721 uint32_t reg; 3722 uint8_t crystalcap; 3723 size_t i; 3724 3725 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3726 3727 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3728 3729 /* Enable BB and RF. */ 3730 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3731 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3732 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3733 R92C_SYS_FUNC_EN_DIO_RF); 3734 3735 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3736 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3737 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3738 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3739 } 3740 3741 urtwn_write_1(sc, R92C_RF_CTRL, 3742 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3743 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3744 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3745 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3746 3747 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3748 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3749 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3750 urtwn_write_1(sc, 0x15, 0xe9); 3751 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3752 } 3753 3754 /* Select BB programming based on board type. */ 3755 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3756 prog = &rtl8188eu_bb_prog; 3757 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3758 prog = &rtl8192eu_bb_prog; 3759 else if (!(sc->chip & URTWN_CHIP_92C)) { 3760 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3761 prog = &rtl8188ce_bb_prog; 3762 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3763 prog = &rtl8188ru_bb_prog; 3764 } else { 3765 prog = &rtl8188cu_bb_prog; 3766 } 3767 } else { 3768 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3769 prog = &rtl8192ce_bb_prog; 3770 } else { 3771 prog = &rtl8192cu_bb_prog; 3772 } 3773 } 3774 /* Write BB initialization values. */ 3775 for (i = 0; i < prog->count; i++) { 3776 /* additional delay depend on registers */ 3777 switch (prog->regs[i]) { 3778 case 0xfe: 3779 urtwn_delay_ms(sc, 50); 3780 break; 3781 case 0xfd: 3782 urtwn_delay_ms(sc, 5); 3783 break; 3784 case 0xfc: 3785 urtwn_delay_ms(sc, 1); 3786 break; 3787 case 0xfb: 3788 DELAY(50); 3789 break; 3790 case 0xfa: 3791 DELAY(5); 3792 break; 3793 case 0xf9: 3794 DELAY(1); 3795 break; 3796 } 3797 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3798 DELAY(1); 3799 } 3800 3801 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3802 /* 8192C 1T only configuration. */ 3803 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3804 reg = (reg & ~0x00000003) | 0x2; 3805 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3806 3807 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3808 reg = (reg & ~0x00300033) | 0x00200022; 3809 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3810 3811 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3812 reg = (reg & ~0xff000000) | (0x45 << 24); 3813 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3814 3815 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3816 reg = (reg & ~0x000000ff) | 0x23; 3817 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3818 3819 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3820 reg = (reg & ~0x00000030) | (1 << 4); 3821 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3822 3823 reg = urtwn_bb_read(sc, 0xe74); 3824 reg = (reg & ~0x0c000000) | (2 << 26); 3825 urtwn_bb_write(sc, 0xe74, reg); 3826 reg = urtwn_bb_read(sc, 0xe78); 3827 reg = (reg & ~0x0c000000) | (2 << 26); 3828 urtwn_bb_write(sc, 0xe78, reg); 3829 reg = urtwn_bb_read(sc, 0xe7c); 3830 reg = (reg & ~0x0c000000) | (2 << 26); 3831 urtwn_bb_write(sc, 0xe7c, reg); 3832 reg = urtwn_bb_read(sc, 0xe80); 3833 reg = (reg & ~0x0c000000) | (2 << 26); 3834 urtwn_bb_write(sc, 0xe80, reg); 3835 reg = urtwn_bb_read(sc, 0xe88); 3836 reg = (reg & ~0x0c000000) | (2 << 26); 3837 urtwn_bb_write(sc, 0xe88, reg); 3838 } 3839 3840 /* Write AGC values. */ 3841 for (i = 0; i < prog->agccount; i++) { 3842 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3843 DELAY(1); 3844 } 3845 3846 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3847 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3848 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3849 DELAY(1); 3850 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3851 DELAY(1); 3852 } 3853 3854 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3855 crystalcap = sc->r88e_rom[0xb9]; 3856 if (crystalcap == 0x00) 3857 crystalcap = 0x20; 3858 crystalcap &= 0x3f; 3859 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3860 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3861 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3862 crystalcap | crystalcap << 6)); 3863 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3864 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3865 crystalcap = sc->r88e_rom[0xb9]; 3866 if (crystalcap == 0xff) 3867 crystalcap = 0x20; 3868 crystalcap &= 0x3f; 3869 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3870 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3871 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3872 crystalcap | crystalcap << 6)); 3873 } else { 3874 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3875 R92C_HSSI_PARAM2_CCK_HIPWR) { 3876 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3877 } 3878 } 3879 } 3880 3881 static void 3882 urtwn_rf_init(struct urtwn_softc *sc) 3883 { 3884 const struct rtwn_rf_prog *prog; 3885 uint32_t reg, mask, saved; 3886 size_t i, j, idx; 3887 3888 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3889 3890 /* Select RF programming based on board type. */ 3891 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3892 prog = rtl8188eu_rf_prog; 3893 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3894 prog = rtl8192eu_rf_prog; 3895 else if (!(sc->chip & URTWN_CHIP_92C)) { 3896 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3897 prog = rtl8188ce_rf_prog; 3898 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3899 prog = rtl8188ru_rf_prog; 3900 } else { 3901 prog = rtl8188cu_rf_prog; 3902 } 3903 } else { 3904 prog = rtl8192ce_rf_prog; 3905 } 3906 3907 for (i = 0; i < sc->nrxchains; i++) { 3908 /* Save RF_ENV control type. */ 3909 idx = i / 2; 3910 mask = 0xffffU << ((i % 2) * 16); 3911 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 3912 3913 /* Set RF_ENV enable. */ 3914 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3915 reg |= 0x100000; 3916 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3917 DELAY(50); 3918 3919 /* Set RF_ENV output high. */ 3920 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3921 reg |= 0x10; 3922 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3923 DELAY(50); 3924 3925 /* Set address and data lengths of RF registers. */ 3926 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3927 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3928 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3929 DELAY(50); 3930 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3931 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3932 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3933 DELAY(50); 3934 3935 /* Write RF initialization values for this chain. */ 3936 for (j = 0; j < prog[i].count; j++) { 3937 if (prog[i].regs[j] >= 0xf9 && 3938 prog[i].regs[j] <= 0xfe) { 3939 /* 3940 * These are fake RF registers offsets that 3941 * indicate a delay is required. 3942 */ 3943 urtwn_delay_ms(sc, 50); 3944 continue; 3945 } 3946 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 3947 DELAY(5); 3948 } 3949 3950 /* Restore RF_ENV control type. */ 3951 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 3952 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 3953 } 3954 3955 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3956 URTWN_CHIP_UMC_A_CUT) { 3957 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3958 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3959 } 3960 3961 /* Cache RF register CHNLBW. */ 3962 for (i = 0; i < 2; i++) { 3963 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3964 } 3965 } 3966 3967 static void 3968 urtwn_cam_init(struct urtwn_softc *sc) 3969 { 3970 uint32_t content, command; 3971 uint8_t idx; 3972 size_t i; 3973 3974 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3975 3976 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3977 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3978 return; 3979 3980 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3981 content = (idx & 3) 3982 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3983 | R92C_CAM_VALID; 3984 3985 command = R92C_CAMCMD_POLLING 3986 | R92C_CAMCMD_WRITE 3987 | R92C_CAM_CTL0(idx); 3988 3989 urtwn_write_4(sc, R92C_CAMWRITE, content); 3990 urtwn_write_4(sc, R92C_CAMCMD, command); 3991 } 3992 3993 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 3994 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 3995 if (i == 0) { 3996 content = (idx & 3) 3997 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 3998 | R92C_CAM_VALID; 3999 } else { 4000 content = 0; 4001 } 4002 4003 command = R92C_CAMCMD_POLLING 4004 | R92C_CAMCMD_WRITE 4005 | R92C_CAM_CTL0(idx) 4006 | i; 4007 4008 urtwn_write_4(sc, R92C_CAMWRITE, content); 4009 urtwn_write_4(sc, R92C_CAMCMD, command); 4010 } 4011 } 4012 4013 /* Invalidate all CAM entries. */ 4014 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4015 } 4016 4017 static void 4018 urtwn_pa_bias_init(struct urtwn_softc *sc) 4019 { 4020 uint8_t reg; 4021 size_t i; 4022 4023 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4024 4025 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4026 4027 for (i = 0; i < sc->nrxchains; i++) { 4028 if (sc->pa_setting & (1U << i)) 4029 continue; 4030 4031 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4032 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4033 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4034 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4035 } 4036 if (!(sc->pa_setting & 0x10)) { 4037 reg = urtwn_read_1(sc, 0x16); 4038 reg = (reg & ~0xf0) | 0x90; 4039 urtwn_write_1(sc, 0x16, reg); 4040 } 4041 } 4042 4043 static void 4044 urtwn_rxfilter_init(struct urtwn_softc *sc) 4045 { 4046 4047 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4048 4049 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4050 4051 /* Initialize Rx filter. */ 4052 /* TODO: use better filter for monitor mode. */ 4053 urtwn_write_4(sc, R92C_RCR, 4054 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4055 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4056 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4057 /* Accept all multicast frames. */ 4058 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4059 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4060 /* Accept all management frames. */ 4061 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4062 /* Reject all control frames. */ 4063 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4064 /* Accept all data frames. */ 4065 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4066 } 4067 4068 static void 4069 urtwn_edca_init(struct urtwn_softc *sc) 4070 { 4071 4072 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4073 4074 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4075 4076 /* set spec SIFS (used in NAV) */ 4077 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4078 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4079 4080 /* set SIFS CCK/OFDM */ 4081 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4082 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4083 4084 /* TXOP */ 4085 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4086 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4087 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4088 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4089 } 4090 4091 static void 4092 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4093 uint16_t power[URTWN_RIDX_COUNT]) 4094 { 4095 uint32_t reg; 4096 4097 DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), 4098 __func__, chain)); 4099 4100 /* Write per-CCK rate Tx power. */ 4101 if (chain == 0) { 4102 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4103 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4104 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4105 4106 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4107 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4108 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4109 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4110 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4111 } else { 4112 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4113 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4114 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4115 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4116 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4117 4118 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4119 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4120 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4121 } 4122 /* Write per-OFDM rate Tx power. */ 4123 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4124 SM(R92C_TXAGC_RATE06, power[ 4]) | 4125 SM(R92C_TXAGC_RATE09, power[ 5]) | 4126 SM(R92C_TXAGC_RATE12, power[ 6]) | 4127 SM(R92C_TXAGC_RATE18, power[ 7])); 4128 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4129 SM(R92C_TXAGC_RATE24, power[ 8]) | 4130 SM(R92C_TXAGC_RATE36, power[ 9]) | 4131 SM(R92C_TXAGC_RATE48, power[10]) | 4132 SM(R92C_TXAGC_RATE54, power[11])); 4133 /* Write per-MCS Tx power. */ 4134 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4135 SM(R92C_TXAGC_MCS00, power[12]) | 4136 SM(R92C_TXAGC_MCS01, power[13]) | 4137 SM(R92C_TXAGC_MCS02, power[14]) | 4138 SM(R92C_TXAGC_MCS03, power[15])); 4139 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4140 SM(R92C_TXAGC_MCS04, power[16]) | 4141 SM(R92C_TXAGC_MCS05, power[17]) | 4142 SM(R92C_TXAGC_MCS06, power[18]) | 4143 SM(R92C_TXAGC_MCS07, power[19])); 4144 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4145 SM(R92C_TXAGC_MCS08, power[20]) | 4146 SM(R92C_TXAGC_MCS09, power[21]) | 4147 SM(R92C_TXAGC_MCS10, power[22]) | 4148 SM(R92C_TXAGC_MCS11, power[23])); 4149 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4150 SM(R92C_TXAGC_MCS12, power[24]) | 4151 SM(R92C_TXAGC_MCS13, power[25]) | 4152 SM(R92C_TXAGC_MCS14, power[26]) | 4153 SM(R92C_TXAGC_MCS15, power[27])); 4154 } 4155 4156 static void 4157 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4158 uint16_t power[URTWN_RIDX_COUNT]) 4159 { 4160 struct r92c_rom *rom = &sc->rom; 4161 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4162 const struct rtwn_txpwr *base; 4163 int ridx, group; 4164 4165 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4166 device_xname(sc->sc_dev), __func__, chain, chan)); 4167 4168 /* Determine channel group. */ 4169 if (chan <= 3) { 4170 group = 0; 4171 } else if (chan <= 9) { 4172 group = 1; 4173 } else { 4174 group = 2; 4175 } 4176 4177 /* Get original Tx power based on board type and RF chain. */ 4178 if (!(sc->chip & URTWN_CHIP_92C)) { 4179 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4180 base = &rtl8188ru_txagc[chain]; 4181 } else { 4182 base = &rtl8192cu_txagc[chain]; 4183 } 4184 } else { 4185 base = &rtl8192cu_txagc[chain]; 4186 } 4187 4188 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4189 if (sc->regulatory == 0) { 4190 for (ridx = 0; ridx <= 3; ridx++) { 4191 power[ridx] = base->pwr[0][ridx]; 4192 } 4193 } 4194 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4195 if (sc->regulatory == 3) { 4196 power[ridx] = base->pwr[0][ridx]; 4197 /* Apply vendor limits. */ 4198 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4199 maxpow = rom->ht40_max_pwr[group]; 4200 } else { 4201 maxpow = rom->ht20_max_pwr[group]; 4202 } 4203 maxpow = (maxpow >> (chain * 4)) & 0xf; 4204 if (power[ridx] > maxpow) { 4205 power[ridx] = maxpow; 4206 } 4207 } else if (sc->regulatory == 1) { 4208 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4209 power[ridx] = base->pwr[group][ridx]; 4210 } 4211 } else if (sc->regulatory != 2) { 4212 power[ridx] = base->pwr[0][ridx]; 4213 } 4214 } 4215 4216 /* Compute per-CCK rate Tx power. */ 4217 cckpow = rom->cck_tx_pwr[chain][group]; 4218 for (ridx = 0; ridx <= 3; ridx++) { 4219 power[ridx] += cckpow; 4220 if (power[ridx] > R92C_MAX_TX_PWR) { 4221 power[ridx] = R92C_MAX_TX_PWR; 4222 } 4223 } 4224 4225 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4226 if (sc->ntxchains > 1) { 4227 /* Apply reduction for 2 spatial streams. */ 4228 diff = rom->ht40_2s_tx_pwr_diff[group]; 4229 diff = (diff >> (chain * 4)) & 0xf; 4230 htpow = (htpow > diff) ? htpow - diff : 0; 4231 } 4232 4233 /* Compute per-OFDM rate Tx power. */ 4234 diff = rom->ofdm_tx_pwr_diff[group]; 4235 diff = (diff >> (chain * 4)) & 0xf; 4236 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4237 for (ridx = 4; ridx <= 11; ridx++) { 4238 power[ridx] += ofdmpow; 4239 if (power[ridx] > R92C_MAX_TX_PWR) { 4240 power[ridx] = R92C_MAX_TX_PWR; 4241 } 4242 } 4243 4244 /* Compute per-MCS Tx power. */ 4245 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4246 diff = rom->ht20_tx_pwr_diff[group]; 4247 diff = (diff >> (chain * 4)) & 0xf; 4248 htpow += diff; /* HT40->HT20 correction. */ 4249 } 4250 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4251 power[ridx] += htpow; 4252 if (power[ridx] > R92C_MAX_TX_PWR) { 4253 power[ridx] = R92C_MAX_TX_PWR; 4254 } 4255 } 4256 #ifdef URTWN_DEBUG 4257 if (urtwn_debug & DBG_RF) { 4258 /* Dump per-rate Tx power values. */ 4259 printf("%s: %s: Tx power for chain %zd:\n", 4260 device_xname(sc->sc_dev), __func__, chain); 4261 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { 4262 printf("%s: %s: Rate %d = %u\n", 4263 device_xname(sc->sc_dev), __func__, ridx, 4264 power[ridx]); 4265 } 4266 } 4267 #endif 4268 } 4269 4270 void 4271 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4272 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4273 { 4274 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4275 const struct rtwn_r88e_txpwr *base; 4276 int ridx, group; 4277 4278 DPRINTFN(DBG_FN, ("%s: %s: chain=%zd, chan=%d\n", 4279 device_xname(sc->sc_dev), __func__, chain, chan)); 4280 4281 /* Determine channel group. */ 4282 if (chan <= 2) 4283 group = 0; 4284 else if (chan <= 5) 4285 group = 1; 4286 else if (chan <= 8) 4287 group = 2; 4288 else if (chan <= 11) 4289 group = 3; 4290 else if (chan <= 13) 4291 group = 4; 4292 else 4293 group = 5; 4294 4295 /* Get original Tx power based on board type and RF chain. */ 4296 base = &rtl8188eu_txagc[chain]; 4297 4298 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4299 if (sc->regulatory == 0) { 4300 for (ridx = 0; ridx <= 3; ridx++) 4301 power[ridx] = base->pwr[0][ridx]; 4302 } 4303 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4304 if (sc->regulatory == 3) 4305 power[ridx] = base->pwr[0][ridx]; 4306 else if (sc->regulatory == 1) { 4307 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4308 power[ridx] = base->pwr[group][ridx]; 4309 } else if (sc->regulatory != 2) 4310 power[ridx] = base->pwr[0][ridx]; 4311 } 4312 4313 /* Compute per-CCK rate Tx power. */ 4314 cckpow = sc->cck_tx_pwr[group]; 4315 for (ridx = 0; ridx <= 3; ridx++) { 4316 power[ridx] += cckpow; 4317 if (power[ridx] > R92C_MAX_TX_PWR) 4318 power[ridx] = R92C_MAX_TX_PWR; 4319 } 4320 4321 htpow = sc->ht40_tx_pwr[group]; 4322 4323 /* Compute per-OFDM rate Tx power. */ 4324 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4325 for (ridx = 4; ridx <= 11; ridx++) { 4326 power[ridx] += ofdmpow; 4327 if (power[ridx] > R92C_MAX_TX_PWR) 4328 power[ridx] = R92C_MAX_TX_PWR; 4329 } 4330 4331 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4332 for (ridx = 12; ridx <= 27; ridx++) { 4333 power[ridx] += bw20pow; 4334 if (power[ridx] > R92C_MAX_TX_PWR) 4335 power[ridx] = R92C_MAX_TX_PWR; 4336 } 4337 } 4338 4339 static void 4340 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4341 { 4342 uint16_t power[URTWN_RIDX_COUNT]; 4343 size_t i; 4344 4345 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4346 4347 for (i = 0; i < sc->ntxchains; i++) { 4348 /* Compute per-rate Tx power values. */ 4349 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4350 ISSET(sc->chip, URTWN_CHIP_92EU)) 4351 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4352 else 4353 urtwn_get_txpower(sc, i, chan, ht40m, power); 4354 /* Write per-rate Tx power values to hardware. */ 4355 urtwn_write_txpower(sc, i, power); 4356 } 4357 } 4358 4359 static void 4360 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4361 { 4362 struct ieee80211com *ic = &sc->sc_ic; 4363 u_int chan; 4364 size_t i; 4365 4366 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4367 4368 DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), 4369 __func__, chan)); 4370 4371 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4372 4373 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4374 chan += 2; 4375 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4376 chan -= 2; 4377 } 4378 4379 /* Set Tx power for this new channel. */ 4380 urtwn_set_txpower(sc, chan, ht40m); 4381 4382 for (i = 0; i < sc->nrxchains; i++) { 4383 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4384 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4385 } 4386 4387 if (ht40m) { 4388 /* Is secondary channel below or above primary? */ 4389 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4390 uint32_t reg; 4391 4392 urtwn_write_1(sc, R92C_BWOPMODE, 4393 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4394 4395 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4396 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4397 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4398 4399 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4400 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4401 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4402 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4403 4404 /* Set CCK side band. */ 4405 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4406 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4407 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4408 4409 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4410 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4411 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4412 4413 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4414 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4415 ~R92C_FPGA0_ANAPARAM2_CBW20); 4416 4417 reg = urtwn_bb_read(sc, 0x818); 4418 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4419 urtwn_bb_write(sc, 0x818, reg); 4420 4421 /* Select 40MHz bandwidth. */ 4422 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4423 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4424 } else { 4425 urtwn_write_1(sc, R92C_BWOPMODE, 4426 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4427 4428 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4429 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4430 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4431 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4432 4433 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4434 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4435 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4436 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4437 R92C_FPGA0_ANAPARAM2_CBW20); 4438 } 4439 4440 /* Select 20MHz bandwidth. */ 4441 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4442 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4443 (ISSET(sc->chip, URTWN_CHIP_88E) || 4444 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4445 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4446 } 4447 } 4448 4449 static void 4450 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4451 { 4452 4453 DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), 4454 __func__, inited)); 4455 4456 uint32_t addaBackup[16], iqkBackup[4], piMode; 4457 4458 #ifdef notyet 4459 uint32_t odfm0_agccore_regs[3]; 4460 uint32_t ant_regs[3]; 4461 uint32_t rf_regs[8]; 4462 #endif 4463 uint32_t reg0, reg1, reg2; 4464 int i, attempt; 4465 4466 #ifdef notyet 4467 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4468 R92E_STBC_SETTING + 2)); 4469 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4470 /* Save AGCCORE regs. */ 4471 for (i = 0; i < sc->nrxchains; i++) { 4472 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4473 R92C_OFDM0_AGCCORE1(i)); 4474 } 4475 #endif 4476 /* Save BB regs. */ 4477 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4478 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4479 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4480 4481 /* Save adda regs to be restored when finished. */ 4482 for (i = 0; i < __arraycount(addaReg); i++) 4483 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4484 /* Save mac regs. */ 4485 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4486 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4487 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4488 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4489 4490 #ifdef notyet 4491 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4492 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4493 4494 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4495 for (i = 0; i < sc->nrxchains; i++) 4496 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4497 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4498 #endif 4499 4500 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4501 R92C_HSSI_PARAM1_PI); 4502 if (piMode == 0) { 4503 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4504 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4505 R92C_HSSI_PARAM1_PI); 4506 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4507 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4508 R92C_HSSI_PARAM1_PI); 4509 } 4510 4511 attempt = 1; 4512 4513 next_attempt: 4514 4515 /* Set mac regs for calibration. */ 4516 for (i = 0; i < __arraycount(addaReg); i++) { 4517 urtwn_bb_write(sc, addaReg[i], 4518 addaReg[__arraycount(addaReg) - 1]); 4519 } 4520 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4521 R92C_CCK0_AFESETTING)); 4522 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4523 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4524 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4525 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4526 4527 if (sc->ntxchains > 1) 4528 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4529 4530 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4531 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4532 ~R92C_BCN_CTRL_EN_BCN)); 4533 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4534 ~R92C_BCN_CTRL_EN_BCN)); 4535 4536 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4537 ~R92C_GPIO_MUXCFG_ENBT)); 4538 4539 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4540 4541 if (sc->ntxchains > 1) 4542 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4543 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4544 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4545 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4546 4547 /* Restore BB regs. */ 4548 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4549 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4550 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4551 4552 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4553 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4554 if (sc->nrxchains > 1) 4555 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4556 4557 if (attempt-- > 0) 4558 goto next_attempt; 4559 4560 /* Restore mode. */ 4561 if (piMode == 0) { 4562 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4563 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4564 ~R92C_HSSI_PARAM1_PI); 4565 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4566 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4567 ~R92C_HSSI_PARAM1_PI); 4568 } 4569 4570 #ifdef notyet 4571 for (i = 0; i < sc->nrxchains; i++) { 4572 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4573 odfm0_agccore_regs[i]); 4574 } 4575 #endif 4576 4577 /* Restore adda regs. */ 4578 for (i = 0; i < __arraycount(addaReg); i++) 4579 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4580 /* Restore mac regs. */ 4581 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4582 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4583 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4584 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4585 4586 #ifdef notyet 4587 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4588 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4589 4590 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4591 for (i = 0; i < sc->nrxchains; i++) 4592 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4593 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4594 #endif 4595 } 4596 4597 static void 4598 urtwn_lc_calib(struct urtwn_softc *sc) 4599 { 4600 uint32_t rf_ac[2]; 4601 uint8_t txmode; 4602 size_t i; 4603 4604 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4605 4606 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4607 4608 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4609 if ((txmode & 0x70) != 0) { 4610 /* Disable all continuous Tx. */ 4611 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4612 4613 /* Set RF mode to standby mode. */ 4614 for (i = 0; i < sc->nrxchains; i++) { 4615 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4616 urtwn_rf_write(sc, i, R92C_RF_AC, 4617 RW(rf_ac[i], R92C_RF_AC_MODE, 4618 R92C_RF_AC_MODE_STANDBY)); 4619 } 4620 } else { 4621 /* Block all Tx queues. */ 4622 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4623 } 4624 /* Start calibration. */ 4625 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4626 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4627 4628 /* Give calibration the time to complete. */ 4629 urtwn_delay_ms(sc, 100); 4630 4631 /* Restore configuration. */ 4632 if ((txmode & 0x70) != 0) { 4633 /* Restore Tx mode. */ 4634 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4635 /* Restore RF mode. */ 4636 for (i = 0; i < sc->nrxchains; i++) { 4637 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4638 } 4639 } else { 4640 /* Unblock all Tx queues. */ 4641 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4642 } 4643 } 4644 4645 static void 4646 urtwn_temp_calib(struct urtwn_softc *sc) 4647 { 4648 int temp, t_meter_reg; 4649 4650 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4651 4652 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4653 4654 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4655 t_meter_reg = R92C_RF_T_METER; 4656 else 4657 t_meter_reg = R92E_RF_T_METER; 4658 4659 if (sc->thcal_state == 0) { 4660 /* Start measuring temperature. */ 4661 DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", 4662 device_xname(sc->sc_dev), __func__)); 4663 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4664 sc->thcal_state = 1; 4665 return; 4666 } 4667 sc->thcal_state = 0; 4668 4669 /* Read measured temperature. */ 4670 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4671 DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), 4672 __func__, temp)); 4673 if (temp == 0) /* Read failed, skip. */ 4674 return; 4675 4676 /* 4677 * Redo LC calibration if temperature changed significantly since 4678 * last calibration. 4679 */ 4680 if (sc->thcal_lctemp == 0) { 4681 /* First LC calibration is performed in urtwn_init(). */ 4682 sc->thcal_lctemp = temp; 4683 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4684 DPRINTFN(DBG_RF, 4685 ("%s: %s: LC calib triggered by temp: %d -> %d\n", 4686 device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, 4687 temp)); 4688 urtwn_lc_calib(sc); 4689 /* Record temperature of last LC calibration. */ 4690 sc->thcal_lctemp = temp; 4691 } 4692 } 4693 4694 static int 4695 urtwn_init(struct ifnet *ifp) 4696 { 4697 struct urtwn_softc *sc = ifp->if_softc; 4698 struct ieee80211com *ic = &sc->sc_ic; 4699 struct urtwn_rx_data *data; 4700 uint32_t reg; 4701 size_t i; 4702 int error; 4703 4704 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4705 4706 urtwn_stop(ifp, 0); 4707 4708 mutex_enter(&sc->sc_write_mtx); 4709 4710 mutex_enter(&sc->sc_task_mtx); 4711 /* Init host async commands ring. */ 4712 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4713 mutex_exit(&sc->sc_task_mtx); 4714 4715 mutex_enter(&sc->sc_fwcmd_mtx); 4716 /* Init firmware commands ring. */ 4717 sc->fwcur = 0; 4718 mutex_exit(&sc->sc_fwcmd_mtx); 4719 4720 /* Allocate Tx/Rx buffers. */ 4721 error = urtwn_alloc_rx_list(sc); 4722 if (error != 0) { 4723 aprint_error_dev(sc->sc_dev, 4724 "could not allocate Rx buffers\n"); 4725 goto fail; 4726 } 4727 error = urtwn_alloc_tx_list(sc); 4728 if (error != 0) { 4729 aprint_error_dev(sc->sc_dev, 4730 "could not allocate Tx buffers\n"); 4731 goto fail; 4732 } 4733 4734 /* Power on adapter. */ 4735 error = urtwn_power_on(sc); 4736 if (error != 0) 4737 goto fail; 4738 4739 /* Initialize DMA. */ 4740 error = urtwn_dma_init(sc); 4741 if (error != 0) 4742 goto fail; 4743 4744 /* Set info size in Rx descriptors (in 64-bit words). */ 4745 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4746 4747 /* Init interrupts. */ 4748 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4749 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4750 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4751 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4752 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4753 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4754 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4755 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4756 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4757 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4758 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4759 } 4760 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4761 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4762 } else { 4763 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4764 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4765 } 4766 4767 /* Set MAC address. */ 4768 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4769 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4770 4771 /* Set initial network type. */ 4772 reg = urtwn_read_4(sc, R92C_CR); 4773 switch (ic->ic_opmode) { 4774 case IEEE80211_M_STA: 4775 default: 4776 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4777 break; 4778 4779 case IEEE80211_M_IBSS: 4780 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4781 break; 4782 } 4783 urtwn_write_4(sc, R92C_CR, reg); 4784 4785 /* Set response rate */ 4786 reg = urtwn_read_4(sc, R92C_RRSR); 4787 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4788 urtwn_write_4(sc, R92C_RRSR, reg); 4789 4790 /* SIFS (used in NAV) */ 4791 urtwn_write_2(sc, R92C_SPEC_SIFS, 4792 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4793 4794 /* Set short/long retry limits. */ 4795 urtwn_write_2(sc, R92C_RL, 4796 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4797 4798 /* Initialize EDCA parameters. */ 4799 urtwn_edca_init(sc); 4800 4801 /* Setup rate fallback. */ 4802 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4803 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4804 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4805 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4806 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4807 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4808 } 4809 4810 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4811 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4812 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4813 /* Set ACK timeout. */ 4814 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4815 4816 /* Setup USB aggregation. */ 4817 /* Tx */ 4818 reg = urtwn_read_4(sc, R92C_TDECTRL); 4819 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4820 urtwn_write_4(sc, R92C_TDECTRL, reg); 4821 /* Rx */ 4822 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4823 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4824 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4825 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4826 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4827 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4828 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4829 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4830 ISSET(sc->chip, URTWN_CHIP_92EU)) 4831 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4832 else 4833 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4834 4835 /* Initialize beacon parameters. */ 4836 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4837 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4838 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4839 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4840 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4841 4842 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4843 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4844 /* Setup AMPDU aggregation. */ 4845 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4846 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4847 urtwn_write_2(sc, 0x4ca, 0x0708); 4848 4849 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4850 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4851 } 4852 4853 /* Load 8051 microcode. */ 4854 error = urtwn_load_firmware(sc); 4855 if (error != 0) 4856 goto fail; 4857 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4858 4859 /* Initialize MAC/BB/RF blocks. */ 4860 /* 4861 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4862 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4863 * XXX: This setting should be removed from rtl8192cu_mac[]. 4864 */ 4865 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4866 urtwn_rxfilter_init(sc); // reset R92C_RCR 4867 urtwn_bb_init(sc); 4868 urtwn_rf_init(sc); 4869 4870 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4871 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4872 urtwn_write_2(sc, R92C_CR, 4873 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4874 R92C_CR_MACRXEN); 4875 } 4876 4877 /* Turn CCK and OFDM blocks on. */ 4878 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4879 reg |= R92C_RFMOD_CCK_EN; 4880 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4881 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4882 reg |= R92C_RFMOD_OFDM_EN; 4883 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4884 4885 /* Clear per-station keys table. */ 4886 urtwn_cam_init(sc); 4887 4888 /* Enable hardware sequence numbering. */ 4889 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4890 4891 /* Perform LO and IQ calibrations. */ 4892 urtwn_iq_calib(sc, sc->iqk_inited); 4893 sc->iqk_inited = true; 4894 4895 /* Perform LC calibration. */ 4896 urtwn_lc_calib(sc); 4897 4898 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4899 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4900 /* Fix USB interference issue. */ 4901 urtwn_write_1(sc, 0xfe40, 0xe0); 4902 urtwn_write_1(sc, 0xfe41, 0x8d); 4903 urtwn_write_1(sc, 0xfe42, 0x80); 4904 urtwn_write_4(sc, 0x20c, 0xfd0320); 4905 4906 urtwn_pa_bias_init(sc); 4907 } 4908 4909 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 4910 !(sc->chip & URTWN_CHIP_92EU)) { 4911 /* 1T1R */ 4912 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 4913 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 4914 } 4915 4916 /* Initialize GPIO setting. */ 4917 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4918 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4919 4920 /* Fix for lower temperature. */ 4921 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4922 !ISSET(sc->chip, URTWN_CHIP_92EU)) 4923 urtwn_write_1(sc, 0x15, 0xe9); 4924 4925 /* Set default channel. */ 4926 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 4927 4928 /* Queue Rx xfers. */ 4929 for (size_t j = 0; j < sc->rx_npipe; j++) { 4930 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 4931 data = &sc->rx_data[j][i]; 4932 usbd_setup_xfer(data->xfer, data, data->buf, 4933 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 4934 urtwn_rxeof); 4935 error = usbd_transfer(data->xfer); 4936 if (__predict_false(error != USBD_NORMAL_COMPLETION && 4937 error != USBD_IN_PROGRESS)) 4938 goto fail; 4939 } 4940 } 4941 4942 /* We're ready to go. */ 4943 ifp->if_flags &= ~IFF_OACTIVE; 4944 ifp->if_flags |= IFF_RUNNING; 4945 sc->sc_running = true; 4946 4947 mutex_exit(&sc->sc_write_mtx); 4948 4949 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4950 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4951 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4952 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4953 urtwn_wait_async(sc); 4954 4955 return 0; 4956 4957 fail: 4958 mutex_exit(&sc->sc_write_mtx); 4959 4960 urtwn_stop(ifp, 1); 4961 return error; 4962 } 4963 4964 static void 4965 urtwn_stop(struct ifnet *ifp, int disable) 4966 { 4967 struct urtwn_softc *sc = ifp->if_softc; 4968 struct ieee80211com *ic = &sc->sc_ic; 4969 size_t i; 4970 int s; 4971 4972 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 4973 4974 s = splusb(); 4975 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4976 urtwn_wait_async(sc); 4977 splx(s); 4978 4979 sc->tx_timer = 0; 4980 ifp->if_timer = 0; 4981 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4982 4983 callout_stop(&sc->sc_scan_to); 4984 callout_stop(&sc->sc_calib_to); 4985 4986 /* Abort Tx. */ 4987 for (i = 0; i < sc->tx_npipe; i++) { 4988 if (sc->tx_pipe[i] != NULL) 4989 usbd_abort_pipe(sc->tx_pipe[i]); 4990 } 4991 4992 /* Stop Rx pipe. */ 4993 for (i = 0; i < sc->rx_npipe; i++) { 4994 if (sc->rx_pipe[i] != NULL) 4995 usbd_abort_pipe(sc->rx_pipe[i]); 4996 } 4997 4998 /* Free Tx/Rx buffers. */ 4999 urtwn_free_tx_list(sc); 5000 urtwn_free_rx_list(sc); 5001 5002 sc->sc_running = false; 5003 if (disable) 5004 urtwn_chip_stop(sc); 5005 } 5006 5007 static int 5008 urtwn_reset(struct ifnet *ifp) 5009 { 5010 struct urtwn_softc *sc = ifp->if_softc; 5011 struct ieee80211com *ic = &sc->sc_ic; 5012 5013 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5014 return ENETRESET; 5015 5016 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5017 5018 return 0; 5019 } 5020 5021 static void 5022 urtwn_chip_stop(struct urtwn_softc *sc) 5023 { 5024 uint32_t reg; 5025 bool disabled = true; 5026 5027 DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 5028 5029 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5030 ISSET(sc->chip, URTWN_CHIP_92EU)) 5031 return; 5032 5033 mutex_enter(&sc->sc_write_mtx); 5034 5035 /* 5036 * RF Off Sequence 5037 */ 5038 /* Pause MAC TX queue */ 5039 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5040 5041 /* Disable RF */ 5042 urtwn_rf_write(sc, 0, 0, 0); 5043 5044 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5045 5046 /* Reset BB state machine */ 5047 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5048 R92C_SYS_FUNC_EN_USBD | 5049 R92C_SYS_FUNC_EN_USBA | 5050 R92C_SYS_FUNC_EN_BB_GLB_RST); 5051 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5052 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5053 5054 /* 5055 * Reset digital sequence 5056 */ 5057 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5058 /* Reset MCU ready status */ 5059 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5060 /* If firmware in ram code, do reset */ 5061 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5062 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5063 ISSET(sc->chip, URTWN_CHIP_92EU)) 5064 urtwn_r88e_fw_reset(sc); 5065 else 5066 urtwn_fw_reset(sc); 5067 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5068 } 5069 } 5070 5071 /* Reset MAC and Enable 8051 */ 5072 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5073 5074 /* Reset MCU ready status */ 5075 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5076 5077 if (disabled) { 5078 /* Disable MAC clock */ 5079 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5080 /* Disable AFE PLL */ 5081 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5082 /* Gated AFE DIG_CLOCK */ 5083 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5084 /* Isolated digital to PON */ 5085 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5086 } 5087 5088 /* 5089 * Pull GPIO PIN to balance level and LED control 5090 */ 5091 /* 1. Disable GPIO[7:0] */ 5092 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5093 5094 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5095 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5096 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5097 5098 /* Disable GPIO[10:8] */ 5099 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5100 5101 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5102 reg |= (((reg & 0x000f) << 4) | 0x0780); 5103 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5104 5105 /* Disable LED0 & 1 */ 5106 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5107 5108 /* 5109 * Reset digital sequence 5110 */ 5111 if (disabled) { 5112 /* Disable ELDR clock */ 5113 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5114 /* Isolated ELDR to PON */ 5115 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5116 } 5117 5118 /* 5119 * Disable analog sequence 5120 */ 5121 if (disabled) { 5122 /* Disable A15 power */ 5123 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5124 /* Disable digital core power */ 5125 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5126 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5127 ~R92C_LDOV12D_CTRL_LDV12_EN); 5128 } 5129 5130 /* Enter PFM mode */ 5131 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5132 5133 /* Set USB suspend */ 5134 urtwn_write_2(sc, R92C_APS_FSMCO, 5135 R92C_APS_FSMCO_APDM_HOST | 5136 R92C_APS_FSMCO_AFSM_HSUS | 5137 R92C_APS_FSMCO_PFM_ALDN); 5138 5139 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5140 5141 mutex_exit(&sc->sc_write_mtx); 5142 } 5143 5144 static void 5145 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5146 { 5147 if (sc->sc_running == false) 5148 DELAY(ms * 1000); 5149 else 5150 usbd_delay_ms(sc->sc_udev, ms); 5151 } 5152 5153 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5154 5155 #ifdef _MODULE 5156 #include "ioconf.c" 5157 #endif 5158 5159 static int 5160 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5161 { 5162 int error = 0; 5163 5164 switch (cmd) { 5165 case MODULE_CMD_INIT: 5166 #ifdef _MODULE 5167 error = config_init_component(cfdriver_ioconf_urtwn, 5168 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5169 #endif 5170 return error; 5171 case MODULE_CMD_FINI: 5172 #ifdef _MODULE 5173 error = config_fini_component(cfdriver_ioconf_urtwn, 5174 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5175 #endif 5176 return error; 5177 default: 5178 return ENOTTY; 5179 } 5180 } 5181