1 /* $NetBSD: if_ure.c,v 1.7 2019/05/28 07:41:50 msaitoh Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 /*- 4 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.7 2019/05/28 07:41:50 msaitoh Exp $"); 33 34 #ifdef _KERNEL_OPT 35 #include "opt_usb.h" 36 #include "opt_inet.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/mutex.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 49 #include <sys/rndsource.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 56 #include <net/bpf.h> 57 58 #include <netinet/in.h> 59 60 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 61 #ifdef INET6 62 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 63 #endif 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 #include <dev/usb/usbdi_util.h> 71 #include <dev/usb/usbdivar.h> 72 #include <dev/usb/usbdevs.h> 73 74 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 75 #include <dev/usb/if_urereg.h> 76 #include <dev/usb/if_urevar.h> 77 78 #define URE_PRINTF(sc, fmt, args...) \ 79 device_printf((sc)->ure_dev, "%s: " fmt, __func__, ##args); 80 81 #define URE_DEBUG 82 #ifdef URE_DEBUG 83 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 84 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 85 int uredebug = 1; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 static const struct usb_devno ure_devs[] = { 92 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 93 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 94 }; 95 96 static int ure_match(device_t, cfdata_t, void *); 97 static void ure_attach(device_t, device_t, void *); 98 static int ure_detach(device_t, int); 99 static int ure_activate(device_t, enum devact); 100 101 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 102 void *, int); 103 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 104 int); 105 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 106 int); 107 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 108 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 109 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 110 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 111 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 112 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 113 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 114 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 115 116 static int ure_init(struct ifnet *); 117 static void ure_stop(struct ifnet *, int); 118 static void ure_start(struct ifnet *); 119 static void ure_reset(struct ure_softc *); 120 static void ure_miibus_statchg(struct ifnet *); 121 static int ure_miibus_readreg(device_t, int, int, uint16_t *); 122 static int ure_miibus_writereg(device_t, int, int, uint16_t); 123 static void ure_lock_mii(struct ure_softc *); 124 static void ure_unlock_mii(struct ure_softc *); 125 126 static int ure_encap(struct ure_softc *, struct mbuf *, int); 127 static uint32_t ure_txcsum(struct mbuf *); 128 static void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 129 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 130 static void ure_txeof(struct usbd_xfer *, void *, usbd_status); 131 static int ure_rx_list_init(struct ure_softc *); 132 static int ure_tx_list_init(struct ure_softc *); 133 134 static void ure_tick_task(void *); 135 static void ure_tick(void *); 136 137 static int ure_ifmedia_upd(struct ifnet *); 138 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 139 static int ure_ioctl(struct ifnet *, u_long, void *); 140 static void ure_rtl8152_init(struct ure_softc *); 141 static void ure_rtl8153_init(struct ure_softc *); 142 static void ure_disable_teredo(struct ure_softc *); 143 static void ure_init_fifo(struct ure_softc *); 144 145 CFATTACH_DECL_NEW(ure, sizeof(struct ure_softc), ure_match, ure_attach, 146 ure_detach, ure_activate); 147 148 static int 149 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 150 void *buf, int len) 151 { 152 usb_device_request_t req; 153 usbd_status err; 154 155 if (sc->ure_dying) 156 return 0; 157 158 if (rw == URE_CTL_WRITE) 159 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 160 else 161 req.bmRequestType = UT_READ_VENDOR_DEVICE; 162 req.bRequest = UR_SET_ADDRESS; 163 USETW(req.wValue, val); 164 USETW(req.wIndex, index); 165 USETW(req.wLength, len); 166 167 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 168 rw, val, index, len)); 169 err = usbd_do_request(sc->ure_udev, &req, buf); 170 if (err) { 171 DPRINTF(("ure_ctl: error %d\n", err)); 172 return -1; 173 } 174 175 return 0; 176 } 177 178 static int 179 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 180 void *buf, int len) 181 { 182 183 return ure_ctl(sc, URE_CTL_READ, addr, index, buf, len); 184 } 185 186 static int 187 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 188 void *buf, int len) 189 { 190 191 return ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len); 192 } 193 194 static uint8_t 195 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 196 { 197 uint32_t val; 198 uint8_t temp[4]; 199 uint8_t shift; 200 201 shift = (reg & 3) << 3; 202 reg &= ~3; 203 204 ure_read_mem(sc, reg, index, &temp, 4); 205 val = UGETDW(temp); 206 val >>= shift; 207 208 return val & 0xff; 209 } 210 211 static uint16_t 212 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 213 { 214 uint32_t val; 215 uint8_t temp[4]; 216 uint8_t shift; 217 218 shift = (reg & 2) << 3; 219 reg &= ~3; 220 221 ure_read_mem(sc, reg, index, &temp, 4); 222 val = UGETDW(temp); 223 val >>= shift; 224 225 return val & 0xffff; 226 } 227 228 static uint32_t 229 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 230 { 231 uint8_t temp[4]; 232 233 ure_read_mem(sc, reg, index, &temp, 4); 234 return UGETDW(temp); 235 } 236 237 static int 238 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 239 { 240 uint16_t byen; 241 uint8_t temp[4]; 242 uint8_t shift; 243 244 byen = URE_BYTE_EN_BYTE; 245 shift = reg & 3; 246 val &= 0xff; 247 248 if (reg & 3) { 249 byen <<= shift; 250 val <<= (shift << 3); 251 reg &= ~3; 252 } 253 254 USETDW(temp, val); 255 return ure_write_mem(sc, reg, index | byen, &temp, 4); 256 } 257 258 static int 259 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 260 { 261 uint16_t byen; 262 uint8_t temp[4]; 263 uint8_t shift; 264 265 byen = URE_BYTE_EN_WORD; 266 shift = reg & 2; 267 val &= 0xffff; 268 269 if (reg & 2) { 270 byen <<= shift; 271 val <<= (shift << 3); 272 reg &= ~3; 273 } 274 275 USETDW(temp, val); 276 return ure_write_mem(sc, reg, index | byen, &temp, 4); 277 } 278 279 static int 280 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 281 { 282 uint8_t temp[4]; 283 284 USETDW(temp, val); 285 return ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 286 } 287 288 static uint16_t 289 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 290 { 291 uint16_t reg; 292 293 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 294 reg = (addr & 0x0fff) | 0xb000; 295 296 return ure_read_2(sc, reg, URE_MCU_TYPE_PLA); 297 } 298 299 static void 300 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 301 { 302 uint16_t reg; 303 304 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 305 reg = (addr & 0x0fff) | 0xb000; 306 307 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 308 } 309 310 static int 311 ure_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 312 { 313 struct ure_softc *sc = device_private(dev); 314 315 if (sc->ure_dying || sc->ure_phyno != phy) /* XXX */ 316 return -1; 317 318 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 319 if (reg == RTK_GMEDIASTAT) { 320 *val = ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 321 return 0; 322 } 323 324 ure_lock_mii(sc); 325 *val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 326 ure_unlock_mii(sc); 327 328 return 0; 329 } 330 331 static int 332 ure_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 333 { 334 struct ure_softc *sc = device_private(dev); 335 336 if (sc->ure_dying || sc->ure_phyno != phy) /* XXX */ 337 return -1; 338 339 ure_lock_mii(sc); 340 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 341 ure_unlock_mii(sc); 342 343 return 0; 344 } 345 346 static void 347 ure_miibus_statchg(struct ifnet *ifp) 348 { 349 struct ure_softc *sc; 350 struct mii_data *mii; 351 352 if (ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) 353 return; 354 355 sc = ifp->if_softc; 356 mii = GET_MII(sc); 357 358 if (mii == NULL) 359 return; 360 361 sc->ure_flags &= ~URE_FLAG_LINK; 362 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 363 (IFM_ACTIVE | IFM_AVALID)) { 364 switch (IFM_SUBTYPE(mii->mii_media_active)) { 365 case IFM_10_T: 366 case IFM_100_TX: 367 sc->ure_flags |= URE_FLAG_LINK; 368 break; 369 case IFM_1000_T: 370 if ((sc->ure_flags & URE_FLAG_8152) != 0) 371 break; 372 sc->ure_flags |= URE_FLAG_LINK; 373 break; 374 default: 375 break; 376 } 377 } 378 } 379 380 static int 381 ure_ifmedia_upd(struct ifnet *ifp) 382 { 383 struct ure_softc *sc = ifp->if_softc; 384 struct mii_data *mii = GET_MII(sc); 385 int err; 386 387 sc->ure_flags &= ~URE_FLAG_LINK; 388 if (mii->mii_instance) { 389 struct mii_softc *miisc; 390 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 391 mii_phy_reset(miisc); 392 } 393 394 err = mii_mediachg(mii); 395 if (err == ENXIO) 396 return 0; /* XXX */ 397 else 398 return err; 399 } 400 401 static void 402 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 403 { 404 struct ure_softc *sc = ifp->if_softc; 405 struct mii_data *mii = GET_MII(sc); 406 407 mii_pollstat(mii); 408 ifmr->ifm_active = mii->mii_media_active; 409 ifmr->ifm_status = mii->mii_media_status; 410 } 411 412 static void 413 ure_iff(struct ure_softc *sc) 414 { 415 struct ethercom *ec = &sc->ure_ec; 416 struct ifnet *ifp = GET_IFP(sc); 417 struct ether_multi *enm; 418 struct ether_multistep step; 419 uint32_t hashes[2] = { 0, 0 }; 420 uint32_t hash; 421 uint32_t rxmode; 422 423 if (sc->ure_dying) 424 return; 425 426 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 427 rxmode &= ~URE_RCR_ACPT_ALL; 428 ifp->if_flags &= ~IFF_ALLMULTI; 429 430 /* 431 * Always accept frames destined to our station address. 432 * Always accept broadcast frames. 433 */ 434 rxmode |= URE_RCR_APM | URE_RCR_AB; 435 436 if (ifp->if_flags & IFF_PROMISC) { 437 rxmode |= URE_RCR_AAP; 438 allmulti: ifp->if_flags |= IFF_ALLMULTI; 439 rxmode |= URE_RCR_AM; 440 hashes[0] = hashes[1] = 0xffffffff; 441 } else { 442 rxmode |= URE_RCR_AM; 443 444 ETHER_LOCK(ec); 445 ETHER_FIRST_MULTI(step, ec, enm); 446 while (enm != NULL) { 447 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 448 ETHER_ADDR_LEN)) { 449 ETHER_UNLOCK(ec); 450 goto allmulti; 451 } 452 453 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 454 >> 26; 455 if (hash < 32) 456 hashes[0] |= (1 << hash); 457 else 458 hashes[1] |= (1 << (hash - 32)); 459 460 ETHER_NEXT_MULTI(step, enm); 461 } 462 ETHER_UNLOCK(ec); 463 464 hash = bswap32(hashes[0]); 465 hashes[0] = bswap32(hashes[1]); 466 hashes[1] = hash; 467 } 468 469 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 470 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 471 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 472 } 473 474 static void 475 ure_reset(struct ure_softc *sc) 476 { 477 int i; 478 479 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 480 481 for (i = 0; i < URE_TIMEOUT; i++) { 482 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 483 URE_CR_RST)) 484 break; 485 usbd_delay_ms(sc->ure_udev, 10); 486 } 487 if (i == URE_TIMEOUT) 488 URE_PRINTF(sc, "reset never completed\n"); 489 } 490 491 static int 492 ure_init(struct ifnet *ifp) 493 { 494 struct ure_softc *sc = ifp->if_softc; 495 struct ure_chain *c; 496 usbd_status err; 497 int s, i; 498 uint8_t eaddr[8]; 499 500 s = splnet(); 501 502 /* Cancel pending I/O. */ 503 if (ifp->if_flags & IFF_RUNNING) 504 ure_stop(ifp, 1); 505 506 /* Set MAC address. */ 507 memset(eaddr, 0, sizeof(eaddr)); 508 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 509 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 510 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 511 eaddr, 8); 512 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 513 514 /* Reset the packet filter. */ 515 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 516 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 517 ~URE_FMC_FCR_MCU_EN); 518 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 519 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 520 URE_FMC_FCR_MCU_EN); 521 522 /* Enable transmit and receive. */ 523 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 524 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 525 URE_CR_TE); 526 527 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 528 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 529 ~URE_RXDY_GATED_EN); 530 531 /* Load the multicast filter. */ 532 ure_iff(sc); 533 534 /* Open RX and TX pipes. */ 535 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 536 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 537 if (err) { 538 URE_PRINTF(sc, "open rx pipe failed: %s\n", usbd_errstr(err)); 539 splx(s); 540 return EIO; 541 } 542 543 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 544 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 545 if (err) { 546 URE_PRINTF(sc, "open tx pipe failed: %s\n", usbd_errstr(err)); 547 splx(s); 548 return EIO; 549 } 550 551 if (ure_rx_list_init(sc)) { 552 URE_PRINTF(sc, "rx list init failed\n"); 553 splx(s); 554 return ENOBUFS; 555 } 556 557 if (ure_tx_list_init(sc)) { 558 URE_PRINTF(sc, "tx list init failed\n"); 559 splx(s); 560 return ENOBUFS; 561 } 562 563 /* Start up the receive pipe. */ 564 for (i = 0; i < URE_RX_LIST_CNT; i++) { 565 c = &sc->ure_cdata.rx_chain[i]; 566 usbd_setup_xfer(c->uc_xfer, c, c->uc_buf, sc->ure_bufsz, 567 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, ure_rxeof); 568 usbd_transfer(c->uc_xfer); 569 } 570 571 /* Indicate we are up and running. */ 572 ifp->if_flags |= IFF_RUNNING; 573 ifp->if_flags &= ~IFF_OACTIVE; 574 575 splx(s); 576 577 callout_reset(&sc->ure_stat_ch, hz, ure_tick, sc); 578 579 return 0; 580 } 581 582 static void 583 ure_start(struct ifnet *ifp) 584 { 585 struct ure_softc *sc = ifp->if_softc; 586 struct mbuf *m; 587 struct ure_cdata *cd = &sc->ure_cdata; 588 int idx; 589 590 if ((sc->ure_flags & URE_FLAG_LINK) == 0 || 591 (ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) { 592 return; 593 } 594 595 idx = cd->tx_prod; 596 while (cd->tx_cnt < URE_TX_LIST_CNT) { 597 IFQ_POLL(&ifp->if_snd, m); 598 if (m == NULL) 599 break; 600 601 if (ure_encap(sc, m, idx)) { 602 ifp->if_oerrors++; 603 break; 604 } 605 IFQ_DEQUEUE(&ifp->if_snd, m); 606 607 bpf_mtap(ifp, m, BPF_D_OUT); 608 m_freem(m); 609 610 idx = (idx + 1) % URE_TX_LIST_CNT; 611 cd->tx_cnt++; 612 } 613 cd->tx_prod = idx; 614 615 if (cd->tx_cnt >= URE_TX_LIST_CNT) 616 ifp->if_flags |= IFF_OACTIVE; 617 } 618 619 static void 620 ure_tick(void *xsc) 621 { 622 struct ure_softc *sc = xsc; 623 624 if (sc == NULL) 625 return; 626 627 if (sc->ure_dying) 628 return; 629 630 usb_add_task(sc->ure_udev, &sc->ure_tick_task, USB_TASKQ_DRIVER); 631 } 632 633 static void 634 ure_stop(struct ifnet *ifp, int disable __unused) 635 { 636 struct ure_softc *sc = ifp->if_softc; 637 struct ure_chain *c; 638 usbd_status err; 639 int i; 640 641 ure_reset(sc); 642 643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 644 645 callout_stop(&sc->ure_stat_ch); 646 647 sc->ure_flags &= ~URE_FLAG_LINK; /* XXX */ 648 649 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 650 err = usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 651 if (err) 652 URE_PRINTF(sc, "abort rx pipe failed: %s\n", 653 usbd_errstr(err)); 654 } 655 656 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 657 err = usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 658 if (err) 659 URE_PRINTF(sc, "abort tx pipe failed: %s\n", 660 usbd_errstr(err)); 661 } 662 663 for (i = 0; i < URE_RX_LIST_CNT; i++) { 664 c = &sc->ure_cdata.rx_chain[i]; 665 if (c->uc_xfer != NULL) { 666 usbd_destroy_xfer(c->uc_xfer); 667 c->uc_xfer = NULL; 668 } 669 } 670 671 for (i = 0; i < URE_TX_LIST_CNT; i++) { 672 c = &sc->ure_cdata.tx_chain[i]; 673 if (c->uc_xfer != NULL) { 674 usbd_destroy_xfer(c->uc_xfer); 675 c->uc_xfer = NULL; 676 } 677 } 678 679 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 680 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 681 if (err) 682 URE_PRINTF(sc, "close rx pipe failed: %s\n", 683 usbd_errstr(err)); 684 sc->ure_ep[URE_ENDPT_RX] = NULL; 685 } 686 687 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 688 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 689 if (err) 690 URE_PRINTF(sc, "close tx pipe failed: %s\n", 691 usbd_errstr(err)); 692 sc->ure_ep[URE_ENDPT_TX] = NULL; 693 } 694 } 695 696 static void 697 ure_rtl8152_init(struct ure_softc *sc) 698 { 699 uint32_t pwrctrl; 700 701 /* Disable ALDPS. */ 702 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 703 URE_DIS_SDSAVE); 704 usbd_delay_ms(sc->ure_udev, 20); 705 706 if (sc->ure_chip & URE_CHIP_VER_4C00) { 707 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 708 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 709 ~URE_LED_MODE_MASK); 710 } 711 712 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 713 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 714 ~URE_POWER_CUT); 715 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 716 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 717 ~URE_RESUME_INDICATE); 718 719 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 720 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 721 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 722 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 723 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 724 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 725 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 726 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 727 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 728 URE_SPDWN_LINKCHG_MSK); 729 730 /* Enable Rx aggregation. */ 731 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 732 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 733 ~URE_RX_AGG_DISABLE); 734 735 /* Disable ALDPS. */ 736 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 737 URE_DIS_SDSAVE); 738 usbd_delay_ms(sc->ure_udev, 20); 739 740 ure_init_fifo(sc); 741 742 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 743 URE_TX_AGG_MAX_THRESHOLD); 744 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 745 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 746 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 747 } 748 749 static void 750 ure_rtl8153_init(struct ure_softc *sc) 751 { 752 uint16_t val; 753 uint8_t u1u2[8]; 754 int i; 755 756 /* Disable ALDPS. */ 757 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 758 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 759 usbd_delay_ms(sc->ure_udev, 20); 760 761 memset(u1u2, 0x00, sizeof(u1u2)); 762 ure_write_mem(sc, URE_USB_TOLERANCE, 763 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 764 765 for (i = 0; i < URE_TIMEOUT; i++) { 766 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 767 URE_AUTOLOAD_DONE) 768 break; 769 usbd_delay_ms(sc->ure_udev, 10); 770 } 771 if (i == URE_TIMEOUT) 772 URE_PRINTF(sc, "timeout waiting for chip autoload\n"); 773 774 for (i = 0; i < URE_TIMEOUT; i++) { 775 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 776 URE_PHY_STAT_MASK; 777 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 778 break; 779 usbd_delay_ms(sc->ure_udev, 10); 780 } 781 if (i == URE_TIMEOUT) 782 URE_PRINTF(sc, "timeout waiting for phy to stabilize\n"); 783 784 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 785 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 786 ~URE_U2P3_ENABLE); 787 788 if (sc->ure_chip & URE_CHIP_VER_5C10) { 789 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 790 val &= ~URE_PWD_DN_SCALE_MASK; 791 val |= URE_PWD_DN_SCALE(96); 792 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 793 794 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 795 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 796 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 797 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 798 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 799 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 800 ~URE_ECM_ALDPS); 801 } 802 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 803 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 804 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 805 0) 806 val &= ~URE_DYNAMIC_BURST; 807 else 808 val |= URE_DYNAMIC_BURST; 809 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 810 } 811 812 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 813 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 814 URE_EP4_FULL_FC); 815 816 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 817 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 818 ~URE_TIMER11_EN); 819 820 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 821 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 822 ~URE_LED_MODE_MASK); 823 824 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 825 sc->ure_udev->ud_speed != USB_SPEED_SUPER) 826 val = URE_LPM_TIMER_500MS; 827 else 828 val = URE_LPM_TIMER_500US; 829 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 830 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 831 832 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 833 val &= ~URE_SEN_VAL_MASK; 834 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 835 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 836 837 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 838 839 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 840 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 841 ~(URE_PWR_EN | URE_PHASE2_EN)); 842 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 843 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 844 ~URE_PCUT_STATUS); 845 846 memset(u1u2, 0xff, sizeof(u1u2)); 847 ure_write_mem(sc, URE_USB_TOLERANCE, 848 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 849 850 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 851 URE_ALDPS_SPDWN_RATIO); 852 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 853 URE_EEE_SPDWN_RATIO); 854 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 855 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 856 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 857 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 858 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 859 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 860 URE_EEE_SPDWN_EN); 861 862 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 863 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 864 val |= URE_U2P3_ENABLE; 865 else 866 val &= ~URE_U2P3_ENABLE; 867 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 868 869 memset(u1u2, 0x00, sizeof(u1u2)); 870 ure_write_mem(sc, URE_USB_TOLERANCE, 871 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 872 873 /* Disable ALDPS. */ 874 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 875 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 876 usbd_delay_ms(sc->ure_udev, 20); 877 878 ure_init_fifo(sc); 879 880 /* Enable Rx aggregation. */ 881 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 882 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 883 ~URE_RX_AGG_DISABLE); 884 885 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 886 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 887 val |= URE_U2P3_ENABLE; 888 else 889 val &= ~URE_U2P3_ENABLE; 890 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 891 892 memset(u1u2, 0xff, sizeof(u1u2)); 893 ure_write_mem(sc, URE_USB_TOLERANCE, 894 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 895 } 896 897 static void 898 ure_disable_teredo(struct ure_softc *sc) 899 { 900 901 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 902 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 903 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 904 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 905 URE_WDT6_SET_MODE); 906 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 907 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 908 } 909 910 static void 911 ure_init_fifo(struct ure_softc *sc) 912 { 913 uint32_t rx_fifo1, rx_fifo2; 914 int i; 915 916 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 917 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 918 URE_RXDY_GATED_EN); 919 920 ure_disable_teredo(sc); 921 922 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 923 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 924 ~URE_RCR_ACPT_ALL); 925 926 if (!(sc->ure_flags & URE_FLAG_8152)) { 927 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 928 URE_CHIP_VER_5C20)) 929 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 930 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 931 if (sc->ure_chip & URE_CHIP_VER_5C00) 932 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 933 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 934 ~URE_CTAP_SHORT_EN); 935 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 936 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 937 URE_EEE_CLKDIV_EN); 938 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 939 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 940 URE_EN_10M_BGOFF); 941 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 942 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 943 URE_EN_10M_PLLOFF); 944 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 945 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 946 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 947 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 948 URE_PFM_PWM_SWITCH); 949 950 /* Enable LPF corner auto tune. */ 951 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 952 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 953 954 /* Adjust 10M amplitude. */ 955 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 956 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 957 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 958 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 959 } 960 961 ure_reset(sc); 962 963 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 964 965 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 966 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 967 ~URE_NOW_IS_OOB); 968 969 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 970 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 971 ~URE_MCU_BORW_EN); 972 for (i = 0; i < URE_TIMEOUT; i++) { 973 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 974 URE_LINK_LIST_READY) 975 break; 976 usbd_delay_ms(sc->ure_udev, 10); 977 } 978 if (i == URE_TIMEOUT) 979 URE_PRINTF(sc, "timeout waiting for OOB control\n"); 980 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 981 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 982 URE_RE_INIT_LL); 983 for (i = 0; i < URE_TIMEOUT; i++) { 984 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 985 URE_LINK_LIST_READY) 986 break; 987 usbd_delay_ms(sc->ure_udev, 10); 988 } 989 if (i == URE_TIMEOUT) 990 URE_PRINTF(sc, "timeout waiting for OOB control\n"); 991 992 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 993 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 994 ~URE_CPCR_RX_VLAN); 995 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 996 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 997 URE_TCR0_AUTO_FIFO); 998 999 /* Configure Rx FIFO threshold and coalescing. */ 1000 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1001 URE_RXFIFO_THR1_NORMAL); 1002 if (sc->ure_udev->ud_speed == USB_SPEED_FULL) { 1003 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1004 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1005 } else { 1006 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1007 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1008 } 1009 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1010 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1011 1012 /* Configure Tx FIFO threshold. */ 1013 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1014 URE_TXFIFO_THR_NORMAL); 1015 } 1016 1017 int 1018 ure_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1019 { 1020 struct ure_softc *sc = ifp->if_softc; 1021 int s, error = 0, oflags = ifp->if_flags; 1022 1023 s = splnet(); 1024 1025 switch (cmd) { 1026 case SIOCSIFFLAGS: 1027 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1028 break; 1029 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1030 case IFF_RUNNING: 1031 ure_stop(ifp, 1); 1032 break; 1033 case IFF_UP: 1034 ure_init(ifp); 1035 break; 1036 case IFF_UP | IFF_RUNNING: 1037 if ((ifp->if_flags ^ oflags) == IFF_PROMISC) 1038 ure_iff(sc); 1039 else 1040 ure_init(ifp); 1041 } 1042 break; 1043 default: 1044 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1045 break; 1046 error = 0; 1047 if ((ifp->if_flags & IFF_RUNNING) == 0) 1048 break; 1049 switch (cmd) { 1050 case SIOCADDMULTI: 1051 case SIOCDELMULTI: 1052 ure_iff(sc); 1053 break; 1054 default: 1055 break; 1056 } 1057 } 1058 1059 splx(s); 1060 1061 return error; 1062 } 1063 1064 static int 1065 ure_match(device_t parent, cfdata_t match, void *aux) 1066 { 1067 struct usb_attach_arg *uaa = aux; 1068 1069 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 1070 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 1071 } 1072 1073 static void 1074 ure_attach(device_t parent, device_t self, void *aux) 1075 { 1076 struct ure_softc *sc = device_private(self); 1077 struct usb_attach_arg *uaa = aux; 1078 struct usbd_device *dev = uaa->uaa_device; 1079 usb_interface_descriptor_t *id; 1080 usb_endpoint_descriptor_t *ed; 1081 struct ifnet *ifp; 1082 struct mii_data *mii; 1083 int error, i, s; 1084 uint16_t ver; 1085 uint8_t eaddr[8]; /* 2byte padded */ 1086 char *devinfop; 1087 1088 aprint_naive("\n"); 1089 aprint_normal("\n"); 1090 1091 sc->ure_dev = self; 1092 sc->ure_udev = dev; 1093 1094 devinfop = usbd_devinfo_alloc(sc->ure_udev, 0); 1095 aprint_normal_dev(self, "%s\n", devinfop); 1096 usbd_devinfo_free(devinfop); 1097 1098 #define URE_CONFIG_NO 1 /* XXX */ 1099 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 1100 if (error) { 1101 aprint_error_dev(self, "failed to set configuration: %s\n", 1102 usbd_errstr(error)); 1103 return; /* XXX */ 1104 } 1105 1106 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 1107 sc->ure_flags |= URE_FLAG_8152; 1108 1109 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 0); 1110 mutex_init(&sc->ure_mii_lock, MUTEX_DEFAULT, IPL_NONE); 1111 1112 #define URE_IFACE_IDX 0 /* XXX */ 1113 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &sc->ure_iface); 1114 if (error) { 1115 aprint_error_dev(self, "failed to get interface handle: %s\n", 1116 usbd_errstr(error)); 1117 return; /* XXX */ 1118 } 1119 1120 sc->ure_bufsz = 16 * 1024; 1121 1122 id = usbd_get_interface_descriptor(sc->ure_iface); 1123 for (i = 0; i < id->bNumEndpoints; i++) { 1124 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1125 if (ed == NULL) { 1126 aprint_error_dev(self, "couldn't get ep %d\n", i); 1127 return; /* XXX */ 1128 } 1129 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1130 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1131 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1132 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1133 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1134 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1135 } 1136 } 1137 1138 s = splnet(); 1139 1140 sc->ure_phyno = 0; 1141 1142 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1143 switch (ver) { 1144 case 0x4c00: 1145 sc->ure_chip |= URE_CHIP_VER_4C00; 1146 break; 1147 case 0x4c10: 1148 sc->ure_chip |= URE_CHIP_VER_4C10; 1149 break; 1150 case 0x5c00: 1151 sc->ure_chip |= URE_CHIP_VER_5C00; 1152 break; 1153 case 0x5c10: 1154 sc->ure_chip |= URE_CHIP_VER_5C10; 1155 break; 1156 case 0x5c20: 1157 sc->ure_chip |= URE_CHIP_VER_5C20; 1158 break; 1159 case 0x5c30: 1160 sc->ure_chip |= URE_CHIP_VER_5C30; 1161 break; 1162 default: 1163 /* fake addr? or just fail? */ 1164 break; 1165 } 1166 aprint_normal_dev(self, "RTL%d %sver %04x\n", 1167 (sc->ure_flags & URE_FLAG_8152) ? 8152 : 8153, 1168 (sc->ure_chip != 0) ? "" : "unknown ", 1169 ver); 1170 1171 if (sc->ure_flags & URE_FLAG_8152) 1172 ure_rtl8152_init(sc); 1173 else 1174 ure_rtl8153_init(sc); 1175 1176 if (sc->ure_chip & URE_CHIP_VER_4C00) 1177 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1178 sizeof(eaddr)); 1179 else 1180 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1181 sizeof(eaddr)); 1182 1183 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1184 1185 ifp = GET_IFP(sc); 1186 ifp->if_softc = sc; 1187 strlcpy(ifp->if_xname, device_xname(sc->ure_dev), IFNAMSIZ); 1188 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1189 ifp->if_init = ure_init; 1190 ifp->if_ioctl = ure_ioctl; 1191 ifp->if_start = ure_start; 1192 ifp->if_stop = ure_stop; 1193 1194 /* 1195 * We don't support TSOv4 and v6 for now, that are required to 1196 * be handled in software for some cases. 1197 */ 1198 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 1199 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 1200 #ifdef INET6 1201 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 1202 #endif 1203 if (sc->ure_chip & ~URE_CHIP_VER_4C00) { 1204 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 1205 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1206 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1207 } 1208 sc->ure_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1209 #ifdef notyet 1210 sc->ure_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1211 #endif 1212 1213 IFQ_SET_READY(&ifp->if_snd); 1214 1215 mii = GET_MII(sc); 1216 mii->mii_ifp = ifp; 1217 mii->mii_readreg = ure_miibus_readreg; 1218 mii->mii_writereg = ure_miibus_writereg; 1219 mii->mii_statchg = ure_miibus_statchg; 1220 mii->mii_flags = MIIF_AUTOTSLEEP; 1221 1222 sc->ure_ec.ec_mii = mii; 1223 ifmedia_init(&mii->mii_media, 0, ure_ifmedia_upd, ure_ifmedia_sts); 1224 mii_attach(self, mii, 0xffffffff, sc->ure_phyno, MII_OFFSET_ANY, 0); 1225 1226 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1227 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1228 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1229 } else 1230 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1231 1232 if_attach(ifp); 1233 ether_ifattach(ifp, eaddr); 1234 1235 rnd_attach_source(&sc->ure_rnd_source, device_xname(sc->ure_dev), 1236 RND_TYPE_NET, RND_FLAG_DEFAULT); 1237 1238 callout_init(&sc->ure_stat_ch, 0); 1239 1240 splx(s); 1241 1242 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->ure_udev, sc->ure_dev); 1243 1244 if (!pmf_device_register(self, NULL, NULL)) 1245 aprint_error_dev(self, "couldn't establish power handler\n"); 1246 } 1247 1248 static int 1249 ure_detach(device_t self, int flags) 1250 { 1251 struct ure_softc *sc = device_private(self); 1252 struct ifnet *ifp = GET_IFP(sc); 1253 int s; 1254 1255 pmf_device_deregister(self); 1256 1257 sc->ure_dying = true; 1258 1259 callout_halt(&sc->ure_stat_ch, NULL); 1260 1261 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1262 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1263 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1264 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1265 1266 usb_rem_task_wait(sc->ure_udev, &sc->ure_tick_task, USB_TASKQ_DRIVER, 1267 NULL); 1268 1269 s = splusb(); 1270 1271 if (ifp->if_flags & IFF_RUNNING) 1272 ure_stop(ifp, 1); 1273 1274 callout_destroy(&sc->ure_stat_ch); 1275 rnd_detach_source(&sc->ure_rnd_source); 1276 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1277 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1278 if (ifp->if_softc != NULL) { 1279 ether_ifdetach(ifp); 1280 if_detach(ifp); 1281 } 1282 1283 if (--sc->ure_refcnt >= 0) { 1284 /* Wait for processes to go away. */ 1285 usb_detach_waitold(sc->ure_dev); 1286 } 1287 splx(s); 1288 1289 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->ure_udev, sc->ure_dev); 1290 1291 mutex_destroy(&sc->ure_mii_lock); 1292 1293 return 0; 1294 } 1295 1296 static int 1297 ure_activate(device_t self, enum devact act) 1298 { 1299 struct ure_softc *sc = device_private(self); 1300 struct ifnet *ifp = GET_IFP(sc); 1301 1302 switch (act) { 1303 case DVACT_DEACTIVATE: 1304 if_deactivate(ifp); 1305 sc->ure_dying = true; 1306 return 0; 1307 default: 1308 return EOPNOTSUPP; 1309 } 1310 return 0; 1311 } 1312 1313 static void 1314 ure_tick_task(void *xsc) 1315 { 1316 struct ure_softc *sc = xsc; 1317 struct ifnet *ifp = GET_IFP(sc); 1318 struct mii_data *mii; 1319 int s; 1320 1321 if (sc == NULL) 1322 return; 1323 1324 if (sc->ure_dying) 1325 return; 1326 1327 mii = GET_MII(sc); 1328 1329 s = splnet(); 1330 mii_tick(mii); 1331 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1332 ure_miibus_statchg(ifp); 1333 callout_reset(&sc->ure_stat_ch, hz, ure_tick, sc); 1334 splx(s); 1335 } 1336 1337 static void 1338 ure_lock_mii(struct ure_softc *sc) 1339 { 1340 1341 sc->ure_refcnt++; 1342 mutex_enter(&sc->ure_mii_lock); 1343 } 1344 1345 static void 1346 ure_unlock_mii(struct ure_softc *sc) 1347 { 1348 1349 mutex_exit(&sc->ure_mii_lock); 1350 if (--sc->ure_refcnt < 0) 1351 usb_detach_wakeupold(sc->ure_dev); 1352 } 1353 1354 static void 1355 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1356 { 1357 struct ure_chain *c = (struct ure_chain *)priv; 1358 struct ure_softc *sc = c->uc_sc; 1359 struct ifnet *ifp = GET_IFP(sc); 1360 uint8_t *buf = c->uc_buf; 1361 uint32_t total_len; 1362 uint16_t pktlen = 0; 1363 struct mbuf *m; 1364 int s; 1365 struct ure_rxpkt rxhdr; 1366 1367 if (sc->ure_dying) 1368 return; 1369 1370 if (!(ifp->if_flags & IFF_RUNNING)) 1371 return; 1372 1373 if (status != USBD_NORMAL_COMPLETION) { 1374 if (status == USBD_INVAL) 1375 return; /* XXX plugged out or down */ 1376 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1377 return; 1378 if (usbd_ratecheck(&sc->ure_rx_notice)) 1379 URE_PRINTF(sc, "usb errors on rx: %s\n", 1380 usbd_errstr(status)); 1381 if (status == USBD_STALLED) 1382 usbd_clear_endpoint_stall_async( 1383 sc->ure_ep[URE_ENDPT_RX]); 1384 goto done; 1385 } 1386 1387 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1388 DPRINTFN(3, ("received %d bytes\n", total_len)); 1389 1390 KASSERTMSG(total_len <= sc->ure_bufsz, "%u vs %u", 1391 total_len, sc->ure_bufsz); 1392 1393 do { 1394 if (total_len < sizeof(rxhdr)) { 1395 DPRINTF(("too few bytes left for a packet header\n")); 1396 ifp->if_ierrors++; 1397 goto done; 1398 } 1399 1400 buf += roundup(pktlen, 8); 1401 1402 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1403 total_len -= sizeof(rxhdr); 1404 1405 pktlen = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1406 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1407 if (pktlen > total_len) { 1408 DPRINTF(("not enough bytes left for next packet\n")); 1409 ifp->if_ierrors++; 1410 goto done; 1411 } 1412 1413 total_len -= roundup(pktlen, 8); 1414 buf += sizeof(rxhdr); 1415 1416 m = m_devget(buf, pktlen - ETHER_CRC_LEN, 0, ifp); 1417 if (m == NULL) { 1418 DPRINTF(("unable to allocate mbuf for next packet\n")); 1419 ifp->if_ierrors++; 1420 goto done; 1421 } 1422 1423 m->m_pkthdr.csum_flags = ure_rxcsum(ifp, &rxhdr); 1424 1425 s = splnet(); 1426 if_percpuq_enqueue(ifp->if_percpuq, m); 1427 splx(s); 1428 } while (total_len > 0); 1429 1430 done: 1431 usbd_setup_xfer(xfer, c, c->uc_buf, sc->ure_bufsz, 1432 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, ure_rxeof); 1433 usbd_transfer(xfer); 1434 } 1435 1436 static int 1437 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1438 { 1439 int enabled = ifp->if_csum_flags_rx, flags = 0; 1440 uint32_t csum, misc; 1441 1442 if (enabled == 0) 1443 return 0; 1444 1445 csum = le32toh(rp->ure_csum); 1446 misc = le32toh(rp->ure_misc); 1447 1448 if (csum & URE_RXPKT_IPV4_CS) { 1449 flags |= M_CSUM_IPv4; 1450 if (csum & URE_RXPKT_TCP_CS) 1451 flags |= M_CSUM_TCPv4; 1452 if (csum & URE_RXPKT_UDP_CS) 1453 flags |= M_CSUM_UDPv4; 1454 } else if (csum & URE_RXPKT_IPV6_CS) { 1455 flags = 0; 1456 if (csum & URE_RXPKT_TCP_CS) 1457 flags |= M_CSUM_TCPv6; 1458 if (csum & URE_RXPKT_UDP_CS) 1459 flags |= M_CSUM_UDPv6; 1460 } 1461 1462 flags &= enabled; 1463 if (__predict_false((flags & M_CSUM_IPv4) && 1464 (misc & URE_RXPKT_IP_F))) 1465 flags |= M_CSUM_IPv4_BAD; 1466 if (__predict_false( 1467 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1468 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1469 )) 1470 flags |= M_CSUM_TCP_UDP_BAD; 1471 1472 return flags; 1473 } 1474 1475 static void 1476 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1477 { 1478 struct ure_chain *c = priv; 1479 struct ure_softc *sc = c->uc_sc; 1480 struct ure_cdata *cd = &sc->ure_cdata; 1481 struct ifnet *ifp = GET_IFP(sc); 1482 int s; 1483 1484 if (sc->ure_dying) 1485 return; 1486 1487 DPRINTFN(2, ("tx completion\n")); 1488 1489 s = splnet(); 1490 1491 KASSERT(cd->tx_cnt > 0); 1492 cd->tx_cnt--; 1493 1494 if (status != USBD_NORMAL_COMPLETION) { 1495 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1496 splx(s); 1497 return; 1498 } 1499 ifp->if_oerrors++; 1500 if (usbd_ratecheck(&sc->ure_tx_notice)) 1501 URE_PRINTF(sc, "usb error on tx: %s\n", 1502 usbd_errstr(status)); 1503 if (status == USBD_STALLED) 1504 usbd_clear_endpoint_stall_async( 1505 sc->ure_ep[URE_ENDPT_TX]); 1506 splx(s); 1507 return; 1508 } 1509 1510 ifp->if_flags &= ~IFF_OACTIVE; 1511 1512 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1513 ure_start(ifp); 1514 1515 splx(s); 1516 } 1517 1518 static int 1519 ure_tx_list_init(struct ure_softc *sc) 1520 { 1521 struct ure_cdata *cd; 1522 struct ure_chain *c; 1523 int i, error; 1524 1525 cd = &sc->ure_cdata; 1526 for (i = 0; i < URE_TX_LIST_CNT; i++) { 1527 c = &cd->tx_chain[i]; 1528 c->uc_sc = sc; 1529 if (c->uc_xfer == NULL) { 1530 error = usbd_create_xfer(sc->ure_ep[URE_ENDPT_TX], 1531 sc->ure_bufsz, USBD_FORCE_SHORT_XFER, 0, 1532 &c->uc_xfer); 1533 if (error) 1534 return error; 1535 c->uc_buf = usbd_get_buffer(c->uc_xfer); 1536 } 1537 } 1538 1539 cd->tx_prod = cd->tx_cnt = 0; 1540 1541 return 0; 1542 } 1543 1544 static int 1545 ure_rx_list_init(struct ure_softc *sc) 1546 { 1547 struct ure_cdata *cd; 1548 struct ure_chain *c; 1549 int i, error; 1550 1551 cd = &sc->ure_cdata; 1552 for (i = 0; i < URE_RX_LIST_CNT; i++) { 1553 c = &cd->rx_chain[i]; 1554 c->uc_sc = sc; 1555 error = usbd_create_xfer(sc->ure_ep[URE_ENDPT_RX], 1556 sc->ure_bufsz, 0, 0, &c->uc_xfer); 1557 if (error) 1558 return error; 1559 c->uc_buf = usbd_get_buffer(c->uc_xfer); 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int 1566 ure_encap(struct ure_softc *sc, struct mbuf *m, int idx) 1567 { 1568 struct ifnet *ifp = GET_IFP(sc); 1569 struct ure_chain *c; 1570 usbd_status err; 1571 struct ure_txpkt txhdr; 1572 uint32_t frm_len = 0; 1573 uint8_t *buf; 1574 1575 c = &sc->ure_cdata.tx_chain[idx]; 1576 buf = c->uc_buf; 1577 1578 /* header */ 1579 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1580 URE_TXPKT_TX_LS); 1581 txhdr.ure_csum = htole32(ure_txcsum(m)); 1582 memcpy(buf, &txhdr, sizeof(txhdr)); 1583 buf += sizeof(txhdr); 1584 frm_len = sizeof(txhdr); 1585 1586 /* packet */ 1587 m_copydata(m, 0, m->m_pkthdr.len, buf); 1588 frm_len += m->m_pkthdr.len; 1589 1590 if (__predict_false(c->uc_xfer == NULL)) 1591 return EIO; /* XXX plugged out or down */ 1592 1593 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1594 usbd_setup_xfer(c->uc_xfer, c, c->uc_buf, frm_len, 1595 USBD_FORCE_SHORT_XFER, 10000, ure_txeof); 1596 1597 err = usbd_transfer(c->uc_xfer); 1598 if (err != USBD_IN_PROGRESS) { 1599 ure_stop(ifp, 0); 1600 return EIO; 1601 } 1602 1603 return 0; 1604 } 1605 1606 /* 1607 * We need to calculate L4 checksum in software, if the offset of 1608 * L4 header is larger than 0x7ff = 2047. 1609 */ 1610 static uint32_t 1611 ure_txcsum(struct mbuf *m) 1612 { 1613 struct ether_header *eh; 1614 int flags = m->m_pkthdr.csum_flags; 1615 uint32_t data = m->m_pkthdr.csum_data; 1616 uint32_t reg = 0; 1617 int l3off, l4off; 1618 uint16_t type; 1619 1620 if (flags == 0) 1621 return 0; 1622 1623 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1624 eh = mtod(m, struct ether_header *); 1625 type = eh->ether_type; 1626 } else 1627 m_copydata(m, offsetof(struct ether_header, ether_type), 1628 sizeof(type), &type); 1629 switch (type = htons(type)) { 1630 case ETHERTYPE_IP: 1631 case ETHERTYPE_IPV6: 1632 l3off = ETHER_HDR_LEN; 1633 break; 1634 case ETHERTYPE_VLAN: 1635 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1636 break; 1637 default: 1638 return 0; 1639 } 1640 1641 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1642 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1643 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1644 in_undefer_cksum(m, l3off, flags); 1645 return 0; 1646 } 1647 reg |= URE_TXPKT_IPV4_CS; 1648 if (flags & M_CSUM_TCPv4) 1649 reg |= URE_TXPKT_TCP_CS; 1650 else 1651 reg |= URE_TXPKT_UDP_CS; 1652 reg |= l4off << URE_L4_OFFSET_SHIFT; 1653 } 1654 #ifdef INET6 1655 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1656 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1657 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1658 in6_undefer_cksum(m, l3off, flags); 1659 return 0; 1660 } 1661 reg |= URE_TXPKT_IPV6_CS; 1662 if (flags & M_CSUM_TCPv6) 1663 reg |= URE_TXPKT_TCP_CS; 1664 else 1665 reg |= URE_TXPKT_UDP_CS; 1666 reg |= l4off << URE_L4_OFFSET_SHIFT; 1667 } 1668 #endif 1669 else if (flags & M_CSUM_IPv4) 1670 reg |= URE_TXPKT_IPV4_CS; 1671 1672 return reg; 1673 } 1674