1 /* $NetBSD: if_ure.c,v 1.33 2019/10/16 13:11:16 bad Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.33 2019/10/16 13:11:16 bad Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_stop_cb(struct ifnet *, int); 89 static int ure_ioctl_cb(struct ifnet *, u_long, void *); 90 static int ure_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_miibus_statchg(struct ifnet *); 93 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 96 static int ure_init(struct ifnet *); 97 98 static int ure_match(device_t, cfdata_t, void *); 99 static void ure_attach(device_t, device_t, void *); 100 101 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 102 usbnet_detach, usbnet_activate); 103 104 static struct usbnet_ops ure_ops = { 105 .uno_stop = ure_stop_cb, 106 .uno_ioctl = ure_ioctl_cb, 107 .uno_read_reg = ure_mii_read_reg, 108 .uno_write_reg = ure_mii_write_reg, 109 .uno_statchg = ure_miibus_statchg, 110 .uno_tx_prepare = ure_tx_prepare, 111 .uno_rx_loop = ure_rx_loop, 112 .uno_init = ure_init, 113 }; 114 115 static int 116 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 117 void *buf, int len) 118 { 119 usb_device_request_t req; 120 usbd_status err; 121 122 if (usbnet_isdying(un)) 123 return 0; 124 125 if (rw == URE_CTL_WRITE) 126 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 127 else 128 req.bmRequestType = UT_READ_VENDOR_DEVICE; 129 req.bRequest = UR_SET_ADDRESS; 130 USETW(req.wValue, val); 131 USETW(req.wIndex, index); 132 USETW(req.wLength, len); 133 134 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 135 rw, val, index, len)); 136 err = usbd_do_request(un->un_udev, &req, buf); 137 if (err) { 138 DPRINTF(("ure_ctl: error %d\n", err)); 139 return -1; 140 } 141 142 return 0; 143 } 144 145 static int 146 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 147 void *buf, int len) 148 { 149 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 150 } 151 152 static int 153 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 154 void *buf, int len) 155 { 156 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 157 } 158 159 static uint8_t 160 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 161 { 162 uint32_t val; 163 uint8_t temp[4]; 164 uint8_t shift; 165 166 shift = (reg & 3) << 3; 167 reg &= ~3; 168 169 ure_read_mem(un, reg, index, &temp, 4); 170 val = UGETDW(temp); 171 val >>= shift; 172 173 return val & 0xff; 174 } 175 176 static uint16_t 177 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 178 { 179 uint32_t val; 180 uint8_t temp[4]; 181 uint8_t shift; 182 183 shift = (reg & 2) << 3; 184 reg &= ~3; 185 186 ure_read_mem(un, reg, index, &temp, 4); 187 val = UGETDW(temp); 188 val >>= shift; 189 190 return val & 0xffff; 191 } 192 193 static uint32_t 194 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 195 { 196 uint8_t temp[4]; 197 198 ure_read_mem(un, reg, index, &temp, 4); 199 return UGETDW(temp); 200 } 201 202 static int 203 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 204 { 205 uint16_t byen; 206 uint8_t temp[4]; 207 uint8_t shift; 208 209 byen = URE_BYTE_EN_BYTE; 210 shift = reg & 3; 211 val &= 0xff; 212 213 if (reg & 3) { 214 byen <<= shift; 215 val <<= (shift << 3); 216 reg &= ~3; 217 } 218 219 USETDW(temp, val); 220 return ure_write_mem(un, reg, index | byen, &temp, 4); 221 } 222 223 static int 224 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 225 { 226 uint16_t byen; 227 uint8_t temp[4]; 228 uint8_t shift; 229 230 byen = URE_BYTE_EN_WORD; 231 shift = reg & 2; 232 val &= 0xffff; 233 234 if (reg & 2) { 235 byen <<= shift; 236 val <<= (shift << 3); 237 reg &= ~3; 238 } 239 240 USETDW(temp, val); 241 return ure_write_mem(un, reg, index | byen, &temp, 4); 242 } 243 244 static int 245 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 246 { 247 uint8_t temp[4]; 248 249 USETDW(temp, val); 250 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 251 } 252 253 static uint16_t 254 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 255 { 256 uint16_t reg; 257 258 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 259 reg = (addr & 0x0fff) | 0xb000; 260 261 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 262 } 263 264 static void 265 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 266 { 267 uint16_t reg; 268 269 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 270 reg = (addr & 0x0fff) | 0xb000; 271 272 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 273 } 274 275 static int 276 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 277 { 278 usbnet_isowned_mii(un); 279 280 if (un->un_phyno != phy) 281 return EINVAL; 282 283 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 284 if (reg == RTK_GMEDIASTAT) { 285 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 286 return USBD_NORMAL_COMPLETION; 287 } 288 289 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 290 291 return 0; 292 } 293 294 static int 295 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 296 { 297 usbnet_isowned_mii(un); 298 299 if (un->un_phyno != phy) 300 return EINVAL; 301 302 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 303 304 return 0; 305 } 306 307 static void 308 ure_miibus_statchg(struct ifnet *ifp) 309 { 310 struct usbnet * const un = ifp->if_softc; 311 struct mii_data * const mii = usbnet_mii(un); 312 313 if (usbnet_isdying(un)) 314 return; 315 316 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 317 (IFM_ACTIVE | IFM_AVALID)) { 318 switch (IFM_SUBTYPE(mii->mii_media_active)) { 319 case IFM_10_T: 320 case IFM_100_TX: 321 usbnet_set_link(un, true); 322 break; 323 case IFM_1000_T: 324 if ((un->un_flags & URE_FLAG_8152) != 0) 325 break; 326 usbnet_set_link(un, true); 327 break; 328 default: 329 break; 330 } 331 } 332 } 333 334 static void 335 ure_setiff_locked(struct usbnet *un) 336 { 337 struct ethercom *ec = usbnet_ec(un); 338 struct ifnet *ifp = usbnet_ifp(un); 339 struct ether_multi *enm; 340 struct ether_multistep step; 341 uint32_t hashes[2] = { 0, 0 }; 342 uint32_t hash; 343 uint32_t rxmode; 344 345 usbnet_isowned(un); 346 347 if (usbnet_isdying(un)) 348 return; 349 350 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 351 rxmode &= ~URE_RCR_ACPT_ALL; 352 353 /* 354 * Always accept frames destined to our station address. 355 * Always accept broadcast frames. 356 */ 357 rxmode |= URE_RCR_APM | URE_RCR_AB; 358 359 if (ifp->if_flags & IFF_PROMISC) { 360 rxmode |= URE_RCR_AAP; 361 allmulti: 362 ETHER_LOCK(ec); 363 ec->ec_flags |= ETHER_F_ALLMULTI; 364 ETHER_UNLOCK(ec); 365 rxmode |= URE_RCR_AM; 366 hashes[0] = hashes[1] = 0xffffffff; 367 } else { 368 rxmode |= URE_RCR_AM; 369 370 ETHER_LOCK(ec); 371 ec->ec_flags &= ~ETHER_F_ALLMULTI; 372 373 ETHER_FIRST_MULTI(step, ec, enm); 374 while (enm != NULL) { 375 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 376 ETHER_ADDR_LEN)) { 377 ETHER_UNLOCK(ec); 378 goto allmulti; 379 } 380 381 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 382 >> 26; 383 if (hash < 32) 384 hashes[0] |= (1 << hash); 385 else 386 hashes[1] |= (1 << (hash - 32)); 387 388 ETHER_NEXT_MULTI(step, enm); 389 } 390 ETHER_UNLOCK(ec); 391 392 hash = bswap32(hashes[0]); 393 hashes[0] = bswap32(hashes[1]); 394 hashes[1] = hash; 395 } 396 397 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 398 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 399 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 400 } 401 402 static void 403 ure_setiff(struct usbnet *un) 404 { 405 406 usbnet_lock(un); 407 ure_setiff_locked(un); 408 usbnet_unlock(un); 409 } 410 411 static void 412 ure_reset(struct usbnet *un) 413 { 414 int i; 415 416 usbnet_isowned(un); 417 418 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 419 420 for (i = 0; i < URE_TIMEOUT; i++) { 421 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 422 URE_CR_RST)) 423 break; 424 usbd_delay_ms(un->un_udev, 10); 425 } 426 if (i == URE_TIMEOUT) 427 URE_PRINTF(un, "reset never completed\n"); 428 } 429 430 static int 431 ure_init_locked(struct ifnet *ifp) 432 { 433 struct usbnet * const un = ifp->if_softc; 434 uint8_t eaddr[8]; 435 436 usbnet_isowned(un); 437 438 if (usbnet_isdying(un)) 439 return EIO; 440 441 /* Cancel pending I/O. */ 442 if (ifp->if_flags & IFF_RUNNING) 443 usbnet_stop(un, ifp, 1); 444 445 /* Set MAC address. */ 446 memset(eaddr, 0, sizeof(eaddr)); 447 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 448 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 449 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 450 eaddr, 8); 451 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 452 453 /* Reset the packet filter. */ 454 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 455 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 456 ~URE_FMC_FCR_MCU_EN); 457 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 458 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 459 URE_FMC_FCR_MCU_EN); 460 461 /* Enable transmit and receive. */ 462 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 463 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 464 URE_CR_TE); 465 466 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 467 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 468 ~URE_RXDY_GATED_EN); 469 470 /* Load the multicast filter. */ 471 ure_setiff_locked(un); 472 473 return usbnet_init_rx_tx(un); 474 } 475 476 static int 477 ure_init(struct ifnet *ifp) 478 { 479 struct usbnet * const un = ifp->if_softc; 480 481 usbnet_lock(un); 482 int ret = ure_init_locked(ifp); 483 usbnet_unlock(un); 484 485 return ret; 486 } 487 488 static void 489 ure_stop_cb(struct ifnet *ifp, int disable __unused) 490 { 491 struct usbnet * const un = ifp->if_softc; 492 493 ure_reset(un); 494 } 495 496 static void 497 ure_rtl8152_init(struct usbnet *un) 498 { 499 uint32_t pwrctrl; 500 501 /* Disable ALDPS. */ 502 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 503 URE_DIS_SDSAVE); 504 usbd_delay_ms(un->un_udev, 20); 505 506 if (un->un_flags & URE_FLAG_VER_4C00) { 507 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 508 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 509 ~URE_LED_MODE_MASK); 510 } 511 512 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 513 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 514 ~URE_POWER_CUT); 515 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 516 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 517 ~URE_RESUME_INDICATE); 518 519 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 520 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 521 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 522 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 523 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 524 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 525 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 526 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 527 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 528 URE_SPDWN_LINKCHG_MSK); 529 530 /* Enable Rx aggregation. */ 531 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 532 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 533 ~URE_RX_AGG_DISABLE); 534 535 /* Disable ALDPS. */ 536 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 537 URE_DIS_SDSAVE); 538 usbd_delay_ms(un->un_udev, 20); 539 540 ure_init_fifo(un); 541 542 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 543 URE_TX_AGG_MAX_THRESHOLD); 544 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 545 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 546 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 547 } 548 549 static void 550 ure_rtl8153_init(struct usbnet *un) 551 { 552 uint16_t val; 553 uint8_t u1u2[8]; 554 int i; 555 556 /* Disable ALDPS. */ 557 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 558 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 559 usbd_delay_ms(un->un_udev, 20); 560 561 memset(u1u2, 0x00, sizeof(u1u2)); 562 ure_write_mem(un, URE_USB_TOLERANCE, 563 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 564 565 for (i = 0; i < URE_TIMEOUT; i++) { 566 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 567 URE_AUTOLOAD_DONE) 568 break; 569 usbd_delay_ms(un->un_udev, 10); 570 } 571 if (i == URE_TIMEOUT) 572 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 573 574 for (i = 0; i < URE_TIMEOUT; i++) { 575 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 576 URE_PHY_STAT_MASK; 577 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 578 break; 579 usbd_delay_ms(un->un_udev, 10); 580 } 581 if (i == URE_TIMEOUT) 582 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 583 584 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 585 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 586 ~URE_U2P3_ENABLE); 587 588 if (un->un_flags & URE_FLAG_VER_5C10) { 589 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 590 val &= ~URE_PWD_DN_SCALE_MASK; 591 val |= URE_PWD_DN_SCALE(96); 592 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 593 594 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 595 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 596 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 597 } else if (un->un_flags & URE_FLAG_VER_5C20) { 598 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 599 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 600 ~URE_ECM_ALDPS); 601 } 602 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 603 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 604 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 605 0) 606 val &= ~URE_DYNAMIC_BURST; 607 else 608 val |= URE_DYNAMIC_BURST; 609 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 610 } 611 612 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 613 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 614 URE_EP4_FULL_FC); 615 616 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 617 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 618 ~URE_TIMER11_EN); 619 620 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 621 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 622 ~URE_LED_MODE_MASK); 623 624 if ((un->un_flags & URE_FLAG_VER_5C10) && 625 un->un_udev->ud_speed != USB_SPEED_SUPER) 626 val = URE_LPM_TIMER_500MS; 627 else 628 val = URE_LPM_TIMER_500US; 629 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 630 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 631 632 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 633 val &= ~URE_SEN_VAL_MASK; 634 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 635 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 636 637 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 638 639 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 640 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 641 ~(URE_PWR_EN | URE_PHASE2_EN)); 642 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 643 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 644 ~URE_PCUT_STATUS); 645 646 memset(u1u2, 0xff, sizeof(u1u2)); 647 ure_write_mem(un, URE_USB_TOLERANCE, 648 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 649 650 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 651 URE_ALDPS_SPDWN_RATIO); 652 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 653 URE_EEE_SPDWN_RATIO); 654 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 655 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 656 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 657 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 658 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 659 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 660 URE_EEE_SPDWN_EN); 661 662 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 663 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 664 val |= URE_U2P3_ENABLE; 665 else 666 val &= ~URE_U2P3_ENABLE; 667 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 668 669 memset(u1u2, 0x00, sizeof(u1u2)); 670 ure_write_mem(un, URE_USB_TOLERANCE, 671 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 672 673 /* Disable ALDPS. */ 674 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 675 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 676 usbd_delay_ms(un->un_udev, 20); 677 678 ure_init_fifo(un); 679 680 /* Enable Rx aggregation. */ 681 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 682 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 683 ~URE_RX_AGG_DISABLE); 684 685 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 686 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 687 val |= URE_U2P3_ENABLE; 688 else 689 val &= ~URE_U2P3_ENABLE; 690 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 691 692 memset(u1u2, 0xff, sizeof(u1u2)); 693 ure_write_mem(un, URE_USB_TOLERANCE, 694 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 695 } 696 697 static void 698 ure_disable_teredo(struct usbnet *un) 699 { 700 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 701 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 702 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 703 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 704 URE_WDT6_SET_MODE); 705 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 706 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 707 } 708 709 static void 710 ure_init_fifo(struct usbnet *un) 711 { 712 uint32_t rx_fifo1, rx_fifo2; 713 int i; 714 715 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 716 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 717 URE_RXDY_GATED_EN); 718 719 ure_disable_teredo(un); 720 721 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 722 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 723 ~URE_RCR_ACPT_ALL); 724 725 if (!(un->un_flags & URE_FLAG_8152)) { 726 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 727 URE_FLAG_VER_5C20)) 728 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 729 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 730 if (un->un_flags & URE_FLAG_VER_5C00) 731 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 732 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 733 ~URE_CTAP_SHORT_EN); 734 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 735 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 736 URE_EEE_CLKDIV_EN); 737 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 738 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 739 URE_EN_10M_BGOFF); 740 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 741 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 742 URE_EN_10M_PLLOFF); 743 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 744 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 745 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 746 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 747 URE_PFM_PWM_SWITCH); 748 749 /* Enable LPF corner auto tune. */ 750 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 751 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 752 753 /* Adjust 10M amplitude. */ 754 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 755 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 756 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 757 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 758 } 759 760 ure_reset(un); 761 762 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 763 764 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 765 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 766 ~URE_NOW_IS_OOB); 767 768 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 769 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 770 ~URE_MCU_BORW_EN); 771 for (i = 0; i < URE_TIMEOUT; i++) { 772 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 773 URE_LINK_LIST_READY) 774 break; 775 usbd_delay_ms(un->un_udev, 10); 776 } 777 if (i == URE_TIMEOUT) 778 URE_PRINTF(un, "timeout waiting for OOB control\n"); 779 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 780 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 781 URE_RE_INIT_LL); 782 for (i = 0; i < URE_TIMEOUT; i++) { 783 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 784 URE_LINK_LIST_READY) 785 break; 786 usbd_delay_ms(un->un_udev, 10); 787 } 788 if (i == URE_TIMEOUT) 789 URE_PRINTF(un, "timeout waiting for OOB control\n"); 790 791 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 792 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 793 ~URE_CPCR_RX_VLAN); 794 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 795 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 796 URE_TCR0_AUTO_FIFO); 797 798 /* Configure Rx FIFO threshold and coalescing. */ 799 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 800 URE_RXFIFO_THR1_NORMAL); 801 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 802 rx_fifo1 = URE_RXFIFO_THR2_FULL; 803 rx_fifo2 = URE_RXFIFO_THR3_FULL; 804 } else { 805 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 806 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 807 } 808 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 809 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 810 811 /* Configure Tx FIFO threshold. */ 812 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 813 URE_TXFIFO_THR_NORMAL); 814 } 815 816 static int 817 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 818 { 819 struct usbnet * const un = ifp->if_softc; 820 821 switch (cmd) { 822 case SIOCADDMULTI: 823 case SIOCDELMULTI: 824 ure_setiff(un); 825 break; 826 default: 827 break; 828 } 829 830 return 0; 831 } 832 833 static int 834 ure_match(device_t parent, cfdata_t match, void *aux) 835 { 836 struct usb_attach_arg *uaa = aux; 837 838 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 839 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 840 } 841 842 static void 843 ure_attach(device_t parent, device_t self, void *aux) 844 { 845 USBNET_MII_DECL_DEFAULT(unm); 846 struct usbnet * const un = device_private(self); 847 struct usb_attach_arg *uaa = aux; 848 struct usbd_device *dev = uaa->uaa_device; 849 usb_interface_descriptor_t *id; 850 usb_endpoint_descriptor_t *ed; 851 int error, i; 852 uint16_t ver; 853 uint8_t eaddr[8]; /* 2byte padded */ 854 char *devinfop; 855 uint32_t maclo, machi; 856 857 aprint_naive("\n"); 858 aprint_normal("\n"); 859 devinfop = usbd_devinfo_alloc(dev, 0); 860 aprint_normal_dev(self, "%s\n", devinfop); 861 usbd_devinfo_free(devinfop); 862 863 un->un_dev = self; 864 un->un_udev = dev; 865 un->un_sc = un; 866 un->un_ops = &ure_ops; 867 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 868 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 869 un->un_rx_list_cnt = URE_RX_LIST_CNT; 870 un->un_tx_list_cnt = URE_TX_LIST_CNT; 871 un->un_rx_bufsz = URE_BUFSZ; 872 un->un_tx_bufsz = URE_BUFSZ; 873 874 #define URE_CONFIG_NO 1 /* XXX */ 875 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 876 if (error) { 877 aprint_error_dev(self, "failed to set configuration: %s\n", 878 usbd_errstr(error)); 879 return; /* XXX */ 880 } 881 882 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 883 un->un_flags |= URE_FLAG_8152; 884 885 #define URE_IFACE_IDX 0 /* XXX */ 886 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 887 if (error) { 888 aprint_error_dev(self, "failed to get interface handle: %s\n", 889 usbd_errstr(error)); 890 return; /* XXX */ 891 } 892 893 id = usbd_get_interface_descriptor(un->un_iface); 894 for (i = 0; i < id->bNumEndpoints; i++) { 895 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 896 if (ed == NULL) { 897 aprint_error_dev(self, "couldn't get ep %d\n", i); 898 return; /* XXX */ 899 } 900 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 901 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 902 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 903 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 904 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 905 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 906 } 907 } 908 909 /* Set these up now for ure_ctl(). */ 910 usbnet_attach(un, "uredet"); 911 912 un->un_phyno = 0; 913 914 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 915 switch (ver) { 916 case 0x4c00: 917 un->un_flags |= URE_FLAG_VER_4C00; 918 break; 919 case 0x4c10: 920 un->un_flags |= URE_FLAG_VER_4C10; 921 break; 922 case 0x5c00: 923 un->un_flags |= URE_FLAG_VER_5C00; 924 break; 925 case 0x5c10: 926 un->un_flags |= URE_FLAG_VER_5C10; 927 break; 928 case 0x5c20: 929 un->un_flags |= URE_FLAG_VER_5C20; 930 break; 931 case 0x5c30: 932 un->un_flags |= URE_FLAG_VER_5C30; 933 break; 934 default: 935 /* fake addr? or just fail? */ 936 break; 937 } 938 aprint_normal_dev(self, "RTL%d %sver %04x\n", 939 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 940 (un->un_flags != 0) ? "" : "unknown ", 941 ver); 942 943 usbnet_lock(un); 944 if (un->un_flags & URE_FLAG_8152) 945 ure_rtl8152_init(un); 946 else 947 ure_rtl8153_init(un); 948 949 if ((un->un_flags & URE_FLAG_VER_4C00) || 950 (un->un_flags & URE_FLAG_VER_4C10)) 951 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 952 sizeof(eaddr)); 953 else 954 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 955 sizeof(eaddr)); 956 usbnet_unlock(un); 957 if (ETHER_IS_ZERO(eaddr)) { 958 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 959 machi = cprng_strong32() & 0xffff; 960 eaddr[0] = maclo & 0xff; 961 eaddr[1] = (maclo >> 8) & 0xff; 962 eaddr[2] = (maclo >> 16) & 0xff; 963 eaddr[3] = (maclo >> 24) & 0xff; 964 eaddr[4] = machi & 0xff; 965 eaddr[5] = (machi >> 8) & 0xff; 966 } 967 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 968 969 struct ifnet *ifp = usbnet_ifp(un); 970 971 /* 972 * We don't support TSOv4 and v6 for now, that are required to 973 * be handled in software for some cases. 974 */ 975 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 976 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 977 #ifdef INET6 978 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 979 #endif 980 if (un->un_flags & ~URE_FLAG_VER_4C00) { 981 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 982 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 983 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 984 } 985 struct ethercom *ec = usbnet_ec(un); 986 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 987 #ifdef notyet 988 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 989 #endif 990 991 unm.un_mii_phyloc = un->un_phyno; 992 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 993 0, &unm); 994 } 995 996 static void 997 ure_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 998 { 999 struct ifnet *ifp = usbnet_ifp(un); 1000 uint8_t *buf = c->unc_buf; 1001 uint16_t pkt_len = 0; 1002 uint16_t pkt_count = 0; 1003 struct ure_rxpkt rxhdr; 1004 1005 usbnet_isowned_rx(un); 1006 1007 do { 1008 if (total_len < sizeof(rxhdr)) { 1009 DPRINTF(("too few bytes left for a packet header\n")); 1010 ifp->if_ierrors++; 1011 return; 1012 } 1013 1014 buf += roundup(pkt_len, 8); 1015 1016 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1017 total_len -= sizeof(rxhdr); 1018 1019 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1020 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1021 if (pkt_len > total_len) { 1022 DPRINTF(("not enough bytes left for next packet\n")); 1023 ifp->if_ierrors++; 1024 return; 1025 } 1026 1027 total_len -= roundup(pkt_len, 8); 1028 buf += sizeof(rxhdr); 1029 1030 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1031 ure_rxcsum(ifp, &rxhdr), 0, 0); 1032 1033 pkt_count++; 1034 1035 } while (total_len > 0); 1036 1037 if (pkt_count) 1038 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1039 } 1040 1041 static int 1042 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1043 { 1044 int enabled = ifp->if_csum_flags_rx, flags = 0; 1045 uint32_t csum, misc; 1046 1047 if (enabled == 0) 1048 return 0; 1049 1050 csum = le32toh(rp->ure_csum); 1051 misc = le32toh(rp->ure_misc); 1052 1053 if (csum & URE_RXPKT_IPV4_CS) { 1054 flags |= M_CSUM_IPv4; 1055 if (csum & URE_RXPKT_TCP_CS) 1056 flags |= M_CSUM_TCPv4; 1057 if (csum & URE_RXPKT_UDP_CS) 1058 flags |= M_CSUM_UDPv4; 1059 } else if (csum & URE_RXPKT_IPV6_CS) { 1060 flags = 0; 1061 if (csum & URE_RXPKT_TCP_CS) 1062 flags |= M_CSUM_TCPv6; 1063 if (csum & URE_RXPKT_UDP_CS) 1064 flags |= M_CSUM_UDPv6; 1065 } 1066 1067 flags &= enabled; 1068 if (__predict_false((flags & M_CSUM_IPv4) && 1069 (misc & URE_RXPKT_IP_F))) 1070 flags |= M_CSUM_IPv4_BAD; 1071 if (__predict_false( 1072 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1073 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1074 )) 1075 flags |= M_CSUM_TCP_UDP_BAD; 1076 1077 return flags; 1078 } 1079 1080 static unsigned 1081 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1082 { 1083 struct ure_txpkt txhdr; 1084 uint32_t frm_len = 0; 1085 uint8_t *buf = c->unc_buf; 1086 1087 usbnet_isowned_tx(un); 1088 1089 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1090 return 0; 1091 1092 /* header */ 1093 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1094 URE_TXPKT_TX_LS); 1095 txhdr.ure_csum = htole32(ure_txcsum(m)); 1096 memcpy(buf, &txhdr, sizeof(txhdr)); 1097 buf += sizeof(txhdr); 1098 frm_len = sizeof(txhdr); 1099 1100 /* packet */ 1101 m_copydata(m, 0, m->m_pkthdr.len, buf); 1102 frm_len += m->m_pkthdr.len; 1103 1104 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1105 1106 return frm_len; 1107 } 1108 1109 /* 1110 * We need to calculate L4 checksum in software, if the offset of 1111 * L4 header is larger than 0x7ff = 2047. 1112 */ 1113 static uint32_t 1114 ure_txcsum(struct mbuf *m) 1115 { 1116 struct ether_header *eh; 1117 int flags = m->m_pkthdr.csum_flags; 1118 uint32_t data = m->m_pkthdr.csum_data; 1119 uint32_t reg = 0; 1120 int l3off, l4off; 1121 uint16_t type; 1122 1123 if (flags == 0) 1124 return 0; 1125 1126 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1127 eh = mtod(m, struct ether_header *); 1128 type = eh->ether_type; 1129 } else 1130 m_copydata(m, offsetof(struct ether_header, ether_type), 1131 sizeof(type), &type); 1132 switch (type = htons(type)) { 1133 case ETHERTYPE_IP: 1134 case ETHERTYPE_IPV6: 1135 l3off = ETHER_HDR_LEN; 1136 break; 1137 case ETHERTYPE_VLAN: 1138 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1139 break; 1140 default: 1141 return 0; 1142 } 1143 1144 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1145 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1146 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1147 in_undefer_cksum(m, l3off, flags); 1148 return 0; 1149 } 1150 reg |= URE_TXPKT_IPV4_CS; 1151 if (flags & M_CSUM_TCPv4) 1152 reg |= URE_TXPKT_TCP_CS; 1153 else 1154 reg |= URE_TXPKT_UDP_CS; 1155 reg |= l4off << URE_L4_OFFSET_SHIFT; 1156 } 1157 #ifdef INET6 1158 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1159 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1160 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1161 in6_undefer_cksum(m, l3off, flags); 1162 return 0; 1163 } 1164 reg |= URE_TXPKT_IPV6_CS; 1165 if (flags & M_CSUM_TCPv6) 1166 reg |= URE_TXPKT_TCP_CS; 1167 else 1168 reg |= URE_TXPKT_UDP_CS; 1169 reg |= l4off << URE_L4_OFFSET_SHIFT; 1170 } 1171 #endif 1172 else if (flags & M_CSUM_IPv4) 1173 reg |= URE_TXPKT_IPV4_CS; 1174 1175 return reg; 1176 } 1177 1178 #ifdef _MODULE 1179 #include "ioconf.c" 1180 #endif 1181 1182 USBNET_MODULE(ure) 1183