1 /* $NetBSD: if_run.c,v 1.21 2016/11/25 12:56:29 skrll Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.21 2016/11/25 12:56:29 skrll Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/firmload.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usbdi_util.h> 67 #include <dev/usb/usbdevs.h> 68 69 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 70 #include <dev/usb/if_runvar.h> 71 72 #ifdef RUN_DEBUG 73 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 75 int run_debug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 82 83 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 84 static const struct usb_devno run_devs[] = { 85 USB_ID(ABOCOM, RT2770), 86 USB_ID(ABOCOM, RT2870), 87 USB_ID(ABOCOM, RT3070), 88 USB_ID(ABOCOM, RT3071), 89 USB_ID(ABOCOM, RT3072), 90 USB_ID(ABOCOM2, RT2870_1), 91 USB_ID(ACCTON, RT2770), 92 USB_ID(ACCTON, RT2870_1), 93 USB_ID(ACCTON, RT2870_2), 94 USB_ID(ACCTON, RT2870_3), 95 USB_ID(ACCTON, RT2870_4), 96 USB_ID(ACCTON, RT2870_5), 97 USB_ID(ACCTON, RT3070), 98 USB_ID(ACCTON, RT3070_1), 99 USB_ID(ACCTON, RT3070_2), 100 USB_ID(ACCTON, RT3070_3), 101 USB_ID(ACCTON, RT3070_4), 102 USB_ID(ACCTON, RT3070_5), 103 USB_ID(ACCTON, RT3070_6), 104 USB_ID(AIRTIES, RT3070), 105 USB_ID(AIRTIES, RT3070_2), 106 USB_ID(ALLWIN, RT2070), 107 USB_ID(ALLWIN, RT2770), 108 USB_ID(ALLWIN, RT2870), 109 USB_ID(ALLWIN, RT3070), 110 USB_ID(ALLWIN, RT3071), 111 USB_ID(ALLWIN, RT3072), 112 USB_ID(ALLWIN, RT3572), 113 USB_ID(AMIGO, RT2870_1), 114 USB_ID(AMIGO, RT2870_2), 115 USB_ID(AMIT, CGWLUSB2GNR), 116 USB_ID(AMIT, RT2870_1), 117 USB_ID(AMIT2, RT2870), 118 USB_ID(ASUSTEK, RT2870_1), 119 USB_ID(ASUSTEK, RT2870_2), 120 USB_ID(ASUSTEK, RT2870_3), 121 USB_ID(ASUSTEK, RT2870_4), 122 USB_ID(ASUSTEK, RT2870_5), 123 USB_ID(ASUSTEK, RT3070), 124 USB_ID(ASUSTEK, RT3070_1), 125 USB_ID(ASUSTEK2, USBN11), 126 USB_ID(AZUREWAVE, RT2870_1), 127 USB_ID(AZUREWAVE, RT2870_2), 128 USB_ID(AZUREWAVE, RT3070), 129 USB_ID(AZUREWAVE, RT3070_2), 130 USB_ID(AZUREWAVE, RT3070_3), 131 USB_ID(AZUREWAVE, RT3070_4), 132 USB_ID(AZUREWAVE, RT3070_5), 133 USB_ID(BELKIN, F5D8053V3), 134 USB_ID(BELKIN, F5D8055), 135 USB_ID(BELKIN, F5D8055V2), 136 USB_ID(BELKIN, F6D4050V1), 137 USB_ID(BELKIN, F6D4050V2), 138 USB_ID(BELKIN, F7D1101V2), 139 USB_ID(BELKIN, RT2870_1), 140 USB_ID(BELKIN, RT2870_2), 141 USB_ID(BEWAN, RT3070), 142 USB_ID(CISCOLINKSYS, AE1000), 143 USB_ID(CISCOLINKSYS, AM10), 144 USB_ID(CISCOLINKSYS2, RT3070), 145 USB_ID(CISCOLINKSYS3, RT3070), 146 USB_ID(CONCEPTRONIC, RT2870_1), 147 USB_ID(CONCEPTRONIC, RT2870_2), 148 USB_ID(CONCEPTRONIC, RT2870_3), 149 USB_ID(CONCEPTRONIC, RT2870_4), 150 USB_ID(CONCEPTRONIC, RT2870_5), 151 USB_ID(CONCEPTRONIC, RT2870_6), 152 USB_ID(CONCEPTRONIC, RT2870_7), 153 USB_ID(CONCEPTRONIC, RT2870_8), 154 USB_ID(CONCEPTRONIC, RT3070_1), 155 USB_ID(CONCEPTRONIC, RT3070_2), 156 USB_ID(CONCEPTRONIC, RT3070_3), 157 USB_ID(COREGA, CGWLUSB300GNM), 158 USB_ID(COREGA, RT2870_1), 159 USB_ID(COREGA, RT2870_2), 160 USB_ID(COREGA, RT2870_3), 161 USB_ID(COREGA, RT3070), 162 USB_ID(CYBERTAN, RT2870), 163 USB_ID(DLINK, RT2870), 164 USB_ID(DLINK, RT3072), 165 USB_ID(DLINK2, DWA130), 166 USB_ID(DLINK2, RT2870_1), 167 USB_ID(DLINK2, RT2870_2), 168 USB_ID(DLINK2, RT3070_1), 169 USB_ID(DLINK2, RT3070_2), 170 USB_ID(DLINK2, RT3070_3), 171 USB_ID(DLINK2, RT3070_4), 172 USB_ID(DLINK2, RT3070_5), 173 USB_ID(DLINK2, RT3072), 174 USB_ID(DLINK2, RT3072_1), 175 USB_ID(DVICO, RT3070), 176 USB_ID(EDIMAX, EW7717), 177 USB_ID(EDIMAX, EW7718), 178 USB_ID(EDIMAX, EW7722UTN), 179 USB_ID(EDIMAX, RT2870_1), 180 USB_ID(ENCORE, RT3070), 181 USB_ID(ENCORE, RT3070_2), 182 USB_ID(ENCORE, RT3070_3), 183 USB_ID(GIGABYTE, GNWB31N), 184 USB_ID(GIGABYTE, GNWB32L), 185 USB_ID(GIGABYTE, RT2870_1), 186 USB_ID(GIGASET, RT3070_1), 187 USB_ID(GIGASET, RT3070_2), 188 USB_ID(GUILLEMOT, HWNU300), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(HAWKING, RT3070), 196 USB_ID(IODATA, RT3072_1), 197 USB_ID(IODATA, RT3072_2), 198 USB_ID(IODATA, RT3072_3), 199 USB_ID(IODATA, RT3072_4), 200 USB_ID(LINKSYS4, RT3070), 201 USB_ID(LINKSYS4, WUSB100), 202 USB_ID(LINKSYS4, WUSB54GC_3), 203 USB_ID(LINKSYS4, WUSB600N), 204 USB_ID(LINKSYS4, WUSB600NV2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, RT2870_1), 207 USB_ID(LOGITEC, RT2870_2), 208 USB_ID(LOGITEC, RT2870_3), 209 USB_ID(LOGITEC, RT3020), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2T), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, GWUS300MINIX), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT5572), 261 USB_ID(RALINK, RT8070), 262 USB_ID(SAMSUNG, RT2870_1), 263 USB_ID(SENAO, RT2870_1), 264 USB_ID(SENAO, RT2870_2), 265 USB_ID(SENAO, RT2870_3), 266 USB_ID(SENAO, RT2870_4), 267 USB_ID(SENAO, RT3070), 268 USB_ID(SENAO, RT3071), 269 USB_ID(SENAO, RT3072), 270 USB_ID(SENAO, RT3072_2), 271 USB_ID(SENAO, RT3072_3), 272 USB_ID(SENAO, RT3072_4), 273 USB_ID(SENAO, RT3072_5), 274 USB_ID(SITECOMEU, RT2870_1), 275 USB_ID(SITECOMEU, RT2870_2), 276 USB_ID(SITECOMEU, RT2870_3), 277 USB_ID(SITECOMEU, RT3070_1), 278 USB_ID(SITECOMEU, RT3072_3), 279 USB_ID(SITECOMEU, RT3072_4), 280 USB_ID(SITECOMEU, RT3072_5), 281 USB_ID(SITECOMEU, WL302), 282 USB_ID(SITECOMEU, WL315), 283 USB_ID(SITECOMEU, WL321), 284 USB_ID(SITECOMEU, WL324), 285 USB_ID(SITECOMEU, WL329), 286 USB_ID(SITECOMEU, WL343), 287 USB_ID(SITECOMEU, WL344), 288 USB_ID(SITECOMEU, WL345), 289 USB_ID(SITECOMEU, WL349V4), 290 USB_ID(SITECOMEU, WL608), 291 USB_ID(SITECOMEU, WLA4000), 292 USB_ID(SITECOMEU, WLA5000), 293 USB_ID(SPARKLAN, RT2870_1), 294 USB_ID(SPARKLAN, RT2870_2), 295 USB_ID(SPARKLAN, RT3070), 296 USB_ID(SWEEX2, LW153), 297 USB_ID(SWEEX2, LW303), 298 USB_ID(SWEEX2, LW313), 299 USB_ID(TOSHIBA, RT3070), 300 USB_ID(UMEDIA, RT2870_1), 301 USB_ID(UMEDIA, TEW645UB), 302 USB_ID(ZCOM, RT2870_1), 303 USB_ID(ZCOM, RT2870_2), 304 USB_ID(ZINWELL, RT2870_1), 305 USB_ID(ZINWELL, RT2870_2), 306 USB_ID(ZINWELL, RT3070), 307 USB_ID(ZINWELL, RT3072), 308 USB_ID(ZINWELL, RT3072_2), 309 USB_ID(ZYXEL, NWD2105), 310 USB_ID(ZYXEL, NWD211AN), 311 USB_ID(ZYXEL, RT2870_1), 312 USB_ID(ZYXEL, RT2870_2), 313 USB_ID(ZYXEL, RT3070), 314 }; 315 316 static int run_match(device_t, cfdata_t, void *); 317 static void run_attach(device_t, device_t, void *); 318 static int run_detach(device_t, int); 319 static int run_activate(device_t, enum devact); 320 321 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 322 run_match, run_attach, run_detach, run_activate); 323 324 static int run_alloc_rx_ring(struct run_softc *); 325 static void run_free_rx_ring(struct run_softc *); 326 static int run_alloc_tx_ring(struct run_softc *, int); 327 static void run_free_tx_ring(struct run_softc *, int); 328 static int run_load_microcode(struct run_softc *); 329 static int run_reset(struct run_softc *); 330 static int run_read(struct run_softc *, uint16_t, uint32_t *); 331 static int run_read_region_1(struct run_softc *, uint16_t, 332 uint8_t *, int); 333 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 334 static int run_write(struct run_softc *, uint16_t, uint32_t); 335 static int run_write_region_1(struct run_softc *, uint16_t, 336 const uint8_t *, int); 337 static int run_set_region_4(struct run_softc *, uint16_t, 338 uint32_t, int); 339 static int run_efuse_read(struct run_softc *, uint16_t, 340 uint16_t *, int); 341 static int run_efuse_read_2(struct run_softc *, uint16_t, 342 uint16_t *); 343 static int run_eeprom_read_2(struct run_softc *, uint16_t, 344 uint16_t *); 345 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 346 uint32_t); 347 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 348 uint8_t *); 349 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 350 uint8_t); 351 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 352 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 353 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 354 static const char * run_get_rf(int); 355 static void run_rt3593_get_txpower(struct run_softc *); 356 static void run_get_txpower(struct run_softc *); 357 static int run_read_eeprom(struct run_softc *); 358 static struct ieee80211_node * 359 run_node_alloc(struct ieee80211_node_table *); 360 static int run_media_change(struct ifnet *); 361 static void run_next_scan(void *); 362 static void run_task(void *); 363 static void run_do_async(struct run_softc *, 364 void (*)(struct run_softc *, void *), void *, int); 365 static int run_newstate(struct ieee80211com *, 366 enum ieee80211_state, int); 367 static void run_newstate_cb(struct run_softc *, void *); 368 static int run_updateedca(struct ieee80211com *); 369 static void run_updateedca_cb(struct run_softc *, void *); 370 #ifdef RUN_HWCRYPTO 371 static int run_set_key(struct ieee80211com *, 372 const struct ieee80211_key *, const uint8_t *); 373 static void run_set_key_cb(struct run_softc *, void *); 374 static int run_delete_key(struct ieee80211com *, 375 const struct ieee80211_key *); 376 static void run_delete_key_cb(struct run_softc *, void *); 377 #endif 378 static void run_calibrate_to(void *); 379 static void run_calibrate_cb(struct run_softc *, void *); 380 static void run_newassoc(struct ieee80211_node *, int); 381 static void run_rx_frame(struct run_softc *, uint8_t *, int); 382 static void run_rxeof(struct usbd_xfer *, void *, 383 usbd_status); 384 static void run_txeof(struct usbd_xfer *, void *, 385 usbd_status); 386 static int run_tx(struct run_softc *, struct mbuf *, 387 struct ieee80211_node *); 388 static void run_start(struct ifnet *); 389 static void run_watchdog(struct ifnet *); 390 static int run_ioctl(struct ifnet *, u_long, void *); 391 static void run_select_chan_group(struct run_softc *, int); 392 static void run_iq_calib(struct run_softc *, u_int); 393 static void run_set_agc(struct run_softc *, uint8_t); 394 static void run_set_rx_antenna(struct run_softc *, int); 395 static void run_rt2870_set_chan(struct run_softc *, u_int); 396 static void run_rt3070_set_chan(struct run_softc *, u_int); 397 static void run_rt3572_set_chan(struct run_softc *, u_int); 398 static void run_rt3593_set_chan(struct run_softc *, u_int); 399 static void run_rt5390_set_chan(struct run_softc *, u_int); 400 static void run_rt5592_set_chan(struct run_softc *, u_int); 401 static int run_set_chan(struct run_softc *, 402 struct ieee80211_channel *); 403 static void run_updateprot(struct run_softc *); 404 static void run_enable_tsf_sync(struct run_softc *); 405 static void run_enable_mrr(struct run_softc *); 406 static void run_set_txpreamble(struct run_softc *); 407 static void run_set_basicrates(struct run_softc *); 408 static void run_set_leds(struct run_softc *, uint16_t); 409 static void run_set_bssid(struct run_softc *, const uint8_t *); 410 static void run_set_macaddr(struct run_softc *, const uint8_t *); 411 static void run_updateslot(struct ifnet *); 412 static void run_updateslot_cb(struct run_softc *, void *); 413 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 414 static void run_rt5390_bbp_init(struct run_softc *); 415 static int run_bbp_init(struct run_softc *); 416 static int run_rt3070_rf_init(struct run_softc *); 417 static int run_rt3593_rf_init(struct run_softc *); 418 static int run_rt5390_rf_init(struct run_softc *); 419 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 420 uint8_t, uint8_t *); 421 static void run_rt3070_rf_setup(struct run_softc *); 422 static void run_rt3593_rf_setup(struct run_softc *); 423 static void run_rt5390_rf_setup(struct run_softc *); 424 static int run_txrx_enable(struct run_softc *); 425 static int run_adjust_freq_offset(struct run_softc *); 426 static int run_init(struct ifnet *); 427 static void run_stop(struct ifnet *, int); 428 #ifndef IEEE80211_STA_ONLY 429 static int run_setup_beacon(struct run_softc *); 430 #endif 431 432 static const struct { 433 uint32_t reg; 434 uint32_t val; 435 } rt2870_def_mac[] = { 436 RT2870_DEF_MAC 437 }; 438 439 static const struct { 440 uint8_t reg; 441 uint8_t val; 442 } rt2860_def_bbp[] = { 443 RT2860_DEF_BBP 444 }, rt5390_def_bbp[] = { 445 RT5390_DEF_BBP 446 }, rt5592_def_bbp[] = { 447 RT5592_DEF_BBP 448 }; 449 450 /* 451 * Default values for BBP register R196 for RT5592. 452 */ 453 static const uint8_t rt5592_bbp_r196[] = { 454 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 455 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 456 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 457 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 458 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 459 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 460 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 461 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 462 0x2e, 0x36, 0x30, 0x6e 463 }; 464 465 static const struct rfprog { 466 uint8_t chan; 467 uint32_t r1, r2, r3, r4; 468 } rt2860_rf2850[] = { 469 RT2860_RF2850 470 }; 471 472 static const struct { 473 uint8_t n, r, k; 474 } rt3070_freqs[] = { 475 RT3070_RF3052 476 }; 477 478 static const struct rt5592_freqs { 479 uint16_t n; 480 uint8_t k, m, r; 481 } rt5592_freqs_20mhz[] = { 482 RT5592_RF5592_20MHZ 483 },rt5592_freqs_40mhz[] = { 484 RT5592_RF5592_40MHZ 485 }; 486 487 static const struct { 488 uint8_t reg; 489 uint8_t val; 490 } rt3070_def_rf[] = { 491 RT3070_DEF_RF 492 }, rt3572_def_rf[] = { 493 RT3572_DEF_RF 494 },rt3593_def_rf[] = { 495 RT3593_DEF_RF 496 },rt5390_def_rf[] = { 497 RT5390_DEF_RF 498 },rt5392_def_rf[] = { 499 RT5392_DEF_RF 500 },rt5592_def_rf[] = { 501 RT5592_DEF_RF 502 },rt5592_2ghz_def_rf[] = { 503 RT5592_2GHZ_DEF_RF 504 },rt5592_5ghz_def_rf[] = { 505 RT5592_5GHZ_DEF_RF 506 }; 507 508 static const struct { 509 u_int firstchan; 510 u_int lastchan; 511 uint8_t reg; 512 uint8_t val; 513 } rt5592_chan_5ghz[] = { 514 RT5592_CHAN_5GHZ 515 }; 516 517 static int 518 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 519 size_t *sizep) 520 { 521 firmware_handle_t fh; 522 int error; 523 524 if ((error = firmware_open(dname, iname, &fh)) != 0) 525 return error; 526 *sizep = firmware_get_size(fh); 527 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 528 firmware_close(fh); 529 return ENOMEM; 530 } 531 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 532 firmware_free(*ucodep, *sizep); 533 firmware_close(fh); 534 535 return error; 536 } 537 538 static int 539 run_match(device_t parent, cfdata_t match, void *aux) 540 { 541 struct usb_attach_arg *uaa = aux; 542 543 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 544 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 545 } 546 547 static void 548 run_attach(device_t parent, device_t self, void *aux) 549 { 550 struct run_softc *sc = device_private(self); 551 struct usb_attach_arg *uaa = aux; 552 struct ieee80211com *ic = &sc->sc_ic; 553 struct ifnet *ifp = &sc->sc_if; 554 usb_interface_descriptor_t *id; 555 usb_endpoint_descriptor_t *ed; 556 char *devinfop; 557 int i, nrx, ntx, ntries, error; 558 uint32_t ver; 559 560 aprint_naive("\n"); 561 aprint_normal("\n"); 562 563 sc->sc_dev = self; 564 sc->sc_udev = uaa->uaa_device; 565 566 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 567 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 568 usbd_devinfo_free(devinfop); 569 570 error = usbd_set_config_no(sc->sc_udev, 1, 0); 571 if (error != 0) { 572 aprint_error_dev(sc->sc_dev, "failed to set configuration" 573 ", err=%s\n", usbd_errstr(error)); 574 return; 575 } 576 577 /* get the first interface handle */ 578 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 579 if (error != 0) { 580 aprint_error_dev(sc->sc_dev, 581 "could not get interface handle\n"); 582 return; 583 } 584 585 /* 586 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 587 * and 6 for TX (4 EDCAs + HCCA + Prio). 588 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 589 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 590 */ 591 nrx = ntx = 0; 592 id = usbd_get_interface_descriptor(sc->sc_iface); 593 for (i = 0; i < id->bNumEndpoints; i++) { 594 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 595 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 596 continue; 597 598 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 599 sc->rxq.pipe_no = ed->bEndpointAddress; 600 nrx++; 601 } else if (ntx < 4) { 602 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 603 ntx++; 604 } 605 } 606 /* make sure we've got them all */ 607 if (nrx < 1 || ntx < 4) { 608 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 609 return; 610 } 611 612 usb_init_task(&sc->sc_task, run_task, sc, 0); 613 callout_init(&sc->scan_to, 0); 614 callout_setfunc(&sc->scan_to, run_next_scan, sc); 615 callout_init(&sc->calib_to, 0); 616 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 617 618 sc->amrr.amrr_min_success_threshold = 1; 619 sc->amrr.amrr_max_success_threshold = 10; 620 621 /* wait for the chip to settle */ 622 for (ntries = 0; ntries < 100; ntries++) { 623 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 624 return; 625 if (ver != 0 && ver != 0xffffffff) 626 break; 627 DELAY(10); 628 } 629 if (ntries == 100) { 630 aprint_error_dev(sc->sc_dev, 631 "timeout waiting for NIC to initialize\n"); 632 return; 633 } 634 sc->mac_ver = ver >> 16; 635 sc->mac_rev = ver & 0xffff; 636 637 /* retrieve RF rev. no and various other things from EEPROM */ 638 run_read_eeprom(sc); 639 640 aprint_error_dev(sc->sc_dev, 641 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 642 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 643 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 644 645 ic->ic_ifp = ifp; 646 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 647 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 648 ic->ic_state = IEEE80211_S_INIT; 649 650 /* set device capabilities */ 651 ic->ic_caps = 652 IEEE80211_C_MONITOR | /* monitor mode supported */ 653 #ifndef IEEE80211_STA_ONLY 654 IEEE80211_C_IBSS | /* IBSS mode supported */ 655 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 656 #endif 657 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 658 IEEE80211_C_SHSLOT | /* short slot time supported */ 659 #ifdef RUN_HWCRYPTO 660 IEEE80211_C_WEP | /* WEP */ 661 IEEE80211_C_TKIP | /* TKIP */ 662 IEEE80211_C_AES_CCM | /* AES CCMP */ 663 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 664 #endif 665 IEEE80211_C_WME | /* WME */ 666 IEEE80211_C_WPA; /* WPA/RSN */ 667 668 if (sc->rf_rev == RT2860_RF_2750 || 669 sc->rf_rev == RT2860_RF_2850 || 670 sc->rf_rev == RT3070_RF_3052 || 671 sc->rf_rev == RT3070_RF_3053 || 672 sc->rf_rev == RT5592_RF_5592) { 673 /* set supported .11a rates */ 674 ic->ic_sup_rates[IEEE80211_MODE_11A] = 675 ieee80211_std_rateset_11a; 676 677 /* set supported .11a channels */ 678 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 679 uint8_t chan = rt2860_rf2850[i].chan; 680 ic->ic_channels[chan].ic_freq = 681 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 682 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 683 } 684 } 685 686 /* set supported .11b and .11g rates */ 687 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 688 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 689 690 /* set supported .11b and .11g channels (1 through 14) */ 691 for (i = 1; i <= 14; i++) { 692 ic->ic_channels[i].ic_freq = 693 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 694 ic->ic_channels[i].ic_flags = 695 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 696 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 697 } 698 699 ifp->if_softc = sc; 700 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 701 ifp->if_init = run_init; 702 ifp->if_ioctl = run_ioctl; 703 ifp->if_start = run_start; 704 ifp->if_watchdog = run_watchdog; 705 IFQ_SET_READY(&ifp->if_snd); 706 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 707 708 if_attach(ifp); 709 ieee80211_ifattach(ic); 710 ic->ic_node_alloc = run_node_alloc; 711 ic->ic_newassoc = run_newassoc; 712 ic->ic_updateslot = run_updateslot; 713 ic->ic_wme.wme_update = run_updateedca; 714 #ifdef RUN_HWCRYPTO 715 ic->ic_crypto.cs_key_set = run_set_key; 716 ic->ic_crypto.cs_key_delete = run_delete_key; 717 #endif 718 /* override state transition machine */ 719 sc->sc_newstate = ic->ic_newstate; 720 ic->ic_newstate = run_newstate; 721 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 722 723 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 724 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 725 &sc->sc_drvbpf); 726 727 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 728 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 729 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 730 731 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 732 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 733 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 734 735 ieee80211_announce(ic); 736 737 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 738 739 if (!pmf_device_register(self, NULL, NULL)) 740 aprint_error_dev(self, "couldn't establish power handler\n"); 741 } 742 743 static int 744 run_detach(device_t self, int flags) 745 { 746 struct run_softc *sc = device_private(self); 747 struct ifnet *ifp = &sc->sc_if; 748 struct ieee80211com *ic = &sc->sc_ic; 749 int s; 750 751 if (ifp->if_softc == NULL) 752 return 0; 753 754 pmf_device_deregister(self); 755 756 s = splusb(); 757 758 sc->sc_flags |= RUN_DETACHING; 759 760 if (ifp->if_flags & IFF_RUNNING) { 761 usb_rem_task(sc->sc_udev, &sc->sc_task); 762 run_stop(ifp, 0); 763 } 764 765 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 766 bpf_detach(ifp); 767 ieee80211_ifdetach(ic); 768 if_detach(ifp); 769 770 splx(s); 771 772 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 773 774 callout_stop(&sc->scan_to); 775 callout_stop(&sc->calib_to); 776 777 callout_destroy(&sc->scan_to); 778 callout_destroy(&sc->calib_to); 779 780 return 0; 781 } 782 783 static int 784 run_activate(device_t self, enum devact act) 785 { 786 struct run_softc *sc = device_private(self); 787 788 switch (act) { 789 case DVACT_DEACTIVATE: 790 if_deactivate(sc->sc_ic.ic_ifp); 791 return 0; 792 default: 793 return EOPNOTSUPP; 794 } 795 } 796 797 static int 798 run_alloc_rx_ring(struct run_softc *sc) 799 { 800 struct run_rx_ring *rxq = &sc->rxq; 801 int i, error; 802 803 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 804 if (error != 0) 805 goto fail; 806 807 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 808 struct run_rx_data *data = &rxq->data[i]; 809 810 data->sc = sc; /* backpointer for callbacks */ 811 812 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 813 USBD_SHORT_XFER_OK, 0, &data->xfer); 814 if (error) 815 goto fail; 816 817 data->buf = usbd_get_buffer(data->xfer); 818 } 819 if (error != 0) 820 fail: run_free_rx_ring(sc); 821 return error; 822 } 823 824 static void 825 run_free_rx_ring(struct run_softc *sc) 826 { 827 struct run_rx_ring *rxq = &sc->rxq; 828 int i; 829 830 if (rxq->pipeh != NULL) { 831 usbd_abort_pipe(rxq->pipeh); 832 } 833 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 834 if (rxq->data[i].xfer != NULL) 835 usbd_destroy_xfer(rxq->data[i].xfer); 836 rxq->data[i].xfer = NULL; 837 } 838 if (rxq->pipeh != NULL) { 839 usbd_close_pipe(rxq->pipeh); 840 rxq->pipeh = NULL; 841 } 842 } 843 844 static int 845 run_alloc_tx_ring(struct run_softc *sc, int qid) 846 { 847 struct run_tx_ring *txq = &sc->txq[qid]; 848 int i, error; 849 850 txq->cur = txq->queued = 0; 851 852 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 853 if (error != 0) 854 goto fail; 855 856 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 857 struct run_tx_data *data = &txq->data[i]; 858 859 data->sc = sc; /* backpointer for callbacks */ 860 data->qid = qid; 861 862 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 863 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 864 if (error) 865 goto fail; 866 867 data->buf = usbd_get_buffer(data->xfer); 868 /* zeroize the TXD + TXWI part */ 869 memset(data->buf, 0, sizeof(struct rt2870_txd) + 870 sizeof(struct rt2860_txwi)); 871 } 872 if (error != 0) 873 fail: run_free_tx_ring(sc, qid); 874 return error; 875 } 876 877 static void 878 run_free_tx_ring(struct run_softc *sc, int qid) 879 { 880 struct run_tx_ring *txq = &sc->txq[qid]; 881 int i; 882 883 if (txq->pipeh != NULL) { 884 usbd_abort_pipe(txq->pipeh); 885 usbd_close_pipe(txq->pipeh); 886 txq->pipeh = NULL; 887 } 888 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 889 if (txq->data[i].xfer != NULL) 890 usbd_destroy_xfer(txq->data[i].xfer); 891 txq->data[i].xfer = NULL; 892 } 893 } 894 895 static int 896 run_load_microcode(struct run_softc *sc) 897 { 898 usb_device_request_t req; 899 const char *fwname; 900 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 901 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 902 uint32_t tmp; 903 int ntries, error; 904 905 /* RT3071/RT3072 use a different firmware */ 906 if (sc->mac_ver != 0x2860 && 907 sc->mac_ver != 0x2872 && 908 sc->mac_ver != 0x3070) 909 fwname = "run-rt3071"; 910 else 911 fwname = "run-rt2870"; 912 913 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 914 aprint_error_dev(sc->sc_dev, 915 "error %d, could not read firmware %s\n", error, fwname); 916 return error; 917 } 918 if (size != 4096) { 919 aprint_error_dev(sc->sc_dev, 920 "invalid firmware size (should be 4KB)\n"); 921 firmware_free(ucode, size); 922 return EINVAL; 923 } 924 925 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 926 /* write microcode image */ 927 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 928 firmware_free(ucode, size); 929 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 930 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 931 932 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 933 req.bRequest = RT2870_RESET; 934 USETW(req.wValue, 8); 935 USETW(req.wIndex, 0); 936 USETW(req.wLength, 0); 937 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 938 return error; 939 940 usbd_delay_ms(sc->sc_udev, 10); 941 run_write(sc, RT2860_H2M_MAILBOX, 0); 942 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 943 return error; 944 945 /* wait until microcontroller is ready */ 946 for (ntries = 0; ntries < 1000; ntries++) { 947 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 948 return error; 949 if (tmp & RT2860_MCU_READY) 950 break; 951 usbd_delay_ms(sc->sc_udev, 10); 952 } 953 if (ntries == 1000) { 954 aprint_error_dev(sc->sc_dev, 955 "timeout waiting for MCU to initialize\n"); 956 return ETIMEDOUT; 957 } 958 959 sc->sc_flags |= RUN_FWLOADED; 960 961 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 962 return 0; 963 } 964 965 static int 966 run_reset(struct run_softc *sc) 967 { 968 usb_device_request_t req; 969 970 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 971 req.bRequest = RT2870_RESET; 972 USETW(req.wValue, 1); 973 USETW(req.wIndex, 0); 974 USETW(req.wLength, 0); 975 return usbd_do_request(sc->sc_udev, &req, NULL); 976 } 977 978 static int 979 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 980 { 981 uint32_t tmp; 982 int error; 983 984 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 985 if (error == 0) 986 *val = le32toh(tmp); 987 else 988 *val = 0xffffffff; 989 return error; 990 } 991 992 static int 993 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 994 { 995 usb_device_request_t req; 996 997 req.bmRequestType = UT_READ_VENDOR_DEVICE; 998 req.bRequest = RT2870_READ_REGION_1; 999 USETW(req.wValue, 0); 1000 USETW(req.wIndex, reg); 1001 USETW(req.wLength, len); 1002 return usbd_do_request(sc->sc_udev, &req, buf); 1003 } 1004 1005 static int 1006 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1007 { 1008 usb_device_request_t req; 1009 1010 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1011 req.bRequest = RT2870_WRITE_2; 1012 USETW(req.wValue, val); 1013 USETW(req.wIndex, reg); 1014 USETW(req.wLength, 0); 1015 return usbd_do_request(sc->sc_udev, &req, NULL); 1016 } 1017 1018 static int 1019 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1020 { 1021 int error; 1022 1023 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1024 error = run_write_2(sc, reg + 2, val >> 16); 1025 return error; 1026 } 1027 1028 static int 1029 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1030 int len) 1031 { 1032 #if 1 1033 int i, error = 0; 1034 /* 1035 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1036 * We thus issue multiple WRITE_2 commands instead. 1037 */ 1038 KASSERT((len & 1) == 0); 1039 for (i = 0; i < len && error == 0; i += 2) 1040 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1041 return error; 1042 #else 1043 usb_device_request_t req; 1044 1045 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1046 req.bRequest = RT2870_WRITE_REGION_1; 1047 USETW(req.wValue, 0); 1048 USETW(req.wIndex, reg); 1049 USETW(req.wLength, len); 1050 return usbd_do_request(sc->sc_udev, &req, buf); 1051 #endif 1052 } 1053 1054 static int 1055 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1056 { 1057 int error = 0; 1058 1059 for (; count > 0 && error == 0; count--, reg += 4) 1060 error = run_write(sc, reg, val); 1061 return error; 1062 } 1063 1064 static int 1065 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1066 { 1067 uint32_t tmp; 1068 uint16_t reg; 1069 int error, ntries; 1070 1071 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1072 return error; 1073 1074 if (count == 2) 1075 addr *= 2; 1076 /*- 1077 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1078 * DATA0: F E D C 1079 * DATA1: B A 9 8 1080 * DATA2: 7 6 5 4 1081 * DATA3: 3 2 1 0 1082 */ 1083 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1084 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1085 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1086 for (ntries = 0; ntries < 100; ntries++) { 1087 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1088 return error; 1089 if (!(tmp & RT3070_EFSROM_KICK)) 1090 break; 1091 usbd_delay_ms(sc->sc_udev, 2); 1092 } 1093 if (ntries == 100) 1094 return ETIMEDOUT; 1095 1096 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1097 *val = 0xffff; /* address not found */ 1098 return 0; 1099 } 1100 /* determine to which 32-bit register our 16-bit word belongs */ 1101 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1102 if ((error = run_read(sc, reg, &tmp)) != 0) 1103 return error; 1104 1105 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1106 return 0; 1107 } 1108 1109 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1110 static int 1111 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1112 { 1113 return (run_efuse_read(sc, addr, val, 2)); 1114 } 1115 1116 static int 1117 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1118 { 1119 usb_device_request_t req; 1120 uint16_t tmp; 1121 int error; 1122 1123 addr *= 2; 1124 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1125 req.bRequest = RT2870_EEPROM_READ; 1126 USETW(req.wValue, 0); 1127 USETW(req.wIndex, addr); 1128 USETW(req.wLength, sizeof(tmp)); 1129 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1130 if (error == 0) 1131 *val = le16toh(tmp); 1132 else 1133 *val = 0xffff; 1134 return error; 1135 } 1136 1137 static __inline int 1138 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1139 { 1140 1141 /* either eFUSE ROM or EEPROM */ 1142 return sc->sc_srom_read(sc, addr, val); 1143 } 1144 1145 static int 1146 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1147 { 1148 uint32_t tmp; 1149 int error, ntries; 1150 1151 for (ntries = 0; ntries < 10; ntries++) { 1152 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1153 return error; 1154 if (!(tmp & RT2860_RF_REG_CTRL)) 1155 break; 1156 } 1157 if (ntries == 10) 1158 return ETIMEDOUT; 1159 1160 /* RF registers are 24-bit on the RT2860 */ 1161 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1162 (val & 0x3fffff) << 2 | (reg & 3); 1163 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1164 } 1165 1166 static int 1167 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1168 { 1169 uint32_t tmp; 1170 int error, ntries; 1171 1172 for (ntries = 0; ntries < 100; ntries++) { 1173 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1174 return error; 1175 if (!(tmp & RT3070_RF_KICK)) 1176 break; 1177 } 1178 if (ntries == 100) 1179 return ETIMEDOUT; 1180 1181 tmp = RT3070_RF_KICK | reg << 8; 1182 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1183 return error; 1184 1185 for (ntries = 0; ntries < 100; ntries++) { 1186 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1187 return error; 1188 if (!(tmp & RT3070_RF_KICK)) 1189 break; 1190 } 1191 if (ntries == 100) 1192 return ETIMEDOUT; 1193 1194 *val = tmp & 0xff; 1195 return 0; 1196 } 1197 1198 static int 1199 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1200 { 1201 uint32_t tmp; 1202 int error, ntries; 1203 1204 for (ntries = 0; ntries < 10; ntries++) { 1205 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1206 return error; 1207 if (!(tmp & RT3070_RF_KICK)) 1208 break; 1209 } 1210 if (ntries == 10) 1211 return ETIMEDOUT; 1212 1213 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1214 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1215 } 1216 1217 static int 1218 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1219 { 1220 uint32_t tmp; 1221 int ntries, error; 1222 1223 for (ntries = 0; ntries < 10; ntries++) { 1224 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1225 return error; 1226 if (!(tmp & RT2860_BBP_CSR_KICK)) 1227 break; 1228 } 1229 if (ntries == 10) 1230 return ETIMEDOUT; 1231 1232 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1233 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1234 return error; 1235 1236 for (ntries = 0; ntries < 10; ntries++) { 1237 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1238 return error; 1239 if (!(tmp & RT2860_BBP_CSR_KICK)) 1240 break; 1241 } 1242 if (ntries == 10) 1243 return ETIMEDOUT; 1244 1245 *val = tmp & 0xff; 1246 return 0; 1247 } 1248 1249 static int 1250 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1251 { 1252 uint32_t tmp; 1253 int ntries, error; 1254 1255 for (ntries = 0; ntries < 10; ntries++) { 1256 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1257 return error; 1258 if (!(tmp & RT2860_BBP_CSR_KICK)) 1259 break; 1260 } 1261 if (ntries == 10) 1262 return ETIMEDOUT; 1263 1264 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1265 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1266 } 1267 1268 /* 1269 * Send a command to the 8051 microcontroller unit. 1270 */ 1271 static int 1272 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1273 { 1274 uint32_t tmp; 1275 int error, ntries; 1276 1277 for (ntries = 0; ntries < 100; ntries++) { 1278 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1279 return error; 1280 if (!(tmp & RT2860_H2M_BUSY)) 1281 break; 1282 } 1283 if (ntries == 100) 1284 return ETIMEDOUT; 1285 1286 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1287 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1288 error = run_write(sc, RT2860_HOST_CMD, cmd); 1289 return error; 1290 } 1291 1292 /* 1293 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1294 * Used to adjust per-rate Tx power registers. 1295 */ 1296 static __inline uint32_t 1297 b4inc(uint32_t b32, int8_t delta) 1298 { 1299 int8_t i, b4; 1300 1301 for (i = 0; i < 8; i++) { 1302 b4 = b32 & 0xf; 1303 b4 += delta; 1304 if (b4 < 0) 1305 b4 = 0; 1306 else if (b4 > 0xf) 1307 b4 = 0xf; 1308 b32 = b32 >> 4 | b4 << 28; 1309 } 1310 return b32; 1311 } 1312 1313 static const char * 1314 run_get_rf(int rev) 1315 { 1316 switch (rev) { 1317 case RT2860_RF_2820: return "RT2820"; 1318 case RT2860_RF_2850: return "RT2850"; 1319 case RT2860_RF_2720: return "RT2720"; 1320 case RT2860_RF_2750: return "RT2750"; 1321 case RT3070_RF_3020: return "RT3020"; 1322 case RT3070_RF_2020: return "RT2020"; 1323 case RT3070_RF_3021: return "RT3021"; 1324 case RT3070_RF_3022: return "RT3022"; 1325 case RT3070_RF_3052: return "RT3052"; 1326 case RT3070_RF_3053: return "RT3053"; 1327 case RT5592_RF_5592: return "RT5592"; 1328 case RT5390_RF_5370: return "RT5370"; 1329 case RT5390_RF_5372: return "RT5372"; 1330 } 1331 return "unknown"; 1332 } 1333 1334 static void 1335 run_rt3593_get_txpower(struct run_softc *sc) 1336 { 1337 uint16_t addr, val; 1338 int i; 1339 1340 /* Read power settings for 2GHz channels. */ 1341 for (i = 0; i < 14; i += 2) { 1342 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1343 RT2860_EEPROM_PWR2GHZ_BASE1; 1344 run_srom_read(sc, addr + i / 2, &val); 1345 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1346 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1347 1348 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1349 RT2860_EEPROM_PWR2GHZ_BASE2; 1350 run_srom_read(sc, addr + i / 2, &val); 1351 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1352 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1353 1354 if (sc->ntxchains == 3) { 1355 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1356 &val); 1357 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1358 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1359 } 1360 } 1361 /* Fix broken Tx power entries. */ 1362 for (i = 0; i < 14; i++) { 1363 if (sc->txpow1[i] > 31) 1364 sc->txpow1[i] = 5; 1365 if (sc->txpow2[i] > 31) 1366 sc->txpow2[i] = 5; 1367 if (sc->ntxchains == 3) { 1368 if (sc->txpow3[i] > 31) 1369 sc->txpow3[i] = 5; 1370 } 1371 } 1372 /* Read power settings for 5GHz channels. */ 1373 for (i = 0; i < 40; i += 2) { 1374 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1375 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1376 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1377 1378 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1379 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1380 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1381 1382 if (sc->ntxchains == 3) { 1383 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1384 &val); 1385 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1386 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1387 } 1388 } 1389 } 1390 1391 static void 1392 run_get_txpower(struct run_softc *sc) 1393 { 1394 uint16_t val; 1395 int i; 1396 1397 /* Read power settings for 2GHz channels. */ 1398 for (i = 0; i < 14; i += 2) { 1399 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1400 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1401 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1402 1403 if (sc->mac_ver != 0x5390) { 1404 run_srom_read(sc, 1405 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1406 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1407 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1408 } 1409 } 1410 /* Fix broken Tx power entries. */ 1411 for (i = 0; i < 14; i++) { 1412 if (sc->mac_ver >= 0x5390) { 1413 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1414 sc->txpow1[i] = 5; 1415 } else { 1416 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1417 sc->txpow1[i] = 5; 1418 } 1419 if (sc->mac_ver > 0x5390) { 1420 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1421 sc->txpow2[i] = 5; 1422 } else if (sc->mac_ver < 0x5390) { 1423 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1424 sc->txpow2[i] = 5; 1425 } 1426 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1427 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1428 } 1429 /* Read power settings for 5GHz channels. */ 1430 for (i = 0; i < 40; i += 2) { 1431 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1432 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1433 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1434 1435 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1436 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1437 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1438 } 1439 /* Fix broken Tx power entries. */ 1440 for (i = 0; i < 40; i++ ) { 1441 if (sc->mac_ver != 0x5592) { 1442 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1443 sc->txpow1[14 + i] = 5; 1444 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1445 sc->txpow2[14 + i] = 5; 1446 } 1447 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1448 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1449 sc->txpow2[14 + i])); 1450 } 1451 } 1452 1453 static int 1454 run_read_eeprom(struct run_softc *sc) 1455 { 1456 struct ieee80211com *ic = &sc->sc_ic; 1457 int8_t delta_2ghz, delta_5ghz; 1458 uint32_t tmp; 1459 uint16_t val; 1460 int ridx, ant, i; 1461 1462 /* check whether the ROM is eFUSE ROM or EEPROM */ 1463 sc->sc_srom_read = run_eeprom_read_2; 1464 if (sc->mac_ver >= 0x3070) { 1465 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1466 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1467 if (tmp & RT3070_SEL_EFUSE) 1468 sc->sc_srom_read = run_efuse_read_2; 1469 } 1470 1471 /* read ROM version */ 1472 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1473 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1474 1475 /* read MAC address */ 1476 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1477 ic->ic_myaddr[0] = val & 0xff; 1478 ic->ic_myaddr[1] = val >> 8; 1479 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1480 ic->ic_myaddr[2] = val & 0xff; 1481 ic->ic_myaddr[3] = val >> 8; 1482 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1483 ic->ic_myaddr[4] = val & 0xff; 1484 ic->ic_myaddr[5] = val >> 8; 1485 1486 /* read vendor BBP settings */ 1487 for (i = 0; i < 10; i++) { 1488 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1489 sc->bbp[i].val = val & 0xff; 1490 sc->bbp[i].reg = val >> 8; 1491 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 1492 } 1493 1494 /* read vendor RF settings */ 1495 for (i = 0; i < 8; i++) { 1496 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val); 1497 sc->rf[i].val = val & 0xff; 1498 sc->rf[i].reg = val >> 8; 1499 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1500 sc->rf[i].val)); 1501 } 1502 1503 /* read RF frequency offset from EEPROM */ 1504 run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); 1505 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1506 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1507 1508 if ((val >> 8) != 0xff) { 1509 /* read LEDs operating mode */ 1510 sc->leds = val >> 8; 1511 run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); 1512 run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); 1513 run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); 1514 } else { 1515 /* broken EEPROM, use default settings */ 1516 sc->leds = 0x01; 1517 sc->led[0] = 0x5555; 1518 sc->led[1] = 0x2221; 1519 sc->led[2] = 0x5627; /* differs from RT2860 */ 1520 } 1521 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1522 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1523 1524 /* read RF information */ 1525 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1526 if (val == 0xffff) { 1527 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1528 if (sc->mac_ver == 0x3572) { 1529 /* default to RF3052 2T2R */ 1530 sc->rf_rev = RT3070_RF_3052; 1531 sc->ntxchains = 2; 1532 sc->nrxchains = 2; 1533 } else if (sc->mac_ver >= 0x3070) { 1534 /* default to RF3020 1T1R */ 1535 sc->rf_rev = RT3070_RF_3020; 1536 sc->ntxchains = 1; 1537 sc->nrxchains = 1; 1538 } else { 1539 /* default to RF2820 1T2R */ 1540 sc->rf_rev = RT2860_RF_2820; 1541 sc->ntxchains = 1; 1542 sc->nrxchains = 2; 1543 } 1544 } else { 1545 sc->rf_rev = (val >> 8) & 0xf; 1546 sc->ntxchains = (val >> 4) & 0xf; 1547 sc->nrxchains = val & 0xf; 1548 } 1549 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1550 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1551 1552 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1553 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1554 /* check if driver should patch the DAC issue */ 1555 if ((val >> 8) != 0xff) 1556 sc->patch_dac = (val >> 15) & 1; 1557 if ((val & 0xff) != 0xff) { 1558 sc->ext_5ghz_lna = (val >> 3) & 1; 1559 sc->ext_2ghz_lna = (val >> 2) & 1; 1560 /* check if RF supports automatic Tx access gain control */ 1561 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1562 /* check if we have a hardware radio switch */ 1563 sc->rfswitch = val & 1; 1564 } 1565 1566 /* Read Tx power settings. */ 1567 if (sc->mac_ver == 0x3593) 1568 run_rt3593_get_txpower(sc); 1569 else 1570 run_get_txpower(sc); 1571 1572 /* read Tx power compensation for each Tx rate */ 1573 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1574 delta_2ghz = delta_5ghz = 0; 1575 if ((val & 0xff) != 0xff && (val & 0x80)) { 1576 delta_2ghz = val & 0xf; 1577 if (!(val & 0x40)) /* negative number */ 1578 delta_2ghz = -delta_2ghz; 1579 } 1580 val >>= 8; 1581 if ((val & 0xff) != 0xff && (val & 0x80)) { 1582 delta_5ghz = val & 0xf; 1583 if (!(val & 0x40)) /* negative number */ 1584 delta_5ghz = -delta_5ghz; 1585 } 1586 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1587 delta_2ghz, delta_5ghz)); 1588 1589 for (ridx = 0; ridx < 5; ridx++) { 1590 uint32_t reg; 1591 1592 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1593 reg = val; 1594 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1595 reg |= (uint32_t)val << 16; 1596 1597 sc->txpow20mhz[ridx] = reg; 1598 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1599 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1600 1601 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1602 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1603 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1604 } 1605 1606 /* read RSSI offsets and LNA gains from EEPROM */ 1607 run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); 1608 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1609 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1610 run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); 1611 if (sc->mac_ver >= 0x3070) { 1612 if (sc->mac_ver == 0x3593) { 1613 sc->txmixgain_2ghz = 0; 1614 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1615 } else { 1616 /* 1617 * On RT3070 chips (limited to 2 Rx chains), this ROM 1618 * field contains the Tx mixer gain for the 2GHz band. 1619 */ 1620 if ((val & 0xff) != 0xff) 1621 sc->txmixgain_2ghz = val & 0x7; 1622 } 1623 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1624 } else { 1625 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1626 } 1627 if (sc->mac_ver == 0x3593) 1628 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1629 sc->lna[2] = val >> 8; /* channel group 2 */ 1630 1631 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1632 RT3593_EEPROM_RSSI2_5GHZ, &val); 1633 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1634 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1635 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1636 RT3593_EEPROM_RSSI2_5GHZ, &val); 1637 if (sc->mac_ver == 0x3572) { 1638 /* 1639 * On RT3572 chips (limited to 2 Rx chains), this ROM 1640 * field contains the Tx mixer gain for the 5GHz band. 1641 */ 1642 if ((val & 0xff) != 0xff) 1643 sc->txmixgain_5ghz = val & 0x7; 1644 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1645 } else { 1646 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1647 } 1648 if (sc->mac_ver == 0x3593) { 1649 sc->txmixgain_5ghz = 0; 1650 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1651 } 1652 sc->lna[3] = val >> 8; /* channel group 3 */ 1653 1654 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1655 RT3593_EEPROM_LNA, &val); 1656 sc->lna[0] = val & 0xff; /* channel group 0 */ 1657 sc->lna[1] = val >> 8; /* channel group 1 */ 1658 1659 /* fix broken 5GHz LNA entries */ 1660 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1661 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1662 sc->lna[2] = sc->lna[1]; 1663 } 1664 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1665 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1666 sc->lna[3] = sc->lna[1]; 1667 } 1668 1669 /* fix broken RSSI offset entries */ 1670 for (ant = 0; ant < 3; ant++) { 1671 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1672 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1673 ant + 1, sc->rssi_2ghz[ant])); 1674 sc->rssi_2ghz[ant] = 0; 1675 } 1676 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1677 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1678 ant + 1, sc->rssi_5ghz[ant])); 1679 sc->rssi_5ghz[ant] = 0; 1680 } 1681 } 1682 return 0; 1683 } 1684 1685 static struct ieee80211_node * 1686 run_node_alloc(struct ieee80211_node_table *nt) 1687 { 1688 struct run_node *rn = 1689 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1690 return rn ? &rn->ni : NULL; 1691 } 1692 1693 static int 1694 run_media_change(struct ifnet *ifp) 1695 { 1696 struct run_softc *sc = ifp->if_softc; 1697 struct ieee80211com *ic = &sc->sc_ic; 1698 uint8_t rate, ridx; 1699 int error; 1700 1701 error = ieee80211_media_change(ifp); 1702 if (error != ENETRESET) 1703 return error; 1704 1705 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1706 rate = ic->ic_sup_rates[ic->ic_curmode]. 1707 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1708 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1709 if (rt2860_rates[ridx].rate == rate) 1710 break; 1711 sc->fixed_ridx = ridx; 1712 } 1713 1714 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1715 run_init(ifp); 1716 1717 return 0; 1718 } 1719 1720 static void 1721 run_next_scan(void *arg) 1722 { 1723 struct run_softc *sc = arg; 1724 1725 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1726 ieee80211_next_scan(&sc->sc_ic); 1727 } 1728 1729 static void 1730 run_task(void *arg) 1731 { 1732 struct run_softc *sc = arg; 1733 struct run_host_cmd_ring *ring = &sc->cmdq; 1734 struct run_host_cmd *cmd; 1735 int s; 1736 1737 /* process host commands */ 1738 s = splusb(); 1739 while (ring->next != ring->cur) { 1740 cmd = &ring->cmd[ring->next]; 1741 splx(s); 1742 /* callback */ 1743 cmd->cb(sc, cmd->data); 1744 s = splusb(); 1745 ring->queued--; 1746 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1747 } 1748 wakeup(ring); 1749 splx(s); 1750 } 1751 1752 static void 1753 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1754 void *arg, int len) 1755 { 1756 struct run_host_cmd_ring *ring = &sc->cmdq; 1757 struct run_host_cmd *cmd; 1758 int s; 1759 1760 if (sc->sc_flags & RUN_DETACHING) 1761 return; 1762 1763 s = splusb(); 1764 cmd = &ring->cmd[ring->cur]; 1765 cmd->cb = cb; 1766 KASSERT(len <= sizeof(cmd->data)); 1767 memcpy(cmd->data, arg, len); 1768 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1769 1770 /* if there is no pending command already, schedule a task */ 1771 if (++ring->queued == 1) 1772 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1773 splx(s); 1774 } 1775 1776 static int 1777 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1778 { 1779 struct run_softc *sc = ic->ic_ifp->if_softc; 1780 struct run_cmd_newstate cmd; 1781 1782 callout_stop(&sc->scan_to); 1783 callout_stop(&sc->calib_to); 1784 1785 /* do it in a process context */ 1786 cmd.state = nstate; 1787 cmd.arg = arg; 1788 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1789 return 0; 1790 } 1791 1792 static void 1793 run_newstate_cb(struct run_softc *sc, void *arg) 1794 { 1795 struct run_cmd_newstate *cmd = arg; 1796 struct ifnet *ifp = &sc->sc_if; 1797 struct ieee80211com *ic = &sc->sc_ic; 1798 enum ieee80211_state ostate; 1799 struct ieee80211_node *ni; 1800 uint32_t tmp, sta[3]; 1801 uint8_t wcid; 1802 int s; 1803 1804 s = splnet(); 1805 ostate = ic->ic_state; 1806 1807 if (ostate == IEEE80211_S_RUN) { 1808 /* turn link LED off */ 1809 run_set_leds(sc, RT2860_LED_RADIO); 1810 } 1811 1812 switch (cmd->state) { 1813 case IEEE80211_S_INIT: 1814 if (ostate == IEEE80211_S_RUN) { 1815 /* abort TSF synchronization */ 1816 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1817 run_write(sc, RT2860_BCN_TIME_CFG, 1818 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1819 RT2860_TBTT_TIMER_EN)); 1820 } 1821 break; 1822 1823 case IEEE80211_S_SCAN: 1824 run_set_chan(sc, ic->ic_curchan); 1825 callout_schedule(&sc->scan_to, hz / 5); 1826 break; 1827 1828 case IEEE80211_S_AUTH: 1829 case IEEE80211_S_ASSOC: 1830 run_set_chan(sc, ic->ic_curchan); 1831 break; 1832 1833 case IEEE80211_S_RUN: 1834 run_set_chan(sc, ic->ic_curchan); 1835 1836 ni = ic->ic_bss; 1837 1838 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1839 run_updateslot(ifp); 1840 run_enable_mrr(sc); 1841 run_set_txpreamble(sc); 1842 run_set_basicrates(sc); 1843 run_set_bssid(sc, ni->ni_bssid); 1844 } 1845 #ifndef IEEE80211_STA_ONLY 1846 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1847 ic->ic_opmode == IEEE80211_M_IBSS) 1848 (void)run_setup_beacon(sc); 1849 #endif 1850 if (ic->ic_opmode == IEEE80211_M_STA) { 1851 /* add BSS entry to the WCID table */ 1852 wcid = RUN_AID2WCID(ni->ni_associd); 1853 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1854 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1855 1856 /* fake a join to init the tx rate */ 1857 run_newassoc(ni, 1); 1858 } 1859 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1860 run_enable_tsf_sync(sc); 1861 1862 /* clear statistic registers used by AMRR */ 1863 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1864 (uint8_t *)sta, sizeof(sta)); 1865 /* start calibration timer */ 1866 callout_schedule(&sc->calib_to, hz); 1867 } 1868 1869 /* turn link LED on */ 1870 run_set_leds(sc, RT2860_LED_RADIO | 1871 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1872 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1873 break; 1874 } 1875 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1876 splx(s); 1877 } 1878 1879 static int 1880 run_updateedca(struct ieee80211com *ic) 1881 { 1882 1883 /* do it in a process context */ 1884 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1885 return 0; 1886 } 1887 1888 /* ARGSUSED */ 1889 static void 1890 run_updateedca_cb(struct run_softc *sc, void *arg) 1891 { 1892 struct ieee80211com *ic = &sc->sc_ic; 1893 int s, aci; 1894 1895 s = splnet(); 1896 /* update MAC TX configuration registers */ 1897 for (aci = 0; aci < WME_NUM_AC; aci++) { 1898 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1899 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1900 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1901 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1902 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1903 } 1904 1905 /* update SCH/DMA registers too */ 1906 run_write(sc, RT2860_WMM_AIFSN_CFG, 1907 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1908 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1909 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1910 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1911 run_write(sc, RT2860_WMM_CWMIN_CFG, 1912 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1913 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1914 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1915 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1916 run_write(sc, RT2860_WMM_CWMAX_CFG, 1917 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1918 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1919 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1920 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1921 run_write(sc, RT2860_WMM_TXOP0_CFG, 1922 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1923 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1924 run_write(sc, RT2860_WMM_TXOP1_CFG, 1925 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1926 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1927 splx(s); 1928 } 1929 1930 #ifdef RUN_HWCRYPTO 1931 static int 1932 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1933 const uint8_t *mac) 1934 { 1935 struct run_softc *sc = ic->ic_ifp->if_softc; 1936 struct ieee80211_node *ni = ic->ic_bss; 1937 struct run_cmd_key cmd; 1938 1939 /* do it in a process context */ 1940 cmd.key = *k; 1941 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1942 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1943 return 1; 1944 } 1945 1946 static void 1947 run_set_key_cb(struct run_softc *sc, void *arg) 1948 { 1949 #ifndef IEEE80211_STA_ONLY 1950 struct ieee80211com *ic = &sc->sc_ic; 1951 #endif 1952 struct run_cmd_key *cmd = arg; 1953 struct ieee80211_key *k = &cmd->key; 1954 uint32_t attr; 1955 uint16_t base; 1956 uint8_t mode, wcid, iv[8]; 1957 1958 /* map net80211 cipher to RT2860 security mode */ 1959 switch (k->wk_cipher->ic_cipher) { 1960 case IEEE80211_CIPHER_WEP: 1961 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 1962 if (k->wk_keylen == 5) 1963 mode = RT2860_MODE_WEP40; 1964 else 1965 mode = RT2860_MODE_WEP104; 1966 break; 1967 case IEEE80211_CIPHER_TKIP: 1968 mode = RT2860_MODE_TKIP; 1969 break; 1970 case IEEE80211_CIPHER_AES_CCM: 1971 mode = RT2860_MODE_AES_CCMP; 1972 break; 1973 default: 1974 return; 1975 } 1976 1977 if (k->wk_flags & IEEE80211_KEY_GROUP) { 1978 wcid = 0; /* NB: update WCID0 for group keys */ 1979 base = RT2860_SKEY(0, k->wk_keyix); 1980 } else { 1981 wcid = RUN_AID2WCID(cmd->associd); 1982 base = RT2860_PKEY(wcid); 1983 } 1984 1985 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 1986 run_write_region_1(sc, base, k->wk_key, 16); 1987 #ifndef IEEE80211_STA_ONLY 1988 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1989 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 1990 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 1991 } else 1992 #endif 1993 { 1994 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 1995 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 1996 } 1997 } else { 1998 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1999 run_write_region_1(sc, base, k->wk_key, 2000 (k->wk_keylen + 1) & ~1); 2001 } 2002 2003 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2004 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2005 /* set initial packet number in IV+EIV */ 2006 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2007 memset(iv, 0, sizeof(iv)); 2008 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2009 } else { 2010 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2011 iv[0] = k->wk_keytsc >> 8; 2012 iv[1] = (iv[0] | 0x20) & 0x7f; 2013 iv[2] = k->wk_keytsc; 2014 } else /* CCMP */ { 2015 iv[0] = k->wk_keytsc; 2016 iv[1] = k->wk_keytsc >> 8; 2017 iv[2] = 0; 2018 } 2019 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2020 iv[4] = k->wk_keytsc >> 16; 2021 iv[5] = k->wk_keytsc >> 24; 2022 iv[6] = k->wk_keytsc >> 32; 2023 iv[7] = k->wk_keytsc >> 40; 2024 } 2025 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2026 } 2027 2028 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2029 /* install group key */ 2030 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2031 attr &= ~(0xf << (k->wk_keyix * 4)); 2032 attr |= mode << (k->wk_keyix * 4); 2033 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2034 } else { 2035 /* install pairwise key */ 2036 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2037 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2038 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2039 } 2040 } 2041 2042 static int 2043 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2044 { 2045 struct run_softc *sc = ic->ic_ifp->if_softc; 2046 struct ieee80211_node *ni = ic->ic_bss; 2047 struct run_cmd_key cmd; 2048 2049 /* do it in a process context */ 2050 cmd.key = *k; 2051 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2052 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2053 return 1; 2054 } 2055 2056 static void 2057 run_delete_key_cb(struct run_softc *sc, void *arg) 2058 { 2059 struct run_cmd_key *cmd = arg; 2060 struct ieee80211_key *k = &cmd->key; 2061 uint32_t attr; 2062 uint8_t wcid; 2063 2064 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2065 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2066 2067 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2068 /* remove group key */ 2069 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2070 attr &= ~(0xf << (k->wk_keyix * 4)); 2071 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2072 2073 } else { 2074 /* remove pairwise key */ 2075 wcid = RUN_AID2WCID(cmd->associd); 2076 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2077 attr &= ~0xf; 2078 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2079 } 2080 } 2081 #endif 2082 2083 static void 2084 run_calibrate_to(void *arg) 2085 { 2086 2087 /* do it in a process context */ 2088 run_do_async(arg, run_calibrate_cb, NULL, 0); 2089 /* next timeout will be rescheduled in the calibration task */ 2090 } 2091 2092 /* ARGSUSED */ 2093 static void 2094 run_calibrate_cb(struct run_softc *sc, void *arg) 2095 { 2096 struct ifnet *ifp = &sc->sc_if; 2097 uint32_t sta[3]; 2098 int s, error; 2099 2100 /* read statistic counters (clear on read) and update AMRR state */ 2101 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2102 sizeof(sta)); 2103 if (error != 0) 2104 goto skip; 2105 2106 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2107 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2108 le32toh(sta[0]) & 0xffff)); 2109 2110 s = splnet(); 2111 /* count failed TX as errors */ 2112 ifp->if_oerrors += le32toh(sta[0]) & 0xffff; 2113 2114 sc->amn.amn_retrycnt = 2115 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2116 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2117 2118 sc->amn.amn_txcnt = 2119 sc->amn.amn_retrycnt + 2120 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2121 2122 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2123 splx(s); 2124 2125 skip: callout_schedule(&sc->calib_to, hz); 2126 } 2127 2128 static void 2129 run_newassoc(struct ieee80211_node *ni, int isnew) 2130 { 2131 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2132 struct run_node *rn = (void *)ni; 2133 struct ieee80211_rateset *rs = &ni->ni_rates; 2134 uint8_t rate; 2135 int ridx, i, j; 2136 2137 DPRINTF(("new assoc isnew=%d addr=%s\n", 2138 isnew, ether_sprintf(ni->ni_macaddr))); 2139 2140 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2141 /* start at lowest available bit-rate, AMRR will raise */ 2142 ni->ni_txrate = 0; 2143 2144 for (i = 0; i < rs->rs_nrates; i++) { 2145 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2146 /* convert 802.11 rate to hardware rate index */ 2147 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2148 if (rt2860_rates[ridx].rate == rate) 2149 break; 2150 rn->ridx[i] = ridx; 2151 /* determine rate of control response frames */ 2152 for (j = i; j >= 0; j--) { 2153 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2154 rt2860_rates[rn->ridx[i]].phy == 2155 rt2860_rates[rn->ridx[j]].phy) 2156 break; 2157 } 2158 if (j >= 0) { 2159 rn->ctl_ridx[i] = rn->ridx[j]; 2160 } else { 2161 /* no basic rate found, use mandatory one */ 2162 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2163 } 2164 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2165 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2166 } 2167 } 2168 2169 /* 2170 * Return the Rx chain with the highest RSSI for a given frame. 2171 */ 2172 static __inline uint8_t 2173 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2174 { 2175 uint8_t rxchain = 0; 2176 2177 if (sc->nrxchains > 1) { 2178 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2179 rxchain = 1; 2180 if (sc->nrxchains > 2) 2181 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2182 rxchain = 2; 2183 } 2184 return rxchain; 2185 } 2186 2187 static void 2188 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2189 { 2190 struct ieee80211com *ic = &sc->sc_ic; 2191 struct ifnet *ifp = &sc->sc_if; 2192 struct ieee80211_frame *wh; 2193 struct ieee80211_node *ni; 2194 struct rt2870_rxd *rxd; 2195 struct rt2860_rxwi *rxwi; 2196 struct mbuf *m; 2197 uint32_t flags; 2198 uint16_t len, rxwisize, phy; 2199 uint8_t ant, rssi; 2200 int s; 2201 #ifdef RUN_HWCRYPTO 2202 int decrypted = 0; 2203 #endif 2204 2205 rxwi = (struct rt2860_rxwi *)buf; 2206 len = le16toh(rxwi->len) & 0xfff; 2207 if (__predict_false(len > dmalen)) { 2208 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2209 return; 2210 } 2211 /* Rx descriptor is located at the end */ 2212 rxd = (struct rt2870_rxd *)(buf + dmalen); 2213 flags = le32toh(rxd->flags); 2214 2215 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2216 ifp->if_ierrors++; 2217 return; 2218 } 2219 2220 rxwisize = sizeof(struct rt2860_rxwi); 2221 if (sc->mac_ver == 0x5592) 2222 rxwisize += sizeof(uint64_t); 2223 else if (sc->mac_ver == 0x3593) 2224 rxwisize += sizeof(uint32_t); 2225 2226 wh = (struct ieee80211_frame *)(((uint8_t *)rxwi) + rxwisize); 2227 #ifdef RUN_HWCRYPTO 2228 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2229 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2230 decrypted = 1; 2231 } 2232 #endif 2233 2234 if (__predict_false((flags & RT2860_RX_MICERR))) { 2235 /* report MIC failures to net80211 for TKIP */ 2236 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2237 ifp->if_ierrors++; 2238 return; 2239 } 2240 2241 if (flags & RT2860_RX_L2PAD) { 2242 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2243 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 2244 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2245 } 2246 2247 /* could use m_devget but net80211 wants contig mgmt frames */ 2248 MGETHDR(m, M_DONTWAIT, MT_DATA); 2249 if (__predict_false(m == NULL)) { 2250 ifp->if_ierrors++; 2251 return; 2252 } 2253 if (len > MHLEN) { 2254 MCLGET(m, M_DONTWAIT); 2255 if (__predict_false(!(m->m_flags & M_EXT))) { 2256 ifp->if_ierrors++; 2257 m_freem(m); 2258 return; 2259 } 2260 } 2261 /* finalize mbuf */ 2262 m_set_rcvif(m, ifp); 2263 memcpy(mtod(m, void *), wh, len); 2264 m->m_pkthdr.len = m->m_len = len; 2265 2266 ant = run_maxrssi_chain(sc, rxwi); 2267 rssi = rxwi->rssi[ant]; 2268 2269 if (__predict_false(sc->sc_drvbpf != NULL)) { 2270 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2271 2272 tap->wr_flags = 0; 2273 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2274 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2275 tap->wr_antsignal = rssi; 2276 tap->wr_antenna = ant; 2277 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2278 tap->wr_rate = 2; /* in case it can't be found below */ 2279 phy = le16toh(rxwi->phy); 2280 switch (phy & RT2860_PHY_MODE) { 2281 case RT2860_PHY_CCK: 2282 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2283 case 0: tap->wr_rate = 2; break; 2284 case 1: tap->wr_rate = 4; break; 2285 case 2: tap->wr_rate = 11; break; 2286 case 3: tap->wr_rate = 22; break; 2287 } 2288 if (phy & RT2860_PHY_SHPRE) 2289 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2290 break; 2291 case RT2860_PHY_OFDM: 2292 switch (phy & RT2860_PHY_MCS) { 2293 case 0: tap->wr_rate = 12; break; 2294 case 1: tap->wr_rate = 18; break; 2295 case 2: tap->wr_rate = 24; break; 2296 case 3: tap->wr_rate = 36; break; 2297 case 4: tap->wr_rate = 48; break; 2298 case 5: tap->wr_rate = 72; break; 2299 case 6: tap->wr_rate = 96; break; 2300 case 7: tap->wr_rate = 108; break; 2301 } 2302 break; 2303 } 2304 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2305 } 2306 2307 s = splnet(); 2308 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2309 #ifdef RUN_HWCRYPTO 2310 if (decrypted) { 2311 uint32_t icflags = ic->ic_flags; 2312 2313 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2314 ieee80211_input(ic, m, ni, rssi, 0); 2315 ic->ic_flags = icflags; 2316 } else 2317 #endif 2318 ieee80211_input(ic, m, ni, rssi, 0); 2319 2320 /* node is no longer needed */ 2321 ieee80211_free_node(ni); 2322 2323 /* 2324 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2325 * without calling if_start(). 2326 */ 2327 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2328 run_start(ifp); 2329 2330 splx(s); 2331 } 2332 2333 static void 2334 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2335 { 2336 struct run_rx_data *data = priv; 2337 struct run_softc *sc = data->sc; 2338 uint8_t *buf; 2339 uint32_t dmalen; 2340 int xferlen; 2341 2342 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2343 return; 2344 2345 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2346 DPRINTF(("RX status=%d\n", status)); 2347 if (status == USBD_STALLED) 2348 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2349 if (status != USBD_CANCELLED) 2350 goto skip; 2351 return; 2352 } 2353 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2354 2355 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2356 sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd)))) { 2357 DPRINTF(("xfer too short %d\n", xferlen)); 2358 goto skip; 2359 } 2360 2361 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2362 buf = data->buf; 2363 while (xferlen > 8) { 2364 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2365 2366 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2367 (dmalen & 3) != 0)) { 2368 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2369 break; 2370 } 2371 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2372 DPRINTF(("bad DMA length %u > %d\n", 2373 dmalen + 8, xferlen)); 2374 break; 2375 } 2376 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2377 buf += dmalen + 8; 2378 xferlen -= dmalen + 8; 2379 } 2380 2381 skip: /* setup a new transfer */ 2382 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2383 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2384 (void)usbd_transfer(xfer); 2385 } 2386 2387 static void 2388 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2389 { 2390 struct run_tx_data *data = priv; 2391 struct run_softc *sc = data->sc; 2392 struct run_tx_ring *txq = &sc->txq[data->qid]; 2393 struct ifnet *ifp = &sc->sc_if; 2394 int s; 2395 2396 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2397 DPRINTF(("TX status=%d\n", status)); 2398 if (status == USBD_STALLED) 2399 usbd_clear_endpoint_stall_async(txq->pipeh); 2400 ifp->if_oerrors++; 2401 return; 2402 } 2403 2404 s = splnet(); 2405 sc->sc_tx_timer = 0; 2406 ifp->if_opackets++; 2407 if (--txq->queued < RUN_TX_RING_COUNT) { 2408 sc->qfullmsk &= ~(1 << data->qid); 2409 ifp->if_flags &= ~IFF_OACTIVE; 2410 run_start(ifp); 2411 } 2412 splx(s); 2413 } 2414 2415 static int 2416 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2417 { 2418 struct ieee80211com *ic = &sc->sc_ic; 2419 struct run_node *rn = (void *)ni; 2420 struct ieee80211_frame *wh; 2421 #ifndef RUN_HWCRYPTO 2422 struct ieee80211_key *k; 2423 #endif 2424 struct run_tx_ring *ring; 2425 struct run_tx_data *data; 2426 struct rt2870_txd *txd; 2427 struct rt2860_txwi *txwi; 2428 uint16_t dur, mcs; 2429 uint8_t type, tid, qid, qos = 0; 2430 int error, hasqos, ridx, ctl_ridx, xferlen, txwisize; 2431 uint8_t pad; 2432 2433 wh = mtod(m, struct ieee80211_frame *); 2434 2435 #ifndef RUN_HWCRYPTO 2436 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2437 k = ieee80211_crypto_encap(ic, ni, m); 2438 if (k == NULL) { 2439 m_freem(m); 2440 return ENOBUFS; 2441 } 2442 2443 /* packet header may have moved, reset our local pointer */ 2444 wh = mtod(m, struct ieee80211_frame *); 2445 } 2446 #endif 2447 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2448 2449 if ((hasqos = ieee80211_has_qos(wh))) { 2450 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2451 tid = qos & IEEE80211_QOS_TID; 2452 qid = TID_TO_WME_AC(tid); 2453 } else { 2454 tid = 0; 2455 qid = WME_AC_BE; 2456 } 2457 ring = &sc->txq[qid]; 2458 data = &ring->data[ring->cur]; 2459 2460 /* pickup a rate index */ 2461 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2462 type != IEEE80211_FC0_TYPE_DATA) { 2463 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2464 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2465 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2466 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2467 ridx = sc->fixed_ridx; 2468 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2469 } else { 2470 ridx = rn->ridx[ni->ni_txrate]; 2471 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2472 } 2473 2474 /* get MCS code from rate index */ 2475 mcs = rt2860_rates[ridx].mcs; 2476 2477 txwisize = (sc->mac_ver == 0x5592) ? 2478 sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi); 2479 xferlen = txwisize + m->m_pkthdr.len; 2480 /* roundup to 32-bit alignment */ 2481 xferlen = (xferlen + 3) & ~3; 2482 2483 txd = (struct rt2870_txd *)data->buf; 2484 txd->flags = RT2860_TX_QSEL_EDCA; 2485 txd->len = htole16(xferlen); 2486 2487 /* 2488 * Ether both are true or both are false, the header 2489 * are nicely aligned to 32-bit. So, no L2 padding. 2490 */ 2491 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2492 pad = 0; 2493 else 2494 pad = 2; 2495 2496 /* setup TX Wireless Information */ 2497 txwi = (struct rt2860_txwi *)(txd + 1); 2498 txwi->flags = 0; 2499 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2500 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2501 RUN_AID2WCID(ni->ni_associd) : 0xff; 2502 txwi->len = htole16(m->m_pkthdr.len - pad); 2503 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2504 txwi->phy = htole16(RT2860_PHY_CCK); 2505 if (ridx != RT2860_RIDX_CCK1 && 2506 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2507 mcs |= RT2860_PHY_SHPRE; 2508 } else 2509 mcs |= RT2860_PHY_OFDM; 2510 txwi->phy |= htole16(mcs); 2511 2512 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2513 2514 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2515 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2516 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2517 txwi->xflags |= RT2860_TX_ACK; 2518 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2519 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2520 else 2521 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2522 *(uint16_t *)wh->i_dur = htole16(dur); 2523 } 2524 2525 #ifndef IEEE80211_STA_ONLY 2526 /* ask MAC to insert timestamp into probe responses */ 2527 if ((wh->i_fc[0] & 2528 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2529 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2530 /* NOTE: beacons do not pass through tx_data() */ 2531 txwi->flags |= RT2860_TX_TS; 2532 #endif 2533 2534 if (__predict_false(sc->sc_drvbpf != NULL)) { 2535 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2536 2537 tap->wt_flags = 0; 2538 tap->wt_rate = rt2860_rates[ridx].rate; 2539 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2540 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2541 tap->wt_hwqueue = qid; 2542 if (mcs & RT2860_PHY_SHPRE) 2543 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2544 2545 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2546 } 2547 2548 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2549 m_freem(m); 2550 2551 xferlen += sizeof(*txd) + 4; 2552 2553 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2554 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2555 error = usbd_transfer(data->xfer); 2556 if (__predict_false(error != USBD_IN_PROGRESS && 2557 error != USBD_NORMAL_COMPLETION)) 2558 return error; 2559 2560 ieee80211_free_node(ni); 2561 2562 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2563 if (++ring->queued >= RUN_TX_RING_COUNT) 2564 sc->qfullmsk |= 1 << qid; 2565 2566 return 0; 2567 } 2568 2569 static void 2570 run_start(struct ifnet *ifp) 2571 { 2572 struct run_softc *sc = ifp->if_softc; 2573 struct ieee80211com *ic = &sc->sc_ic; 2574 struct ether_header *eh; 2575 struct ieee80211_node *ni; 2576 struct mbuf *m; 2577 2578 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2579 return; 2580 2581 for (;;) { 2582 if (sc->qfullmsk != 0) { 2583 ifp->if_flags |= IFF_OACTIVE; 2584 break; 2585 } 2586 /* send pending management frames first */ 2587 IF_DEQUEUE(&ic->ic_mgtq, m); 2588 if (m != NULL) { 2589 ni = M_GETCTX(m, struct ieee80211_node *); 2590 M_CLEARCTX(m); 2591 goto sendit; 2592 } 2593 if (ic->ic_state != IEEE80211_S_RUN) 2594 break; 2595 2596 /* encapsulate and send data frames */ 2597 IFQ_DEQUEUE(&ifp->if_snd, m); 2598 if (m == NULL) 2599 break; 2600 if (m->m_len < (int)sizeof(*eh) && 2601 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2602 ifp->if_oerrors++; 2603 continue; 2604 } 2605 2606 eh = mtod(m, struct ether_header *); 2607 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2608 if (ni == NULL) { 2609 m_freem(m); 2610 ifp->if_oerrors++; 2611 continue; 2612 } 2613 2614 bpf_mtap(ifp, m); 2615 2616 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2617 ieee80211_free_node(ni); 2618 ifp->if_oerrors++; 2619 continue; 2620 } 2621 sendit: 2622 bpf_mtap3(ic->ic_rawbpf, m); 2623 2624 if (run_tx(sc, m, ni) != 0) { 2625 ieee80211_free_node(ni); 2626 ifp->if_oerrors++; 2627 continue; 2628 } 2629 2630 sc->sc_tx_timer = 5; 2631 ifp->if_timer = 1; 2632 } 2633 } 2634 2635 static void 2636 run_watchdog(struct ifnet *ifp) 2637 { 2638 struct run_softc *sc = ifp->if_softc; 2639 struct ieee80211com *ic = &sc->sc_ic; 2640 2641 ifp->if_timer = 0; 2642 2643 if (sc->sc_tx_timer > 0) { 2644 if (--sc->sc_tx_timer == 0) { 2645 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2646 /* run_init(ifp); XXX needs a process context! */ 2647 ifp->if_oerrors++; 2648 return; 2649 } 2650 ifp->if_timer = 1; 2651 } 2652 2653 ieee80211_watchdog(ic); 2654 } 2655 2656 static int 2657 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2658 { 2659 struct run_softc *sc = ifp->if_softc; 2660 struct ieee80211com *ic = &sc->sc_ic; 2661 int s, error = 0; 2662 2663 s = splnet(); 2664 2665 switch (cmd) { 2666 case SIOCSIFFLAGS: 2667 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2668 break; 2669 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2670 case IFF_UP|IFF_RUNNING: 2671 break; 2672 case IFF_UP: 2673 run_init(ifp); 2674 break; 2675 case IFF_RUNNING: 2676 run_stop(ifp, 1); 2677 break; 2678 case 0: 2679 break; 2680 } 2681 break; 2682 2683 case SIOCADDMULTI: 2684 case SIOCDELMULTI: 2685 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2686 /* setup multicast filter, etc */ 2687 error = 0; 2688 } 2689 break; 2690 2691 default: 2692 error = ieee80211_ioctl(ic, cmd, data); 2693 break; 2694 } 2695 2696 if (error == ENETRESET) { 2697 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2698 (IFF_UP | IFF_RUNNING)) { 2699 run_init(ifp); 2700 } 2701 error = 0; 2702 } 2703 2704 splx(s); 2705 2706 return error; 2707 } 2708 2709 static void 2710 run_select_chan_group(struct run_softc *sc, int group) 2711 { 2712 uint32_t tmp; 2713 uint8_t agc; 2714 2715 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2716 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2717 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2718 run_bbp_write(sc, 86, 0x00); 2719 2720 if (group == 0) { 2721 if (sc->ext_2ghz_lna) { 2722 run_bbp_write(sc, 82, 0x62); 2723 run_bbp_write(sc, 75, 0x46); 2724 } else { 2725 run_bbp_write(sc, 82, 0x84); 2726 run_bbp_write(sc, 75, 0x50); 2727 } 2728 } else { 2729 if (sc->mac_ver == 0x3572) 2730 run_bbp_write(sc, 82, 0x94); 2731 else 2732 run_bbp_write(sc, 82, 0xf2); 2733 if (sc->ext_5ghz_lna) 2734 run_bbp_write(sc, 75, 0x46); 2735 else 2736 run_bbp_write(sc, 75, 0x50); 2737 } 2738 2739 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2740 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2741 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2742 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2743 2744 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2745 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2746 if (sc->nrxchains > 1) 2747 tmp |= RT2860_LNA_PE1_EN; 2748 if (group == 0) { /* 2GHz */ 2749 tmp |= RT2860_PA_PE_G0_EN; 2750 if (sc->ntxchains > 1) 2751 tmp |= RT2860_PA_PE_G1_EN; 2752 } else { /* 5GHz */ 2753 tmp |= RT2860_PA_PE_A0_EN; 2754 if (sc->ntxchains > 1) 2755 tmp |= RT2860_PA_PE_A1_EN; 2756 } 2757 if (sc->mac_ver == 0x3572) { 2758 run_rt3070_rf_write(sc, 8, 0x00); 2759 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2760 run_rt3070_rf_write(sc, 8, 0x80); 2761 } else 2762 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2763 2764 /* set initial AGC value */ 2765 if (group == 0) { /* 2GHz band */ 2766 if (sc->mac_ver >= 0x3070) 2767 agc = 0x1c + sc->lna[0] * 2; 2768 else 2769 agc = 0x2e + sc->lna[0]; 2770 } else { /* 5GHz band */ 2771 if (sc->mac_ver == 0x3572) 2772 agc = 0x22 + (sc->lna[group] * 5) / 3; 2773 else 2774 agc = 0x32 + (sc->lna[group] * 5) / 3; 2775 } 2776 run_set_agc(sc, agc); 2777 } 2778 2779 static void 2780 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2781 { 2782 const struct rfprog *rfprog = rt2860_rf2850; 2783 uint32_t r2, r3, r4; 2784 int8_t txpow1, txpow2; 2785 int i; 2786 2787 /* find the settings for this channel (we know it exists) */ 2788 for (i = 0; rfprog[i].chan != chan; i++); 2789 2790 r2 = rfprog[i].r2; 2791 if (sc->ntxchains == 1) 2792 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2793 if (sc->nrxchains == 1) 2794 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2795 else if (sc->nrxchains == 2) 2796 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2797 2798 /* use Tx power values from EEPROM */ 2799 txpow1 = sc->txpow1[i]; 2800 txpow2 = sc->txpow2[i]; 2801 if (chan > 14) { 2802 if (txpow1 >= 0) 2803 txpow1 = txpow1 << 1 | 1; 2804 else 2805 txpow1 = (7 + txpow1) << 1; 2806 if (txpow2 >= 0) 2807 txpow2 = txpow2 << 1 | 1; 2808 else 2809 txpow2 = (7 + txpow2) << 1; 2810 } 2811 r3 = rfprog[i].r3 | txpow1 << 7; 2812 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2813 2814 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2815 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2816 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2817 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2818 2819 usbd_delay_ms(sc->sc_udev, 10); 2820 2821 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2822 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2823 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2824 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2825 2826 usbd_delay_ms(sc->sc_udev, 10); 2827 2828 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2829 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2830 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2831 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2832 } 2833 2834 static void 2835 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2836 { 2837 int8_t txpow1, txpow2; 2838 uint8_t rf; 2839 int i; 2840 2841 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2842 2843 /* find the settings for this channel (we know it exists) */ 2844 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2845 continue; 2846 2847 /* use Tx power values from EEPROM */ 2848 txpow1 = sc->txpow1[i]; 2849 txpow2 = sc->txpow2[i]; 2850 2851 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2852 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2853 run_rt3070_rf_read(sc, 6, &rf); 2854 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2855 run_rt3070_rf_write(sc, 6, rf); 2856 2857 /* set Tx0 power */ 2858 run_rt3070_rf_read(sc, 12, &rf); 2859 rf = (rf & ~0x1f) | txpow1; 2860 run_rt3070_rf_write(sc, 12, rf); 2861 2862 /* set Tx1 power */ 2863 run_rt3070_rf_read(sc, 13, &rf); 2864 rf = (rf & ~0x1f) | txpow2; 2865 run_rt3070_rf_write(sc, 13, rf); 2866 2867 run_rt3070_rf_read(sc, 1, &rf); 2868 rf &= ~0xfc; 2869 if (sc->ntxchains == 1) 2870 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2871 else if (sc->ntxchains == 2) 2872 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2873 if (sc->nrxchains == 1) 2874 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2875 else if (sc->nrxchains == 2) 2876 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2877 run_rt3070_rf_write(sc, 1, rf); 2878 2879 /* set RF offset */ 2880 run_rt3070_rf_read(sc, 23, &rf); 2881 rf = (rf & ~0x7f) | sc->freq; 2882 run_rt3070_rf_write(sc, 23, rf); 2883 2884 /* program RF filter */ 2885 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2886 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2887 run_rt3070_rf_write(sc, 24, rf); 2888 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2889 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2890 run_rt3070_rf_write(sc, 31, rf); 2891 2892 /* enable RF tuning */ 2893 run_rt3070_rf_read(sc, 7, &rf); 2894 run_rt3070_rf_write(sc, 7, rf | 0x01); 2895 } 2896 2897 static void 2898 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 2899 { 2900 int8_t txpow1, txpow2; 2901 uint32_t tmp; 2902 uint8_t rf; 2903 int i; 2904 2905 /* find the settings for this channel (we know it exists) */ 2906 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2907 2908 /* use Tx power values from EEPROM */ 2909 txpow1 = sc->txpow1[i]; 2910 txpow2 = sc->txpow2[i]; 2911 2912 if (chan <= 14) { 2913 run_bbp_write(sc, 25, sc->bbp25); 2914 run_bbp_write(sc, 26, sc->bbp26); 2915 } else { 2916 /* enable IQ phase correction */ 2917 run_bbp_write(sc, 25, 0x09); 2918 run_bbp_write(sc, 26, 0xff); 2919 } 2920 2921 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2922 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2923 run_rt3070_rf_read(sc, 6, &rf); 2924 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 2925 rf |= (chan <= 14) ? 0x08 : 0x04; 2926 run_rt3070_rf_write(sc, 6, rf); 2927 2928 /* set PLL mode */ 2929 run_rt3070_rf_read(sc, 5, &rf); 2930 rf &= ~(0x08 | 0x04); 2931 rf |= (chan <= 14) ? 0x04 : 0x08; 2932 run_rt3070_rf_write(sc, 5, rf); 2933 2934 /* set Tx power for chain 0 */ 2935 if (chan <= 14) 2936 rf = 0x60 | txpow1; 2937 else 2938 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 2939 run_rt3070_rf_write(sc, 12, rf); 2940 2941 /* set Tx power for chain 1 */ 2942 if (chan <= 14) 2943 rf = 0x60 | txpow2; 2944 else 2945 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 2946 run_rt3070_rf_write(sc, 13, rf); 2947 2948 /* set Tx/Rx streams */ 2949 run_rt3070_rf_read(sc, 1, &rf); 2950 rf &= ~0xfc; 2951 if (sc->ntxchains == 1) 2952 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2953 else if (sc->ntxchains == 2) 2954 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2955 if (sc->nrxchains == 1) 2956 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2957 else if (sc->nrxchains == 2) 2958 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2959 run_rt3070_rf_write(sc, 1, rf); 2960 2961 /* set RF offset */ 2962 run_rt3070_rf_read(sc, 23, &rf); 2963 rf = (rf & ~0x7f) | sc->freq; 2964 run_rt3070_rf_write(sc, 23, rf); 2965 2966 /* program RF filter */ 2967 rf = sc->rf24_20mhz; 2968 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 2969 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 2970 2971 /* enable RF tuning */ 2972 run_rt3070_rf_read(sc, 7, &rf); 2973 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 2974 run_rt3070_rf_write(sc, 7, rf); 2975 2976 /* TSSI */ 2977 rf = (chan <= 14) ? 0xc3 : 0xc0; 2978 run_rt3070_rf_write(sc, 9, rf); 2979 2980 /* set loop filter 1 */ 2981 run_rt3070_rf_write(sc, 10, 0xf1); 2982 /* set loop filter 2 */ 2983 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 2984 2985 /* set tx_mx2_ic */ 2986 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 2987 /* set tx_mx1_ic */ 2988 if (chan <= 14) 2989 rf = 0x48 | sc->txmixgain_2ghz; 2990 else 2991 rf = 0x78 | sc->txmixgain_5ghz; 2992 run_rt3070_rf_write(sc, 16, rf); 2993 2994 /* set tx_lo1 */ 2995 run_rt3070_rf_write(sc, 17, 0x23); 2996 /* set tx_lo2 */ 2997 if (chan <= 14) 2998 rf = 0x93; 2999 else if (chan <= 64) 3000 rf = 0xb7; 3001 else if (chan <= 128) 3002 rf = 0x74; 3003 else 3004 rf = 0x72; 3005 run_rt3070_rf_write(sc, 19, rf); 3006 3007 /* set rx_lo1 */ 3008 if (chan <= 14) 3009 rf = 0xb3; 3010 else if (chan <= 64) 3011 rf = 0xf6; 3012 else if (chan <= 128) 3013 rf = 0xf4; 3014 else 3015 rf = 0xf3; 3016 run_rt3070_rf_write(sc, 20, rf); 3017 3018 /* set pfd_delay */ 3019 if (chan <= 14) 3020 rf = 0x15; 3021 else if (chan <= 64) 3022 rf = 0x3d; 3023 else 3024 rf = 0x01; 3025 run_rt3070_rf_write(sc, 25, rf); 3026 3027 /* set rx_lo2 */ 3028 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3029 /* set ldo_rf_vc */ 3030 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3031 /* set drv_cc */ 3032 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3033 3034 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3035 tmp &= ~0x8080; 3036 if (chan <= 14) 3037 tmp |= 0x80; 3038 run_write(sc, RT2860_GPIO_CTRL, tmp); 3039 3040 /* enable RF tuning */ 3041 run_rt3070_rf_read(sc, 7, &rf); 3042 run_rt3070_rf_write(sc, 7, rf | 0x01); 3043 3044 usbd_delay_ms(sc->sc_udev, 2); 3045 } 3046 3047 static void 3048 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3049 { 3050 int8_t txpow1, txpow2, txpow3; 3051 uint8_t h20mhz, rf; 3052 int i; 3053 3054 /* find the settings for this channel (we know it exists) */ 3055 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3056 3057 /* use Tx power values from EEPROM */ 3058 txpow1 = sc->txpow1[i]; 3059 txpow2 = sc->txpow2[i]; 3060 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3061 3062 if (chan <= 14) { 3063 run_bbp_write(sc, 25, sc->bbp25); 3064 run_bbp_write(sc, 26, sc->bbp26); 3065 } else { 3066 /* Enable IQ phase correction. */ 3067 run_bbp_write(sc, 25, 0x09); 3068 run_bbp_write(sc, 26, 0xff); 3069 } 3070 3071 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3072 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3073 run_rt3070_rf_read(sc, 11, &rf); 3074 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3075 run_rt3070_rf_write(sc, 11, rf); 3076 3077 /* Set pll_idoh. */ 3078 run_rt3070_rf_read(sc, 11, &rf); 3079 rf &= ~0x4c; 3080 rf |= (chan <= 14) ? 0x44 : 0x48; 3081 run_rt3070_rf_write(sc, 11, rf); 3082 3083 if (chan <= 14) 3084 rf = txpow1 & 0x1f; 3085 else 3086 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3087 run_rt3070_rf_write(sc, 53, rf); 3088 3089 if (chan <= 14) 3090 rf = txpow2 & 0x1f; 3091 else 3092 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3093 run_rt3070_rf_write(sc, 55, rf); 3094 3095 if (chan <= 14) 3096 rf = txpow3 & 0x1f; 3097 else 3098 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3099 run_rt3070_rf_write(sc, 54, rf); 3100 3101 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3102 if (sc->ntxchains == 3) 3103 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3104 else 3105 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3106 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3107 run_rt3070_rf_write(sc, 1, rf); 3108 3109 run_adjust_freq_offset(sc); 3110 3111 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3112 3113 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3114 run_rt3070_rf_read(sc, 30, &rf); 3115 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3116 run_rt3070_rf_write(sc, 30, rf); 3117 3118 run_rt3070_rf_read(sc, 36, &rf); 3119 if (chan <= 14) 3120 rf |= 0x80; 3121 else 3122 rf &= ~0x80; 3123 run_rt3070_rf_write(sc, 36, rf); 3124 3125 /* Set vcolo_bs. */ 3126 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3127 /* Set pfd_delay. */ 3128 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3129 3130 /* Set vco bias current control. */ 3131 run_rt3070_rf_read(sc, 6, &rf); 3132 rf &= ~0xc0; 3133 if (chan <= 14) 3134 rf |= 0x40; 3135 else if (chan <= 128) 3136 rf |= 0x80; 3137 else 3138 rf |= 0x40; 3139 run_rt3070_rf_write(sc, 6, rf); 3140 3141 run_rt3070_rf_read(sc, 30, &rf); 3142 rf = (rf & ~0x18) | 0x10; 3143 run_rt3070_rf_write(sc, 30, rf); 3144 3145 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3146 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3147 3148 run_rt3070_rf_read(sc, 51, &rf); 3149 rf = (rf & ~0x03) | 0x01; 3150 run_rt3070_rf_write(sc, 51, rf); 3151 /* Set tx_mx1_cc. */ 3152 run_rt3070_rf_read(sc, 51, &rf); 3153 rf &= ~0x1c; 3154 rf |= (chan <= 14) ? 0x14 : 0x10; 3155 run_rt3070_rf_write(sc, 51, rf); 3156 /* Set tx_mx1_ic. */ 3157 run_rt3070_rf_read(sc, 51, &rf); 3158 rf &= ~0xe0; 3159 rf |= (chan <= 14) ? 0x60 : 0x40; 3160 run_rt3070_rf_write(sc, 51, rf); 3161 /* Set tx_lo1_ic. */ 3162 run_rt3070_rf_read(sc, 49, &rf); 3163 rf &= ~0x1c; 3164 rf |= (chan <= 14) ? 0x0c : 0x08; 3165 run_rt3070_rf_write(sc, 49, rf); 3166 /* Set tx_lo1_en. */ 3167 run_rt3070_rf_read(sc, 50, &rf); 3168 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3169 /* Set drv_cc. */ 3170 run_rt3070_rf_read(sc, 57, &rf); 3171 rf &= ~0xfc; 3172 rf |= (chan <= 14) ? 0x6c : 0x3c; 3173 run_rt3070_rf_write(sc, 57, rf); 3174 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3175 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3176 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3177 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3178 /* Enable VCO calibration. */ 3179 run_rt3070_rf_read(sc, 3, &rf); 3180 rf &= ~RT5390_VCOCAL; 3181 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3182 run_rt3070_rf_write(sc, 3, rf); 3183 3184 if (chan <= 14) 3185 rf = 0x23; 3186 else if (chan <= 64) 3187 rf = 0x36; 3188 else if (chan <= 128) 3189 rf = 0x32; 3190 else 3191 rf = 0x30; 3192 run_rt3070_rf_write(sc, 39, rf); 3193 if (chan <= 14) 3194 rf = 0xbb; 3195 else if (chan <= 64) 3196 rf = 0xeb; 3197 else if (chan <= 128) 3198 rf = 0xb3; 3199 else 3200 rf = 0x9b; 3201 run_rt3070_rf_write(sc, 45, rf); 3202 3203 /* Set FEQ/AEQ control. */ 3204 run_bbp_write(sc, 105, 0x34); 3205 } 3206 3207 static void 3208 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3209 { 3210 int8_t txpow1, txpow2; 3211 uint8_t rf; 3212 int i; 3213 3214 /* find the settings for this channel (we know it exists) */ 3215 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3216 3217 /* use Tx power values from EEPROM */ 3218 txpow1 = sc->txpow1[i]; 3219 txpow2 = sc->txpow2[i]; 3220 3221 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3222 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3223 run_rt3070_rf_read(sc, 11, &rf); 3224 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3225 run_rt3070_rf_write(sc, 11, rf); 3226 3227 run_rt3070_rf_read(sc, 49, &rf); 3228 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3229 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3230 if ((rf & 0x3f) > 0x27) 3231 rf = (rf & ~0x3f) | 0x27; 3232 run_rt3070_rf_write(sc, 49, rf); 3233 3234 if (sc->mac_ver == 0x5392) { 3235 run_rt3070_rf_read(sc, 50, &rf); 3236 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3237 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3238 if ((rf & 0x3f) > 0x27) 3239 rf = (rf & ~0x3f) | 0x27; 3240 run_rt3070_rf_write(sc, 50, rf); 3241 } 3242 3243 run_rt3070_rf_read(sc, 1, &rf); 3244 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3245 if (sc->mac_ver == 0x5392) 3246 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3247 run_rt3070_rf_write(sc, 1, rf); 3248 3249 if (sc->mac_ver != 0x5392) { 3250 run_rt3070_rf_read(sc, 2, &rf); 3251 rf |= 0x80; 3252 run_rt3070_rf_write(sc, 2, rf); 3253 usbd_delay_ms(sc->sc_udev, 10); 3254 rf &= 0x7f; 3255 run_rt3070_rf_write(sc, 2, rf); 3256 } 3257 3258 run_adjust_freq_offset(sc); 3259 3260 if (sc->mac_ver == 0x5392) { 3261 /* Fix for RT5392C. */ 3262 if (sc->mac_rev >= 0x0223) { 3263 if (chan <= 4) 3264 rf = 0x0f; 3265 else if (chan >= 5 && chan <= 7) 3266 rf = 0x0e; 3267 else 3268 rf = 0x0d; 3269 run_rt3070_rf_write(sc, 23, rf); 3270 3271 if (chan <= 4) 3272 rf = 0x0c; 3273 else if (chan == 5) 3274 rf = 0x0b; 3275 else if (chan >= 6 && chan <= 7) 3276 rf = 0x0a; 3277 else if (chan >= 8 && chan <= 10) 3278 rf = 0x09; 3279 else 3280 rf = 0x08; 3281 run_rt3070_rf_write(sc, 59, rf); 3282 } else { 3283 if (chan <= 11) 3284 rf = 0x0f; 3285 else 3286 rf = 0x0b; 3287 run_rt3070_rf_write(sc, 59, rf); 3288 } 3289 } else { 3290 /* Fix for RT5390F. */ 3291 if (sc->mac_rev >= 0x0502) { 3292 if (chan <= 11) 3293 rf = 0x43; 3294 else 3295 rf = 0x23; 3296 run_rt3070_rf_write(sc, 55, rf); 3297 3298 if (chan <= 11) 3299 rf = 0x0f; 3300 else if (chan == 12) 3301 rf = 0x0d; 3302 else 3303 rf = 0x0b; 3304 run_rt3070_rf_write(sc, 59, rf); 3305 } else { 3306 run_rt3070_rf_write(sc, 55, 0x44); 3307 run_rt3070_rf_write(sc, 59, 0x8f); 3308 } 3309 } 3310 3311 /* Enable VCO calibration. */ 3312 run_rt3070_rf_read(sc, 3, &rf); 3313 rf |= RT5390_VCOCAL; 3314 run_rt3070_rf_write(sc, 3, rf); 3315 } 3316 3317 static void 3318 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3319 { 3320 const struct rt5592_freqs *freqs; 3321 uint32_t tmp; 3322 uint8_t reg, rf, txpow_bound; 3323 int8_t txpow1, txpow2; 3324 int i; 3325 3326 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3327 freqs = (tmp & RT5592_SEL_XTAL) ? 3328 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3329 3330 /* find the settings for this channel (we know it exists) */ 3331 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3332 3333 /* use Tx power values from EEPROM */ 3334 txpow1 = sc->txpow1[i]; 3335 txpow2 = sc->txpow2[i]; 3336 3337 run_read(sc, RT3070_LDO_CFG0, &tmp); 3338 tmp &= ~0x1c000000; 3339 if (chan > 14) 3340 tmp |= 0x14000000; 3341 run_write(sc, RT3070_LDO_CFG0, tmp); 3342 3343 /* N setting. */ 3344 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3345 run_rt3070_rf_read(sc, 9, &rf); 3346 rf &= ~(1 << 4); 3347 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3348 run_rt3070_rf_write(sc, 9, rf); 3349 3350 /* K setting. */ 3351 run_rt3070_rf_read(sc, 9, &rf); 3352 rf &= ~0x0f; 3353 rf |= (freqs->k & 0x0f); 3354 run_rt3070_rf_write(sc, 9, rf); 3355 3356 /* Mode setting. */ 3357 run_rt3070_rf_read(sc, 11, &rf); 3358 rf &= ~0x0c; 3359 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3360 run_rt3070_rf_write(sc, 11, rf); 3361 run_rt3070_rf_read(sc, 9, &rf); 3362 rf &= ~(1 << 7); 3363 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3364 run_rt3070_rf_write(sc, 9, rf); 3365 3366 /* R setting. */ 3367 run_rt3070_rf_read(sc, 11, &rf); 3368 rf &= ~0x03; 3369 rf |= (freqs->r - 0x1); 3370 run_rt3070_rf_write(sc, 11, rf); 3371 3372 if (chan <= 14) { 3373 /* Initialize RF registers for 2GHZ. */ 3374 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3375 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3376 rt5592_2ghz_def_rf[i].val); 3377 } 3378 3379 rf = (chan <= 10) ? 0x07 : 0x06; 3380 run_rt3070_rf_write(sc, 23, rf); 3381 run_rt3070_rf_write(sc, 59, rf); 3382 3383 run_rt3070_rf_write(sc, 55, 0x43); 3384 3385 /* 3386 * RF R49/R50 Tx power ALC code. 3387 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3388 */ 3389 reg = 2; 3390 txpow_bound = 0x27; 3391 } else { 3392 /* Initialize RF registers for 5GHZ. */ 3393 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3394 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3395 rt5592_5ghz_def_rf[i].val); 3396 } 3397 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3398 if (chan >= rt5592_chan_5ghz[i].firstchan && 3399 chan <= rt5592_chan_5ghz[i].lastchan) { 3400 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3401 rt5592_chan_5ghz[i].val); 3402 } 3403 } 3404 3405 /* 3406 * RF R49/R50 Tx power ALC code. 3407 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3408 */ 3409 reg = 3; 3410 txpow_bound = 0x2b; 3411 } 3412 3413 /* RF R49 ch0 Tx power ALC code. */ 3414 run_rt3070_rf_read(sc, 49, &rf); 3415 rf &= ~0xc0; 3416 rf |= (reg << 6); 3417 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3418 if ((rf & 0x3f) > txpow_bound) 3419 rf = (rf & ~0x3f) | txpow_bound; 3420 run_rt3070_rf_write(sc, 49, rf); 3421 3422 /* RF R50 ch1 Tx power ALC code. */ 3423 run_rt3070_rf_read(sc, 50, &rf); 3424 rf &= ~(1 << 7 | 1 << 6); 3425 rf |= (reg << 6); 3426 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3427 if ((rf & 0x3f) > txpow_bound) 3428 rf = (rf & ~0x3f) | txpow_bound; 3429 run_rt3070_rf_write(sc, 50, rf); 3430 3431 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3432 run_rt3070_rf_read(sc, 1, &rf); 3433 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3434 if (sc->ntxchains > 1) 3435 rf |= RT3070_TX1_PD; 3436 if (sc->nrxchains > 1) 3437 rf |= RT3070_RX1_PD; 3438 run_rt3070_rf_write(sc, 1, rf); 3439 3440 run_rt3070_rf_write(sc, 6, 0xe4); 3441 3442 run_rt3070_rf_write(sc, 30, 0x10); 3443 run_rt3070_rf_write(sc, 31, 0x80); 3444 run_rt3070_rf_write(sc, 32, 0x80); 3445 3446 run_adjust_freq_offset(sc); 3447 3448 /* Enable VCO calibration. */ 3449 run_rt3070_rf_read(sc, 3, &rf); 3450 rf |= RT5390_VCOCAL; 3451 run_rt3070_rf_write(sc, 3, rf); 3452 } 3453 3454 static void 3455 run_iq_calib(struct run_softc *sc, u_int chan) 3456 { 3457 uint16_t val; 3458 3459 /* Tx0 IQ gain. */ 3460 run_bbp_write(sc, 158, 0x2c); 3461 if (chan <= 14) 3462 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3463 else if (chan <= 64) { 3464 run_efuse_read(sc, 3465 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3466 &val, 1); 3467 } else if (chan <= 138) { 3468 run_efuse_read(sc, 3469 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3470 &val, 1); 3471 } else if (chan <= 165) { 3472 run_efuse_read(sc, 3473 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3474 &val, 1); 3475 } else 3476 val = 0; 3477 run_bbp_write(sc, 159, val); 3478 3479 /* Tx0 IQ phase. */ 3480 run_bbp_write(sc, 158, 0x2d); 3481 if (chan <= 14) { 3482 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3483 &val, 1); 3484 } else if (chan <= 64) { 3485 run_efuse_read(sc, 3486 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3487 &val, 1); 3488 } else if (chan <= 138) { 3489 run_efuse_read(sc, 3490 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3491 &val, 1); 3492 } else if (chan <= 165) { 3493 run_efuse_read(sc, 3494 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3495 &val, 1); 3496 } else 3497 val = 0; 3498 run_bbp_write(sc, 159, val); 3499 3500 /* Tx1 IQ gain. */ 3501 run_bbp_write(sc, 158, 0x4a); 3502 if (chan <= 14) { 3503 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3504 &val, 1); 3505 } else if (chan <= 64) { 3506 run_efuse_read(sc, 3507 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3508 &val, 1); 3509 } else if (chan <= 138) { 3510 run_efuse_read(sc, 3511 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3512 &val, 1); 3513 } else if (chan <= 165) { 3514 run_efuse_read(sc, 3515 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3516 &val, 1); 3517 } else 3518 val = 0; 3519 run_bbp_write(sc, 159, val); 3520 3521 /* Tx1 IQ phase. */ 3522 run_bbp_write(sc, 158, 0x4b); 3523 if (chan <= 14) { 3524 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3525 &val, 1); 3526 } else if (chan <= 64) { 3527 run_efuse_read(sc, 3528 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3529 &val, 1); 3530 } else if (chan <= 138) { 3531 run_efuse_read(sc, 3532 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3533 &val, 1); 3534 } else if (chan <= 165) { 3535 run_efuse_read(sc, 3536 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3537 &val, 1); 3538 } else 3539 val = 0; 3540 run_bbp_write(sc, 159, val); 3541 3542 /* RF IQ compensation control. */ 3543 run_bbp_write(sc, 158, 0x04); 3544 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3545 &val, 1); 3546 run_bbp_write(sc, 159, val); 3547 3548 /* RF IQ imbalance compensation control. */ 3549 run_bbp_write(sc, 158, 0x03); 3550 run_efuse_read(sc, 3551 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3552 run_bbp_write(sc, 159, val); 3553 } 3554 3555 static void 3556 run_set_agc(struct run_softc *sc, uint8_t agc) 3557 { 3558 uint8_t bbp; 3559 3560 if (sc->mac_ver == 0x3572) { 3561 run_bbp_read(sc, 27, &bbp); 3562 bbp &= ~(0x3 << 5); 3563 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3564 run_bbp_write(sc, 66, agc); 3565 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3566 run_bbp_write(sc, 66, agc); 3567 } else 3568 run_bbp_write(sc, 66, agc); 3569 } 3570 3571 static void 3572 run_set_rx_antenna(struct run_softc *sc, int aux) 3573 { 3574 uint32_t tmp; 3575 uint8_t bbp152; 3576 3577 if (sc->rf_rev == RT5390_RF_5370) { 3578 run_bbp_read(sc, 152, &bbp152); 3579 bbp152 &= ~0x80; 3580 if (aux) 3581 bbp152 |= 0x80; 3582 run_bbp_write(sc, 152, bbp152); 3583 } else { 3584 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3585 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3586 tmp &= ~0x0808; 3587 if (aux) 3588 tmp |= 0x08; 3589 run_write(sc, RT2860_GPIO_CTRL, tmp); 3590 } 3591 } 3592 3593 static int 3594 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3595 { 3596 struct ieee80211com *ic = &sc->sc_ic; 3597 u_int chan, group; 3598 3599 chan = ieee80211_chan2ieee(ic, c); 3600 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3601 return EINVAL; 3602 3603 if (sc->mac_ver == 0x5592) 3604 run_rt5592_set_chan(sc, chan); 3605 else if (sc->mac_ver >= 0x5390) 3606 run_rt5390_set_chan(sc, chan); 3607 else if (sc->mac_ver == 0x3593) 3608 run_rt3593_set_chan(sc, chan); 3609 else if (sc->mac_ver == 0x3572) 3610 run_rt3572_set_chan(sc, chan); 3611 else if (sc->mac_ver >= 0x3070) 3612 run_rt3070_set_chan(sc, chan); 3613 else 3614 run_rt2870_set_chan(sc, chan); 3615 3616 /* determine channel group */ 3617 if (chan <= 14) 3618 group = 0; 3619 else if (chan <= 64) 3620 group = 1; 3621 else if (chan <= 128) 3622 group = 2; 3623 else 3624 group = 3; 3625 3626 /* XXX necessary only when group has changed! */ 3627 run_select_chan_group(sc, group); 3628 3629 usbd_delay_ms(sc->sc_udev, 10); 3630 3631 /* Perform IQ calibration. */ 3632 if (sc->mac_ver >= 0x5392) 3633 run_iq_calib(sc, chan); 3634 3635 return 0; 3636 } 3637 3638 static void 3639 run_updateprot(struct run_softc *sc) 3640 { 3641 struct ieee80211com *ic = &sc->sc_ic; 3642 uint32_t tmp; 3643 3644 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3645 /* setup protection frame rate (MCS code) */ 3646 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3647 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3648 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3649 3650 /* CCK frames don't require protection */ 3651 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3652 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3653 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3654 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3655 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3656 tmp |= RT2860_PROT_CTRL_CTS; 3657 } 3658 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3659 } 3660 3661 static void 3662 run_enable_tsf_sync(struct run_softc *sc) 3663 { 3664 struct ieee80211com *ic = &sc->sc_ic; 3665 uint32_t tmp; 3666 3667 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3668 tmp &= ~0x1fffff; 3669 tmp |= ic->ic_bss->ni_intval * 16; 3670 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3671 if (ic->ic_opmode == IEEE80211_M_STA) { 3672 /* 3673 * Local TSF is always updated with remote TSF on beacon 3674 * reception. 3675 */ 3676 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3677 } 3678 #ifndef IEEE80211_STA_ONLY 3679 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3680 tmp |= RT2860_BCN_TX_EN; 3681 /* 3682 * Local TSF is updated with remote TSF on beacon reception 3683 * only if the remote TSF is greater than local TSF. 3684 */ 3685 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3686 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3687 tmp |= RT2860_BCN_TX_EN; 3688 /* SYNC with nobody */ 3689 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3690 } 3691 #endif 3692 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3693 } 3694 3695 static void 3696 run_enable_mrr(struct run_softc *sc) 3697 { 3698 #define CCK(mcs) (mcs) 3699 #define OFDM(mcs) (1 << 3 | (mcs)) 3700 run_write(sc, RT2860_LG_FBK_CFG0, 3701 OFDM(6) << 28 | /* 54->48 */ 3702 OFDM(5) << 24 | /* 48->36 */ 3703 OFDM(4) << 20 | /* 36->24 */ 3704 OFDM(3) << 16 | /* 24->18 */ 3705 OFDM(2) << 12 | /* 18->12 */ 3706 OFDM(1) << 8 | /* 12-> 9 */ 3707 OFDM(0) << 4 | /* 9-> 6 */ 3708 OFDM(0)); /* 6-> 6 */ 3709 3710 run_write(sc, RT2860_LG_FBK_CFG1, 3711 CCK(2) << 12 | /* 11->5.5 */ 3712 CCK(1) << 8 | /* 5.5-> 2 */ 3713 CCK(0) << 4 | /* 2-> 1 */ 3714 CCK(0)); /* 1-> 1 */ 3715 #undef OFDM 3716 #undef CCK 3717 } 3718 3719 static void 3720 run_set_txpreamble(struct run_softc *sc) 3721 { 3722 uint32_t tmp; 3723 3724 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3725 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3726 tmp |= RT2860_CCK_SHORT_EN; 3727 else 3728 tmp &= ~RT2860_CCK_SHORT_EN; 3729 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3730 } 3731 3732 static void 3733 run_set_basicrates(struct run_softc *sc) 3734 { 3735 struct ieee80211com *ic = &sc->sc_ic; 3736 3737 /* set basic rates mask */ 3738 if (ic->ic_curmode == IEEE80211_MODE_11B) 3739 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3740 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3741 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3742 else /* 11g */ 3743 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3744 } 3745 3746 static void 3747 run_set_leds(struct run_softc *sc, uint16_t which) 3748 { 3749 3750 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3751 which | (sc->leds & 0x7f)); 3752 } 3753 3754 static void 3755 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3756 { 3757 3758 run_write(sc, RT2860_MAC_BSSID_DW0, 3759 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3760 run_write(sc, RT2860_MAC_BSSID_DW1, 3761 bssid[4] | bssid[5] << 8); 3762 } 3763 3764 static void 3765 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3766 { 3767 3768 run_write(sc, RT2860_MAC_ADDR_DW0, 3769 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3770 run_write(sc, RT2860_MAC_ADDR_DW1, 3771 addr[4] | addr[5] << 8 | 0xff << 16); 3772 } 3773 3774 static void 3775 run_updateslot(struct ifnet *ifp) 3776 { 3777 3778 /* do it in a process context */ 3779 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3780 } 3781 3782 /* ARGSUSED */ 3783 static void 3784 run_updateslot_cb(struct run_softc *sc, void *arg) 3785 { 3786 uint32_t tmp; 3787 3788 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3789 tmp &= ~0xff; 3790 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3791 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3792 } 3793 3794 static int8_t 3795 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3796 { 3797 struct ieee80211com *ic = &sc->sc_ic; 3798 struct ieee80211_channel *c = ic->ic_curchan; 3799 int delta; 3800 3801 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3802 u_int chan = ieee80211_chan2ieee(ic, c); 3803 delta = sc->rssi_5ghz[rxchain]; 3804 3805 /* determine channel group */ 3806 if (chan <= 64) 3807 delta -= sc->lna[1]; 3808 else if (chan <= 128) 3809 delta -= sc->lna[2]; 3810 else 3811 delta -= sc->lna[3]; 3812 } else 3813 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3814 3815 return -12 - delta - rssi; 3816 } 3817 3818 static void 3819 run_rt5390_bbp_init(struct run_softc *sc) 3820 { 3821 u_int i; 3822 uint8_t bbp; 3823 3824 /* Apply maximum likelihood detection for 2 stream case. */ 3825 run_bbp_read(sc, 105, &bbp); 3826 if (sc->nrxchains > 1) 3827 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3828 3829 /* Avoid data lost and CRC error. */ 3830 run_bbp_read(sc, 4, &bbp); 3831 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3832 3833 if (sc->mac_ver == 0x5592) { 3834 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3835 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3836 rt5592_def_bbp[i].val); 3837 } 3838 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3839 run_bbp_write(sc, 195, i + 0x80); 3840 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3841 } 3842 } else { 3843 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3844 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3845 rt5390_def_bbp[i].val); 3846 } 3847 } 3848 if (sc->mac_ver == 0x5392) { 3849 run_bbp_write(sc, 88, 0x90); 3850 run_bbp_write(sc, 95, 0x9a); 3851 run_bbp_write(sc, 98, 0x12); 3852 run_bbp_write(sc, 106, 0x12); 3853 run_bbp_write(sc, 134, 0xd0); 3854 run_bbp_write(sc, 135, 0xf6); 3855 run_bbp_write(sc, 148, 0x84); 3856 } 3857 3858 run_bbp_read(sc, 152, &bbp); 3859 run_bbp_write(sc, 152, bbp | 0x80); 3860 3861 /* Fix BBP254 for RT5592C. */ 3862 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3863 run_bbp_read(sc, 254, &bbp); 3864 run_bbp_write(sc, 254, bbp | 0x80); 3865 } 3866 3867 /* Disable hardware antenna diversity. */ 3868 if (sc->mac_ver == 0x5390) 3869 run_bbp_write(sc, 154, 0); 3870 3871 /* Initialize Rx CCK/OFDM frequency offset report. */ 3872 run_bbp_write(sc, 142, 1); 3873 run_bbp_write(sc, 143, 57); 3874 } 3875 3876 static int 3877 run_bbp_init(struct run_softc *sc) 3878 { 3879 int i, error, ntries; 3880 uint8_t bbp0; 3881 3882 /* wait for BBP to wake up */ 3883 for (ntries = 0; ntries < 20; ntries++) { 3884 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3885 return error; 3886 if (bbp0 != 0 && bbp0 != 0xff) 3887 break; 3888 } 3889 if (ntries == 20) 3890 return ETIMEDOUT; 3891 3892 /* initialize BBP registers to default values */ 3893 if (sc->mac_ver >= 0x5390) 3894 run_rt5390_bbp_init(sc); 3895 else { 3896 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3897 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3898 rt2860_def_bbp[i].val); 3899 } 3900 } 3901 3902 if (sc->mac_ver == 0x3593) { 3903 run_bbp_write(sc, 79, 0x13); 3904 run_bbp_write(sc, 80, 0x05); 3905 run_bbp_write(sc, 81, 0x33); 3906 run_bbp_write(sc, 86, 0x46); 3907 run_bbp_write(sc, 137, 0x0f); 3908 } 3909 3910 /* fix BBP84 for RT2860E */ 3911 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3912 run_bbp_write(sc, 84, 0x19); 3913 3914 if (sc->mac_ver >= 0x3070) { 3915 run_bbp_write(sc, 79, 0x13); 3916 run_bbp_write(sc, 80, 0x05); 3917 run_bbp_write(sc, 81, 0x33); 3918 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3919 run_bbp_write(sc, 69, 0x16); 3920 run_bbp_write(sc, 73, 0x12); 3921 } 3922 return 0; 3923 } 3924 3925 static int 3926 run_rt3070_rf_init(struct run_softc *sc) 3927 { 3928 uint32_t tmp; 3929 uint8_t rf, target, bbp4; 3930 int i; 3931 3932 run_rt3070_rf_read(sc, 30, &rf); 3933 /* toggle RF R30 bit 7 */ 3934 run_rt3070_rf_write(sc, 30, rf | 0x80); 3935 usbd_delay_ms(sc->sc_udev, 10); 3936 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3937 3938 /* initialize RF registers to default value */ 3939 if (sc->mac_ver == 0x3572) { 3940 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 3941 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3942 rt3572_def_rf[i].val); 3943 } 3944 } else { 3945 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 3946 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3947 rt3070_def_rf[i].val); 3948 } 3949 } 3950 if (sc->mac_ver == 0x3572) { 3951 run_rt3070_rf_read(sc, 6, &rf); 3952 run_rt3070_rf_write(sc, 6, rf | 0x40); 3953 run_rt3070_rf_write(sc, 31, 0x14); 3954 3955 run_read(sc, RT3070_LDO_CFG0, &tmp); 3956 tmp &= ~0x1f000000; 3957 if (sc->mac_rev < 0x0211 && sc->patch_dac) 3958 tmp |= 0x0d000000; /* 1.3V */ 3959 else 3960 tmp |= 0x01000000; /* 1.2V */ 3961 run_write(sc, RT3070_LDO_CFG0, tmp); 3962 } else if (sc->mac_ver == 0x3071) { 3963 run_rt3070_rf_read(sc, 6, &rf); 3964 run_rt3070_rf_write(sc, 6, rf | 0x40); 3965 run_rt3070_rf_write(sc, 31, 0x14); 3966 3967 run_read(sc, RT3070_LDO_CFG0, &tmp); 3968 tmp &= ~0x1f000000; 3969 if (sc->mac_rev < 0x0211) 3970 tmp |= 0x0d000000; /* 1.35V */ 3971 else 3972 tmp |= 0x01000000; /* 1.2V */ 3973 run_write(sc, RT3070_LDO_CFG0, tmp); 3974 3975 /* patch LNA_PE_G1 */ 3976 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3977 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3978 } else if (sc->mac_ver == 0x3070) { 3979 /* increase voltage from 1.2V to 1.35V */ 3980 run_read(sc, RT3070_LDO_CFG0, &tmp); 3981 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3982 run_write(sc, RT3070_LDO_CFG0, tmp); 3983 } 3984 3985 /* select 20MHz bandwidth */ 3986 run_rt3070_rf_read(sc, 31, &rf); 3987 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3988 3989 /* calibrate filter for 20MHz bandwidth */ 3990 sc->rf24_20mhz = 0x1f; /* default value */ 3991 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3992 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3993 3994 /* select 40MHz bandwidth */ 3995 run_bbp_read(sc, 4, &bbp4); 3996 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 3997 run_rt3070_rf_read(sc, 31, &rf); 3998 run_rt3070_rf_write(sc, 31, rf | 0x20); 3999 4000 /* calibrate filter for 40MHz bandwidth */ 4001 sc->rf24_40mhz = 0x2f; /* default value */ 4002 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4003 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4004 4005 /* go back to 20MHz bandwidth */ 4006 run_bbp_read(sc, 4, &bbp4); 4007 run_bbp_write(sc, 4, bbp4 & ~0x18); 4008 4009 if (sc->mac_ver == 0x3572) { 4010 /* save default BBP registers 25 and 26 values */ 4011 run_bbp_read(sc, 25, &sc->bbp25); 4012 run_bbp_read(sc, 26, &sc->bbp26); 4013 } else if (sc->mac_rev < 0x0211) 4014 run_rt3070_rf_write(sc, 27, 0x03); 4015 4016 run_read(sc, RT3070_OPT_14, &tmp); 4017 run_write(sc, RT3070_OPT_14, tmp | 1); 4018 4019 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4020 run_rt3070_rf_read(sc, 17, &rf); 4021 rf &= ~RT3070_TX_LO1; 4022 if ((sc->mac_ver == 0x3070 || 4023 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4024 !sc->ext_2ghz_lna) 4025 rf |= 0x20; /* fix for long range Rx issue */ 4026 if (sc->txmixgain_2ghz >= 1) 4027 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4028 run_rt3070_rf_write(sc, 17, rf); 4029 } 4030 if (sc->mac_ver == 0x3071) { 4031 run_rt3070_rf_read(sc, 1, &rf); 4032 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4033 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4034 run_rt3070_rf_write(sc, 1, rf); 4035 4036 run_rt3070_rf_read(sc, 15, &rf); 4037 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4038 4039 run_rt3070_rf_read(sc, 20, &rf); 4040 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4041 4042 run_rt3070_rf_read(sc, 21, &rf); 4043 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4044 } 4045 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4046 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4047 run_rt3070_rf_read(sc, 27, &rf); 4048 rf &= ~0x77; 4049 if (sc->mac_rev < 0x0211) 4050 rf |= 0x03; 4051 run_rt3070_rf_write(sc, 27, rf); 4052 } 4053 return 0; 4054 } 4055 4056 static int 4057 run_rt3593_rf_init(struct run_softc *sc) 4058 { 4059 uint32_t tmp; 4060 uint8_t rf; 4061 int i; 4062 4063 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4064 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4065 tmp &= ~(1 << 4 | 1 << 7); 4066 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4067 4068 /* Initialize RF registers to default value. */ 4069 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4070 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4071 rt3593_def_rf[i].val); 4072 } 4073 4074 /* Toggle RF R2 to initiate calibration. */ 4075 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4076 4077 /* Initialize RF frequency offset. */ 4078 run_adjust_freq_offset(sc); 4079 4080 run_rt3070_rf_read(sc, 18, &rf); 4081 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4082 4083 /* 4084 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4085 * decrease voltage back to 1.2V. 4086 */ 4087 run_read(sc, RT3070_LDO_CFG0, &tmp); 4088 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4089 run_write(sc, RT3070_LDO_CFG0, tmp); 4090 usbd_delay_ms(sc->sc_udev, 1); 4091 tmp = (tmp & ~0x1f000000) | 0x01000000; 4092 run_write(sc, RT3070_LDO_CFG0, tmp); 4093 4094 sc->rf24_20mhz = 0x1f; 4095 sc->rf24_40mhz = 0x2f; 4096 4097 /* Save default BBP registers 25 and 26 values. */ 4098 run_bbp_read(sc, 25, &sc->bbp25); 4099 run_bbp_read(sc, 26, &sc->bbp26); 4100 4101 run_read(sc, RT3070_OPT_14, &tmp); 4102 run_write(sc, RT3070_OPT_14, tmp | 1); 4103 return (0); 4104 } 4105 4106 static int 4107 run_rt5390_rf_init(struct run_softc *sc) 4108 { 4109 uint32_t tmp; 4110 uint8_t rf; 4111 int i; 4112 4113 /* Toggle RF R2 to initiate calibration. */ 4114 if (sc->mac_ver == 0x5390) { 4115 run_rt3070_rf_read(sc, 2, &rf); 4116 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4117 usbd_delay_ms(sc->sc_udev, 10); 4118 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4119 } else { 4120 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4121 usbd_delay_ms(sc->sc_udev, 10); 4122 } 4123 4124 /* Initialize RF registers to default value. */ 4125 if (sc->mac_ver == 0x5592) { 4126 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4127 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4128 rt5592_def_rf[i].val); 4129 } 4130 /* Initialize RF frequency offset. */ 4131 run_adjust_freq_offset(sc); 4132 } else if (sc->mac_ver == 0x5392) { 4133 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4134 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4135 rt5392_def_rf[i].val); 4136 } 4137 if (sc->mac_rev >= 0x0223) { 4138 run_rt3070_rf_write(sc, 23, 0x0f); 4139 run_rt3070_rf_write(sc, 24, 0x3e); 4140 run_rt3070_rf_write(sc, 51, 0x32); 4141 run_rt3070_rf_write(sc, 53, 0x22); 4142 run_rt3070_rf_write(sc, 56, 0xc1); 4143 run_rt3070_rf_write(sc, 59, 0x0f); 4144 } 4145 } else { 4146 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4147 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4148 rt5390_def_rf[i].val); 4149 } 4150 if (sc->mac_rev >= 0x0502) { 4151 run_rt3070_rf_write(sc, 6, 0xe0); 4152 run_rt3070_rf_write(sc, 25, 0x80); 4153 run_rt3070_rf_write(sc, 46, 0x73); 4154 run_rt3070_rf_write(sc, 53, 0x00); 4155 run_rt3070_rf_write(sc, 56, 0x42); 4156 run_rt3070_rf_write(sc, 61, 0xd1); 4157 } 4158 } 4159 4160 sc->rf24_20mhz = 0x1f; /* default value */ 4161 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4162 4163 if (sc->mac_rev < 0x0211) 4164 run_rt3070_rf_write(sc, 27, 0x3); 4165 4166 run_read(sc, RT3070_OPT_14, &tmp); 4167 run_write(sc, RT3070_OPT_14, tmp | 1); 4168 return (0); 4169 } 4170 4171 static int 4172 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4173 uint8_t *val) 4174 { 4175 uint8_t rf22, rf24; 4176 uint8_t bbp55_pb, bbp55_sb, delta; 4177 int ntries; 4178 4179 /* program filter */ 4180 run_rt3070_rf_read(sc, 24, &rf24); 4181 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4182 run_rt3070_rf_write(sc, 24, rf24); 4183 4184 /* enable baseband loopback mode */ 4185 run_rt3070_rf_read(sc, 22, &rf22); 4186 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4187 4188 /* set power and frequency of passband test tone */ 4189 run_bbp_write(sc, 24, 0x00); 4190 for (ntries = 0; ntries < 100; ntries++) { 4191 /* transmit test tone */ 4192 run_bbp_write(sc, 25, 0x90); 4193 usbd_delay_ms(sc->sc_udev, 10); 4194 /* read received power */ 4195 run_bbp_read(sc, 55, &bbp55_pb); 4196 if (bbp55_pb != 0) 4197 break; 4198 } 4199 if (ntries == 100) 4200 return ETIMEDOUT; 4201 4202 /* set power and frequency of stopband test tone */ 4203 run_bbp_write(sc, 24, 0x06); 4204 for (ntries = 0; ntries < 100; ntries++) { 4205 /* transmit test tone */ 4206 run_bbp_write(sc, 25, 0x90); 4207 usbd_delay_ms(sc->sc_udev, 10); 4208 /* read received power */ 4209 run_bbp_read(sc, 55, &bbp55_sb); 4210 4211 delta = bbp55_pb - bbp55_sb; 4212 if (delta > target) 4213 break; 4214 4215 /* reprogram filter */ 4216 rf24++; 4217 run_rt3070_rf_write(sc, 24, rf24); 4218 } 4219 if (ntries < 100) { 4220 if (rf24 != init) 4221 rf24--; /* backtrack */ 4222 *val = rf24; 4223 run_rt3070_rf_write(sc, 24, rf24); 4224 } 4225 4226 /* restore initial state */ 4227 run_bbp_write(sc, 24, 0x00); 4228 4229 /* disable baseband loopback mode */ 4230 run_rt3070_rf_read(sc, 22, &rf22); 4231 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4232 4233 return 0; 4234 } 4235 4236 static void 4237 run_rt3070_rf_setup(struct run_softc *sc) 4238 { 4239 uint8_t bbp, rf; 4240 int i; 4241 4242 if (sc->mac_ver == 0x3572) { 4243 /* enable DC filter */ 4244 if (sc->mac_rev >= 0x0201) 4245 run_bbp_write(sc, 103, 0xc0); 4246 4247 run_bbp_read(sc, 138, &bbp); 4248 if (sc->ntxchains == 1) 4249 bbp |= 0x20; /* turn off DAC1 */ 4250 if (sc->nrxchains == 1) 4251 bbp &= ~0x02; /* turn off ADC1 */ 4252 run_bbp_write(sc, 138, bbp); 4253 4254 if (sc->mac_rev >= 0x0211) { 4255 /* improve power consumption */ 4256 run_bbp_read(sc, 31, &bbp); 4257 run_bbp_write(sc, 31, bbp & ~0x03); 4258 } 4259 4260 run_rt3070_rf_read(sc, 16, &rf); 4261 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4262 run_rt3070_rf_write(sc, 16, rf); 4263 } else if (sc->mac_ver == 0x3071) { 4264 /* enable DC filter */ 4265 if (sc->mac_rev >= 0x0201) 4266 run_bbp_write(sc, 103, 0xc0); 4267 4268 run_bbp_read(sc, 138, &bbp); 4269 if (sc->ntxchains == 1) 4270 bbp |= 0x20; /* turn off DAC1 */ 4271 if (sc->nrxchains == 1) 4272 bbp &= ~0x02; /* turn off ADC1 */ 4273 run_bbp_write(sc, 138, bbp); 4274 4275 if (sc->mac_rev >= 0x0211) { 4276 /* improve power consumption */ 4277 run_bbp_read(sc, 31, &bbp); 4278 run_bbp_write(sc, 31, bbp & ~0x03); 4279 } 4280 4281 run_write(sc, RT2860_TX_SW_CFG1, 0); 4282 if (sc->mac_rev < 0x0211) { 4283 run_write(sc, RT2860_TX_SW_CFG2, 4284 sc->patch_dac ? 0x2c : 0x0f); 4285 } else 4286 run_write(sc, RT2860_TX_SW_CFG2, 0); 4287 } else if (sc->mac_ver == 0x3070) { 4288 if (sc->mac_rev >= 0x0201) { 4289 /* enable DC filter */ 4290 run_bbp_write(sc, 103, 0xc0); 4291 4292 /* improve power consumption */ 4293 run_bbp_read(sc, 31, &bbp); 4294 run_bbp_write(sc, 31, bbp & ~0x03); 4295 } 4296 4297 if (sc->mac_rev < 0x0211) { 4298 run_write(sc, RT2860_TX_SW_CFG1, 0); 4299 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4300 } else 4301 run_write(sc, RT2860_TX_SW_CFG2, 0); 4302 } 4303 4304 /* initialize RF registers from ROM for >=RT3071*/ 4305 if (sc->mac_ver >= 0x3071) { 4306 for (i = 0; i < 10; i++) { 4307 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4308 continue; 4309 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4310 } 4311 } 4312 } 4313 4314 static void 4315 run_rt3593_rf_setup(struct run_softc *sc) 4316 { 4317 uint8_t bbp, rf; 4318 4319 if (sc->mac_rev >= 0x0211) { 4320 /* Enable DC filter. */ 4321 run_bbp_write(sc, 103, 0xc0); 4322 } 4323 run_write(sc, RT2860_TX_SW_CFG1, 0); 4324 if (sc->mac_rev < 0x0211) { 4325 run_write(sc, RT2860_TX_SW_CFG2, 4326 sc->patch_dac ? 0x2c : 0x0f); 4327 } else 4328 run_write(sc, RT2860_TX_SW_CFG2, 0); 4329 4330 run_rt3070_rf_read(sc, 50, &rf); 4331 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4332 4333 run_rt3070_rf_read(sc, 51, &rf); 4334 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4335 ((sc->txmixgain_2ghz & 0x07) << 2); 4336 run_rt3070_rf_write(sc, 51, rf); 4337 4338 run_rt3070_rf_read(sc, 38, &rf); 4339 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4340 4341 run_rt3070_rf_read(sc, 39, &rf); 4342 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4343 4344 run_rt3070_rf_read(sc, 1, &rf); 4345 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4346 4347 run_rt3070_rf_read(sc, 30, &rf); 4348 rf = (rf & ~0x18) | 0x10; 4349 run_rt3070_rf_write(sc, 30, rf); 4350 4351 /* Apply maximum likelihood detection for 2 stream case. */ 4352 run_bbp_read(sc, 105, &bbp); 4353 if (sc->nrxchains > 1) 4354 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4355 4356 /* Avoid data lost and CRC error. */ 4357 run_bbp_read(sc, 4, &bbp); 4358 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4359 4360 run_bbp_write(sc, 92, 0x02); 4361 run_bbp_write(sc, 82, 0x82); 4362 run_bbp_write(sc, 106, 0x05); 4363 run_bbp_write(sc, 104, 0x92); 4364 run_bbp_write(sc, 88, 0x90); 4365 run_bbp_write(sc, 148, 0xc8); 4366 run_bbp_write(sc, 47, 0x48); 4367 run_bbp_write(sc, 120, 0x50); 4368 4369 run_bbp_write(sc, 163, 0x9d); 4370 4371 /* SNR mapping. */ 4372 run_bbp_write(sc, 142, 0x06); 4373 run_bbp_write(sc, 143, 0xa0); 4374 run_bbp_write(sc, 142, 0x07); 4375 run_bbp_write(sc, 143, 0xa1); 4376 run_bbp_write(sc, 142, 0x08); 4377 run_bbp_write(sc, 143, 0xa2); 4378 4379 run_bbp_write(sc, 31, 0x08); 4380 run_bbp_write(sc, 68, 0x0b); 4381 run_bbp_write(sc, 105, 0x04); 4382 } 4383 4384 static void 4385 run_rt5390_rf_setup(struct run_softc *sc) 4386 { 4387 uint8_t bbp, rf; 4388 4389 if (sc->mac_rev >= 0x0211) { 4390 /* Enable DC filter. */ 4391 run_bbp_write(sc, 103, 0xc0); 4392 4393 if (sc->mac_ver != 0x5592) { 4394 /* Improve power consumption. */ 4395 run_bbp_read(sc, 31, &bbp); 4396 run_bbp_write(sc, 31, bbp & ~0x03); 4397 } 4398 } 4399 4400 run_bbp_read(sc, 138, &bbp); 4401 if (sc->ntxchains == 1) 4402 bbp |= 0x20; /* turn off DAC1 */ 4403 if (sc->nrxchains == 1) 4404 bbp &= ~0x02; /* turn off ADC1 */ 4405 run_bbp_write(sc, 138, bbp); 4406 4407 run_rt3070_rf_read(sc, 38, &rf); 4408 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4409 4410 run_rt3070_rf_read(sc, 39, &rf); 4411 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4412 4413 /* Avoid data lost and CRC error. */ 4414 run_bbp_read(sc, 4, &bbp); 4415 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4416 4417 run_rt3070_rf_read(sc, 30, &rf); 4418 rf = (rf & ~0x18) | 0x10; 4419 run_rt3070_rf_write(sc, 30, rf); 4420 4421 if (sc->mac_ver != 0x5592) { 4422 run_write(sc, RT2860_TX_SW_CFG1, 0); 4423 if (sc->mac_rev < 0x0211) { 4424 run_write(sc, RT2860_TX_SW_CFG2, 4425 sc->patch_dac ? 0x2c : 0x0f); 4426 } else 4427 run_write(sc, RT2860_TX_SW_CFG2, 0); 4428 } 4429 } 4430 4431 static int 4432 run_txrx_enable(struct run_softc *sc) 4433 { 4434 uint32_t tmp; 4435 int error, ntries; 4436 4437 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4438 for (ntries = 0; ntries < 200; ntries++) { 4439 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4440 return error; 4441 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4442 break; 4443 usbd_delay_ms(sc->sc_udev, 50); 4444 } 4445 if (ntries == 200) 4446 return ETIMEDOUT; 4447 4448 usbd_delay_ms(sc->sc_udev, 50); 4449 4450 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4451 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4452 4453 /* enable Rx bulk aggregation (set timeout and limit) */ 4454 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4455 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4456 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4457 4458 /* set Rx filter */ 4459 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4460 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4461 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4462 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4463 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4464 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4465 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4466 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4467 } 4468 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4469 4470 run_write(sc, RT2860_MAC_SYS_CTRL, 4471 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4472 4473 return 0; 4474 } 4475 4476 static int 4477 run_adjust_freq_offset(struct run_softc *sc) 4478 { 4479 uint8_t rf, tmp; 4480 4481 run_rt3070_rf_read(sc, 17, &rf); 4482 tmp = rf; 4483 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4484 rf = MIN(rf, 0x5f); 4485 4486 if (tmp != rf) 4487 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4488 4489 return (0); 4490 } 4491 4492 static int 4493 run_init(struct ifnet *ifp) 4494 { 4495 struct run_softc *sc = ifp->if_softc; 4496 struct ieee80211com *ic = &sc->sc_ic; 4497 uint32_t tmp; 4498 uint8_t bbp1, bbp3; 4499 int i, error, qid, ridx, ntries; 4500 4501 for (ntries = 0; ntries < 100; ntries++) { 4502 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4503 goto fail; 4504 if (tmp != 0 && tmp != 0xffffffff) 4505 break; 4506 usbd_delay_ms(sc->sc_udev, 10); 4507 } 4508 if (ntries == 100) { 4509 error = ETIMEDOUT; 4510 goto fail; 4511 } 4512 4513 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4514 (error = run_load_microcode(sc)) != 0) { 4515 aprint_error_dev(sc->sc_dev, 4516 "could not load 8051 microcode\n"); 4517 goto fail; 4518 } 4519 4520 if (ifp->if_flags & IFF_RUNNING) 4521 run_stop(ifp, 0); 4522 4523 /* init host command ring */ 4524 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4525 4526 /* init Tx rings (4 EDCAs) */ 4527 for (qid = 0; qid < 4; qid++) { 4528 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4529 goto fail; 4530 } 4531 /* init Rx ring */ 4532 if ((error = run_alloc_rx_ring(sc)) != 0) 4533 goto fail; 4534 4535 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4536 run_set_macaddr(sc, ic->ic_myaddr); 4537 4538 for (ntries = 0; ntries < 100; ntries++) { 4539 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4540 goto fail; 4541 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4542 break; 4543 usbd_delay_ms(sc->sc_udev, 10); 4544 } 4545 if (ntries == 100) { 4546 aprint_error_dev(sc->sc_dev, 4547 "timeout waiting for DMA engine\n"); 4548 error = ETIMEDOUT; 4549 goto fail; 4550 } 4551 tmp &= 0xff0; 4552 tmp |= RT2860_TX_WB_DDONE; 4553 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4554 4555 /* turn off PME_OEN to solve high-current issue */ 4556 run_read(sc, RT2860_SYS_CTRL, &tmp); 4557 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4558 4559 run_write(sc, RT2860_MAC_SYS_CTRL, 4560 RT2860_BBP_HRST | RT2860_MAC_SRST); 4561 run_write(sc, RT2860_USB_DMA_CFG, 0); 4562 4563 if ((error = run_reset(sc)) != 0) { 4564 aprint_error_dev(sc->sc_dev, "could not reset chipset\n"); 4565 goto fail; 4566 } 4567 4568 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4569 4570 /* init Tx power for all Tx rates (from EEPROM) */ 4571 for (ridx = 0; ridx < 5; ridx++) { 4572 if (sc->txpow20mhz[ridx] == 0xffffffff) 4573 continue; 4574 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4575 } 4576 4577 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4578 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4579 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4580 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4581 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4582 4583 if (sc->mac_ver >= 0x5390) { 4584 run_write(sc, RT2860_TX_SW_CFG0, 4585 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4586 if (sc->mac_ver >= 0x5392) { 4587 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4588 if (sc->mac_ver == 0x5592) { 4589 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4590 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4591 } else { 4592 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4593 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4594 } 4595 } 4596 } else if (sc->mac_ver >= 0x3593) { 4597 run_write(sc, RT2860_TX_SW_CFG0, 4598 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4599 } else if (sc->mac_ver >= 0x3070) { 4600 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4601 run_write(sc, RT2860_TX_SW_CFG0, 4602 4 << RT2860_DLY_PAPE_EN_SHIFT); 4603 } 4604 4605 /* wait while MAC is busy */ 4606 for (ntries = 0; ntries < 100; ntries++) { 4607 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4608 goto fail; 4609 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4610 break; 4611 DELAY(1000); 4612 } 4613 if (ntries == 100) { 4614 error = ETIMEDOUT; 4615 goto fail; 4616 } 4617 4618 /* clear Host to MCU mailbox */ 4619 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4620 run_write(sc, RT2860_H2M_MAILBOX, 0); 4621 usbd_delay_ms(sc->sc_udev, 10); 4622 4623 if ((error = run_bbp_init(sc)) != 0) { 4624 aprint_error_dev(sc->sc_dev, "could not initialize BBP\n"); 4625 goto fail; 4626 } 4627 4628 /* abort TSF synchronization */ 4629 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4630 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4631 RT2860_TBTT_TIMER_EN); 4632 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4633 4634 /* clear RX WCID search table */ 4635 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4636 /* clear Pair-wise key table */ 4637 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4638 /* clear IV/EIV table */ 4639 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4640 /* clear WCID attribute table */ 4641 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4642 /* clear shared key table */ 4643 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4644 /* clear shared key mode */ 4645 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4646 4647 /* clear RX WCID search table */ 4648 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4649 /* clear WCID attribute table */ 4650 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4651 4652 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4653 tmp = (tmp & ~0xff) | 0x1e; 4654 run_write(sc, RT2860_US_CYC_CNT, tmp); 4655 4656 if (sc->mac_rev != 0x0101) 4657 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4658 4659 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4660 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4661 4662 /* write vendor-specific BBP values (from EEPROM) */ 4663 if (sc->mac_ver < 0x3593) { 4664 for (i = 0; i < 10; i++) { 4665 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4666 continue; 4667 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4668 } 4669 } 4670 4671 /* select Main antenna for 1T1R devices */ 4672 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4673 run_set_rx_antenna(sc, 0); 4674 4675 /* send LEDs operating mode to microcontroller */ 4676 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4677 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4678 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4679 4680 if (sc->mac_ver >= 0x5390) 4681 run_rt5390_rf_init(sc); 4682 else if (sc->mac_ver == 0x3593) 4683 run_rt3593_rf_init(sc); 4684 else if (sc->mac_ver >= 0x3070) 4685 run_rt3070_rf_init(sc); 4686 4687 /* disable non-existing Rx chains */ 4688 run_bbp_read(sc, 3, &bbp3); 4689 bbp3 &= ~(1 << 3 | 1 << 4); 4690 if (sc->nrxchains == 2) 4691 bbp3 |= 1 << 3; 4692 else if (sc->nrxchains == 3) 4693 bbp3 |= 1 << 4; 4694 run_bbp_write(sc, 3, bbp3); 4695 4696 /* disable non-existing Tx chains */ 4697 run_bbp_read(sc, 1, &bbp1); 4698 if (sc->ntxchains == 1) 4699 bbp1 &= ~(1 << 3 | 1 << 4); 4700 run_bbp_write(sc, 1, bbp1); 4701 4702 if (sc->mac_ver >= 0x5390) 4703 run_rt5390_rf_setup(sc); 4704 else if (sc->mac_ver == 0x3593) 4705 run_rt3593_rf_setup(sc); 4706 else if (sc->mac_ver >= 0x3070) 4707 run_rt3070_rf_setup(sc); 4708 4709 /* select default channel */ 4710 run_set_chan(sc, ic->ic_curchan); 4711 4712 /* setup initial protection mode */ 4713 run_updateprot(sc); 4714 4715 /* turn radio LED on */ 4716 run_set_leds(sc, RT2860_LED_RADIO); 4717 4718 #ifdef RUN_HWCRYPTO 4719 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4720 /* install WEP keys */ 4721 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4722 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4723 NULL); 4724 } 4725 #endif 4726 4727 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4728 struct run_rx_data *data = &sc->rxq.data[i]; 4729 4730 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4731 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4732 error = usbd_transfer(data->xfer); 4733 if (error != USBD_NORMAL_COMPLETION && 4734 error != USBD_IN_PROGRESS) 4735 goto fail; 4736 } 4737 4738 if ((error = run_txrx_enable(sc)) != 0) 4739 goto fail; 4740 4741 ifp->if_flags &= ~IFF_OACTIVE; 4742 ifp->if_flags |= IFF_RUNNING; 4743 4744 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4745 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4746 else 4747 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4748 4749 if (error != 0) 4750 fail: run_stop(ifp, 1); 4751 return error; 4752 } 4753 4754 static void 4755 run_stop(struct ifnet *ifp, int disable) 4756 { 4757 struct run_softc *sc = ifp->if_softc; 4758 struct ieee80211com *ic = &sc->sc_ic; 4759 uint32_t tmp; 4760 int ntries, qid; 4761 4762 if (ifp->if_flags & IFF_RUNNING) 4763 run_set_leds(sc, 0); /* turn all LEDs off */ 4764 4765 sc->sc_tx_timer = 0; 4766 ifp->if_timer = 0; 4767 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4768 4769 callout_stop(&sc->scan_to); 4770 callout_stop(&sc->calib_to); 4771 4772 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4773 /* wait for all queued asynchronous commands to complete */ 4774 while (sc->cmdq.queued > 0) 4775 tsleep(&sc->cmdq, 0, "cmdq", 0); 4776 4777 /* disable Tx/Rx */ 4778 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4779 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4780 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4781 4782 /* wait for pending Tx to complete */ 4783 for (ntries = 0; ntries < 100; ntries++) { 4784 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4785 break; 4786 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4787 break; 4788 } 4789 DELAY(1000); 4790 run_write(sc, RT2860_USB_DMA_CFG, 0); 4791 4792 /* reset adapter */ 4793 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4794 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4795 4796 /* reset Tx and Rx rings */ 4797 sc->qfullmsk = 0; 4798 for (qid = 0; qid < 4; qid++) 4799 run_free_tx_ring(sc, qid); 4800 run_free_rx_ring(sc); 4801 } 4802 4803 #ifndef IEEE80211_STA_ONLY 4804 static int 4805 run_setup_beacon(struct run_softc *sc) 4806 { 4807 struct ieee80211com *ic = &sc->sc_ic; 4808 struct rt2860_txwi txwi; 4809 struct mbuf *m; 4810 uint16_t txwisize; 4811 int ridx; 4812 4813 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4814 return ENOBUFS; 4815 4816 memset(&txwi, 0, sizeof(txwi)); 4817 txwi.wcid = 0xff; 4818 txwi.len = htole16(m->m_pkthdr.len); 4819 /* send beacons at the lowest available rate */ 4820 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4821 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4822 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4823 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4824 txwi.phy |= htole16(RT2860_PHY_OFDM); 4825 txwi.txop = RT2860_TX_TXOP_HT; 4826 txwi.flags = RT2860_TX_TS; 4827 4828 txwisize = (sc->mac_ver == 0x5592) ? 4829 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4830 run_write_region_1(sc, RT2860_BCN_BASE(0), 4831 (uint8_t *)&txwi, txwisize); 4832 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4833 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4834 4835 m_freem(m); 4836 4837 return 0; 4838 } 4839 #endif 4840 4841 MODULE(MODULE_CLASS_DRIVER, if_run, "bpf"); 4842 4843 #ifdef _MODULE 4844 #include "ioconf.c" 4845 #endif 4846 4847 static int 4848 if_run_modcmd(modcmd_t cmd, void *arg) 4849 { 4850 int error = 0; 4851 4852 switch (cmd) { 4853 case MODULE_CMD_INIT: 4854 #ifdef _MODULE 4855 error = config_init_component(cfdriver_ioconf_run, 4856 cfattach_ioconf_run, cfdata_ioconf_run); 4857 #endif 4858 return error; 4859 case MODULE_CMD_FINI: 4860 #ifdef _MODULE 4861 error = config_fini_component(cfdriver_ioconf_run, 4862 cfattach_ioconf_run, cfdata_ioconf_run); 4863 #endif 4864 return error; 4865 default: 4866 return ENOTTY; 4867 } 4868 } 4869