1 /* $NetBSD: if_run.c,v 1.36 2020/01/29 06:35:28 thorpej Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.36 2020/01/29 06:35:28 thorpej Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 #include <sys/atomic.h> 45 46 #include <sys/bus.h> 47 #include <machine/endian.h> 48 #include <sys/intr.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/firmload.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usbdi_util.h> 68 #include <dev/usb/usbdevs.h> 69 70 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 71 #include <dev/usb/if_runvar.h> 72 73 #ifdef RUN_DEBUG 74 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 76 int run_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 83 84 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 85 static const struct usb_devno run_devs[] = { 86 USB_ID(ABOCOM, RT2770), 87 USB_ID(ABOCOM, RT2870), 88 USB_ID(ABOCOM, RT3070), 89 USB_ID(ABOCOM, RT3071), 90 USB_ID(ABOCOM, RT3072), 91 USB_ID(ABOCOM2, RT2870_1), 92 USB_ID(ACCTON, RT2770), 93 USB_ID(ACCTON, RT2870_1), 94 USB_ID(ACCTON, RT2870_2), 95 USB_ID(ACCTON, RT2870_3), 96 USB_ID(ACCTON, RT2870_4), 97 USB_ID(ACCTON, RT2870_5), 98 USB_ID(ACCTON, RT3070), 99 USB_ID(ACCTON, RT3070_1), 100 USB_ID(ACCTON, RT3070_2), 101 USB_ID(ACCTON, RT3070_3), 102 USB_ID(ACCTON, RT3070_4), 103 USB_ID(ACCTON, RT3070_5), 104 USB_ID(ACCTON, RT3070_6), 105 USB_ID(AIRTIES, RT3070), 106 USB_ID(AIRTIES, RT3070_2), 107 USB_ID(ALLWIN, RT2070), 108 USB_ID(ALLWIN, RT2770), 109 USB_ID(ALLWIN, RT2870), 110 USB_ID(ALLWIN, RT3070), 111 USB_ID(ALLWIN, RT3071), 112 USB_ID(ALLWIN, RT3072), 113 USB_ID(ALLWIN, RT3572), 114 USB_ID(AMIGO, RT2870_1), 115 USB_ID(AMIGO, RT2870_2), 116 USB_ID(AMIT, CGWLUSB2GNR), 117 USB_ID(AMIT, RT2870_1), 118 USB_ID(AMIT2, RT2870), 119 USB_ID(ASUSTEK, RT2870_1), 120 USB_ID(ASUSTEK, RT2870_2), 121 USB_ID(ASUSTEK, RT2870_3), 122 USB_ID(ASUSTEK, RT2870_4), 123 USB_ID(ASUSTEK, RT2870_5), 124 USB_ID(ASUSTEK, RT3070), 125 USB_ID(ASUSTEK, RT3070_1), 126 USB_ID(ASUSTEK, USBN53), 127 USB_ID(ASUSTEK, USBN66), 128 USB_ID(ASUSTEK2, USBN11), 129 USB_ID(AZUREWAVE, RT2870_1), 130 USB_ID(AZUREWAVE, RT2870_2), 131 USB_ID(AZUREWAVE, RT3070), 132 USB_ID(AZUREWAVE, RT3070_2), 133 USB_ID(AZUREWAVE, RT3070_3), 134 USB_ID(AZUREWAVE, RT3070_4), 135 USB_ID(AZUREWAVE, RT3070_5), 136 USB_ID(BELKIN, F5D8053V3), 137 USB_ID(BELKIN, F5D8055), 138 USB_ID(BELKIN, F5D8055V2), 139 USB_ID(BELKIN, F6D4050V1), 140 USB_ID(BELKIN, F6D4050V2), 141 USB_ID(BELKIN, F7D1101V2), 142 USB_ID(BELKIN, RT2870_1), 143 USB_ID(BELKIN, RT2870_2), 144 USB_ID(BELKIN, RTL8192CU_2), 145 USB_ID(BEWAN, RT3070), 146 USB_ID(CISCOLINKSYS, AE1000), 147 USB_ID(CISCOLINKSYS, AM10), 148 USB_ID(CISCOLINKSYS2, RT3070), 149 USB_ID(CISCOLINKSYS3, RT3070), 150 USB_ID(CONCEPTRONIC, RT2870_1), 151 USB_ID(CONCEPTRONIC, RT2870_2), 152 USB_ID(CONCEPTRONIC, RT2870_3), 153 USB_ID(CONCEPTRONIC, RT2870_4), 154 USB_ID(CONCEPTRONIC, RT2870_5), 155 USB_ID(CONCEPTRONIC, RT2870_6), 156 USB_ID(CONCEPTRONIC, RT2870_7), 157 USB_ID(CONCEPTRONIC, RT2870_8), 158 USB_ID(CONCEPTRONIC, RT3070_1), 159 USB_ID(CONCEPTRONIC, RT3070_2), 160 USB_ID(CONCEPTRONIC, RT3070_3), 161 USB_ID(COREGA, CGWLUSB300GNM), 162 USB_ID(COREGA, RT2870_1), 163 USB_ID(COREGA, RT2870_2), 164 USB_ID(COREGA, RT2870_3), 165 USB_ID(COREGA, RT3070), 166 USB_ID(CYBERTAN, RT2870), 167 USB_ID(DLINK, RT2870), 168 USB_ID(DLINK, RT3072), 169 USB_ID(DLINK, DWA127), 170 USB_ID(DLINK, DWA140B3), 171 USB_ID(DLINK, DWA160B2), 172 USB_ID(DLINK, DWA162), 173 USB_ID(DLINK2, DWA130), 174 USB_ID(DLINK2, RT2870_1), 175 USB_ID(DLINK2, RT2870_2), 176 USB_ID(DLINK2, RT3070_1), 177 USB_ID(DLINK2, RT3070_2), 178 USB_ID(DLINK2, RT3070_3), 179 USB_ID(DLINK2, RT3070_4), 180 USB_ID(DLINK2, RT3070_5), 181 USB_ID(DLINK2, RT3072), 182 USB_ID(DLINK2, RT3072_1), 183 USB_ID(DVICO, RT3070), 184 USB_ID(EDIMAX, EW7717), 185 USB_ID(EDIMAX, EW7718), 186 USB_ID(EDIMAX, EW7722UTN), 187 USB_ID(EDIMAX, RT2870_1), 188 USB_ID(ENCORE, RT3070), 189 USB_ID(ENCORE, RT3070_2), 190 USB_ID(ENCORE, RT3070_3), 191 USB_ID(GIGABYTE, GNWB31N), 192 USB_ID(GIGABYTE, GNWB32L), 193 USB_ID(GIGABYTE, RT2870_1), 194 USB_ID(GIGASET, RT3070_1), 195 USB_ID(GIGASET, RT3070_2), 196 USB_ID(GUILLEMOT, HWNU300), 197 USB_ID(HAWKING, HWUN2), 198 USB_ID(HAWKING, RT2870_1), 199 USB_ID(HAWKING, RT2870_2), 200 USB_ID(HAWKING, RT2870_3), 201 USB_ID(HAWKING, RT2870_4), 202 USB_ID(HAWKING, RT2870_5), 203 USB_ID(HAWKING, RT3070), 204 USB_ID(IODATA, RT3072_1), 205 USB_ID(IODATA, RT3072_2), 206 USB_ID(IODATA, RT3072_3), 207 USB_ID(IODATA, RT3072_4), 208 USB_ID(LINKSYS4, RT3070), 209 USB_ID(LINKSYS4, WUSB100), 210 USB_ID(LINKSYS4, WUSB54GC_3), 211 USB_ID(LINKSYS4, WUSB600N), 212 USB_ID(LINKSYS4, WUSB600NV2), 213 USB_ID(LOGITEC, LANW300NU2), 214 USB_ID(LOGITEC, LANW300NU2S), 215 USB_ID(LOGITEC, LAN_W300ANU2), 216 USB_ID(LOGITEC, LAN_W450ANU2E), 217 USB_ID(LOGITEC, RT2870_1), 218 USB_ID(LOGITEC, RT2870_2), 219 USB_ID(LOGITEC, RT2870_3), 220 USB_ID(LOGITEC, RT3020), 221 USB_ID(MELCO, RT2870_1), 222 USB_ID(MELCO, RT2870_2), 223 USB_ID(MELCO, WLIUCAG300N), 224 USB_ID(MELCO, WLIUCG300N), 225 USB_ID(MELCO, WLIUCG301N), 226 USB_ID(MELCO, WLIUCGN), 227 USB_ID(MELCO, WLIUCGNHP), 228 USB_ID(MELCO, WLIUCGNM), 229 USB_ID(MELCO, WLIUCGNM2T), 230 USB_ID(MOTOROLA4, RT2770), 231 USB_ID(MOTOROLA4, RT3070), 232 USB_ID(MSI, RT3070), 233 USB_ID(MSI, RT3070_2), 234 USB_ID(MSI, RT3070_3), 235 USB_ID(MSI, RT3070_4), 236 USB_ID(MSI, RT3070_5), 237 USB_ID(MSI, RT3070_6), 238 USB_ID(MSI, RT3070_7), 239 USB_ID(MSI, RT3070_8), 240 USB_ID(MSI, RT3070_9), 241 USB_ID(MSI, RT3070_10), 242 USB_ID(MSI, RT3070_11), 243 USB_ID(MSI, RT3070_12), 244 USB_ID(MSI, RT3070_13), 245 USB_ID(MSI, RT3070_14), 246 USB_ID(MSI, RT3070_15), 247 USB_ID(OVISLINK, RT3071), 248 USB_ID(OVISLINK, RT3072), 249 USB_ID(PARA, RT3070), 250 USB_ID(PEGATRON, RT2870), 251 USB_ID(PEGATRON, RT3070), 252 USB_ID(PEGATRON, RT3070_2), 253 USB_ID(PEGATRON, RT3070_3), 254 USB_ID(PEGATRON, RT3072), 255 USB_ID(PHILIPS, RT2870), 256 USB_ID(PLANEX2, GWUS300MINIS), 257 USB_ID(PLANEX2, GWUSMICRO300), 258 USB_ID(PLANEX2, GWUSMICRON), 259 USB_ID(PLANEX2, GWUS300MINIX), 260 USB_ID(PLANEX2, RT3070), 261 USB_ID(QCOM, RT2870), 262 USB_ID(QUANTA, RT3070), 263 USB_ID(RALINK, RT2070), 264 USB_ID(RALINK, RT2770), 265 USB_ID(RALINK, RT2870), 266 USB_ID(RALINK, RT3070), 267 USB_ID(RALINK, RT3071), 268 USB_ID(RALINK, RT3072), 269 USB_ID(RALINK, RT3370), 270 USB_ID(RALINK, RT3572), 271 USB_ID(RALINK, RT3573), 272 USB_ID(RALINK, RT5370), 273 USB_ID(RALINK, RT5572), 274 USB_ID(RALINK, RT8070), 275 USB_ID(SAMSUNG, RT2870_1), 276 USB_ID(SENAO, RT2870_1), 277 USB_ID(SENAO, RT2870_2), 278 USB_ID(SENAO, RT2870_3), 279 USB_ID(SENAO, RT2870_4), 280 USB_ID(SENAO, RT3070), 281 USB_ID(SENAO, RT3071), 282 USB_ID(SENAO, RT3072), 283 USB_ID(SENAO, RT3072_2), 284 USB_ID(SENAO, RT3072_3), 285 USB_ID(SENAO, RT3072_4), 286 USB_ID(SENAO, RT3072_5), 287 USB_ID(SITECOMEU, RT2870_1), 288 USB_ID(SITECOMEU, RT2870_2), 289 USB_ID(SITECOMEU, RT2870_3), 290 USB_ID(SITECOMEU, RT3070_1), 291 USB_ID(SITECOMEU, RT3070_3), 292 USB_ID(SITECOMEU, RT3072_3), 293 USB_ID(SITECOMEU, RT3072_4), 294 USB_ID(SITECOMEU, RT3072_5), 295 USB_ID(SITECOMEU, RT3072_6), 296 USB_ID(SITECOMEU, WL302), 297 USB_ID(SITECOMEU, WL315), 298 USB_ID(SITECOMEU, WL321), 299 USB_ID(SITECOMEU, WL324), 300 USB_ID(SITECOMEU, WL329), 301 USB_ID(SITECOMEU, WL343), 302 USB_ID(SITECOMEU, WL344), 303 USB_ID(SITECOMEU, WL345), 304 USB_ID(SITECOMEU, WL349V4), 305 USB_ID(SITECOMEU, WL608), 306 USB_ID(SITECOMEU, WLA4000), 307 USB_ID(SITECOMEU, WLA5000), 308 USB_ID(SPARKLAN, RT2870_1), 309 USB_ID(SPARKLAN, RT2870_2), 310 USB_ID(SPARKLAN, RT3070), 311 USB_ID(SWEEX2, LW153), 312 USB_ID(SWEEX2, LW303), 313 USB_ID(SWEEX2, LW313), 314 USB_ID(TOSHIBA, RT3070), 315 USB_ID(UMEDIA, RT2870_1), 316 USB_ID(UMEDIA, TEW645UB), 317 USB_ID(ZCOM, RT2870_1), 318 USB_ID(ZCOM, RT2870_2), 319 USB_ID(ZINWELL, RT2870_1), 320 USB_ID(ZINWELL, RT2870_2), 321 USB_ID(ZINWELL, RT3070), 322 USB_ID(ZINWELL, RT3072), 323 USB_ID(ZINWELL, RT3072_2), 324 USB_ID(ZYXEL, NWD2105), 325 USB_ID(ZYXEL, NWD211AN), 326 USB_ID(ZYXEL, RT2870_1), 327 USB_ID(ZYXEL, RT2870_2), 328 USB_ID(ZYXEL, RT3070), 329 }; 330 331 static int run_match(device_t, cfdata_t, void *); 332 static void run_attach(device_t, device_t, void *); 333 static int run_detach(device_t, int); 334 static int run_activate(device_t, enum devact); 335 336 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 337 run_match, run_attach, run_detach, run_activate); 338 339 static int run_alloc_rx_ring(struct run_softc *); 340 static void run_free_rx_ring(struct run_softc *); 341 static int run_alloc_tx_ring(struct run_softc *, int); 342 static void run_free_tx_ring(struct run_softc *, int); 343 static int run_load_microcode(struct run_softc *); 344 static int run_reset(struct run_softc *); 345 static int run_read(struct run_softc *, uint16_t, uint32_t *); 346 static int run_read_region_1(struct run_softc *, uint16_t, 347 uint8_t *, int); 348 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 349 static int run_write(struct run_softc *, uint16_t, uint32_t); 350 static int run_write_region_1(struct run_softc *, uint16_t, 351 const uint8_t *, int); 352 static int run_set_region_4(struct run_softc *, uint16_t, 353 uint32_t, int); 354 static int run_efuse_read(struct run_softc *, uint16_t, 355 uint16_t *, int); 356 static int run_efuse_read_2(struct run_softc *, uint16_t, 357 uint16_t *); 358 static int run_eeprom_read_2(struct run_softc *, uint16_t, 359 uint16_t *); 360 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 361 uint32_t); 362 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 363 uint8_t *); 364 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 365 uint8_t); 366 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 367 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 368 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 369 static const char * run_get_rf(uint16_t); 370 static void run_rt3593_get_txpower(struct run_softc *); 371 static void run_get_txpower(struct run_softc *); 372 static int run_read_eeprom(struct run_softc *); 373 static struct ieee80211_node * 374 run_node_alloc(struct ieee80211_node_table *); 375 static int run_media_change(struct ifnet *); 376 static void run_next_scan(void *); 377 static void run_task(void *); 378 static void run_do_async(struct run_softc *, 379 void (*)(struct run_softc *, void *), void *, int); 380 static int run_newstate(struct ieee80211com *, 381 enum ieee80211_state, int); 382 static void run_newstate_cb(struct run_softc *, void *); 383 static int run_updateedca(struct ieee80211com *); 384 static void run_updateedca_cb(struct run_softc *, void *); 385 #ifdef RUN_HWCRYPTO 386 static int run_set_key(struct ieee80211com *, 387 const struct ieee80211_key *, const uint8_t *); 388 static void run_set_key_cb(struct run_softc *, void *); 389 static int run_delete_key(struct ieee80211com *, 390 const struct ieee80211_key *); 391 static void run_delete_key_cb(struct run_softc *, void *); 392 #endif 393 static void run_calibrate_to(void *); 394 static void run_calibrate_cb(struct run_softc *, void *); 395 static void run_newassoc(struct ieee80211_node *, int); 396 static void run_rx_frame(struct run_softc *, uint8_t *, int); 397 static void run_rxeof(struct usbd_xfer *, void *, 398 usbd_status); 399 static void run_txeof(struct usbd_xfer *, void *, 400 usbd_status); 401 static int run_tx(struct run_softc *, struct mbuf *, 402 struct ieee80211_node *); 403 static void run_start(struct ifnet *); 404 static void run_watchdog(struct ifnet *); 405 static int run_ioctl(struct ifnet *, u_long, void *); 406 static void run_select_chan_group(struct run_softc *, int); 407 static void run_iq_calib(struct run_softc *, u_int); 408 static void run_set_agc(struct run_softc *, uint8_t); 409 static void run_set_rx_antenna(struct run_softc *, int); 410 static void run_rt2870_set_chan(struct run_softc *, u_int); 411 static void run_rt3070_set_chan(struct run_softc *, u_int); 412 static void run_rt3572_set_chan(struct run_softc *, u_int); 413 static void run_rt3593_set_chan(struct run_softc *, u_int); 414 static void run_rt5390_set_chan(struct run_softc *, u_int); 415 static void run_rt5592_set_chan(struct run_softc *, u_int); 416 static int run_set_chan(struct run_softc *, 417 struct ieee80211_channel *); 418 static void run_updateprot(struct run_softc *); 419 static void run_enable_tsf_sync(struct run_softc *); 420 static void run_enable_mrr(struct run_softc *); 421 static void run_set_txpreamble(struct run_softc *); 422 static void run_set_basicrates(struct run_softc *); 423 static void run_set_leds(struct run_softc *, uint16_t); 424 static void run_set_bssid(struct run_softc *, const uint8_t *); 425 static void run_set_macaddr(struct run_softc *, const uint8_t *); 426 static void run_updateslot(struct ifnet *); 427 static void run_updateslot_cb(struct run_softc *, void *); 428 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 429 static void run_rt5390_bbp_init(struct run_softc *); 430 static int run_bbp_init(struct run_softc *); 431 static int run_rt3070_rf_init(struct run_softc *); 432 static int run_rt3593_rf_init(struct run_softc *); 433 static int run_rt5390_rf_init(struct run_softc *); 434 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 435 uint8_t, uint8_t *); 436 static void run_rt3070_rf_setup(struct run_softc *); 437 static void run_rt3593_rf_setup(struct run_softc *); 438 static void run_rt5390_rf_setup(struct run_softc *); 439 static int run_txrx_enable(struct run_softc *); 440 static int run_adjust_freq_offset(struct run_softc *); 441 static int run_init(struct ifnet *); 442 static void run_stop(struct ifnet *, int); 443 #ifndef IEEE80211_STA_ONLY 444 static int run_setup_beacon(struct run_softc *); 445 #endif 446 447 static const struct { 448 uint32_t reg; 449 uint32_t val; 450 } rt2870_def_mac[] = { 451 RT2870_DEF_MAC 452 }; 453 454 static const struct { 455 uint8_t reg; 456 uint8_t val; 457 } rt2860_def_bbp[] = { 458 RT2860_DEF_BBP 459 }, rt5390_def_bbp[] = { 460 RT5390_DEF_BBP 461 }, rt5592_def_bbp[] = { 462 RT5592_DEF_BBP 463 }; 464 465 /* 466 * Default values for BBP register R196 for RT5592. 467 */ 468 static const uint8_t rt5592_bbp_r196[] = { 469 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 470 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 471 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 472 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 473 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 474 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 476 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 477 0x2e, 0x36, 0x30, 0x6e 478 }; 479 480 static const struct rfprog { 481 uint8_t chan; 482 uint32_t r1, r2, r3, r4; 483 } rt2860_rf2850[] = { 484 RT2860_RF2850 485 }; 486 487 static const struct { 488 uint8_t n, r, k; 489 } rt3070_freqs[] = { 490 RT3070_RF3052 491 }; 492 493 static const struct rt5592_freqs { 494 uint16_t n; 495 uint8_t k, m, r; 496 } rt5592_freqs_20mhz[] = { 497 RT5592_RF5592_20MHZ 498 },rt5592_freqs_40mhz[] = { 499 RT5592_RF5592_40MHZ 500 }; 501 502 static const struct { 503 uint8_t reg; 504 uint8_t val; 505 } rt3070_def_rf[] = { 506 RT3070_DEF_RF 507 }, rt3572_def_rf[] = { 508 RT3572_DEF_RF 509 },rt3593_def_rf[] = { 510 RT3593_DEF_RF 511 },rt5390_def_rf[] = { 512 RT5390_DEF_RF 513 },rt5392_def_rf[] = { 514 RT5392_DEF_RF 515 },rt5592_def_rf[] = { 516 RT5592_DEF_RF 517 },rt5592_2ghz_def_rf[] = { 518 RT5592_2GHZ_DEF_RF 519 },rt5592_5ghz_def_rf[] = { 520 RT5592_5GHZ_DEF_RF 521 }; 522 523 static const struct { 524 u_int firstchan; 525 u_int lastchan; 526 uint8_t reg; 527 uint8_t val; 528 } rt5592_chan_5ghz[] = { 529 RT5592_CHAN_5GHZ 530 }; 531 532 static int 533 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 534 size_t *sizep) 535 { 536 firmware_handle_t fh; 537 int error; 538 539 if ((error = firmware_open(dname, iname, &fh)) != 0) 540 return error; 541 *sizep = firmware_get_size(fh); 542 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 543 firmware_close(fh); 544 return ENOMEM; 545 } 546 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 547 firmware_free(*ucodep, *sizep); 548 firmware_close(fh); 549 550 return error; 551 } 552 553 static int 554 run_match(device_t parent, cfdata_t match, void *aux) 555 { 556 struct usb_attach_arg *uaa = aux; 557 558 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 559 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 560 } 561 562 static void 563 run_attach(device_t parent, device_t self, void *aux) 564 { 565 struct run_softc *sc = device_private(self); 566 struct usb_attach_arg *uaa = aux; 567 struct ieee80211com *ic = &sc->sc_ic; 568 struct ifnet *ifp = &sc->sc_if; 569 usb_interface_descriptor_t *id; 570 usb_endpoint_descriptor_t *ed; 571 char *devinfop; 572 int i, nrx, ntx, ntries, error; 573 uint32_t ver; 574 575 aprint_naive("\n"); 576 aprint_normal("\n"); 577 578 sc->sc_dev = self; 579 sc->sc_udev = uaa->uaa_device; 580 581 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 582 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 583 usbd_devinfo_free(devinfop); 584 585 error = usbd_set_config_no(sc->sc_udev, 1, 0); 586 if (error != 0) { 587 aprint_error_dev(sc->sc_dev, "failed to set configuration" 588 ", err=%s\n", usbd_errstr(error)); 589 return; 590 } 591 592 /* get the first interface handle */ 593 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 594 if (error != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "could not get interface handle\n"); 597 return; 598 } 599 600 /* 601 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 602 * and 6 for TX (4 EDCAs + HCCA + Prio). 603 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 604 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 605 */ 606 nrx = ntx = 0; 607 id = usbd_get_interface_descriptor(sc->sc_iface); 608 for (i = 0; i < id->bNumEndpoints; i++) { 609 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 610 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 611 continue; 612 613 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 614 sc->rxq.pipe_no = ed->bEndpointAddress; 615 nrx++; 616 } else if (ntx < RUN_MAXEPOUT) { 617 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 618 ntx++; 619 } 620 } 621 /* make sure we've got them all */ 622 if (nrx < 1 || ntx < RUN_MAXEPOUT) { 623 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 624 return; 625 } 626 627 usb_init_task(&sc->sc_task, run_task, sc, 0); 628 callout_init(&sc->scan_to, 0); 629 callout_setfunc(&sc->scan_to, run_next_scan, sc); 630 callout_init(&sc->calib_to, 0); 631 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 632 633 sc->amrr.amrr_min_success_threshold = 1; 634 sc->amrr.amrr_max_success_threshold = 10; 635 636 /* wait for the chip to settle */ 637 for (ntries = 0; ntries < 100; ntries++) { 638 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 639 return; 640 if (ver != 0 && ver != 0xffffffff) 641 break; 642 DELAY(10); 643 } 644 if (ntries == 100) { 645 aprint_error_dev(sc->sc_dev, 646 "timeout waiting for NIC to initialize\n"); 647 return; 648 } 649 sc->mac_ver = ver >> 16; 650 sc->mac_rev = ver & 0xffff; 651 652 /* retrieve RF rev. no and various other things from EEPROM */ 653 run_read_eeprom(sc); 654 655 aprint_verbose_dev(sc->sc_dev, 656 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 657 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 658 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 659 660 ic->ic_ifp = ifp; 661 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 662 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 663 ic->ic_state = IEEE80211_S_INIT; 664 665 /* set device capabilities */ 666 ic->ic_caps = 667 IEEE80211_C_MONITOR | /* monitor mode supported */ 668 #ifndef IEEE80211_STA_ONLY 669 IEEE80211_C_IBSS | /* IBSS mode supported */ 670 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 671 #endif 672 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 673 IEEE80211_C_SHSLOT | /* short slot time supported */ 674 #ifdef RUN_HWCRYPTO 675 IEEE80211_C_WEP | /* WEP */ 676 IEEE80211_C_TKIP | /* TKIP */ 677 IEEE80211_C_AES_CCM | /* AES CCMP */ 678 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 679 #endif 680 IEEE80211_C_WME | /* WME */ 681 IEEE80211_C_WPA; /* WPA/RSN */ 682 683 if (sc->rf_rev == RT2860_RF_2750 || 684 sc->rf_rev == RT2860_RF_2850 || 685 sc->rf_rev == RT3070_RF_3052 || 686 sc->rf_rev == RT3070_RF_3053 || 687 sc->rf_rev == RT5592_RF_5592) { 688 /* set supported .11a rates */ 689 ic->ic_sup_rates[IEEE80211_MODE_11A] = 690 ieee80211_std_rateset_11a; 691 692 /* set supported .11a channels */ 693 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 694 uint8_t chan = rt2860_rf2850[i].chan; 695 ic->ic_channels[chan].ic_freq = 696 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 697 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 698 } 699 } 700 701 /* set supported .11b and .11g rates */ 702 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 703 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 704 705 /* set supported .11b and .11g channels (1 through 14) */ 706 for (i = 1; i <= 14; i++) { 707 ic->ic_channels[i].ic_freq = 708 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 709 ic->ic_channels[i].ic_flags = 710 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 711 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 712 } 713 714 ifp->if_softc = sc; 715 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 716 ifp->if_init = run_init; 717 ifp->if_ioctl = run_ioctl; 718 ifp->if_start = run_start; 719 ifp->if_watchdog = run_watchdog; 720 IFQ_SET_READY(&ifp->if_snd); 721 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 722 723 if_attach(ifp); 724 ieee80211_ifattach(ic); 725 ic->ic_node_alloc = run_node_alloc; 726 ic->ic_newassoc = run_newassoc; 727 ic->ic_updateslot = run_updateslot; 728 ic->ic_wme.wme_update = run_updateedca; 729 #ifdef RUN_HWCRYPTO 730 ic->ic_crypto.cs_key_set = run_set_key; 731 ic->ic_crypto.cs_key_delete = run_delete_key; 732 #endif 733 /* override state transition machine */ 734 sc->sc_newstate = ic->ic_newstate; 735 ic->ic_newstate = run_newstate; 736 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 737 738 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 739 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 740 &sc->sc_drvbpf); 741 742 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 743 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 744 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 745 746 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 747 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 748 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 749 750 ieee80211_announce(ic); 751 752 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 753 754 if (!pmf_device_register(self, NULL, NULL)) 755 aprint_error_dev(self, "couldn't establish power handler\n"); 756 } 757 758 static int 759 run_detach(device_t self, int flags) 760 { 761 struct run_softc *sc = device_private(self); 762 struct ifnet *ifp = &sc->sc_if; 763 struct ieee80211com *ic = &sc->sc_ic; 764 int s; 765 766 if (ifp->if_softc == NULL) 767 return 0; 768 769 pmf_device_deregister(self); 770 771 s = splusb(); 772 773 sc->sc_flags |= RUN_DETACHING; 774 775 if (ifp->if_flags & IFF_RUNNING) { 776 run_stop(ifp, 0); 777 callout_halt(&sc->scan_to, NULL); 778 callout_halt(&sc->calib_to, NULL); 779 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 780 NULL); 781 } 782 783 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 784 bpf_detach(ifp); 785 ieee80211_ifdetach(ic); 786 if_detach(ifp); 787 788 splx(s); 789 790 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 791 792 callout_stop(&sc->scan_to); 793 callout_stop(&sc->calib_to); 794 795 callout_destroy(&sc->scan_to); 796 callout_destroy(&sc->calib_to); 797 798 return 0; 799 } 800 801 static int 802 run_activate(device_t self, enum devact act) 803 { 804 struct run_softc *sc = device_private(self); 805 806 switch (act) { 807 case DVACT_DEACTIVATE: 808 if_deactivate(sc->sc_ic.ic_ifp); 809 return 0; 810 default: 811 return EOPNOTSUPP; 812 } 813 } 814 815 static int 816 run_alloc_rx_ring(struct run_softc *sc) 817 { 818 struct run_rx_ring *rxq = &sc->rxq; 819 int i, error; 820 821 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 822 if (error != 0) 823 goto fail; 824 825 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 826 struct run_rx_data *data = &rxq->data[i]; 827 828 data->sc = sc; /* backpointer for callbacks */ 829 830 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 831 0, 0, &data->xfer); 832 if (error) 833 goto fail; 834 835 data->buf = usbd_get_buffer(data->xfer); 836 } 837 if (error != 0) 838 fail: run_free_rx_ring(sc); 839 return error; 840 } 841 842 static void 843 run_free_rx_ring(struct run_softc *sc) 844 { 845 struct run_rx_ring *rxq = &sc->rxq; 846 int i; 847 848 if (rxq->pipeh != NULL) { 849 usbd_abort_pipe(rxq->pipeh); 850 } 851 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 852 if (rxq->data[i].xfer != NULL) 853 usbd_destroy_xfer(rxq->data[i].xfer); 854 rxq->data[i].xfer = NULL; 855 } 856 if (rxq->pipeh != NULL) { 857 usbd_close_pipe(rxq->pipeh); 858 rxq->pipeh = NULL; 859 } 860 } 861 862 static int 863 run_alloc_tx_ring(struct run_softc *sc, int qid) 864 { 865 struct run_tx_ring *txq = &sc->txq[qid]; 866 int i, error; 867 uint16_t txwisize; 868 869 txwisize = sizeof(struct rt2860_txwi); 870 if (sc->mac_ver == 0x5592) 871 txwisize += sizeof(uint32_t); 872 873 txq->cur = txq->queued = 0; 874 875 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 876 if (error != 0) 877 goto fail; 878 879 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 880 struct run_tx_data *data = &txq->data[i]; 881 882 data->sc = sc; /* backpointer for callbacks */ 883 data->qid = qid; 884 885 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 886 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 887 if (error) 888 goto fail; 889 890 data->buf = usbd_get_buffer(data->xfer); 891 /* zeroize the TXD + TXWI part */ 892 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 893 } 894 if (error != 0) 895 fail: run_free_tx_ring(sc, qid); 896 return error; 897 } 898 899 static void 900 run_free_tx_ring(struct run_softc *sc, int qid) 901 { 902 struct run_tx_ring *txq = &sc->txq[qid]; 903 int i; 904 905 if (txq->pipeh != NULL) { 906 usbd_abort_pipe(txq->pipeh); 907 usbd_close_pipe(txq->pipeh); 908 txq->pipeh = NULL; 909 } 910 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 911 if (txq->data[i].xfer != NULL) 912 usbd_destroy_xfer(txq->data[i].xfer); 913 txq->data[i].xfer = NULL; 914 } 915 } 916 917 static int 918 run_load_microcode(struct run_softc *sc) 919 { 920 usb_device_request_t req; 921 const char *fwname; 922 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 923 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 924 uint32_t tmp; 925 int ntries, error; 926 927 /* RT3071/RT3072 use a different firmware */ 928 if (sc->mac_ver != 0x2860 && 929 sc->mac_ver != 0x2872 && 930 sc->mac_ver != 0x3070) 931 fwname = "run-rt3071"; 932 else 933 fwname = "run-rt2870"; 934 935 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 936 device_printf(sc->sc_dev, 937 "error %d, could not read firmware %s\n", error, fwname); 938 return error; 939 } 940 if (size != 4096) { 941 device_printf(sc->sc_dev, 942 "invalid firmware size (should be 4KB)\n"); 943 firmware_free(ucode, size); 944 return EINVAL; 945 } 946 947 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 948 /* write microcode image */ 949 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 950 firmware_free(ucode, size); 951 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 952 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 953 954 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 955 req.bRequest = RT2870_RESET; 956 USETW(req.wValue, 8); 957 USETW(req.wIndex, 0); 958 USETW(req.wLength, 0); 959 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 960 return error; 961 962 usbd_delay_ms(sc->sc_udev, 10); 963 run_write(sc, RT2860_H2M_BBPAGENT, 0); 964 run_write(sc, RT2860_H2M_MAILBOX, 0); 965 run_write(sc, RT2860_H2M_INTSRC, 0); 966 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 967 return error; 968 969 /* wait until microcontroller is ready */ 970 for (ntries = 0; ntries < 1000; ntries++) { 971 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 972 return error; 973 if (tmp & RT2860_MCU_READY) 974 break; 975 usbd_delay_ms(sc->sc_udev, 10); 976 } 977 if (ntries == 1000) { 978 device_printf(sc->sc_dev, 979 "timeout waiting for MCU to initialize\n"); 980 return ETIMEDOUT; 981 } 982 983 sc->sc_flags |= RUN_FWLOADED; 984 985 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 986 return 0; 987 } 988 989 static int 990 run_reset(struct run_softc *sc) 991 { 992 usb_device_request_t req; 993 994 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 995 req.bRequest = RT2870_RESET; 996 USETW(req.wValue, 1); 997 USETW(req.wIndex, 0); 998 USETW(req.wLength, 0); 999 return usbd_do_request(sc->sc_udev, &req, NULL); 1000 } 1001 1002 static int 1003 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 1004 { 1005 uint32_t tmp; 1006 int error; 1007 1008 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 1009 if (error == 0) 1010 *val = le32toh(tmp); 1011 else 1012 *val = 0xffffffff; 1013 return error; 1014 } 1015 1016 static int 1017 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 1018 { 1019 usb_device_request_t req; 1020 1021 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1022 req.bRequest = RT2870_READ_REGION_1; 1023 USETW(req.wValue, 0); 1024 USETW(req.wIndex, reg); 1025 USETW(req.wLength, len); 1026 return usbd_do_request(sc->sc_udev, &req, buf); 1027 } 1028 1029 static int 1030 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1031 { 1032 usb_device_request_t req; 1033 1034 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1035 req.bRequest = RT2870_WRITE_2; 1036 USETW(req.wValue, val); 1037 USETW(req.wIndex, reg); 1038 USETW(req.wLength, 0); 1039 return usbd_do_request(sc->sc_udev, &req, NULL); 1040 } 1041 1042 static int 1043 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1044 { 1045 int error; 1046 1047 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1048 error = run_write_2(sc, reg + 2, val >> 16); 1049 return error; 1050 } 1051 1052 static int 1053 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1054 int len) 1055 { 1056 #if 1 1057 int i, error = 0; 1058 /* 1059 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1060 * We thus issue multiple WRITE_2 commands instead. 1061 */ 1062 KASSERT((len & 1) == 0); 1063 for (i = 0; i < len && error == 0; i += 2) 1064 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1065 return error; 1066 #else 1067 usb_device_request_t req; 1068 1069 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1070 req.bRequest = RT2870_WRITE_REGION_1; 1071 USETW(req.wValue, 0); 1072 USETW(req.wIndex, reg); 1073 USETW(req.wLength, len); 1074 return usbd_do_request(sc->sc_udev, &req, __UNCONST(buf)); 1075 #endif 1076 } 1077 1078 static int 1079 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1080 { 1081 int error = 0; 1082 1083 for (; count > 0 && error == 0; count--, reg += 4) 1084 error = run_write(sc, reg, val); 1085 return error; 1086 } 1087 1088 static int 1089 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1090 { 1091 uint32_t tmp; 1092 uint16_t reg; 1093 int error, ntries; 1094 1095 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1096 return error; 1097 1098 if (count == 2) 1099 addr *= 2; 1100 /*- 1101 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1102 * DATA0: F E D C 1103 * DATA1: B A 9 8 1104 * DATA2: 7 6 5 4 1105 * DATA3: 3 2 1 0 1106 */ 1107 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1108 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1109 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1110 for (ntries = 0; ntries < 100; ntries++) { 1111 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1112 return error; 1113 if (!(tmp & RT3070_EFSROM_KICK)) 1114 break; 1115 usbd_delay_ms(sc->sc_udev, 2); 1116 } 1117 if (ntries == 100) 1118 return ETIMEDOUT; 1119 1120 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1121 *val = 0xffff; /* address not found */ 1122 return 0; 1123 } 1124 /* determine to which 32-bit register our 16-bit word belongs */ 1125 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1126 if ((error = run_read(sc, reg, &tmp)) != 0) 1127 return error; 1128 1129 tmp >>= (8 * (addr & 0x3)); 1130 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1131 return 0; 1132 } 1133 1134 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1135 static int 1136 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1137 { 1138 return run_efuse_read(sc, addr, val, 2); 1139 } 1140 1141 static int 1142 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1143 { 1144 usb_device_request_t req; 1145 uint16_t tmp; 1146 int error; 1147 1148 addr *= 2; 1149 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1150 req.bRequest = RT2870_EEPROM_READ; 1151 USETW(req.wValue, 0); 1152 USETW(req.wIndex, addr); 1153 USETW(req.wLength, sizeof(tmp)); 1154 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1155 if (error == 0) 1156 *val = le16toh(tmp); 1157 else 1158 *val = 0xffff; 1159 return error; 1160 } 1161 1162 static __inline int 1163 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1164 { 1165 1166 /* either eFUSE ROM or EEPROM */ 1167 return sc->sc_srom_read(sc, addr, val); 1168 } 1169 1170 static int 1171 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1172 { 1173 uint32_t tmp; 1174 int error, ntries; 1175 1176 for (ntries = 0; ntries < 10; ntries++) { 1177 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1178 return error; 1179 if (!(tmp & RT2860_RF_REG_CTRL)) 1180 break; 1181 } 1182 if (ntries == 10) 1183 return ETIMEDOUT; 1184 1185 /* RF registers are 24-bit on the RT2860 */ 1186 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1187 (val & 0x3fffff) << 2 | (reg & 3); 1188 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1189 } 1190 1191 static int 1192 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1193 { 1194 uint32_t tmp; 1195 int error, ntries; 1196 1197 for (ntries = 0; ntries < 100; ntries++) { 1198 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1199 return error; 1200 if (!(tmp & RT3070_RF_KICK)) 1201 break; 1202 } 1203 if (ntries == 100) 1204 return ETIMEDOUT; 1205 1206 tmp = RT3070_RF_KICK | reg << 8; 1207 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1208 return error; 1209 1210 for (ntries = 0; ntries < 100; ntries++) { 1211 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1212 return error; 1213 if (!(tmp & RT3070_RF_KICK)) 1214 break; 1215 } 1216 if (ntries == 100) 1217 return ETIMEDOUT; 1218 1219 *val = tmp & 0xff; 1220 return 0; 1221 } 1222 1223 static int 1224 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1225 { 1226 uint32_t tmp; 1227 int error, ntries; 1228 1229 for (ntries = 0; ntries < 10; ntries++) { 1230 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1231 return error; 1232 if (!(tmp & RT3070_RF_KICK)) 1233 break; 1234 } 1235 if (ntries == 10) 1236 return ETIMEDOUT; 1237 1238 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1239 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1240 } 1241 1242 static int 1243 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1244 { 1245 uint32_t tmp; 1246 int ntries, error; 1247 1248 for (ntries = 0; ntries < 10; ntries++) { 1249 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1250 return error; 1251 if (!(tmp & RT2860_BBP_CSR_KICK)) 1252 break; 1253 } 1254 if (ntries == 10) 1255 return ETIMEDOUT; 1256 1257 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1258 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1259 return error; 1260 1261 for (ntries = 0; ntries < 10; ntries++) { 1262 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1263 return error; 1264 if (!(tmp & RT2860_BBP_CSR_KICK)) 1265 break; 1266 } 1267 if (ntries == 10) 1268 return ETIMEDOUT; 1269 1270 *val = tmp & 0xff; 1271 return 0; 1272 } 1273 1274 static int 1275 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1276 { 1277 uint32_t tmp; 1278 int ntries, error; 1279 1280 for (ntries = 0; ntries < 10; ntries++) { 1281 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1282 return error; 1283 if (!(tmp & RT2860_BBP_CSR_KICK)) 1284 break; 1285 } 1286 if (ntries == 10) 1287 return ETIMEDOUT; 1288 1289 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1290 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1291 } 1292 1293 /* 1294 * Send a command to the 8051 microcontroller unit. 1295 */ 1296 static int 1297 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1298 { 1299 uint32_t tmp; 1300 int error, ntries; 1301 1302 for (ntries = 0; ntries < 100; ntries++) { 1303 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1304 return error; 1305 if (!(tmp & RT2860_H2M_BUSY)) 1306 break; 1307 } 1308 if (ntries == 100) 1309 return ETIMEDOUT; 1310 1311 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1312 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1313 error = run_write(sc, RT2860_HOST_CMD, cmd); 1314 return error; 1315 } 1316 1317 /* 1318 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1319 * Used to adjust per-rate Tx power registers. 1320 */ 1321 static __inline uint32_t 1322 b4inc(uint32_t b32, int8_t delta) 1323 { 1324 int8_t i, b4; 1325 1326 for (i = 0; i < 8; i++) { 1327 b4 = b32 & 0xf; 1328 b4 += delta; 1329 if (b4 < 0) 1330 b4 = 0; 1331 else if (b4 > 0xf) 1332 b4 = 0xf; 1333 b32 = b32 >> 4 | b4 << 28; 1334 } 1335 return b32; 1336 } 1337 1338 static const char * 1339 run_get_rf(uint16_t rev) 1340 { 1341 switch (rev) { 1342 case RT2860_RF_2820: return "RT2820"; 1343 case RT2860_RF_2850: return "RT2850"; 1344 case RT2860_RF_2720: return "RT2720"; 1345 case RT2860_RF_2750: return "RT2750"; 1346 case RT3070_RF_3020: return "RT3020"; 1347 case RT3070_RF_2020: return "RT2020"; 1348 case RT3070_RF_3021: return "RT3021"; 1349 case RT3070_RF_3022: return "RT3022"; 1350 case RT3070_RF_3052: return "RT3052"; 1351 case RT3070_RF_3053: return "RT3053"; 1352 case RT5592_RF_5592: return "RT5592"; 1353 case RT5390_RF_5370: return "RT5370"; 1354 case RT5390_RF_5372: return "RT5372"; 1355 } 1356 return "unknown"; 1357 } 1358 1359 static void 1360 run_rt3593_get_txpower(struct run_softc *sc) 1361 { 1362 uint16_t addr, val; 1363 int i; 1364 1365 /* Read power settings for 2GHz channels. */ 1366 for (i = 0; i < 14; i += 2) { 1367 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1368 RT2860_EEPROM_PWR2GHZ_BASE1; 1369 run_srom_read(sc, addr + i / 2, &val); 1370 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1371 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1372 1373 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1374 RT2860_EEPROM_PWR2GHZ_BASE2; 1375 run_srom_read(sc, addr + i / 2, &val); 1376 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1377 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1378 1379 if (sc->ntxchains == 3) { 1380 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1381 &val); 1382 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1383 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1384 } 1385 } 1386 /* Fix broken Tx power entries. */ 1387 for (i = 0; i < 14; i++) { 1388 if (sc->txpow1[i] > 31) 1389 sc->txpow1[i] = 5; 1390 if (sc->txpow2[i] > 31) 1391 sc->txpow2[i] = 5; 1392 if (sc->ntxchains == 3) { 1393 if (sc->txpow3[i] > 31) 1394 sc->txpow3[i] = 5; 1395 } 1396 } 1397 /* Read power settings for 5GHz channels. */ 1398 for (i = 0; i < 40; i += 2) { 1399 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1400 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1401 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1402 1403 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1404 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1405 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1406 1407 if (sc->ntxchains == 3) { 1408 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1409 &val); 1410 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1411 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1412 } 1413 } 1414 } 1415 1416 static void 1417 run_get_txpower(struct run_softc *sc) 1418 { 1419 uint16_t val; 1420 int i; 1421 1422 /* Read power settings for 2GHz channels. */ 1423 for (i = 0; i < 14; i += 2) { 1424 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1425 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1426 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1427 1428 if (sc->mac_ver != 0x5390) { 1429 run_srom_read(sc, 1430 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1431 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1432 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1433 } 1434 } 1435 /* Fix broken Tx power entries. */ 1436 for (i = 0; i < 14; i++) { 1437 if (sc->mac_ver >= 0x5390) { 1438 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1439 sc->txpow1[i] = 5; 1440 } else { 1441 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1442 sc->txpow1[i] = 5; 1443 } 1444 if (sc->mac_ver > 0x5390) { 1445 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1446 sc->txpow2[i] = 5; 1447 } else if (sc->mac_ver < 0x5390) { 1448 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1449 sc->txpow2[i] = 5; 1450 } 1451 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1452 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1453 } 1454 /* Read power settings for 5GHz channels. */ 1455 for (i = 0; i < 40; i += 2) { 1456 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1457 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1458 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1459 1460 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1461 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1462 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1463 } 1464 /* Fix broken Tx power entries. */ 1465 for (i = 0; i < 40; i++ ) { 1466 if (sc->mac_ver != 0x5592) { 1467 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1468 sc->txpow1[14 + i] = 5; 1469 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1470 sc->txpow2[14 + i] = 5; 1471 } 1472 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1473 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1474 sc->txpow2[14 + i])); 1475 } 1476 } 1477 1478 static int 1479 run_read_eeprom(struct run_softc *sc) 1480 { 1481 struct ieee80211com *ic = &sc->sc_ic; 1482 int8_t delta_2ghz, delta_5ghz; 1483 uint32_t tmp; 1484 uint16_t val; 1485 int ridx, ant, i; 1486 1487 /* check whether the ROM is eFUSE ROM or EEPROM */ 1488 sc->sc_srom_read = run_eeprom_read_2; 1489 if (sc->mac_ver >= 0x3070) { 1490 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1491 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1492 if (tmp & RT3070_SEL_EFUSE) 1493 sc->sc_srom_read = run_efuse_read_2; 1494 } 1495 1496 /* read ROM version */ 1497 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1498 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1499 1500 /* read MAC address */ 1501 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1502 ic->ic_myaddr[0] = val & 0xff; 1503 ic->ic_myaddr[1] = val >> 8; 1504 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1505 ic->ic_myaddr[2] = val & 0xff; 1506 ic->ic_myaddr[3] = val >> 8; 1507 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1508 ic->ic_myaddr[4] = val & 0xff; 1509 ic->ic_myaddr[5] = val >> 8; 1510 1511 if (sc->mac_ver < 0x3593) { 1512 /* read vendor BBP settings */ 1513 for (i = 0; i < 10; i++) { 1514 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1515 sc->bbp[i].val = val & 0xff; 1516 sc->bbp[i].reg = val >> 8; 1517 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1518 sc->bbp[i].val)); 1519 } 1520 1521 if (sc->mac_ver >= 0x3071) { 1522 /* read vendor RF settings */ 1523 for (i = 0; i < 8; i++) { 1524 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1525 &val); 1526 sc->rf[i].val = val & 0xff; 1527 sc->rf[i].reg = val >> 8; 1528 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1529 sc->rf[i].val)); 1530 } 1531 } 1532 } 1533 1534 /* read RF frequency offset from EEPROM */ 1535 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1536 RT3593_EEPROM_FREQ, &val); 1537 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1538 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1539 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1540 RT3593_EEPROM_FREQ, &val); 1541 if ((val >> 8) != 0xff) { 1542 /* read LEDs operating mode */ 1543 sc->leds = val >> 8; 1544 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1545 RT3593_EEPROM_LED1, &sc->led[0]); 1546 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1547 RT3593_EEPROM_LED2, &sc->led[1]); 1548 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1549 RT3593_EEPROM_LED3, &sc->led[2]); 1550 } else { 1551 /* broken EEPROM, use default settings */ 1552 sc->leds = 0x01; 1553 sc->led[0] = 0x5555; 1554 sc->led[1] = 0x2221; 1555 sc->led[2] = 0x5627; /* differs from RT2860 */ 1556 } 1557 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1558 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1559 1560 /* read RF information */ 1561 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1562 run_srom_read(sc, 0x00, &val); 1563 else 1564 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1565 if (val == 0xffff) { 1566 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1567 if (sc->mac_ver == 0x3572) { 1568 /* default to RF3052 2T2R */ 1569 sc->rf_rev = RT3070_RF_3052; 1570 sc->ntxchains = 2; 1571 sc->nrxchains = 2; 1572 } else if (sc->mac_ver >= 0x3070) { 1573 /* default to RF3020 1T1R */ 1574 sc->rf_rev = RT3070_RF_3020; 1575 sc->ntxchains = 1; 1576 sc->nrxchains = 1; 1577 } else { 1578 /* default to RF2820 1T2R */ 1579 sc->rf_rev = RT2860_RF_2820; 1580 sc->ntxchains = 1; 1581 sc->nrxchains = 2; 1582 } 1583 } else { 1584 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1585 sc->rf_rev = val; 1586 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1587 } else 1588 sc->rf_rev = (val >> 8) & 0xf; 1589 sc->ntxchains = (val >> 4) & 0xf; 1590 sc->nrxchains = val & 0xf; 1591 } 1592 DPRINTF(("EEPROM RF rev=0x%04x chains=%dT%dR\n", 1593 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1594 1595 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1596 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1597 /* check if driver should patch the DAC issue */ 1598 if ((val >> 8) != 0xff) 1599 sc->patch_dac = (val >> 15) & 1; 1600 if ((val & 0xff) != 0xff) { 1601 sc->ext_5ghz_lna = (val >> 3) & 1; 1602 sc->ext_2ghz_lna = (val >> 2) & 1; 1603 /* check if RF supports automatic Tx access gain control */ 1604 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1605 /* check if we have a hardware radio switch */ 1606 sc->rfswitch = val & 1; 1607 } 1608 1609 /* Read Tx power settings. */ 1610 if (sc->mac_ver == 0x3593) 1611 run_rt3593_get_txpower(sc); 1612 else 1613 run_get_txpower(sc); 1614 1615 /* read Tx power compensation for each Tx rate */ 1616 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1617 delta_2ghz = delta_5ghz = 0; 1618 if ((val & 0xff) != 0xff && (val & 0x80)) { 1619 delta_2ghz = val & 0xf; 1620 if (!(val & 0x40)) /* negative number */ 1621 delta_2ghz = -delta_2ghz; 1622 } 1623 val >>= 8; 1624 if ((val & 0xff) != 0xff && (val & 0x80)) { 1625 delta_5ghz = val & 0xf; 1626 if (!(val & 0x40)) /* negative number */ 1627 delta_5ghz = -delta_5ghz; 1628 } 1629 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1630 delta_2ghz, delta_5ghz)); 1631 1632 for (ridx = 0; ridx < 5; ridx++) { 1633 uint32_t reg; 1634 1635 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1636 reg = val; 1637 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1638 reg |= (uint32_t)val << 16; 1639 1640 sc->txpow20mhz[ridx] = reg; 1641 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1642 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1643 1644 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1645 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1646 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1647 } 1648 1649 DPRINTF(("mac_ver %hx\n", sc->mac_ver)); 1650 /* read RSSI offsets and LNA gains from EEPROM */ 1651 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1652 RT3593_EEPROM_RSSI1_2GHZ, &val); 1653 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1654 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1655 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1656 RT3593_EEPROM_RSSI2_2GHZ, &val); 1657 if (sc->mac_ver >= 0x3070) { 1658 if (sc->mac_ver == 0x3593) { 1659 sc->txmixgain_2ghz = 0; 1660 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1661 } else { 1662 /* 1663 * On RT3070 chips (limited to 2 Rx chains), this ROM 1664 * field contains the Tx mixer gain for the 2GHz band. 1665 */ 1666 if ((val & 0xff) != 0xff) 1667 sc->txmixgain_2ghz = val & 0x7; 1668 } 1669 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1670 } else { 1671 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1672 } 1673 if (sc->mac_ver == 0x3593) 1674 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1675 sc->lna[2] = val >> 8; /* channel group 2 */ 1676 1677 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1678 RT3593_EEPROM_RSSI1_5GHZ, &val); 1679 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1680 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1681 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1682 RT3593_EEPROM_RSSI2_5GHZ, &val); 1683 if (sc->mac_ver == 0x3572) { 1684 /* 1685 * On RT3572 chips (limited to 2 Rx chains), this ROM 1686 * field contains the Tx mixer gain for the 5GHz band. 1687 */ 1688 if ((val & 0xff) != 0xff) 1689 sc->txmixgain_5ghz = val & 0x7; 1690 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1691 } else { 1692 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1693 } 1694 if (sc->mac_ver == 0x3593) { 1695 sc->txmixgain_5ghz = 0; 1696 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1697 } 1698 sc->lna[3] = val >> 8; /* channel group 3 */ 1699 1700 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1701 RT3593_EEPROM_LNA, &val); 1702 sc->lna[0] = val & 0xff; /* channel group 0 */ 1703 sc->lna[1] = val >> 8; /* channel group 1 */ 1704 1705 /* fix broken 5GHz LNA entries */ 1706 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1707 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1708 sc->lna[2] = sc->lna[1]; 1709 } 1710 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1711 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1712 sc->lna[3] = sc->lna[1]; 1713 } 1714 1715 /* fix broken RSSI offset entries */ 1716 for (ant = 0; ant < 3; ant++) { 1717 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1718 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1719 ant + 1, sc->rssi_2ghz[ant])); 1720 sc->rssi_2ghz[ant] = 0; 1721 } 1722 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1723 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1724 ant + 1, sc->rssi_5ghz[ant])); 1725 sc->rssi_5ghz[ant] = 0; 1726 } 1727 } 1728 return 0; 1729 } 1730 1731 static struct ieee80211_node * 1732 run_node_alloc(struct ieee80211_node_table *nt) 1733 { 1734 struct run_node *rn = 1735 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1736 return rn ? &rn->ni : NULL; 1737 } 1738 1739 static int 1740 run_media_change(struct ifnet *ifp) 1741 { 1742 struct run_softc *sc = ifp->if_softc; 1743 struct ieee80211com *ic = &sc->sc_ic; 1744 uint8_t rate, ridx; 1745 int error; 1746 1747 error = ieee80211_media_change(ifp); 1748 if (error != ENETRESET) 1749 return error; 1750 1751 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1752 rate = ic->ic_sup_rates[ic->ic_curmode]. 1753 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1754 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1755 if (rt2860_rates[ridx].rate == rate) 1756 break; 1757 sc->fixed_ridx = ridx; 1758 } 1759 1760 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1761 run_init(ifp); 1762 1763 return 0; 1764 } 1765 1766 static void 1767 run_next_scan(void *arg) 1768 { 1769 struct run_softc *sc = arg; 1770 1771 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1772 ieee80211_next_scan(&sc->sc_ic); 1773 } 1774 1775 static void 1776 run_task(void *arg) 1777 { 1778 struct run_softc *sc = arg; 1779 struct run_host_cmd_ring *ring = &sc->cmdq; 1780 struct run_host_cmd *cmd; 1781 int s; 1782 1783 /* process host commands */ 1784 s = splusb(); 1785 while (ring->next != ring->cur) { 1786 cmd = &ring->cmd[ring->next]; 1787 splx(s); 1788 membar_consumer(); 1789 /* callback */ 1790 cmd->cb(sc, cmd->data); 1791 s = splusb(); 1792 atomic_dec_uint(&ring->queued); 1793 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1794 } 1795 wakeup(ring); 1796 splx(s); 1797 } 1798 1799 static void 1800 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1801 void *arg, int len) 1802 { 1803 struct run_host_cmd_ring *ring = &sc->cmdq; 1804 struct run_host_cmd *cmd; 1805 int s; 1806 1807 if (sc->sc_flags & RUN_DETACHING) 1808 return; 1809 1810 s = splusb(); 1811 cmd = &ring->cmd[ring->cur]; 1812 cmd->cb = cb; 1813 KASSERT(len <= sizeof(cmd->data)); 1814 memcpy(cmd->data, arg, len); 1815 membar_producer(); 1816 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1817 1818 /* if there is no pending command already, schedule a task */ 1819 if (atomic_inc_uint_nv(&ring->queued) == 1) 1820 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1821 splx(s); 1822 } 1823 1824 static int 1825 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1826 { 1827 struct run_softc *sc = ic->ic_ifp->if_softc; 1828 struct run_cmd_newstate cmd; 1829 1830 callout_stop(&sc->scan_to); 1831 callout_stop(&sc->calib_to); 1832 1833 /* do it in a process context */ 1834 cmd.state = nstate; 1835 cmd.arg = arg; 1836 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1837 return 0; 1838 } 1839 1840 static void 1841 run_newstate_cb(struct run_softc *sc, void *arg) 1842 { 1843 struct run_cmd_newstate *cmd = arg; 1844 struct ifnet *ifp = &sc->sc_if; 1845 struct ieee80211com *ic = &sc->sc_ic; 1846 enum ieee80211_state ostate; 1847 struct ieee80211_node *ni; 1848 uint32_t tmp, sta[3]; 1849 uint8_t wcid; 1850 int s; 1851 1852 s = splnet(); 1853 ostate = ic->ic_state; 1854 1855 if (ostate == IEEE80211_S_RUN) { 1856 /* turn link LED off */ 1857 run_set_leds(sc, RT2860_LED_RADIO); 1858 } 1859 1860 switch (cmd->state) { 1861 case IEEE80211_S_INIT: 1862 if (ostate == IEEE80211_S_RUN) { 1863 /* abort TSF synchronization */ 1864 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1865 run_write(sc, RT2860_BCN_TIME_CFG, 1866 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1867 RT2860_TBTT_TIMER_EN)); 1868 } 1869 break; 1870 1871 case IEEE80211_S_SCAN: 1872 run_set_chan(sc, ic->ic_curchan); 1873 callout_schedule(&sc->scan_to, hz / 5); 1874 break; 1875 1876 case IEEE80211_S_AUTH: 1877 case IEEE80211_S_ASSOC: 1878 run_set_chan(sc, ic->ic_curchan); 1879 break; 1880 1881 case IEEE80211_S_RUN: 1882 run_set_chan(sc, ic->ic_curchan); 1883 1884 ni = ic->ic_bss; 1885 1886 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1887 run_updateslot(ifp); 1888 run_enable_mrr(sc); 1889 run_set_txpreamble(sc); 1890 run_set_basicrates(sc); 1891 run_set_bssid(sc, ni->ni_bssid); 1892 } 1893 #ifndef IEEE80211_STA_ONLY 1894 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1895 ic->ic_opmode == IEEE80211_M_IBSS) 1896 (void)run_setup_beacon(sc); 1897 #endif 1898 if (ic->ic_opmode == IEEE80211_M_STA) { 1899 /* add BSS entry to the WCID table */ 1900 wcid = RUN_AID2WCID(ni->ni_associd); 1901 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1902 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1903 1904 /* fake a join to init the tx rate */ 1905 run_newassoc(ni, 1); 1906 } 1907 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1908 run_enable_tsf_sync(sc); 1909 1910 /* clear statistic registers used by AMRR */ 1911 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1912 (uint8_t *)sta, sizeof(sta)); 1913 /* start calibration timer */ 1914 callout_schedule(&sc->calib_to, hz); 1915 } 1916 1917 /* turn link LED on */ 1918 run_set_leds(sc, RT2860_LED_RADIO | 1919 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1920 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1921 break; 1922 } 1923 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1924 splx(s); 1925 } 1926 1927 static int 1928 run_updateedca(struct ieee80211com *ic) 1929 { 1930 1931 /* do it in a process context */ 1932 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1933 return 0; 1934 } 1935 1936 /* ARGSUSED */ 1937 static void 1938 run_updateedca_cb(struct run_softc *sc, void *arg) 1939 { 1940 struct ieee80211com *ic = &sc->sc_ic; 1941 int s, aci; 1942 1943 s = splnet(); 1944 /* update MAC TX configuration registers */ 1945 for (aci = 0; aci < WME_NUM_AC; aci++) { 1946 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1947 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1948 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1949 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1950 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1951 } 1952 1953 /* update SCH/DMA registers too */ 1954 run_write(sc, RT2860_WMM_AIFSN_CFG, 1955 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1956 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1957 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1958 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1959 run_write(sc, RT2860_WMM_CWMIN_CFG, 1960 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1961 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1962 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1963 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1964 run_write(sc, RT2860_WMM_CWMAX_CFG, 1965 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1966 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1967 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1968 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1969 run_write(sc, RT2860_WMM_TXOP0_CFG, 1970 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1971 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1972 run_write(sc, RT2860_WMM_TXOP1_CFG, 1973 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1974 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1975 splx(s); 1976 } 1977 1978 #ifdef RUN_HWCRYPTO 1979 static int 1980 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1981 const uint8_t *mac) 1982 { 1983 struct run_softc *sc = ic->ic_ifp->if_softc; 1984 struct ieee80211_node *ni = ic->ic_bss; 1985 struct run_cmd_key cmd; 1986 1987 /* do it in a process context */ 1988 cmd.key = *k; 1989 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1990 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1991 return 1; 1992 } 1993 1994 static void 1995 run_set_key_cb(struct run_softc *sc, void *arg) 1996 { 1997 #ifndef IEEE80211_STA_ONLY 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 #endif 2000 struct run_cmd_key *cmd = arg; 2001 struct ieee80211_key *k = &cmd->key; 2002 uint32_t attr; 2003 uint16_t base; 2004 uint8_t mode, wcid, iv[8]; 2005 2006 /* map net80211 cipher to RT2860 security mode */ 2007 switch (k->wk_cipher->ic_cipher) { 2008 case IEEE80211_CIPHER_WEP: 2009 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2010 if (k->wk_keylen == 5) 2011 mode = RT2860_MODE_WEP40; 2012 else 2013 mode = RT2860_MODE_WEP104; 2014 break; 2015 case IEEE80211_CIPHER_TKIP: 2016 mode = RT2860_MODE_TKIP; 2017 break; 2018 case IEEE80211_CIPHER_AES_CCM: 2019 mode = RT2860_MODE_AES_CCMP; 2020 break; 2021 default: 2022 return; 2023 } 2024 2025 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2026 wcid = 0; /* NB: update WCID0 for group keys */ 2027 base = RT2860_SKEY(0, k->wk_keyix); 2028 } else { 2029 wcid = RUN_AID2WCID(cmd->associd); 2030 base = RT2860_PKEY(wcid); 2031 } 2032 2033 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2034 run_write_region_1(sc, base, k->wk_key, 16); 2035 #ifndef IEEE80211_STA_ONLY 2036 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2037 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 2038 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 2039 } else 2040 #endif 2041 { 2042 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 2043 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 2044 } 2045 } else { 2046 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2047 run_write_region_1(sc, base, k->wk_key, 2048 (k->wk_keylen + 1) & ~1); 2049 } 2050 2051 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2052 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2053 /* set initial packet number in IV+EIV */ 2054 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2055 memset(iv, 0, sizeof(iv)); 2056 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2057 } else { 2058 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2059 iv[0] = k->wk_keytsc >> 8; 2060 iv[1] = (iv[0] | 0x20) & 0x7f; 2061 iv[2] = k->wk_keytsc; 2062 } else /* CCMP */ { 2063 iv[0] = k->wk_keytsc; 2064 iv[1] = k->wk_keytsc >> 8; 2065 iv[2] = 0; 2066 } 2067 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2068 iv[4] = k->wk_keytsc >> 16; 2069 iv[5] = k->wk_keytsc >> 24; 2070 iv[6] = k->wk_keytsc >> 32; 2071 iv[7] = k->wk_keytsc >> 40; 2072 } 2073 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2074 } 2075 2076 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2077 /* install group key */ 2078 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2079 attr &= ~(0xf << (k->wk_keyix * 4)); 2080 attr |= mode << (k->wk_keyix * 4); 2081 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2082 } else { 2083 /* install pairwise key */ 2084 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2085 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2086 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2087 } 2088 } 2089 2090 static int 2091 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2092 { 2093 struct run_softc *sc = ic->ic_ifp->if_softc; 2094 struct ieee80211_node *ni = ic->ic_bss; 2095 struct run_cmd_key cmd; 2096 2097 /* do it in a process context */ 2098 cmd.key = *k; 2099 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2100 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2101 return 1; 2102 } 2103 2104 static void 2105 run_delete_key_cb(struct run_softc *sc, void *arg) 2106 { 2107 struct run_cmd_key *cmd = arg; 2108 struct ieee80211_key *k = &cmd->key; 2109 uint32_t attr; 2110 uint8_t wcid; 2111 2112 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2113 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2114 2115 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2116 /* remove group key */ 2117 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2118 attr &= ~(0xf << (k->wk_keyix * 4)); 2119 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2120 2121 } else { 2122 /* remove pairwise key */ 2123 wcid = RUN_AID2WCID(cmd->associd); 2124 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2125 attr &= ~0xf; 2126 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2127 } 2128 } 2129 #endif 2130 2131 static void 2132 run_calibrate_to(void *arg) 2133 { 2134 2135 /* do it in a process context */ 2136 run_do_async(arg, run_calibrate_cb, NULL, 0); 2137 /* next timeout will be rescheduled in the calibration task */ 2138 } 2139 2140 /* ARGSUSED */ 2141 static void 2142 run_calibrate_cb(struct run_softc *sc, void *arg) 2143 { 2144 struct ifnet *ifp = &sc->sc_if; 2145 uint32_t sta[3]; 2146 int s, error; 2147 2148 /* read statistic counters (clear on read) and update AMRR state */ 2149 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2150 sizeof(sta)); 2151 if (error != 0) 2152 goto skip; 2153 2154 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2155 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2156 le32toh(sta[0]) & 0xffff)); 2157 2158 s = splnet(); 2159 /* count failed TX as errors */ 2160 if_statadd(ifp, if_oerrors, le32toh(sta[0]) & 0xffff); 2161 2162 sc->amn.amn_retrycnt = 2163 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2164 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2165 2166 sc->amn.amn_txcnt = 2167 sc->amn.amn_retrycnt + 2168 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2169 2170 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2171 splx(s); 2172 2173 skip: callout_schedule(&sc->calib_to, hz); 2174 } 2175 2176 static void 2177 run_newassoc(struct ieee80211_node *ni, int isnew) 2178 { 2179 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2180 struct run_node *rn = (void *)ni; 2181 struct ieee80211_rateset *rs = &ni->ni_rates; 2182 uint8_t rate; 2183 int ridx, i, j; 2184 2185 DPRINTF(("new assoc isnew=%d addr=%s\n", 2186 isnew, ether_sprintf(ni->ni_macaddr))); 2187 2188 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2189 /* start at lowest available bit-rate, AMRR will raise */ 2190 ni->ni_txrate = 0; 2191 2192 for (i = 0; i < rs->rs_nrates; i++) { 2193 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2194 /* convert 802.11 rate to hardware rate index */ 2195 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2196 if (rt2860_rates[ridx].rate == rate) 2197 break; 2198 rn->ridx[i] = ridx; 2199 /* determine rate of control response frames */ 2200 for (j = i; j >= 0; j--) { 2201 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2202 rt2860_rates[rn->ridx[i]].phy == 2203 rt2860_rates[rn->ridx[j]].phy) 2204 break; 2205 } 2206 if (j >= 0) { 2207 rn->ctl_ridx[i] = rn->ridx[j]; 2208 } else { 2209 /* no basic rate found, use mandatory one */ 2210 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2211 } 2212 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2213 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2214 } 2215 } 2216 2217 /* 2218 * Return the Rx chain with the highest RSSI for a given frame. 2219 */ 2220 static __inline uint8_t 2221 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2222 { 2223 uint8_t rxchain = 0; 2224 2225 if (sc->nrxchains > 1) { 2226 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2227 rxchain = 1; 2228 if (sc->nrxchains > 2) 2229 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2230 rxchain = 2; 2231 } 2232 return rxchain; 2233 } 2234 2235 static void 2236 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2237 { 2238 struct ieee80211com *ic = &sc->sc_ic; 2239 struct ifnet *ifp = &sc->sc_if; 2240 struct ieee80211_frame *wh; 2241 struct ieee80211_node *ni; 2242 struct rt2870_rxd *rxd; 2243 struct rt2860_rxwi *rxwi; 2244 struct mbuf *m; 2245 uint32_t flags; 2246 uint16_t len, rxwisize, phy; 2247 uint8_t ant, rssi; 2248 int s; 2249 #ifdef RUN_HWCRYPTO 2250 int decrypted = 0; 2251 #endif 2252 2253 rxwi = (struct rt2860_rxwi *)buf; 2254 rxwisize = sizeof(struct rt2860_rxwi); 2255 if (sc->mac_ver == 0x5592) 2256 rxwisize += sizeof(uint64_t); 2257 else if (sc->mac_ver == 0x3593) 2258 rxwisize += sizeof(uint32_t); 2259 len = le16toh(rxwi->len) & 0xfff; 2260 if (__predict_false(len > dmalen)) { 2261 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2262 return; 2263 } 2264 /* Rx descriptor is located at the end */ 2265 rxd = (struct rt2870_rxd *)(buf + dmalen); 2266 flags = le32toh(rxd->flags); 2267 2268 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2269 if_statinc(ifp, if_ierrors); 2270 return; 2271 } 2272 2273 wh = (struct ieee80211_frame *)(buf + rxwisize); 2274 2275 if (__predict_false((flags & RT2860_RX_MICERR))) { 2276 /* report MIC failures to net80211 for TKIP */ 2277 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2278 if_statinc(ifp, if_ierrors); 2279 return; 2280 } 2281 2282 if (flags & RT2860_RX_L2PAD) { 2283 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2284 memmove((uint8_t *)wh + 2, wh, hdrlen); 2285 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2286 } 2287 2288 #ifdef RUN_HWCRYPTO 2289 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2290 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2291 decrypted = 1; 2292 } 2293 #endif 2294 2295 /* could use m_devget but net80211 wants contig mgmt frames */ 2296 MGETHDR(m, M_DONTWAIT, MT_DATA); 2297 if (__predict_false(m == NULL)) { 2298 if_statinc(ifp, if_ierrors); 2299 return; 2300 } 2301 if (len > MHLEN) { 2302 MCLGET(m, M_DONTWAIT); 2303 if (__predict_false(!(m->m_flags & M_EXT))) { 2304 if_statinc(ifp, if_ierrors); 2305 m_freem(m); 2306 return; 2307 } 2308 } 2309 /* finalize mbuf */ 2310 m_set_rcvif(m, ifp); 2311 memcpy(mtod(m, void *), wh, len); 2312 m->m_pkthdr.len = m->m_len = len; 2313 2314 ant = run_maxrssi_chain(sc, rxwi); 2315 rssi = rxwi->rssi[ant]; 2316 2317 if (__predict_false(sc->sc_drvbpf != NULL)) { 2318 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2319 2320 tap->wr_flags = 0; 2321 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2322 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2323 tap->wr_antsignal = rssi; 2324 tap->wr_antenna = ant; 2325 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2326 tap->wr_rate = 2; /* in case it can't be found below */ 2327 phy = le16toh(rxwi->phy); 2328 switch (phy & RT2860_PHY_MODE) { 2329 case RT2860_PHY_CCK: 2330 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2331 case 0: tap->wr_rate = 2; break; 2332 case 1: tap->wr_rate = 4; break; 2333 case 2: tap->wr_rate = 11; break; 2334 case 3: tap->wr_rate = 22; break; 2335 } 2336 if (phy & RT2860_PHY_SHPRE) 2337 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2338 break; 2339 case RT2860_PHY_OFDM: 2340 switch (phy & RT2860_PHY_MCS) { 2341 case 0: tap->wr_rate = 12; break; 2342 case 1: tap->wr_rate = 18; break; 2343 case 2: tap->wr_rate = 24; break; 2344 case 3: tap->wr_rate = 36; break; 2345 case 4: tap->wr_rate = 48; break; 2346 case 5: tap->wr_rate = 72; break; 2347 case 6: tap->wr_rate = 96; break; 2348 case 7: tap->wr_rate = 108; break; 2349 } 2350 break; 2351 } 2352 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2353 } 2354 2355 s = splnet(); 2356 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2357 #ifdef RUN_HWCRYPTO 2358 if (decrypted) { 2359 uint32_t icflags = ic->ic_flags; 2360 2361 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2362 ieee80211_input(ic, m, ni, rssi, 0); 2363 ic->ic_flags = icflags; 2364 } else 2365 #endif 2366 ieee80211_input(ic, m, ni, rssi, 0); 2367 2368 /* node is no longer needed */ 2369 ieee80211_free_node(ni); 2370 2371 /* 2372 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2373 * without calling if_start(). 2374 */ 2375 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2376 run_start(ifp); 2377 2378 splx(s); 2379 } 2380 2381 static void 2382 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2383 { 2384 struct run_rx_data *data = priv; 2385 struct run_softc *sc = data->sc; 2386 uint8_t *buf; 2387 uint32_t dmalen; 2388 int xferlen; 2389 uint16_t rxwisize; 2390 2391 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2392 return; 2393 2394 rxwisize = sizeof(struct rt2860_rxwi); 2395 if (sc->mac_ver == 0x5592) 2396 rxwisize += sizeof(uint64_t); 2397 else if (sc->mac_ver == 0x3593) 2398 rxwisize += sizeof(uint32_t); 2399 2400 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2401 DPRINTF(("RX status=%s\n", usbd_errstr(status))); 2402 if (status == USBD_STALLED) 2403 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2404 if (status != USBD_CANCELLED) 2405 goto skip; 2406 return; 2407 } 2408 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2409 2410 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2411 rxwisize + sizeof(struct rt2870_rxd)))) { 2412 DPRINTF(("xfer too short %d\n", xferlen)); 2413 goto skip; 2414 } 2415 2416 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2417 buf = data->buf; 2418 while (xferlen > 8) { 2419 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2420 2421 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2422 (dmalen & 3) != 0)) { 2423 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2424 break; 2425 } 2426 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2427 DPRINTF(("bad DMA length %u > %d\n", 2428 dmalen + 8, xferlen)); 2429 break; 2430 } 2431 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2432 buf += dmalen + 8; 2433 xferlen -= dmalen + 8; 2434 } 2435 2436 skip: /* setup a new transfer */ 2437 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2438 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2439 status = usbd_transfer(xfer); 2440 if (status != USBD_NORMAL_COMPLETION && 2441 status != USBD_IN_PROGRESS) 2442 device_printf(sc->sc_dev, "requeuing rx failed: %s\n", 2443 usbd_errstr(status)); 2444 } 2445 2446 static void 2447 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2448 { 2449 struct run_tx_data *data = priv; 2450 struct run_softc *sc = data->sc; 2451 struct run_tx_ring *txq = &sc->txq[data->qid]; 2452 struct ifnet *ifp = &sc->sc_if; 2453 int s; 2454 2455 s = splnet(); 2456 txq->queued--; 2457 sc->qfullmsk &= ~(1 << data->qid); 2458 2459 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2460 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2461 return; 2462 2463 DPRINTF(("%s: usb error on tx: %s\n", 2464 device_xname(sc->sc_dev), usbd_errstr(status))); 2465 if (status == USBD_STALLED) 2466 usbd_clear_endpoint_stall_async(txq->pipeh); 2467 if_statinc(ifp, if_oerrors); 2468 splx(s); 2469 return; 2470 } 2471 2472 sc->sc_tx_timer = 0; 2473 if_statinc(ifp, if_opackets); 2474 ifp->if_flags &= ~IFF_OACTIVE; 2475 run_start(ifp); 2476 splx(s); 2477 } 2478 2479 static int 2480 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2481 { 2482 struct ieee80211com *ic = &sc->sc_ic; 2483 struct run_node *rn = (void *)ni; 2484 struct ieee80211_frame *wh; 2485 #ifndef RUN_HWCRYPTO 2486 struct ieee80211_key *k; 2487 #endif 2488 struct run_tx_ring *ring; 2489 struct run_tx_data *data; 2490 struct rt2870_txd *txd; 2491 struct rt2860_txwi *txwi; 2492 uint16_t qos, dur, mcs; 2493 uint16_t txwisize; 2494 uint8_t type, tid, qid; 2495 int hasqos, ridx, ctl_ridx, xferlen; 2496 uint8_t pad; 2497 usbd_status status; 2498 2499 wh = mtod(m, struct ieee80211_frame *); 2500 2501 #ifndef RUN_HWCRYPTO 2502 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2503 k = ieee80211_crypto_encap(ic, ni, m); 2504 if (k == NULL) { 2505 m_freem(m); 2506 return ENOBUFS; 2507 } 2508 2509 /* packet header may have moved, reset our local pointer */ 2510 wh = mtod(m, struct ieee80211_frame *); 2511 } 2512 #endif 2513 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2514 2515 if ((hasqos = ieee80211_has_qos(wh))) { 2516 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2517 tid = qos & IEEE80211_QOS_TID; 2518 qid = TID_TO_WME_AC(tid); 2519 } else { 2520 qos = 0; 2521 tid = 0; 2522 qid = WME_AC_BE; 2523 } 2524 ring = &sc->txq[qid]; 2525 data = &ring->data[ring->cur]; 2526 2527 /* pickup a rate index */ 2528 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2529 type != IEEE80211_FC0_TYPE_DATA) { 2530 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2531 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2532 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2533 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2534 ridx = sc->fixed_ridx; 2535 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2536 } else { 2537 ridx = rn->ridx[ni->ni_txrate]; 2538 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2539 } 2540 2541 /* get MCS code from rate index */ 2542 mcs = rt2860_rates[ridx].mcs; 2543 2544 txwisize = sizeof(struct rt2860_txwi); 2545 if (sc->mac_ver == 0x5592) 2546 txwisize += sizeof(uint32_t); 2547 xferlen = txwisize + m->m_pkthdr.len; 2548 2549 /* roundup to 32-bit alignment */ 2550 xferlen = (xferlen + 3) & ~3; 2551 2552 txd = (struct rt2870_txd *)data->buf; 2553 txd->flags = RT2860_TX_QSEL_EDCA; 2554 txd->len = htole16(xferlen); 2555 2556 /* 2557 * Ether both are true or both are false, the header 2558 * are nicely aligned to 32-bit. So, no L2 padding. 2559 */ 2560 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2561 pad = 0; 2562 else 2563 pad = 2; 2564 2565 /* setup TX Wireless Information */ 2566 txwi = (struct rt2860_txwi *)(txd + 1); 2567 txwi->flags = 0; 2568 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2569 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2570 RUN_AID2WCID(ni->ni_associd) : 0xff; 2571 txwi->len = htole16(m->m_pkthdr.len - pad); 2572 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2573 txwi->phy = htole16(RT2860_PHY_CCK); 2574 if (ridx != RT2860_RIDX_CCK1 && 2575 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2576 mcs |= RT2860_PHY_SHPRE; 2577 } else 2578 mcs |= RT2860_PHY_OFDM; 2579 txwi->phy = htole16(mcs); 2580 2581 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2582 2583 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2584 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2585 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2586 txwi->xflags |= RT2860_TX_ACK; 2587 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2588 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2589 else 2590 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2591 *(uint16_t *)wh->i_dur = htole16(dur); 2592 } 2593 2594 #ifndef IEEE80211_STA_ONLY 2595 /* ask MAC to insert timestamp into probe responses */ 2596 if ((wh->i_fc[0] & 2597 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2598 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2599 /* NOTE: beacons do not pass through tx_data() */ 2600 txwi->flags |= RT2860_TX_TS; 2601 #endif 2602 2603 if (__predict_false(sc->sc_drvbpf != NULL)) { 2604 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2605 2606 tap->wt_flags = 0; 2607 tap->wt_rate = rt2860_rates[ridx].rate; 2608 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2609 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2610 tap->wt_hwqueue = qid; 2611 if (mcs & RT2860_PHY_SHPRE) 2612 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2613 2614 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2615 } 2616 2617 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2618 m_freem(m); 2619 2620 xferlen += sizeof(*txd) + 4; 2621 2622 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2623 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2624 status = usbd_transfer(data->xfer); 2625 if (__predict_false(status != USBD_IN_PROGRESS && 2626 status != USBD_NORMAL_COMPLETION)) { 2627 device_printf(sc->sc_dev, "queuing tx failed: %s\n", 2628 usbd_errstr(status)); 2629 return EIO; 2630 } 2631 2632 ieee80211_free_node(ni); 2633 2634 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2635 if (++ring->queued >= RUN_TX_RING_COUNT) 2636 sc->qfullmsk |= 1 << qid; 2637 2638 return 0; 2639 } 2640 2641 static void 2642 run_start(struct ifnet *ifp) 2643 { 2644 struct run_softc *sc = ifp->if_softc; 2645 struct ieee80211com *ic = &sc->sc_ic; 2646 struct ether_header *eh; 2647 struct ieee80211_node *ni; 2648 struct mbuf *m; 2649 2650 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2651 return; 2652 2653 for (;;) { 2654 if (sc->qfullmsk != 0) { 2655 ifp->if_flags |= IFF_OACTIVE; 2656 break; 2657 } 2658 /* send pending management frames first */ 2659 IF_DEQUEUE(&ic->ic_mgtq, m); 2660 if (m != NULL) { 2661 ni = M_GETCTX(m, struct ieee80211_node *); 2662 M_CLEARCTX(m); 2663 goto sendit; 2664 } 2665 if (ic->ic_state != IEEE80211_S_RUN) 2666 break; 2667 2668 /* encapsulate and send data frames */ 2669 IFQ_DEQUEUE(&ifp->if_snd, m); 2670 if (m == NULL) 2671 break; 2672 if (m->m_len < (int)sizeof(*eh) && 2673 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2674 if_statinc(ifp, if_oerrors); 2675 continue; 2676 } 2677 2678 eh = mtod(m, struct ether_header *); 2679 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2680 if (ni == NULL) { 2681 m_freem(m); 2682 if_statinc(ifp, if_oerrors); 2683 continue; 2684 } 2685 2686 bpf_mtap(ifp, m, BPF_D_OUT); 2687 2688 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2689 ieee80211_free_node(ni); 2690 if_statinc(ifp, if_oerrors); 2691 continue; 2692 } 2693 sendit: 2694 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2695 2696 if (run_tx(sc, m, ni) != 0) { 2697 ieee80211_free_node(ni); 2698 if_statinc(ifp, if_oerrors); 2699 continue; 2700 } 2701 2702 sc->sc_tx_timer = 5; 2703 ifp->if_timer = 1; 2704 } 2705 } 2706 2707 static void 2708 run_watchdog(struct ifnet *ifp) 2709 { 2710 struct run_softc *sc = ifp->if_softc; 2711 struct ieee80211com *ic = &sc->sc_ic; 2712 2713 ifp->if_timer = 0; 2714 2715 if (sc->sc_tx_timer > 0) { 2716 if (--sc->sc_tx_timer == 0) { 2717 device_printf(sc->sc_dev, "device timeout\n"); 2718 /* run_init(ifp); XXX needs a process context! */ 2719 if_statinc(ifp, if_oerrors); 2720 return; 2721 } 2722 ifp->if_timer = 1; 2723 } 2724 2725 ieee80211_watchdog(ic); 2726 } 2727 2728 static int 2729 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2730 { 2731 struct run_softc *sc = ifp->if_softc; 2732 struct ieee80211com *ic = &sc->sc_ic; 2733 int s, error = 0; 2734 2735 s = splnet(); 2736 2737 switch (cmd) { 2738 case SIOCSIFFLAGS: 2739 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2740 break; 2741 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2742 case IFF_UP|IFF_RUNNING: 2743 break; 2744 case IFF_UP: 2745 run_init(ifp); 2746 break; 2747 case IFF_RUNNING: 2748 run_stop(ifp, 1); 2749 break; 2750 case 0: 2751 break; 2752 } 2753 break; 2754 2755 case SIOCADDMULTI: 2756 case SIOCDELMULTI: 2757 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2758 /* setup multicast filter, etc */ 2759 error = 0; 2760 } 2761 break; 2762 2763 default: 2764 error = ieee80211_ioctl(ic, cmd, data); 2765 break; 2766 } 2767 2768 if (error == ENETRESET) { 2769 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2770 (IFF_UP | IFF_RUNNING)) { 2771 run_init(ifp); 2772 } 2773 error = 0; 2774 } 2775 2776 splx(s); 2777 2778 return error; 2779 } 2780 2781 static void 2782 run_select_chan_group(struct run_softc *sc, int group) 2783 { 2784 uint32_t tmp; 2785 uint8_t agc; 2786 2787 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2788 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2789 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2790 if (sc->mac_ver < 0x3572) 2791 run_bbp_write(sc, 86, 0x00); 2792 2793 if (sc->mac_ver == 0x3593) { 2794 run_bbp_write(sc, 77, 0x98); 2795 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2796 } 2797 2798 if (group == 0) { 2799 if (sc->ext_2ghz_lna) { 2800 if (sc->mac_ver >= 0x5390) 2801 run_bbp_write(sc, 75, 0x52); 2802 else { 2803 run_bbp_write(sc, 82, 0x62); 2804 run_bbp_write(sc, 75, 0x46); 2805 } 2806 } else { 2807 if (sc->mac_ver == 0x5592) { 2808 run_bbp_write(sc, 79, 0x1c); 2809 run_bbp_write(sc, 80, 0x0e); 2810 run_bbp_write(sc, 81, 0x3a); 2811 run_bbp_write(sc, 82, 0x62); 2812 2813 run_bbp_write(sc, 195, 0x80); 2814 run_bbp_write(sc, 196, 0xe0); 2815 run_bbp_write(sc, 195, 0x81); 2816 run_bbp_write(sc, 196, 0x1f); 2817 run_bbp_write(sc, 195, 0x82); 2818 run_bbp_write(sc, 196, 0x38); 2819 run_bbp_write(sc, 195, 0x83); 2820 run_bbp_write(sc, 196, 0x32); 2821 run_bbp_write(sc, 195, 0x85); 2822 run_bbp_write(sc, 196, 0x28); 2823 run_bbp_write(sc, 195, 0x86); 2824 run_bbp_write(sc, 196, 0x19); 2825 } else if (sc->mac_ver >= 0x5390) { 2826 run_bbp_write(sc, 75, 0x50); 2827 } else { 2828 run_bbp_write(sc, 82, 2829 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2830 run_bbp_write(sc, 75, 0x50); 2831 } 2832 } 2833 } else { 2834 if (sc->mac_ver == 0x5592) { 2835 run_bbp_write(sc, 79, 0x18); 2836 run_bbp_write(sc, 80, 0x08); 2837 run_bbp_write(sc, 81, 0x38); 2838 run_bbp_write(sc, 82, 0x92); 2839 2840 run_bbp_write(sc, 195, 0x80); 2841 run_bbp_write(sc, 196, 0xf0); 2842 run_bbp_write(sc, 195, 0x81); 2843 run_bbp_write(sc, 196, 0x1e); 2844 run_bbp_write(sc, 195, 0x82); 2845 run_bbp_write(sc, 196, 0x28); 2846 run_bbp_write(sc, 195, 0x83); 2847 run_bbp_write(sc, 196, 0x20); 2848 run_bbp_write(sc, 195, 0x85); 2849 run_bbp_write(sc, 196, 0x7f); 2850 run_bbp_write(sc, 195, 0x86); 2851 run_bbp_write(sc, 196, 0x7f); 2852 } else if (sc->mac_ver == 0x3572) 2853 run_bbp_write(sc, 82, 0x94); 2854 else 2855 run_bbp_write(sc, 82, 2856 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2857 if (sc->ext_5ghz_lna) 2858 run_bbp_write(sc, 75, 0x46); 2859 else 2860 run_bbp_write(sc, 75, 0x50); 2861 } 2862 2863 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2864 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2865 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2866 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2867 2868 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2869 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2870 if (sc->mac_ver == 0x3593) 2871 tmp |= RT3593_LNA_PE_G2_EN | RT3593_LNA_PE_A2_EN; 2872 if (sc->nrxchains > 1) 2873 tmp |= RT2860_LNA_PE1_EN; 2874 if (group == 0) { /* 2GHz */ 2875 tmp |= RT2860_PA_PE_G0_EN; 2876 if (sc->ntxchains > 1) 2877 tmp |= RT2860_PA_PE_G1_EN; 2878 } else { /* 5GHz */ 2879 tmp |= RT2860_PA_PE_A0_EN; 2880 if (sc->ntxchains > 1) 2881 tmp |= RT2860_PA_PE_A1_EN; 2882 if (sc->mac_ver == 0x3593) { 2883 if (sc->ntxchains > 2) 2884 tmp |= RT3593_PA_PE_G2_EN; 2885 } 2886 } 2887 if (sc->mac_ver == 0x3572) { 2888 run_rt3070_rf_write(sc, 8, 0x00); 2889 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2890 run_rt3070_rf_write(sc, 8, 0x80); 2891 } else 2892 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2893 2894 if (sc->mac_ver == 0x5592) { 2895 run_bbp_write(sc, 195, 0x8d); 2896 run_bbp_write(sc, 196, 0x1a); 2897 } 2898 2899 if (sc->mac_ver == 0x3593) { 2900 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2901 tmp &= ~0x01010000; 2902 if (group == 0) 2903 tmp |= 0x00010000; 2904 tmp = (tmp & ~0x00009090) | 0x00000090; 2905 run_write(sc, RT2860_GPIO_CTRL, tmp); 2906 } 2907 2908 /* set initial AGC value */ 2909 if (group == 0) { /* 2GHz band */ 2910 if (sc->mac_ver >= 0x3070) 2911 agc = 0x1c + sc->lna[0] * 2; 2912 else 2913 agc = 0x2e + sc->lna[0]; 2914 } else { /* 5GHz band */ 2915 if (sc->mac_ver == 0x3572) 2916 agc = 0x22 + (sc->lna[group] * 5) / 3; 2917 else 2918 agc = 0x32 + (sc->lna[group] * 5) / 3; 2919 } 2920 run_set_agc(sc, agc); 2921 } 2922 2923 static void 2924 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2925 { 2926 const struct rfprog *rfprog = rt2860_rf2850; 2927 uint32_t r2, r3, r4; 2928 int8_t txpow1, txpow2; 2929 int i; 2930 2931 /* find the settings for this channel (we know it exists) */ 2932 for (i = 0; rfprog[i].chan != chan; i++); 2933 2934 r2 = rfprog[i].r2; 2935 if (sc->ntxchains == 1) 2936 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2937 if (sc->nrxchains == 1) 2938 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2939 else if (sc->nrxchains == 2) 2940 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2941 2942 /* use Tx power values from EEPROM */ 2943 txpow1 = sc->txpow1[i]; 2944 txpow2 = sc->txpow2[i]; 2945 if (chan > 14) { 2946 if (txpow1 >= 0) 2947 txpow1 = txpow1 << 1 | 1; 2948 else 2949 txpow1 = (7 + txpow1) << 1; 2950 if (txpow2 >= 0) 2951 txpow2 = txpow2 << 1 | 1; 2952 else 2953 txpow2 = (7 + txpow2) << 1; 2954 } 2955 r3 = rfprog[i].r3 | txpow1 << 7; 2956 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2957 2958 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2959 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2960 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2961 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2962 2963 usbd_delay_ms(sc->sc_udev, 10); 2964 2965 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2966 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2967 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2968 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2969 2970 usbd_delay_ms(sc->sc_udev, 10); 2971 2972 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2973 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2974 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2975 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2976 } 2977 2978 static void 2979 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2980 { 2981 int8_t txpow1, txpow2; 2982 uint8_t rf; 2983 int i; 2984 2985 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2986 2987 /* find the settings for this channel (we know it exists) */ 2988 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2989 continue; 2990 2991 /* use Tx power values from EEPROM */ 2992 txpow1 = sc->txpow1[i]; 2993 txpow2 = sc->txpow2[i]; 2994 2995 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2996 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2997 run_rt3070_rf_read(sc, 6, &rf); 2998 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2999 run_rt3070_rf_write(sc, 6, rf); 3000 3001 /* set Tx0 power */ 3002 run_rt3070_rf_read(sc, 12, &rf); 3003 rf = (rf & ~0x1f) | txpow1; 3004 run_rt3070_rf_write(sc, 12, rf); 3005 3006 /* set Tx1 power */ 3007 run_rt3070_rf_read(sc, 13, &rf); 3008 rf = (rf & ~0x1f) | txpow2; 3009 run_rt3070_rf_write(sc, 13, rf); 3010 3011 run_rt3070_rf_read(sc, 1, &rf); 3012 rf &= ~0xfc; 3013 if (sc->ntxchains == 1) 3014 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3015 else if (sc->ntxchains == 2) 3016 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3017 if (sc->nrxchains == 1) 3018 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3019 else if (sc->nrxchains == 2) 3020 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3021 run_rt3070_rf_write(sc, 1, rf); 3022 3023 /* set RF offset */ 3024 run_rt3070_rf_read(sc, 23, &rf); 3025 rf = (rf & ~0x7f) | sc->freq; 3026 run_rt3070_rf_write(sc, 23, rf); 3027 3028 /* program RF filter */ 3029 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 3030 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3031 run_rt3070_rf_write(sc, 24, rf); 3032 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3033 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3034 run_rt3070_rf_write(sc, 31, rf); 3035 3036 /* enable RF tuning */ 3037 run_rt3070_rf_read(sc, 7, &rf); 3038 run_rt3070_rf_write(sc, 7, rf | 0x01); 3039 } 3040 3041 static void 3042 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3043 { 3044 int8_t txpow1, txpow2; 3045 uint32_t tmp; 3046 uint8_t rf; 3047 int i; 3048 3049 /* find the settings for this channel (we know it exists) */ 3050 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3051 3052 /* use Tx power values from EEPROM */ 3053 txpow1 = sc->txpow1[i]; 3054 txpow2 = sc->txpow2[i]; 3055 3056 if (chan <= 14) { 3057 run_bbp_write(sc, 25, sc->bbp25); 3058 run_bbp_write(sc, 26, sc->bbp26); 3059 } else { 3060 /* enable IQ phase correction */ 3061 run_bbp_write(sc, 25, 0x09); 3062 run_bbp_write(sc, 26, 0xff); 3063 } 3064 3065 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3066 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3067 run_rt3070_rf_read(sc, 6, &rf); 3068 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3069 rf |= (chan <= 14) ? 0x08 : 0x04; 3070 run_rt3070_rf_write(sc, 6, rf); 3071 3072 /* set PLL mode */ 3073 run_rt3070_rf_read(sc, 5, &rf); 3074 rf &= ~(0x08 | 0x04); 3075 rf |= (chan <= 14) ? 0x04 : 0x08; 3076 run_rt3070_rf_write(sc, 5, rf); 3077 3078 /* set Tx power for chain 0 */ 3079 if (chan <= 14) 3080 rf = 0x60 | txpow1; 3081 else 3082 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3083 run_rt3070_rf_write(sc, 12, rf); 3084 3085 /* set Tx power for chain 1 */ 3086 if (chan <= 14) 3087 rf = 0x60 | txpow2; 3088 else 3089 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3090 run_rt3070_rf_write(sc, 13, rf); 3091 3092 /* set Tx/Rx streams */ 3093 run_rt3070_rf_read(sc, 1, &rf); 3094 rf &= ~0xfc; 3095 if (sc->ntxchains == 1) 3096 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3097 else if (sc->ntxchains == 2) 3098 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3099 if (sc->nrxchains == 1) 3100 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3101 else if (sc->nrxchains == 2) 3102 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3103 run_rt3070_rf_write(sc, 1, rf); 3104 3105 /* set RF offset */ 3106 run_rt3070_rf_read(sc, 23, &rf); 3107 rf = (rf & ~0x7f) | sc->freq; 3108 run_rt3070_rf_write(sc, 23, rf); 3109 3110 /* program RF filter */ 3111 rf = sc->rf24_20mhz; 3112 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3113 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3114 3115 /* enable RF tuning */ 3116 run_rt3070_rf_read(sc, 7, &rf); 3117 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3118 run_rt3070_rf_write(sc, 7, rf); 3119 3120 /* TSSI */ 3121 rf = (chan <= 14) ? 0xc3 : 0xc0; 3122 run_rt3070_rf_write(sc, 9, rf); 3123 3124 /* set loop filter 1 */ 3125 run_rt3070_rf_write(sc, 10, 0xf1); 3126 /* set loop filter 2 */ 3127 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3128 3129 /* set tx_mx2_ic */ 3130 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3131 /* set tx_mx1_ic */ 3132 if (chan <= 14) 3133 rf = 0x48 | sc->txmixgain_2ghz; 3134 else 3135 rf = 0x78 | sc->txmixgain_5ghz; 3136 run_rt3070_rf_write(sc, 16, rf); 3137 3138 /* set tx_lo1 */ 3139 run_rt3070_rf_write(sc, 17, 0x23); 3140 /* set tx_lo2 */ 3141 if (chan <= 14) 3142 rf = 0x93; 3143 else if (chan <= 64) 3144 rf = 0xb7; 3145 else if (chan <= 128) 3146 rf = 0x74; 3147 else 3148 rf = 0x72; 3149 run_rt3070_rf_write(sc, 19, rf); 3150 3151 /* set rx_lo1 */ 3152 if (chan <= 14) 3153 rf = 0xb3; 3154 else if (chan <= 64) 3155 rf = 0xf6; 3156 else if (chan <= 128) 3157 rf = 0xf4; 3158 else 3159 rf = 0xf3; 3160 run_rt3070_rf_write(sc, 20, rf); 3161 3162 /* set pfd_delay */ 3163 if (chan <= 14) 3164 rf = 0x15; 3165 else if (chan <= 64) 3166 rf = 0x3d; 3167 else 3168 rf = 0x01; 3169 run_rt3070_rf_write(sc, 25, rf); 3170 3171 /* set rx_lo2 */ 3172 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3173 /* set ldo_rf_vc */ 3174 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3175 /* set drv_cc */ 3176 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3177 3178 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3179 tmp &= ~0x8080; 3180 if (chan <= 14) 3181 tmp |= 0x80; 3182 run_write(sc, RT2860_GPIO_CTRL, tmp); 3183 3184 /* enable RF tuning */ 3185 run_rt3070_rf_read(sc, 7, &rf); 3186 run_rt3070_rf_write(sc, 7, rf | 0x01); 3187 3188 usbd_delay_ms(sc->sc_udev, 2); 3189 } 3190 3191 static void 3192 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3193 { 3194 int8_t txpow1, txpow2, txpow3; 3195 uint8_t h20mhz, rf; 3196 int i; 3197 3198 /* find the settings for this channel (we know it exists) */ 3199 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3200 3201 /* use Tx power values from EEPROM */ 3202 txpow1 = sc->txpow1[i]; 3203 txpow2 = sc->txpow2[i]; 3204 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3205 3206 if (chan <= 14) { 3207 run_bbp_write(sc, 25, sc->bbp25); 3208 run_bbp_write(sc, 26, sc->bbp26); 3209 } else { 3210 /* Enable IQ phase correction. */ 3211 run_bbp_write(sc, 25, 0x09); 3212 run_bbp_write(sc, 26, 0xff); 3213 } 3214 3215 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3216 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3217 run_rt3070_rf_read(sc, 11, &rf); 3218 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3219 run_rt3070_rf_write(sc, 11, rf); 3220 3221 /* Set pll_idoh. */ 3222 run_rt3070_rf_read(sc, 11, &rf); 3223 rf &= ~0x4c; 3224 rf |= (chan <= 14) ? 0x44 : 0x48; 3225 run_rt3070_rf_write(sc, 11, rf); 3226 3227 if (chan <= 14) 3228 rf = txpow1 & 0x1f; 3229 else 3230 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3231 run_rt3070_rf_write(sc, 53, rf); 3232 3233 if (chan <= 14) 3234 rf = txpow2 & 0x1f; 3235 else 3236 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3237 run_rt3070_rf_write(sc, 55, rf); 3238 3239 if (chan <= 14) 3240 rf = txpow3 & 0x1f; 3241 else 3242 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3243 run_rt3070_rf_write(sc, 54, rf); 3244 3245 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3246 if (sc->ntxchains == 3) 3247 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3248 else 3249 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3250 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3251 run_rt3070_rf_write(sc, 1, rf); 3252 3253 run_adjust_freq_offset(sc); 3254 3255 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3256 3257 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3258 run_rt3070_rf_read(sc, 30, &rf); 3259 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3260 run_rt3070_rf_write(sc, 30, rf); 3261 3262 run_rt3070_rf_read(sc, 36, &rf); 3263 if (chan <= 14) 3264 rf |= 0x80; 3265 else 3266 rf &= ~0x80; 3267 run_rt3070_rf_write(sc, 36, rf); 3268 3269 /* Set vcolo_bs. */ 3270 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3271 /* Set pfd_delay. */ 3272 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3273 3274 /* Set vco bias current control. */ 3275 run_rt3070_rf_read(sc, 6, &rf); 3276 rf &= ~0xc0; 3277 if (chan <= 14) 3278 rf |= 0x40; 3279 else if (chan <= 128) 3280 rf |= 0x80; 3281 else 3282 rf |= 0x40; 3283 run_rt3070_rf_write(sc, 6, rf); 3284 3285 run_rt3070_rf_read(sc, 30, &rf); 3286 rf = (rf & ~0x18) | 0x10; 3287 run_rt3070_rf_write(sc, 30, rf); 3288 3289 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3290 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3291 3292 run_rt3070_rf_read(sc, 51, &rf); 3293 rf = (rf & ~0x03) | 0x01; 3294 run_rt3070_rf_write(sc, 51, rf); 3295 /* Set tx_mx1_cc. */ 3296 run_rt3070_rf_read(sc, 51, &rf); 3297 rf &= ~0x1c; 3298 rf |= (chan <= 14) ? 0x14 : 0x10; 3299 run_rt3070_rf_write(sc, 51, rf); 3300 /* Set tx_mx1_ic. */ 3301 run_rt3070_rf_read(sc, 51, &rf); 3302 rf &= ~0xe0; 3303 rf |= (chan <= 14) ? 0x60 : 0x40; 3304 run_rt3070_rf_write(sc, 51, rf); 3305 /* Set tx_lo1_ic. */ 3306 run_rt3070_rf_read(sc, 49, &rf); 3307 rf &= ~0x1c; 3308 rf |= (chan <= 14) ? 0x0c : 0x08; 3309 run_rt3070_rf_write(sc, 49, rf); 3310 /* Set tx_lo1_en. */ 3311 run_rt3070_rf_read(sc, 50, &rf); 3312 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3313 /* Set drv_cc. */ 3314 run_rt3070_rf_read(sc, 57, &rf); 3315 rf &= ~0xfc; 3316 rf |= (chan <= 14) ? 0x6c : 0x3c; 3317 run_rt3070_rf_write(sc, 57, rf); 3318 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3319 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3320 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3321 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3322 /* Enable VCO calibration. */ 3323 run_rt3070_rf_read(sc, 3, &rf); 3324 rf &= ~RT5390_VCOCAL; 3325 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3326 run_rt3070_rf_write(sc, 3, rf); 3327 3328 if (chan <= 14) 3329 rf = 0x23; 3330 else if (chan <= 64) 3331 rf = 0x36; 3332 else if (chan <= 128) 3333 rf = 0x32; 3334 else 3335 rf = 0x30; 3336 run_rt3070_rf_write(sc, 39, rf); 3337 if (chan <= 14) 3338 rf = 0xbb; 3339 else if (chan <= 64) 3340 rf = 0xeb; 3341 else if (chan <= 128) 3342 rf = 0xb3; 3343 else 3344 rf = 0x9b; 3345 run_rt3070_rf_write(sc, 45, rf); 3346 3347 /* Set FEQ/AEQ control. */ 3348 run_bbp_write(sc, 105, 0x34); 3349 } 3350 3351 static void 3352 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3353 { 3354 int8_t txpow1, txpow2; 3355 uint8_t rf; 3356 int i; 3357 3358 /* find the settings for this channel (we know it exists) */ 3359 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3360 3361 /* use Tx power values from EEPROM */ 3362 txpow1 = sc->txpow1[i]; 3363 txpow2 = sc->txpow2[i]; 3364 3365 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3366 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3367 run_rt3070_rf_read(sc, 11, &rf); 3368 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3369 run_rt3070_rf_write(sc, 11, rf); 3370 3371 run_rt3070_rf_read(sc, 49, &rf); 3372 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3373 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3374 if ((rf & 0x3f) > 0x27) 3375 rf = (rf & ~0x3f) | 0x27; 3376 run_rt3070_rf_write(sc, 49, rf); 3377 3378 if (sc->mac_ver == 0x5392) { 3379 run_rt3070_rf_read(sc, 50, &rf); 3380 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3381 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3382 if ((rf & 0x3f) > 0x27) 3383 rf = (rf & ~0x3f) | 0x27; 3384 run_rt3070_rf_write(sc, 50, rf); 3385 } 3386 3387 run_rt3070_rf_read(sc, 1, &rf); 3388 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3389 if (sc->mac_ver == 0x5392) 3390 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3391 run_rt3070_rf_write(sc, 1, rf); 3392 3393 if (sc->mac_ver != 0x5392) { 3394 run_rt3070_rf_read(sc, 2, &rf); 3395 rf |= 0x80; 3396 run_rt3070_rf_write(sc, 2, rf); 3397 usbd_delay_ms(sc->sc_udev, 10); 3398 rf &= 0x7f; 3399 run_rt3070_rf_write(sc, 2, rf); 3400 } 3401 3402 run_adjust_freq_offset(sc); 3403 3404 if (sc->mac_ver == 0x5392) { 3405 /* Fix for RT5392C. */ 3406 if (sc->mac_rev >= 0x0223) { 3407 if (chan <= 4) 3408 rf = 0x0f; 3409 else if (chan >= 5 && chan <= 7) 3410 rf = 0x0e; 3411 else 3412 rf = 0x0d; 3413 run_rt3070_rf_write(sc, 23, rf); 3414 3415 if (chan <= 4) 3416 rf = 0x0c; 3417 else if (chan == 5) 3418 rf = 0x0b; 3419 else if (chan >= 6 && chan <= 7) 3420 rf = 0x0a; 3421 else if (chan >= 8 && chan <= 10) 3422 rf = 0x09; 3423 else 3424 rf = 0x08; 3425 run_rt3070_rf_write(sc, 59, rf); 3426 } else { 3427 if (chan <= 11) 3428 rf = 0x0f; 3429 else 3430 rf = 0x0b; 3431 run_rt3070_rf_write(sc, 59, rf); 3432 } 3433 } else { 3434 /* Fix for RT5390F. */ 3435 if (sc->mac_rev >= 0x0502) { 3436 if (chan <= 11) 3437 rf = 0x43; 3438 else 3439 rf = 0x23; 3440 run_rt3070_rf_write(sc, 55, rf); 3441 3442 if (chan <= 11) 3443 rf = 0x0f; 3444 else if (chan == 12) 3445 rf = 0x0d; 3446 else 3447 rf = 0x0b; 3448 run_rt3070_rf_write(sc, 59, rf); 3449 } else { 3450 run_rt3070_rf_write(sc, 55, 0x44); 3451 run_rt3070_rf_write(sc, 59, 0x8f); 3452 } 3453 } 3454 3455 /* Enable VCO calibration. */ 3456 run_rt3070_rf_read(sc, 3, &rf); 3457 rf |= RT5390_VCOCAL; 3458 run_rt3070_rf_write(sc, 3, rf); 3459 } 3460 3461 static void 3462 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3463 { 3464 const struct rt5592_freqs *freqs; 3465 uint32_t tmp; 3466 uint8_t reg, rf, txpow_bound; 3467 int8_t txpow1, txpow2; 3468 int i; 3469 3470 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3471 freqs = (tmp & RT5592_SEL_XTAL) ? 3472 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3473 3474 /* find the settings for this channel (we know it exists) */ 3475 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3476 3477 /* use Tx power values from EEPROM */ 3478 txpow1 = sc->txpow1[i]; 3479 txpow2 = sc->txpow2[i]; 3480 3481 run_read(sc, RT3070_LDO_CFG0, &tmp); 3482 tmp &= ~0x1c000000; 3483 if (chan > 14) 3484 tmp |= 0x14000000; 3485 run_write(sc, RT3070_LDO_CFG0, tmp); 3486 3487 /* N setting. */ 3488 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3489 run_rt3070_rf_read(sc, 9, &rf); 3490 rf &= ~(1 << 4); 3491 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3492 run_rt3070_rf_write(sc, 9, rf); 3493 3494 /* K setting. */ 3495 run_rt3070_rf_read(sc, 9, &rf); 3496 rf &= ~0x0f; 3497 rf |= (freqs->k & 0x0f); 3498 run_rt3070_rf_write(sc, 9, rf); 3499 3500 /* Mode setting. */ 3501 run_rt3070_rf_read(sc, 11, &rf); 3502 rf &= ~0x0c; 3503 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3504 run_rt3070_rf_write(sc, 11, rf); 3505 run_rt3070_rf_read(sc, 9, &rf); 3506 rf &= ~(1 << 7); 3507 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3508 run_rt3070_rf_write(sc, 9, rf); 3509 3510 /* R setting. */ 3511 run_rt3070_rf_read(sc, 11, &rf); 3512 rf &= ~0x03; 3513 rf |= (freqs->r - 0x1); 3514 run_rt3070_rf_write(sc, 11, rf); 3515 3516 if (chan <= 14) { 3517 /* Initialize RF registers for 2GHZ. */ 3518 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3519 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3520 rt5592_2ghz_def_rf[i].val); 3521 } 3522 3523 rf = (chan <= 10) ? 0x07 : 0x06; 3524 run_rt3070_rf_write(sc, 23, rf); 3525 run_rt3070_rf_write(sc, 59, rf); 3526 3527 run_rt3070_rf_write(sc, 55, 0x43); 3528 3529 /* 3530 * RF R49/R50 Tx power ALC code. 3531 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3532 */ 3533 reg = 2; 3534 txpow_bound = 0x27; 3535 } else { 3536 /* Initialize RF registers for 5GHZ. */ 3537 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3538 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3539 rt5592_5ghz_def_rf[i].val); 3540 } 3541 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3542 if (chan >= rt5592_chan_5ghz[i].firstchan && 3543 chan <= rt5592_chan_5ghz[i].lastchan) { 3544 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3545 rt5592_chan_5ghz[i].val); 3546 } 3547 } 3548 3549 /* 3550 * RF R49/R50 Tx power ALC code. 3551 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3552 */ 3553 reg = 3; 3554 txpow_bound = 0x2b; 3555 } 3556 3557 /* RF R49 ch0 Tx power ALC code. */ 3558 run_rt3070_rf_read(sc, 49, &rf); 3559 rf &= ~0xc0; 3560 rf |= (reg << 6); 3561 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3562 if ((rf & 0x3f) > txpow_bound) 3563 rf = (rf & ~0x3f) | txpow_bound; 3564 run_rt3070_rf_write(sc, 49, rf); 3565 3566 /* RF R50 ch1 Tx power ALC code. */ 3567 run_rt3070_rf_read(sc, 50, &rf); 3568 rf &= ~(1 << 7 | 1 << 6); 3569 rf |= (reg << 6); 3570 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3571 if ((rf & 0x3f) > txpow_bound) 3572 rf = (rf & ~0x3f) | txpow_bound; 3573 run_rt3070_rf_write(sc, 50, rf); 3574 3575 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3576 run_rt3070_rf_read(sc, 1, &rf); 3577 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3578 if (sc->ntxchains > 1) 3579 rf |= RT3070_TX1_PD; 3580 if (sc->nrxchains > 1) 3581 rf |= RT3070_RX1_PD; 3582 run_rt3070_rf_write(sc, 1, rf); 3583 3584 run_rt3070_rf_write(sc, 6, 0xe4); 3585 3586 run_rt3070_rf_write(sc, 30, 0x10); 3587 run_rt3070_rf_write(sc, 31, 0x80); 3588 run_rt3070_rf_write(sc, 32, 0x80); 3589 3590 run_adjust_freq_offset(sc); 3591 3592 /* Enable VCO calibration. */ 3593 run_rt3070_rf_read(sc, 3, &rf); 3594 rf |= RT5390_VCOCAL; 3595 run_rt3070_rf_write(sc, 3, rf); 3596 } 3597 3598 static void 3599 run_iq_calib(struct run_softc *sc, u_int chan) 3600 { 3601 uint16_t val; 3602 3603 /* Tx0 IQ gain. */ 3604 run_bbp_write(sc, 158, 0x2c); 3605 if (chan <= 14) 3606 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3607 else if (chan <= 64) { 3608 run_efuse_read(sc, 3609 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3610 &val, 1); 3611 } else if (chan <= 138) { 3612 run_efuse_read(sc, 3613 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3614 &val, 1); 3615 } else if (chan <= 165) { 3616 run_efuse_read(sc, 3617 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3618 &val, 1); 3619 } else 3620 val = 0; 3621 run_bbp_write(sc, 159, val); 3622 3623 /* Tx0 IQ phase. */ 3624 run_bbp_write(sc, 158, 0x2d); 3625 if (chan <= 14) { 3626 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3627 &val, 1); 3628 } else if (chan <= 64) { 3629 run_efuse_read(sc, 3630 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3631 &val, 1); 3632 } else if (chan <= 138) { 3633 run_efuse_read(sc, 3634 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3635 &val, 1); 3636 } else if (chan <= 165) { 3637 run_efuse_read(sc, 3638 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3639 &val, 1); 3640 } else 3641 val = 0; 3642 run_bbp_write(sc, 159, val); 3643 3644 /* Tx1 IQ gain. */ 3645 run_bbp_write(sc, 158, 0x4a); 3646 if (chan <= 14) { 3647 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3648 &val, 1); 3649 } else if (chan <= 64) { 3650 run_efuse_read(sc, 3651 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3652 &val, 1); 3653 } else if (chan <= 138) { 3654 run_efuse_read(sc, 3655 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3656 &val, 1); 3657 } else if (chan <= 165) { 3658 run_efuse_read(sc, 3659 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3660 &val, 1); 3661 } else 3662 val = 0; 3663 run_bbp_write(sc, 159, val); 3664 3665 /* Tx1 IQ phase. */ 3666 run_bbp_write(sc, 158, 0x4b); 3667 if (chan <= 14) { 3668 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3669 &val, 1); 3670 } else if (chan <= 64) { 3671 run_efuse_read(sc, 3672 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3673 &val, 1); 3674 } else if (chan <= 138) { 3675 run_efuse_read(sc, 3676 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3677 &val, 1); 3678 } else if (chan <= 165) { 3679 run_efuse_read(sc, 3680 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3681 &val, 1); 3682 } else 3683 val = 0; 3684 run_bbp_write(sc, 159, val); 3685 3686 /* RF IQ compensation control. */ 3687 run_bbp_write(sc, 158, 0x04); 3688 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3689 &val, 1); 3690 run_bbp_write(sc, 159, val); 3691 3692 /* RF IQ imbalance compensation control. */ 3693 run_bbp_write(sc, 158, 0x03); 3694 run_efuse_read(sc, 3695 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3696 run_bbp_write(sc, 159, val); 3697 } 3698 3699 static void 3700 run_set_agc(struct run_softc *sc, uint8_t agc) 3701 { 3702 uint8_t bbp; 3703 3704 if (sc->mac_ver == 0x3572) { 3705 run_bbp_read(sc, 27, &bbp); 3706 bbp &= ~(0x3 << 5); 3707 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3708 run_bbp_write(sc, 66, agc); 3709 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3710 run_bbp_write(sc, 66, agc); 3711 } else 3712 run_bbp_write(sc, 66, agc); 3713 } 3714 3715 static void 3716 run_set_rx_antenna(struct run_softc *sc, int aux) 3717 { 3718 uint32_t tmp; 3719 uint8_t bbp152; 3720 3721 if (aux) { 3722 if (sc->rf_rev == RT5390_RF_5370) { 3723 run_bbp_read(sc, 152, &bbp152); 3724 bbp152 &= ~0x80; 3725 run_bbp_write(sc, 152, bbp152); 3726 } else { 3727 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3728 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3729 tmp &= ~0x0808; 3730 tmp |= 0x08; 3731 run_write(sc, RT2860_GPIO_CTRL, tmp); 3732 } 3733 } else { 3734 if (sc->rf_rev == RT5390_RF_5370) { 3735 run_bbp_read(sc, 152, &bbp152); 3736 bbp152 |= 0x80; 3737 run_bbp_write(sc, 152, bbp152); 3738 } else { 3739 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3740 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3741 tmp &= ~0x0808; 3742 run_write(sc, RT2860_GPIO_CTRL, tmp); 3743 } 3744 } 3745 } 3746 3747 static int 3748 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3749 { 3750 struct ieee80211com *ic = &sc->sc_ic; 3751 u_int chan, group; 3752 3753 chan = ieee80211_chan2ieee(ic, c); 3754 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3755 return EINVAL; 3756 3757 if (sc->mac_ver == 0x5592) 3758 run_rt5592_set_chan(sc, chan); 3759 else if (sc->mac_ver >= 0x5390) 3760 run_rt5390_set_chan(sc, chan); 3761 else if (sc->mac_ver == 0x3593) 3762 run_rt3593_set_chan(sc, chan); 3763 else if (sc->mac_ver == 0x3572) 3764 run_rt3572_set_chan(sc, chan); 3765 else if (sc->mac_ver >= 0x3070) 3766 run_rt3070_set_chan(sc, chan); 3767 else 3768 run_rt2870_set_chan(sc, chan); 3769 3770 /* determine channel group */ 3771 if (chan <= 14) 3772 group = 0; 3773 else if (chan <= 64) 3774 group = 1; 3775 else if (chan <= 128) 3776 group = 2; 3777 else 3778 group = 3; 3779 3780 /* XXX necessary only when group has changed! */ 3781 run_select_chan_group(sc, group); 3782 3783 usbd_delay_ms(sc->sc_udev, 10); 3784 3785 /* Perform IQ calibration. */ 3786 if (sc->mac_ver >= 0x5392) 3787 run_iq_calib(sc, chan); 3788 3789 return 0; 3790 } 3791 3792 static void 3793 run_updateprot(struct run_softc *sc) 3794 { 3795 struct ieee80211com *ic = &sc->sc_ic; 3796 uint32_t tmp; 3797 3798 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3799 /* setup protection frame rate (MCS code) */ 3800 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3801 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3802 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3803 3804 /* CCK frames don't require protection */ 3805 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3806 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3807 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3808 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3809 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3810 tmp |= RT2860_PROT_CTRL_CTS; 3811 } 3812 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3813 } 3814 3815 static void 3816 run_enable_tsf_sync(struct run_softc *sc) 3817 { 3818 struct ieee80211com *ic = &sc->sc_ic; 3819 uint32_t tmp; 3820 3821 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3822 tmp &= ~0x1fffff; 3823 tmp |= ic->ic_bss->ni_intval * 16; 3824 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3825 if (ic->ic_opmode == IEEE80211_M_STA) { 3826 /* 3827 * Local TSF is always updated with remote TSF on beacon 3828 * reception. 3829 */ 3830 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3831 } 3832 #ifndef IEEE80211_STA_ONLY 3833 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3834 tmp |= RT2860_BCN_TX_EN; 3835 /* 3836 * Local TSF is updated with remote TSF on beacon reception 3837 * only if the remote TSF is greater than local TSF. 3838 */ 3839 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3840 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3841 tmp |= RT2860_BCN_TX_EN; 3842 /* SYNC with nobody */ 3843 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3844 } 3845 #endif 3846 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3847 } 3848 3849 static void 3850 run_enable_mrr(struct run_softc *sc) 3851 { 3852 #define CCK(mcs) (mcs) 3853 #define OFDM(mcs) (1 << 3 | (mcs)) 3854 run_write(sc, RT2860_LG_FBK_CFG0, 3855 OFDM(6) << 28 | /* 54->48 */ 3856 OFDM(5) << 24 | /* 48->36 */ 3857 OFDM(4) << 20 | /* 36->24 */ 3858 OFDM(3) << 16 | /* 24->18 */ 3859 OFDM(2) << 12 | /* 18->12 */ 3860 OFDM(1) << 8 | /* 12-> 9 */ 3861 OFDM(0) << 4 | /* 9-> 6 */ 3862 OFDM(0)); /* 6-> 6 */ 3863 3864 run_write(sc, RT2860_LG_FBK_CFG1, 3865 CCK(2) << 12 | /* 11->5.5 */ 3866 CCK(1) << 8 | /* 5.5-> 2 */ 3867 CCK(0) << 4 | /* 2-> 1 */ 3868 CCK(0)); /* 1-> 1 */ 3869 #undef OFDM 3870 #undef CCK 3871 } 3872 3873 static void 3874 run_set_txpreamble(struct run_softc *sc) 3875 { 3876 uint32_t tmp; 3877 3878 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3879 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3880 tmp |= RT2860_CCK_SHORT_EN; 3881 else 3882 tmp &= ~RT2860_CCK_SHORT_EN; 3883 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3884 } 3885 3886 static void 3887 run_set_basicrates(struct run_softc *sc) 3888 { 3889 struct ieee80211com *ic = &sc->sc_ic; 3890 3891 /* set basic rates mask */ 3892 if (ic->ic_curmode == IEEE80211_MODE_11B) 3893 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3894 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3895 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3896 else /* 11g */ 3897 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3898 } 3899 3900 static void 3901 run_set_leds(struct run_softc *sc, uint16_t which) 3902 { 3903 3904 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3905 which | (sc->leds & 0x7f)); 3906 } 3907 3908 static void 3909 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3910 { 3911 3912 run_write(sc, RT2860_MAC_BSSID_DW0, 3913 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3914 run_write(sc, RT2860_MAC_BSSID_DW1, 3915 bssid[4] | bssid[5] << 8); 3916 } 3917 3918 static void 3919 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3920 { 3921 3922 run_write(sc, RT2860_MAC_ADDR_DW0, 3923 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3924 run_write(sc, RT2860_MAC_ADDR_DW1, 3925 addr[4] | addr[5] << 8 | 0xff << 16); 3926 } 3927 3928 static void 3929 run_updateslot(struct ifnet *ifp) 3930 { 3931 3932 /* do it in a process context */ 3933 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3934 } 3935 3936 /* ARGSUSED */ 3937 static void 3938 run_updateslot_cb(struct run_softc *sc, void *arg) 3939 { 3940 uint32_t tmp; 3941 3942 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3943 tmp &= ~0xff; 3944 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3945 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3946 } 3947 3948 static int8_t 3949 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3950 { 3951 struct ieee80211com *ic = &sc->sc_ic; 3952 struct ieee80211_channel *c = ic->ic_curchan; 3953 int delta; 3954 3955 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3956 u_int chan = ieee80211_chan2ieee(ic, c); 3957 delta = sc->rssi_5ghz[rxchain]; 3958 3959 /* determine channel group */ 3960 if (chan <= 64) 3961 delta -= sc->lna[1]; 3962 else if (chan <= 128) 3963 delta -= sc->lna[2]; 3964 else 3965 delta -= sc->lna[3]; 3966 } else 3967 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3968 3969 return -12 - delta - rssi; 3970 } 3971 3972 static void 3973 run_rt5390_bbp_init(struct run_softc *sc) 3974 { 3975 u_int i; 3976 uint8_t bbp; 3977 3978 /* Apply maximum likelihood detection for 2 stream case. */ 3979 run_bbp_read(sc, 105, &bbp); 3980 if (sc->nrxchains > 1) 3981 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3982 3983 /* Avoid data lost and CRC error. */ 3984 run_bbp_read(sc, 4, &bbp); 3985 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3986 3987 if (sc->mac_ver == 0x5592) { 3988 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3989 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3990 rt5592_def_bbp[i].val); 3991 } 3992 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3993 run_bbp_write(sc, 195, i + 0x80); 3994 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3995 } 3996 } else { 3997 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3998 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3999 rt5390_def_bbp[i].val); 4000 } 4001 } 4002 if (sc->mac_ver == 0x5392) { 4003 run_bbp_write(sc, 88, 0x90); 4004 run_bbp_write(sc, 95, 0x9a); 4005 run_bbp_write(sc, 98, 0x12); 4006 run_bbp_write(sc, 106, 0x12); 4007 run_bbp_write(sc, 134, 0xd0); 4008 run_bbp_write(sc, 135, 0xf6); 4009 run_bbp_write(sc, 148, 0x84); 4010 } 4011 4012 run_bbp_read(sc, 152, &bbp); 4013 run_bbp_write(sc, 152, bbp | 0x80); 4014 4015 /* Fix BBP254 for RT5592C. */ 4016 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 4017 run_bbp_read(sc, 254, &bbp); 4018 run_bbp_write(sc, 254, bbp | 0x80); 4019 } 4020 4021 /* Disable hardware antenna diversity. */ 4022 if (sc->mac_ver == 0x5390) 4023 run_bbp_write(sc, 154, 0); 4024 4025 /* Initialize Rx CCK/OFDM frequency offset report. */ 4026 run_bbp_write(sc, 142, 1); 4027 run_bbp_write(sc, 143, 57); 4028 } 4029 4030 static int 4031 run_bbp_init(struct run_softc *sc) 4032 { 4033 int i, error, ntries; 4034 uint8_t bbp0; 4035 4036 /* wait for BBP to wake up */ 4037 for (ntries = 0; ntries < 20; ntries++) { 4038 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 4039 return error; 4040 if (bbp0 != 0 && bbp0 != 0xff) 4041 break; 4042 } 4043 if (ntries == 20) 4044 return ETIMEDOUT; 4045 4046 /* initialize BBP registers to default values */ 4047 if (sc->mac_ver >= 0x5390) 4048 run_rt5390_bbp_init(sc); 4049 else { 4050 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 4051 run_bbp_write(sc, rt2860_def_bbp[i].reg, 4052 rt2860_def_bbp[i].val); 4053 } 4054 } 4055 4056 if (sc->mac_ver == 0x3593) { 4057 run_bbp_write(sc, 79, 0x13); 4058 run_bbp_write(sc, 80, 0x05); 4059 run_bbp_write(sc, 81, 0x33); 4060 run_bbp_write(sc, 86, 0x46); 4061 run_bbp_write(sc, 137, 0x0f); 4062 } 4063 4064 /* fix BBP84 for RT2860E */ 4065 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 4066 run_bbp_write(sc, 84, 0x19); 4067 4068 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 4069 sc->mac_ver != 0x5592)) { 4070 run_bbp_write(sc, 79, 0x13); 4071 run_bbp_write(sc, 80, 0x05); 4072 run_bbp_write(sc, 81, 0x33); 4073 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 4074 run_bbp_write(sc, 69, 0x16); 4075 run_bbp_write(sc, 73, 0x12); 4076 } 4077 return 0; 4078 } 4079 4080 static int 4081 run_rt3070_rf_init(struct run_softc *sc) 4082 { 4083 uint32_t tmp; 4084 uint8_t rf, target, bbp4; 4085 int i; 4086 4087 run_rt3070_rf_read(sc, 30, &rf); 4088 /* toggle RF R30 bit 7 */ 4089 run_rt3070_rf_write(sc, 30, rf | 0x80); 4090 usbd_delay_ms(sc->sc_udev, 10); 4091 run_rt3070_rf_write(sc, 30, rf & ~0x80); 4092 4093 /* initialize RF registers to default value */ 4094 if (sc->mac_ver == 0x3572) { 4095 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 4096 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 4097 rt3572_def_rf[i].val); 4098 } 4099 } else { 4100 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 4101 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 4102 rt3070_def_rf[i].val); 4103 } 4104 } 4105 if (sc->mac_ver == 0x3572) { 4106 run_rt3070_rf_read(sc, 6, &rf); 4107 run_rt3070_rf_write(sc, 6, rf | 0x40); 4108 run_rt3070_rf_write(sc, 31, 0x14); 4109 4110 run_read(sc, RT3070_LDO_CFG0, &tmp); 4111 tmp &= ~0x1f000000; 4112 if (sc->mac_rev < 0x0211 && sc->patch_dac) 4113 tmp |= 0x0d000000; /* 1.3V */ 4114 else 4115 tmp |= 0x01000000; /* 1.2V */ 4116 run_write(sc, RT3070_LDO_CFG0, tmp); 4117 } else if (sc->mac_ver == 0x3071) { 4118 run_rt3070_rf_read(sc, 6, &rf); 4119 run_rt3070_rf_write(sc, 6, rf | 0x40); 4120 run_rt3070_rf_write(sc, 31, 0x14); 4121 4122 run_read(sc, RT3070_LDO_CFG0, &tmp); 4123 tmp &= ~0x1f000000; 4124 if (sc->mac_rev < 0x0211) 4125 tmp |= 0x0d000000; /* 1.35V */ 4126 else 4127 tmp |= 0x01000000; /* 1.2V */ 4128 run_write(sc, RT3070_LDO_CFG0, tmp); 4129 4130 /* patch LNA_PE_G1 */ 4131 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4132 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 4133 } else if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 4134 /* 4135 * Change voltage from 1.2V to 1.35V for RT3070. 4136 * The DAC issue (RT3070_LD0_CFG0) has been fixed 4137 * in RT3070(F). 4138 */ 4139 run_read(sc, RT3070_LDO_CFG0, &tmp); 4140 tmp = (tmp & ~0x0f000000) | 0x0d000000; 4141 run_write(sc, RT3070_LDO_CFG0, tmp); 4142 } 4143 4144 /* select 20MHz bandwidth */ 4145 run_rt3070_rf_read(sc, 31, &rf); 4146 run_rt3070_rf_write(sc, 31, rf & ~0x20); 4147 4148 /* calibrate filter for 20MHz bandwidth */ 4149 sc->rf24_20mhz = 0x1f; /* default value */ 4150 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 4151 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 4152 4153 /* select 40MHz bandwidth */ 4154 run_bbp_read(sc, 4, &bbp4); 4155 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 4156 run_rt3070_rf_read(sc, 31, &rf); 4157 run_rt3070_rf_write(sc, 31, rf | 0x20); 4158 4159 /* calibrate filter for 40MHz bandwidth */ 4160 sc->rf24_40mhz = 0x2f; /* default value */ 4161 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4162 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4163 4164 /* go back to 20MHz bandwidth */ 4165 run_bbp_read(sc, 4, &bbp4); 4166 run_bbp_write(sc, 4, bbp4 & ~0x18); 4167 4168 if (sc->mac_ver == 0x3572) { 4169 /* save default BBP registers 25 and 26 values */ 4170 run_bbp_read(sc, 25, &sc->bbp25); 4171 run_bbp_read(sc, 26, &sc->bbp26); 4172 } else if (sc->mac_rev < 0x0211) 4173 run_rt3070_rf_write(sc, 27, 0x03); 4174 4175 run_read(sc, RT3070_OPT_14, &tmp); 4176 run_write(sc, RT3070_OPT_14, tmp | 1); 4177 4178 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4179 run_rt3070_rf_read(sc, 17, &rf); 4180 rf &= ~RT3070_TX_LO1; 4181 if ((sc->mac_ver == 0x3070 || 4182 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4183 !sc->ext_2ghz_lna) 4184 rf |= 0x20; /* fix for long range Rx issue */ 4185 if (sc->txmixgain_2ghz >= 1) 4186 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4187 run_rt3070_rf_write(sc, 17, rf); 4188 } 4189 if (sc->mac_ver == 0x3071) { 4190 run_rt3070_rf_read(sc, 1, &rf); 4191 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4192 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4193 run_rt3070_rf_write(sc, 1, rf); 4194 4195 run_rt3070_rf_read(sc, 15, &rf); 4196 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4197 4198 run_rt3070_rf_read(sc, 20, &rf); 4199 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4200 4201 run_rt3070_rf_read(sc, 21, &rf); 4202 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4203 } 4204 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4205 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4206 run_rt3070_rf_read(sc, 27, &rf); 4207 rf &= ~0x77; 4208 if (sc->mac_rev < 0x0211) 4209 rf |= 0x03; 4210 run_rt3070_rf_write(sc, 27, rf); 4211 } 4212 return 0; 4213 } 4214 4215 static int 4216 run_rt3593_rf_init(struct run_softc *sc) 4217 { 4218 uint32_t tmp; 4219 uint8_t rf; 4220 int i; 4221 4222 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4223 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4224 tmp &= ~(1 << 4 | 1 << 7); 4225 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4226 4227 /* Initialize RF registers to default value. */ 4228 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4229 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4230 rt3593_def_rf[i].val); 4231 } 4232 4233 /* Toggle RF R2 to initiate calibration. */ 4234 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4235 4236 /* Initialize RF frequency offset. */ 4237 run_adjust_freq_offset(sc); 4238 4239 run_rt3070_rf_read(sc, 18, &rf); 4240 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4241 4242 /* 4243 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4244 * decrease voltage back to 1.2V. 4245 */ 4246 run_read(sc, RT3070_LDO_CFG0, &tmp); 4247 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4248 run_write(sc, RT3070_LDO_CFG0, tmp); 4249 usbd_delay_ms(sc->sc_udev, 1); 4250 tmp = (tmp & ~0x1f000000) | 0x01000000; 4251 run_write(sc, RT3070_LDO_CFG0, tmp); 4252 4253 sc->rf24_20mhz = 0x1f; 4254 sc->rf24_40mhz = 0x2f; 4255 4256 /* Save default BBP registers 25 and 26 values. */ 4257 run_bbp_read(sc, 25, &sc->bbp25); 4258 run_bbp_read(sc, 26, &sc->bbp26); 4259 4260 run_read(sc, RT3070_OPT_14, &tmp); 4261 run_write(sc, RT3070_OPT_14, tmp | 1); 4262 return 0; 4263 } 4264 4265 static int 4266 run_rt5390_rf_init(struct run_softc *sc) 4267 { 4268 uint32_t tmp; 4269 uint8_t rf; 4270 int i; 4271 4272 /* Toggle RF R2 to initiate calibration. */ 4273 if (sc->mac_ver == 0x5390) { 4274 run_rt3070_rf_read(sc, 2, &rf); 4275 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4276 usbd_delay_ms(sc->sc_udev, 10); 4277 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4278 } else { 4279 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4280 usbd_delay_ms(sc->sc_udev, 10); 4281 } 4282 4283 /* Initialize RF registers to default value. */ 4284 if (sc->mac_ver == 0x5592) { 4285 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4286 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4287 rt5592_def_rf[i].val); 4288 } 4289 /* Initialize RF frequency offset. */ 4290 run_adjust_freq_offset(sc); 4291 } else if (sc->mac_ver == 0x5392) { 4292 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4293 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4294 rt5392_def_rf[i].val); 4295 } 4296 if (sc->mac_rev >= 0x0223) { 4297 run_rt3070_rf_write(sc, 23, 0x0f); 4298 run_rt3070_rf_write(sc, 24, 0x3e); 4299 run_rt3070_rf_write(sc, 51, 0x32); 4300 run_rt3070_rf_write(sc, 53, 0x22); 4301 run_rt3070_rf_write(sc, 56, 0xc1); 4302 run_rt3070_rf_write(sc, 59, 0x0f); 4303 } 4304 } else { 4305 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4306 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4307 rt5390_def_rf[i].val); 4308 } 4309 if (sc->mac_rev >= 0x0502) { 4310 run_rt3070_rf_write(sc, 6, 0xe0); 4311 run_rt3070_rf_write(sc, 25, 0x80); 4312 run_rt3070_rf_write(sc, 46, 0x73); 4313 run_rt3070_rf_write(sc, 53, 0x00); 4314 run_rt3070_rf_write(sc, 56, 0x42); 4315 run_rt3070_rf_write(sc, 61, 0xd1); 4316 } 4317 } 4318 4319 sc->rf24_20mhz = 0x1f; /* default value */ 4320 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4321 4322 if (sc->mac_rev < 0x0211) 4323 run_rt3070_rf_write(sc, 27, 0x3); 4324 4325 run_read(sc, RT3070_OPT_14, &tmp); 4326 run_write(sc, RT3070_OPT_14, tmp | 1); 4327 return 0; 4328 } 4329 4330 static int 4331 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4332 uint8_t *val) 4333 { 4334 uint8_t rf22, rf24; 4335 uint8_t bbp55_pb, bbp55_sb, delta; 4336 int ntries; 4337 4338 /* program filter */ 4339 run_rt3070_rf_read(sc, 24, &rf24); 4340 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4341 run_rt3070_rf_write(sc, 24, rf24); 4342 4343 /* enable baseband loopback mode */ 4344 run_rt3070_rf_read(sc, 22, &rf22); 4345 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4346 4347 /* set power and frequency of passband test tone */ 4348 run_bbp_write(sc, 24, 0x00); 4349 for (ntries = 0; ntries < 100; ntries++) { 4350 /* transmit test tone */ 4351 run_bbp_write(sc, 25, 0x90); 4352 usbd_delay_ms(sc->sc_udev, 10); 4353 /* read received power */ 4354 run_bbp_read(sc, 55, &bbp55_pb); 4355 if (bbp55_pb != 0) 4356 break; 4357 } 4358 if (ntries == 100) 4359 return ETIMEDOUT; 4360 4361 /* set power and frequency of stopband test tone */ 4362 run_bbp_write(sc, 24, 0x06); 4363 for (ntries = 0; ntries < 100; ntries++) { 4364 /* transmit test tone */ 4365 run_bbp_write(sc, 25, 0x90); 4366 usbd_delay_ms(sc->sc_udev, 10); 4367 /* read received power */ 4368 run_bbp_read(sc, 55, &bbp55_sb); 4369 4370 delta = bbp55_pb - bbp55_sb; 4371 if (delta > target) 4372 break; 4373 4374 /* reprogram filter */ 4375 rf24++; 4376 run_rt3070_rf_write(sc, 24, rf24); 4377 } 4378 if (ntries < 100) { 4379 if (rf24 != init) 4380 rf24--; /* backtrack */ 4381 *val = rf24; 4382 run_rt3070_rf_write(sc, 24, rf24); 4383 } 4384 4385 /* restore initial state */ 4386 run_bbp_write(sc, 24, 0x00); 4387 4388 /* disable baseband loopback mode */ 4389 run_rt3070_rf_read(sc, 22, &rf22); 4390 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4391 4392 return 0; 4393 } 4394 4395 static void 4396 run_rt3070_rf_setup(struct run_softc *sc) 4397 { 4398 uint8_t bbp, rf; 4399 int i; 4400 4401 if (sc->mac_ver == 0x3572) { 4402 /* enable DC filter */ 4403 if (sc->mac_rev >= 0x0201) 4404 run_bbp_write(sc, 103, 0xc0); 4405 4406 run_bbp_read(sc, 138, &bbp); 4407 if (sc->ntxchains == 1) 4408 bbp |= 0x20; /* turn off DAC1 */ 4409 if (sc->nrxchains == 1) 4410 bbp &= ~0x02; /* turn off ADC1 */ 4411 run_bbp_write(sc, 138, bbp); 4412 4413 if (sc->mac_rev >= 0x0211) { 4414 /* improve power consumption */ 4415 run_bbp_read(sc, 31, &bbp); 4416 run_bbp_write(sc, 31, bbp & ~0x03); 4417 } 4418 4419 run_rt3070_rf_read(sc, 16, &rf); 4420 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4421 run_rt3070_rf_write(sc, 16, rf); 4422 } else if (sc->mac_ver == 0x3071) { 4423 /* enable DC filter */ 4424 if (sc->mac_rev >= 0x0201) 4425 run_bbp_write(sc, 103, 0xc0); 4426 4427 run_bbp_read(sc, 138, &bbp); 4428 if (sc->ntxchains == 1) 4429 bbp |= 0x20; /* turn off DAC1 */ 4430 if (sc->nrxchains == 1) 4431 bbp &= ~0x02; /* turn off ADC1 */ 4432 run_bbp_write(sc, 138, bbp); 4433 4434 if (sc->mac_rev >= 0x0211) { 4435 /* improve power consumption */ 4436 run_bbp_read(sc, 31, &bbp); 4437 run_bbp_write(sc, 31, bbp & ~0x03); 4438 } 4439 4440 run_write(sc, RT2860_TX_SW_CFG1, 0); 4441 if (sc->mac_rev < 0x0211) { 4442 run_write(sc, RT2860_TX_SW_CFG2, 4443 sc->patch_dac ? 0x2c : 0x0f); 4444 } else 4445 run_write(sc, RT2860_TX_SW_CFG2, 0); 4446 } else if (sc->mac_ver == 0x3070) { 4447 if (sc->mac_rev >= 0x0201) { 4448 /* enable DC filter */ 4449 run_bbp_write(sc, 103, 0xc0); 4450 4451 /* improve power consumption */ 4452 run_bbp_read(sc, 31, &bbp); 4453 run_bbp_write(sc, 31, bbp & ~0x03); 4454 } 4455 4456 if (sc->mac_rev < 0x0211) { 4457 run_write(sc, RT2860_TX_SW_CFG1, 0); 4458 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4459 } else 4460 run_write(sc, RT2860_TX_SW_CFG2, 0); 4461 } 4462 4463 /* initialize RF registers from ROM for >=RT3071*/ 4464 if (sc->mac_ver >= 0x3071) { 4465 for (i = 0; i < 10; i++) { 4466 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4467 continue; 4468 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4469 } 4470 } 4471 } 4472 4473 static void 4474 run_rt3593_rf_setup(struct run_softc *sc) 4475 { 4476 uint8_t bbp, rf; 4477 4478 if (sc->mac_rev >= 0x0211) { 4479 /* Enable DC filter. */ 4480 run_bbp_write(sc, 103, 0xc0); 4481 } 4482 run_write(sc, RT2860_TX_SW_CFG1, 0); 4483 if (sc->mac_rev < 0x0211) { 4484 run_write(sc, RT2860_TX_SW_CFG2, 4485 sc->patch_dac ? 0x2c : 0x0f); 4486 } else 4487 run_write(sc, RT2860_TX_SW_CFG2, 0); 4488 4489 run_rt3070_rf_read(sc, 50, &rf); 4490 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4491 4492 run_rt3070_rf_read(sc, 51, &rf); 4493 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4494 ((sc->txmixgain_2ghz & 0x07) << 2); 4495 run_rt3070_rf_write(sc, 51, rf); 4496 4497 run_rt3070_rf_read(sc, 38, &rf); 4498 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4499 4500 run_rt3070_rf_read(sc, 39, &rf); 4501 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4502 4503 run_rt3070_rf_read(sc, 1, &rf); 4504 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4505 4506 run_rt3070_rf_read(sc, 30, &rf); 4507 rf = (rf & ~0x18) | 0x10; 4508 run_rt3070_rf_write(sc, 30, rf); 4509 4510 /* Apply maximum likelihood detection for 2 stream case. */ 4511 run_bbp_read(sc, 105, &bbp); 4512 if (sc->nrxchains > 1) 4513 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4514 4515 /* Avoid data lost and CRC error. */ 4516 run_bbp_read(sc, 4, &bbp); 4517 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4518 4519 run_bbp_write(sc, 92, 0x02); 4520 run_bbp_write(sc, 82, 0x82); 4521 run_bbp_write(sc, 106, 0x05); 4522 run_bbp_write(sc, 104, 0x92); 4523 run_bbp_write(sc, 88, 0x90); 4524 run_bbp_write(sc, 148, 0xc8); 4525 run_bbp_write(sc, 47, 0x48); 4526 run_bbp_write(sc, 120, 0x50); 4527 4528 run_bbp_write(sc, 163, 0x9d); 4529 4530 /* SNR mapping. */ 4531 run_bbp_write(sc, 142, 0x06); 4532 run_bbp_write(sc, 143, 0xa0); 4533 run_bbp_write(sc, 142, 0x07); 4534 run_bbp_write(sc, 143, 0xa1); 4535 run_bbp_write(sc, 142, 0x08); 4536 run_bbp_write(sc, 143, 0xa2); 4537 4538 run_bbp_write(sc, 31, 0x08); 4539 run_bbp_write(sc, 68, 0x0b); 4540 run_bbp_write(sc, 105, 0x04); 4541 } 4542 4543 static void 4544 run_rt5390_rf_setup(struct run_softc *sc) 4545 { 4546 uint8_t bbp, rf; 4547 4548 if (sc->mac_rev >= 0x0211) { 4549 /* Enable DC filter. */ 4550 run_bbp_write(sc, 103, 0xc0); 4551 4552 if (sc->mac_ver != 0x5592) { 4553 /* Improve power consumption. */ 4554 run_bbp_read(sc, 31, &bbp); 4555 run_bbp_write(sc, 31, bbp & ~0x03); 4556 } 4557 } 4558 4559 run_bbp_read(sc, 138, &bbp); 4560 if (sc->ntxchains == 1) 4561 bbp |= 0x20; /* turn off DAC1 */ 4562 if (sc->nrxchains == 1) 4563 bbp &= ~0x02; /* turn off ADC1 */ 4564 run_bbp_write(sc, 138, bbp); 4565 4566 run_rt3070_rf_read(sc, 38, &rf); 4567 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4568 4569 run_rt3070_rf_read(sc, 39, &rf); 4570 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4571 4572 /* Avoid data lost and CRC error. */ 4573 run_bbp_read(sc, 4, &bbp); 4574 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4575 4576 run_rt3070_rf_read(sc, 30, &rf); 4577 rf = (rf & ~0x18) | 0x10; 4578 run_rt3070_rf_write(sc, 30, rf); 4579 4580 if (sc->mac_ver != 0x5592) { 4581 run_write(sc, RT2860_TX_SW_CFG1, 0); 4582 if (sc->mac_rev < 0x0211) { 4583 run_write(sc, RT2860_TX_SW_CFG2, 4584 sc->patch_dac ? 0x2c : 0x0f); 4585 } else 4586 run_write(sc, RT2860_TX_SW_CFG2, 0); 4587 } 4588 } 4589 4590 static int 4591 run_txrx_enable(struct run_softc *sc) 4592 { 4593 uint32_t tmp; 4594 int error, ntries; 4595 4596 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4597 for (ntries = 0; ntries < 200; ntries++) { 4598 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4599 return error; 4600 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4601 break; 4602 usbd_delay_ms(sc->sc_udev, 50); 4603 } 4604 if (ntries == 200) 4605 return ETIMEDOUT; 4606 4607 usbd_delay_ms(sc->sc_udev, 50); 4608 4609 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4610 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4611 4612 /* enable Rx bulk aggregation (set timeout and limit) */ 4613 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4614 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4615 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4616 4617 /* set Rx filter */ 4618 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4619 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4620 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4621 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4622 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4623 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4624 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4625 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4626 } 4627 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4628 4629 run_write(sc, RT2860_MAC_SYS_CTRL, 4630 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4631 4632 return 0; 4633 } 4634 4635 static int 4636 run_adjust_freq_offset(struct run_softc *sc) 4637 { 4638 uint8_t rf, tmp; 4639 4640 run_rt3070_rf_read(sc, 17, &rf); 4641 tmp = rf; 4642 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4643 rf = MIN(rf, 0x5f); 4644 4645 if (tmp != rf) 4646 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4647 4648 return 0; 4649 } 4650 4651 static int 4652 run_init(struct ifnet *ifp) 4653 { 4654 struct run_softc *sc = ifp->if_softc; 4655 struct ieee80211com *ic = &sc->sc_ic; 4656 uint32_t tmp; 4657 uint8_t bbp1, bbp3; 4658 int i, error, qid, ridx, ntries; 4659 usbd_status status; 4660 4661 for (ntries = 0; ntries < 100; ntries++) { 4662 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4663 goto fail; 4664 if (tmp != 0 && tmp != 0xffffffff) 4665 break; 4666 usbd_delay_ms(sc->sc_udev, 10); 4667 } 4668 if (ntries == 100) { 4669 error = ETIMEDOUT; 4670 goto fail; 4671 } 4672 4673 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4674 (error = run_load_microcode(sc)) != 0) { 4675 device_printf(sc->sc_dev, 4676 "could not load 8051 microcode\n"); 4677 goto fail; 4678 } 4679 4680 if (ifp->if_flags & IFF_RUNNING) 4681 run_stop(ifp, 0); 4682 4683 /* init host command ring */ 4684 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4685 4686 /* init Tx rings (4 EDCAs) */ 4687 for (qid = 0; qid < 4; qid++) { 4688 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4689 goto fail; 4690 } 4691 /* init Rx ring */ 4692 if ((error = run_alloc_rx_ring(sc)) != 0) 4693 goto fail; 4694 4695 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4696 run_set_macaddr(sc, ic->ic_myaddr); 4697 4698 for (ntries = 0; ntries < 100; ntries++) { 4699 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4700 goto fail; 4701 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4702 break; 4703 usbd_delay_ms(sc->sc_udev, 10); 4704 } 4705 if (ntries == 100) { 4706 device_printf(sc->sc_dev, 4707 "timeout waiting for DMA engine\n"); 4708 error = ETIMEDOUT; 4709 goto fail; 4710 } 4711 tmp &= 0xff0; 4712 tmp |= RT2860_TX_WB_DDONE; 4713 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4714 4715 /* turn off PME_OEN to solve high-current issue */ 4716 run_read(sc, RT2860_SYS_CTRL, &tmp); 4717 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4718 4719 run_write(sc, RT2860_MAC_SYS_CTRL, 4720 RT2860_BBP_HRST | RT2860_MAC_SRST); 4721 run_write(sc, RT2860_USB_DMA_CFG, 0); 4722 4723 if ((error = run_reset(sc)) != 0) { 4724 device_printf(sc->sc_dev, "could not reset chipset\n"); 4725 goto fail; 4726 } 4727 4728 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4729 4730 /* init Tx power for all Tx rates (from EEPROM) */ 4731 for (ridx = 0; ridx < 5; ridx++) { 4732 if (sc->txpow20mhz[ridx] == 0xffffffff) 4733 continue; 4734 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4735 } 4736 4737 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4738 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4739 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4740 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4741 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4742 4743 if (sc->mac_ver >= 0x5390) { 4744 run_write(sc, RT2860_TX_SW_CFG0, 4745 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4746 if (sc->mac_ver >= 0x5392) { 4747 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4748 if (sc->mac_ver == 0x5592) { 4749 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4750 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4751 } else { 4752 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4753 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4754 } 4755 } 4756 } else if (sc->mac_ver >= 0x3593) { 4757 run_write(sc, RT2860_TX_SW_CFG0, 4758 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4759 } else if (sc->mac_ver >= 0x3070) { 4760 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4761 run_write(sc, RT2860_TX_SW_CFG0, 4762 4 << RT2860_DLY_PAPE_EN_SHIFT); 4763 } 4764 4765 /* wait while MAC is busy */ 4766 for (ntries = 0; ntries < 100; ntries++) { 4767 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4768 goto fail; 4769 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4770 break; 4771 DELAY(1000); 4772 } 4773 if (ntries == 100) { 4774 error = ETIMEDOUT; 4775 goto fail; 4776 } 4777 4778 /* clear Host to MCU mailbox */ 4779 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4780 run_write(sc, RT2860_H2M_MAILBOX, 0); 4781 usbd_delay_ms(sc->sc_udev, 10); 4782 4783 if ((error = run_bbp_init(sc)) != 0) { 4784 device_printf(sc->sc_dev, "could not initialize BBP\n"); 4785 goto fail; 4786 } 4787 4788 /* abort TSF synchronization */ 4789 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4790 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4791 RT2860_TBTT_TIMER_EN); 4792 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4793 4794 /* clear RX WCID search table */ 4795 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4796 /* clear Pair-wise key table */ 4797 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4798 /* clear IV/EIV table */ 4799 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4800 /* clear WCID attribute table */ 4801 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4802 /* clear shared key table */ 4803 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4804 /* clear shared key mode */ 4805 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4806 4807 /* clear RX WCID search table */ 4808 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4809 /* clear WCID attribute table */ 4810 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4811 4812 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4813 tmp = (tmp & ~0xff) | 0x1e; 4814 run_write(sc, RT2860_US_CYC_CNT, tmp); 4815 4816 if (sc->mac_rev != 0x0101) 4817 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4818 4819 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4820 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4821 4822 /* write vendor-specific BBP values (from EEPROM) */ 4823 if (sc->mac_ver < 0x3593) { 4824 for (i = 0; i < 10; i++) { 4825 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4826 continue; 4827 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4828 } 4829 } 4830 4831 /* select Main antenna for 1T1R devices */ 4832 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4833 run_set_rx_antenna(sc, 0); 4834 4835 /* send LEDs operating mode to microcontroller */ 4836 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4837 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4838 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4839 4840 if (sc->mac_ver >= 0x5390) 4841 run_rt5390_rf_init(sc); 4842 else if (sc->mac_ver == 0x3593) 4843 run_rt3593_rf_init(sc); 4844 else if (sc->mac_ver >= 0x3070) 4845 run_rt3070_rf_init(sc); 4846 4847 /* disable non-existing Rx chains */ 4848 run_bbp_read(sc, 3, &bbp3); 4849 bbp3 &= ~(1 << 3 | 1 << 4); 4850 if (sc->nrxchains == 2) 4851 bbp3 |= 1 << 3; 4852 else if (sc->nrxchains == 3) 4853 bbp3 |= 1 << 4; 4854 run_bbp_write(sc, 3, bbp3); 4855 4856 /* disable non-existing Tx chains */ 4857 run_bbp_read(sc, 1, &bbp1); 4858 if (sc->ntxchains == 1) 4859 bbp1 &= ~(1 << 3 | 1 << 4); 4860 run_bbp_write(sc, 1, bbp1); 4861 4862 if (sc->mac_ver >= 0x5390) 4863 run_rt5390_rf_setup(sc); 4864 else if (sc->mac_ver == 0x3593) 4865 run_rt3593_rf_setup(sc); 4866 else if (sc->mac_ver >= 0x3070) 4867 run_rt3070_rf_setup(sc); 4868 4869 /* select default channel */ 4870 run_set_chan(sc, ic->ic_curchan); 4871 4872 /* setup initial protection mode */ 4873 run_updateprot(sc); 4874 4875 /* turn radio LED on */ 4876 run_set_leds(sc, RT2860_LED_RADIO); 4877 4878 #ifdef RUN_HWCRYPTO 4879 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4880 /* install WEP keys */ 4881 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4882 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4883 NULL); 4884 } 4885 #endif 4886 4887 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4888 struct run_rx_data *data = &sc->rxq.data[i]; 4889 4890 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4891 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4892 status = usbd_transfer(data->xfer); 4893 if (status != USBD_NORMAL_COMPLETION && 4894 status != USBD_IN_PROGRESS) { 4895 device_printf(sc->sc_dev, "queuing rx failed: %s\n", 4896 usbd_errstr(status)); 4897 error = EIO; 4898 goto fail; 4899 } 4900 } 4901 4902 if ((error = run_txrx_enable(sc)) != 0) 4903 goto fail; 4904 4905 ifp->if_flags &= ~IFF_OACTIVE; 4906 ifp->if_flags |= IFF_RUNNING; 4907 4908 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4909 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4910 else 4911 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4912 4913 if (error != 0) 4914 fail: run_stop(ifp, 1); 4915 return error; 4916 } 4917 4918 static void 4919 run_stop(struct ifnet *ifp, int disable) 4920 { 4921 struct run_softc *sc = ifp->if_softc; 4922 struct ieee80211com *ic = &sc->sc_ic; 4923 uint32_t tmp; 4924 int ntries, qid; 4925 4926 if (ifp->if_flags & IFF_RUNNING) 4927 run_set_leds(sc, 0); /* turn all LEDs off */ 4928 4929 sc->sc_tx_timer = 0; 4930 ifp->if_timer = 0; 4931 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4932 4933 callout_stop(&sc->scan_to); 4934 callout_stop(&sc->calib_to); 4935 4936 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4937 /* wait for all queued asynchronous commands to complete */ 4938 while (sc->cmdq.queued > 0) 4939 tsleep(&sc->cmdq, 0, "cmdq", 0); 4940 4941 /* disable Tx/Rx */ 4942 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4943 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4944 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4945 4946 /* wait for pending Tx to complete */ 4947 for (ntries = 0; ntries < 100; ntries++) { 4948 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4949 break; 4950 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4951 break; 4952 } 4953 DELAY(1000); 4954 run_write(sc, RT2860_USB_DMA_CFG, 0); 4955 4956 /* reset adapter */ 4957 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4958 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4959 4960 /* reset Tx and Rx rings */ 4961 sc->qfullmsk = 0; 4962 for (qid = 0; qid < 4; qid++) 4963 run_free_tx_ring(sc, qid); 4964 run_free_rx_ring(sc); 4965 } 4966 4967 #ifndef IEEE80211_STA_ONLY 4968 static int 4969 run_setup_beacon(struct run_softc *sc) 4970 { 4971 struct ieee80211com *ic = &sc->sc_ic; 4972 struct rt2860_txwi txwi; 4973 struct mbuf *m; 4974 uint16_t txwisize; 4975 int ridx; 4976 4977 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4978 return ENOBUFS; 4979 4980 memset(&txwi, 0, sizeof(txwi)); 4981 txwi.wcid = 0xff; 4982 txwi.len = htole16(m->m_pkthdr.len); 4983 /* send beacons at the lowest available rate */ 4984 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4985 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4986 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4987 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4988 txwi.phy |= htole16(RT2860_PHY_OFDM); 4989 txwi.txop = RT2860_TX_TXOP_HT; 4990 txwi.flags = RT2860_TX_TS; 4991 4992 txwisize = (sc->mac_ver == 0x5592) ? 4993 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4994 run_write_region_1(sc, RT2860_BCN_BASE(0), 4995 (uint8_t *)&txwi, txwisize); 4996 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4997 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4998 4999 m_freem(m); 5000 5001 return 0; 5002 } 5003 #endif 5004 5005 MODULE(MODULE_CLASS_DRIVER, if_run, NULL); 5006 5007 #ifdef _MODULE 5008 #include "ioconf.c" 5009 #endif 5010 5011 static int 5012 if_run_modcmd(modcmd_t cmd, void *arg) 5013 { 5014 int error = 0; 5015 5016 switch (cmd) { 5017 case MODULE_CMD_INIT: 5018 #ifdef _MODULE 5019 error = config_init_component(cfdriver_ioconf_run, 5020 cfattach_ioconf_run, cfdata_ioconf_run); 5021 #endif 5022 return error; 5023 case MODULE_CMD_FINI: 5024 #ifdef _MODULE 5025 error = config_fini_component(cfdriver_ioconf_run, 5026 cfattach_ioconf_run, cfdata_ioconf_run); 5027 #endif 5028 return error; 5029 default: 5030 return ENOTTY; 5031 } 5032 } 5033