1 /* $NetBSD: if_run.c,v 1.33 2019/10/08 07:30:58 mlelstv Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.33 2019/10/08 07:30:58 mlelstv Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/firmload.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usbdi_util.h> 67 #include <dev/usb/usbdevs.h> 68 69 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 70 #include <dev/usb/if_runvar.h> 71 72 #ifdef RUN_DEBUG 73 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 75 int run_debug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 82 83 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 84 static const struct usb_devno run_devs[] = { 85 USB_ID(ABOCOM, RT2770), 86 USB_ID(ABOCOM, RT2870), 87 USB_ID(ABOCOM, RT3070), 88 USB_ID(ABOCOM, RT3071), 89 USB_ID(ABOCOM, RT3072), 90 USB_ID(ABOCOM2, RT2870_1), 91 USB_ID(ACCTON, RT2770), 92 USB_ID(ACCTON, RT2870_1), 93 USB_ID(ACCTON, RT2870_2), 94 USB_ID(ACCTON, RT2870_3), 95 USB_ID(ACCTON, RT2870_4), 96 USB_ID(ACCTON, RT2870_5), 97 USB_ID(ACCTON, RT3070), 98 USB_ID(ACCTON, RT3070_1), 99 USB_ID(ACCTON, RT3070_2), 100 USB_ID(ACCTON, RT3070_3), 101 USB_ID(ACCTON, RT3070_4), 102 USB_ID(ACCTON, RT3070_5), 103 USB_ID(ACCTON, RT3070_6), 104 USB_ID(AIRTIES, RT3070), 105 USB_ID(AIRTIES, RT3070_2), 106 USB_ID(ALLWIN, RT2070), 107 USB_ID(ALLWIN, RT2770), 108 USB_ID(ALLWIN, RT2870), 109 USB_ID(ALLWIN, RT3070), 110 USB_ID(ALLWIN, RT3071), 111 USB_ID(ALLWIN, RT3072), 112 USB_ID(ALLWIN, RT3572), 113 USB_ID(AMIGO, RT2870_1), 114 USB_ID(AMIGO, RT2870_2), 115 USB_ID(AMIT, CGWLUSB2GNR), 116 USB_ID(AMIT, RT2870_1), 117 USB_ID(AMIT2, RT2870), 118 USB_ID(ASUSTEK, RT2870_1), 119 USB_ID(ASUSTEK, RT2870_2), 120 USB_ID(ASUSTEK, RT2870_3), 121 USB_ID(ASUSTEK, RT2870_4), 122 USB_ID(ASUSTEK, RT2870_5), 123 USB_ID(ASUSTEK, RT3070), 124 USB_ID(ASUSTEK, RT3070_1), 125 USB_ID(ASUSTEK, USBN53), 126 USB_ID(ASUSTEK, USBN66), 127 USB_ID(ASUSTEK2, USBN11), 128 USB_ID(AZUREWAVE, RT2870_1), 129 USB_ID(AZUREWAVE, RT2870_2), 130 USB_ID(AZUREWAVE, RT3070), 131 USB_ID(AZUREWAVE, RT3070_2), 132 USB_ID(AZUREWAVE, RT3070_3), 133 USB_ID(AZUREWAVE, RT3070_4), 134 USB_ID(AZUREWAVE, RT3070_5), 135 USB_ID(BELKIN, F5D8053V3), 136 USB_ID(BELKIN, F5D8055), 137 USB_ID(BELKIN, F5D8055V2), 138 USB_ID(BELKIN, F6D4050V1), 139 USB_ID(BELKIN, F6D4050V2), 140 USB_ID(BELKIN, F7D1101V2), 141 USB_ID(BELKIN, RT2870_1), 142 USB_ID(BELKIN, RT2870_2), 143 USB_ID(BELKIN, RTL8192CU_2), 144 USB_ID(BEWAN, RT3070), 145 USB_ID(CISCOLINKSYS, AE1000), 146 USB_ID(CISCOLINKSYS, AM10), 147 USB_ID(CISCOLINKSYS2, RT3070), 148 USB_ID(CISCOLINKSYS3, RT3070), 149 USB_ID(CONCEPTRONIC, RT2870_1), 150 USB_ID(CONCEPTRONIC, RT2870_2), 151 USB_ID(CONCEPTRONIC, RT2870_3), 152 USB_ID(CONCEPTRONIC, RT2870_4), 153 USB_ID(CONCEPTRONIC, RT2870_5), 154 USB_ID(CONCEPTRONIC, RT2870_6), 155 USB_ID(CONCEPTRONIC, RT2870_7), 156 USB_ID(CONCEPTRONIC, RT2870_8), 157 USB_ID(CONCEPTRONIC, RT3070_1), 158 USB_ID(CONCEPTRONIC, RT3070_2), 159 USB_ID(CONCEPTRONIC, RT3070_3), 160 USB_ID(COREGA, CGWLUSB300GNM), 161 USB_ID(COREGA, RT2870_1), 162 USB_ID(COREGA, RT2870_2), 163 USB_ID(COREGA, RT2870_3), 164 USB_ID(COREGA, RT3070), 165 USB_ID(CYBERTAN, RT2870), 166 USB_ID(DLINK, RT2870), 167 USB_ID(DLINK, RT3072), 168 USB_ID(DLINK, DWA127), 169 USB_ID(DLINK, DWA140B3), 170 USB_ID(DLINK, DWA160B2), 171 USB_ID(DLINK, DWA162), 172 USB_ID(DLINK2, DWA130), 173 USB_ID(DLINK2, RT2870_1), 174 USB_ID(DLINK2, RT2870_2), 175 USB_ID(DLINK2, RT3070_1), 176 USB_ID(DLINK2, RT3070_2), 177 USB_ID(DLINK2, RT3070_3), 178 USB_ID(DLINK2, RT3070_4), 179 USB_ID(DLINK2, RT3070_5), 180 USB_ID(DLINK2, RT3072), 181 USB_ID(DLINK2, RT3072_1), 182 USB_ID(DVICO, RT3070), 183 USB_ID(EDIMAX, EW7717), 184 USB_ID(EDIMAX, EW7718), 185 USB_ID(EDIMAX, EW7722UTN), 186 USB_ID(EDIMAX, RT2870_1), 187 USB_ID(ENCORE, RT3070), 188 USB_ID(ENCORE, RT3070_2), 189 USB_ID(ENCORE, RT3070_3), 190 USB_ID(GIGABYTE, GNWB31N), 191 USB_ID(GIGABYTE, GNWB32L), 192 USB_ID(GIGABYTE, RT2870_1), 193 USB_ID(GIGASET, RT3070_1), 194 USB_ID(GIGASET, RT3070_2), 195 USB_ID(GUILLEMOT, HWNU300), 196 USB_ID(HAWKING, HWUN2), 197 USB_ID(HAWKING, RT2870_1), 198 USB_ID(HAWKING, RT2870_2), 199 USB_ID(HAWKING, RT2870_3), 200 USB_ID(HAWKING, RT2870_4), 201 USB_ID(HAWKING, RT2870_5), 202 USB_ID(HAWKING, RT3070), 203 USB_ID(IODATA, RT3072_1), 204 USB_ID(IODATA, RT3072_2), 205 USB_ID(IODATA, RT3072_3), 206 USB_ID(IODATA, RT3072_4), 207 USB_ID(LINKSYS4, RT3070), 208 USB_ID(LINKSYS4, WUSB100), 209 USB_ID(LINKSYS4, WUSB54GC_3), 210 USB_ID(LINKSYS4, WUSB600N), 211 USB_ID(LINKSYS4, WUSB600NV2), 212 USB_ID(LOGITEC, LANW300NU2), 213 USB_ID(LOGITEC, LANW300NU2S), 214 USB_ID(LOGITEC, LAN_W300ANU2), 215 USB_ID(LOGITEC, LAN_W450ANU2E), 216 USB_ID(LOGITEC, RT2870_1), 217 USB_ID(LOGITEC, RT2870_2), 218 USB_ID(LOGITEC, RT2870_3), 219 USB_ID(LOGITEC, RT3020), 220 USB_ID(MELCO, RT2870_1), 221 USB_ID(MELCO, RT2870_2), 222 USB_ID(MELCO, WLIUCAG300N), 223 USB_ID(MELCO, WLIUCG300N), 224 USB_ID(MELCO, WLIUCG301N), 225 USB_ID(MELCO, WLIUCGN), 226 USB_ID(MELCO, WLIUCGNHP), 227 USB_ID(MELCO, WLIUCGNM), 228 USB_ID(MELCO, WLIUCGNM2T), 229 USB_ID(MOTOROLA4, RT2770), 230 USB_ID(MOTOROLA4, RT3070), 231 USB_ID(MSI, RT3070), 232 USB_ID(MSI, RT3070_2), 233 USB_ID(MSI, RT3070_3), 234 USB_ID(MSI, RT3070_4), 235 USB_ID(MSI, RT3070_5), 236 USB_ID(MSI, RT3070_6), 237 USB_ID(MSI, RT3070_7), 238 USB_ID(MSI, RT3070_8), 239 USB_ID(MSI, RT3070_9), 240 USB_ID(MSI, RT3070_10), 241 USB_ID(MSI, RT3070_11), 242 USB_ID(MSI, RT3070_12), 243 USB_ID(MSI, RT3070_13), 244 USB_ID(MSI, RT3070_14), 245 USB_ID(MSI, RT3070_15), 246 USB_ID(OVISLINK, RT3071), 247 USB_ID(OVISLINK, RT3072), 248 USB_ID(PARA, RT3070), 249 USB_ID(PEGATRON, RT2870), 250 USB_ID(PEGATRON, RT3070), 251 USB_ID(PEGATRON, RT3070_2), 252 USB_ID(PEGATRON, RT3070_3), 253 USB_ID(PEGATRON, RT3072), 254 USB_ID(PHILIPS, RT2870), 255 USB_ID(PLANEX2, GWUS300MINIS), 256 USB_ID(PLANEX2, GWUSMICRO300), 257 USB_ID(PLANEX2, GWUSMICRON), 258 USB_ID(PLANEX2, GWUS300MINIX), 259 USB_ID(PLANEX2, RT3070), 260 USB_ID(QCOM, RT2870), 261 USB_ID(QUANTA, RT3070), 262 USB_ID(RALINK, RT2070), 263 USB_ID(RALINK, RT2770), 264 USB_ID(RALINK, RT2870), 265 USB_ID(RALINK, RT3070), 266 USB_ID(RALINK, RT3071), 267 USB_ID(RALINK, RT3072), 268 USB_ID(RALINK, RT3370), 269 USB_ID(RALINK, RT3572), 270 USB_ID(RALINK, RT3573), 271 USB_ID(RALINK, RT5370), 272 USB_ID(RALINK, RT5572), 273 USB_ID(RALINK, RT8070), 274 USB_ID(SAMSUNG, RT2870_1), 275 USB_ID(SENAO, RT2870_1), 276 USB_ID(SENAO, RT2870_2), 277 USB_ID(SENAO, RT2870_3), 278 USB_ID(SENAO, RT2870_4), 279 USB_ID(SENAO, RT3070), 280 USB_ID(SENAO, RT3071), 281 USB_ID(SENAO, RT3072), 282 USB_ID(SENAO, RT3072_2), 283 USB_ID(SENAO, RT3072_3), 284 USB_ID(SENAO, RT3072_4), 285 USB_ID(SENAO, RT3072_5), 286 USB_ID(SITECOMEU, RT2870_1), 287 USB_ID(SITECOMEU, RT2870_2), 288 USB_ID(SITECOMEU, RT2870_3), 289 USB_ID(SITECOMEU, RT3070_1), 290 USB_ID(SITECOMEU, RT3070_3), 291 USB_ID(SITECOMEU, RT3072_3), 292 USB_ID(SITECOMEU, RT3072_4), 293 USB_ID(SITECOMEU, RT3072_5), 294 USB_ID(SITECOMEU, RT3072_6), 295 USB_ID(SITECOMEU, WL302), 296 USB_ID(SITECOMEU, WL315), 297 USB_ID(SITECOMEU, WL321), 298 USB_ID(SITECOMEU, WL324), 299 USB_ID(SITECOMEU, WL329), 300 USB_ID(SITECOMEU, WL343), 301 USB_ID(SITECOMEU, WL344), 302 USB_ID(SITECOMEU, WL345), 303 USB_ID(SITECOMEU, WL349V4), 304 USB_ID(SITECOMEU, WL608), 305 USB_ID(SITECOMEU, WLA4000), 306 USB_ID(SITECOMEU, WLA5000), 307 USB_ID(SPARKLAN, RT2870_1), 308 USB_ID(SPARKLAN, RT2870_2), 309 USB_ID(SPARKLAN, RT3070), 310 USB_ID(SWEEX2, LW153), 311 USB_ID(SWEEX2, LW303), 312 USB_ID(SWEEX2, LW313), 313 USB_ID(TOSHIBA, RT3070), 314 USB_ID(UMEDIA, RT2870_1), 315 USB_ID(UMEDIA, TEW645UB), 316 USB_ID(ZCOM, RT2870_1), 317 USB_ID(ZCOM, RT2870_2), 318 USB_ID(ZINWELL, RT2870_1), 319 USB_ID(ZINWELL, RT2870_2), 320 USB_ID(ZINWELL, RT3070), 321 USB_ID(ZINWELL, RT3072), 322 USB_ID(ZINWELL, RT3072_2), 323 USB_ID(ZYXEL, NWD2105), 324 USB_ID(ZYXEL, NWD211AN), 325 USB_ID(ZYXEL, RT2870_1), 326 USB_ID(ZYXEL, RT2870_2), 327 USB_ID(ZYXEL, RT3070), 328 }; 329 330 static int run_match(device_t, cfdata_t, void *); 331 static void run_attach(device_t, device_t, void *); 332 static int run_detach(device_t, int); 333 static int run_activate(device_t, enum devact); 334 335 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 336 run_match, run_attach, run_detach, run_activate); 337 338 static int run_alloc_rx_ring(struct run_softc *); 339 static void run_free_rx_ring(struct run_softc *); 340 static int run_alloc_tx_ring(struct run_softc *, int); 341 static void run_free_tx_ring(struct run_softc *, int); 342 static int run_load_microcode(struct run_softc *); 343 static int run_reset(struct run_softc *); 344 static int run_read(struct run_softc *, uint16_t, uint32_t *); 345 static int run_read_region_1(struct run_softc *, uint16_t, 346 uint8_t *, int); 347 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 348 static int run_write(struct run_softc *, uint16_t, uint32_t); 349 static int run_write_region_1(struct run_softc *, uint16_t, 350 const uint8_t *, int); 351 static int run_set_region_4(struct run_softc *, uint16_t, 352 uint32_t, int); 353 static int run_efuse_read(struct run_softc *, uint16_t, 354 uint16_t *, int); 355 static int run_efuse_read_2(struct run_softc *, uint16_t, 356 uint16_t *); 357 static int run_eeprom_read_2(struct run_softc *, uint16_t, 358 uint16_t *); 359 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 360 uint32_t); 361 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 362 uint8_t *); 363 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 364 uint8_t); 365 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 366 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 367 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 368 static const char * run_get_rf(uint16_t); 369 static void run_rt3593_get_txpower(struct run_softc *); 370 static void run_get_txpower(struct run_softc *); 371 static int run_read_eeprom(struct run_softc *); 372 static struct ieee80211_node * 373 run_node_alloc(struct ieee80211_node_table *); 374 static int run_media_change(struct ifnet *); 375 static void run_next_scan(void *); 376 static void run_task(void *); 377 static void run_do_async(struct run_softc *, 378 void (*)(struct run_softc *, void *), void *, int); 379 static int run_newstate(struct ieee80211com *, 380 enum ieee80211_state, int); 381 static void run_newstate_cb(struct run_softc *, void *); 382 static int run_updateedca(struct ieee80211com *); 383 static void run_updateedca_cb(struct run_softc *, void *); 384 #ifdef RUN_HWCRYPTO 385 static int run_set_key(struct ieee80211com *, 386 const struct ieee80211_key *, const uint8_t *); 387 static void run_set_key_cb(struct run_softc *, void *); 388 static int run_delete_key(struct ieee80211com *, 389 const struct ieee80211_key *); 390 static void run_delete_key_cb(struct run_softc *, void *); 391 #endif 392 static void run_calibrate_to(void *); 393 static void run_calibrate_cb(struct run_softc *, void *); 394 static void run_newassoc(struct ieee80211_node *, int); 395 static void run_rx_frame(struct run_softc *, uint8_t *, int); 396 static void run_rxeof(struct usbd_xfer *, void *, 397 usbd_status); 398 static void run_txeof(struct usbd_xfer *, void *, 399 usbd_status); 400 static int run_tx(struct run_softc *, struct mbuf *, 401 struct ieee80211_node *); 402 static void run_start(struct ifnet *); 403 static void run_watchdog(struct ifnet *); 404 static int run_ioctl(struct ifnet *, u_long, void *); 405 static void run_select_chan_group(struct run_softc *, int); 406 static void run_iq_calib(struct run_softc *, u_int); 407 static void run_set_agc(struct run_softc *, uint8_t); 408 static void run_set_rx_antenna(struct run_softc *, int); 409 static void run_rt2870_set_chan(struct run_softc *, u_int); 410 static void run_rt3070_set_chan(struct run_softc *, u_int); 411 static void run_rt3572_set_chan(struct run_softc *, u_int); 412 static void run_rt3593_set_chan(struct run_softc *, u_int); 413 static void run_rt5390_set_chan(struct run_softc *, u_int); 414 static void run_rt5592_set_chan(struct run_softc *, u_int); 415 static int run_set_chan(struct run_softc *, 416 struct ieee80211_channel *); 417 static void run_updateprot(struct run_softc *); 418 static void run_enable_tsf_sync(struct run_softc *); 419 static void run_enable_mrr(struct run_softc *); 420 static void run_set_txpreamble(struct run_softc *); 421 static void run_set_basicrates(struct run_softc *); 422 static void run_set_leds(struct run_softc *, uint16_t); 423 static void run_set_bssid(struct run_softc *, const uint8_t *); 424 static void run_set_macaddr(struct run_softc *, const uint8_t *); 425 static void run_updateslot(struct ifnet *); 426 static void run_updateslot_cb(struct run_softc *, void *); 427 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 428 static void run_rt5390_bbp_init(struct run_softc *); 429 static int run_bbp_init(struct run_softc *); 430 static int run_rt3070_rf_init(struct run_softc *); 431 static int run_rt3593_rf_init(struct run_softc *); 432 static int run_rt5390_rf_init(struct run_softc *); 433 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 434 uint8_t, uint8_t *); 435 static void run_rt3070_rf_setup(struct run_softc *); 436 static void run_rt3593_rf_setup(struct run_softc *); 437 static void run_rt5390_rf_setup(struct run_softc *); 438 static int run_txrx_enable(struct run_softc *); 439 static int run_adjust_freq_offset(struct run_softc *); 440 static int run_init(struct ifnet *); 441 static void run_stop(struct ifnet *, int); 442 #ifndef IEEE80211_STA_ONLY 443 static int run_setup_beacon(struct run_softc *); 444 #endif 445 446 static const struct { 447 uint32_t reg; 448 uint32_t val; 449 } rt2870_def_mac[] = { 450 RT2870_DEF_MAC 451 }; 452 453 static const struct { 454 uint8_t reg; 455 uint8_t val; 456 } rt2860_def_bbp[] = { 457 RT2860_DEF_BBP 458 }, rt5390_def_bbp[] = { 459 RT5390_DEF_BBP 460 }, rt5592_def_bbp[] = { 461 RT5592_DEF_BBP 462 }; 463 464 /* 465 * Default values for BBP register R196 for RT5592. 466 */ 467 static const uint8_t rt5592_bbp_r196[] = { 468 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 469 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 470 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 471 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 472 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 473 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 474 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 475 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 476 0x2e, 0x36, 0x30, 0x6e 477 }; 478 479 static const struct rfprog { 480 uint8_t chan; 481 uint32_t r1, r2, r3, r4; 482 } rt2860_rf2850[] = { 483 RT2860_RF2850 484 }; 485 486 static const struct { 487 uint8_t n, r, k; 488 } rt3070_freqs[] = { 489 RT3070_RF3052 490 }; 491 492 static const struct rt5592_freqs { 493 uint16_t n; 494 uint8_t k, m, r; 495 } rt5592_freqs_20mhz[] = { 496 RT5592_RF5592_20MHZ 497 },rt5592_freqs_40mhz[] = { 498 RT5592_RF5592_40MHZ 499 }; 500 501 static const struct { 502 uint8_t reg; 503 uint8_t val; 504 } rt3070_def_rf[] = { 505 RT3070_DEF_RF 506 }, rt3572_def_rf[] = { 507 RT3572_DEF_RF 508 },rt3593_def_rf[] = { 509 RT3593_DEF_RF 510 },rt5390_def_rf[] = { 511 RT5390_DEF_RF 512 },rt5392_def_rf[] = { 513 RT5392_DEF_RF 514 },rt5592_def_rf[] = { 515 RT5592_DEF_RF 516 },rt5592_2ghz_def_rf[] = { 517 RT5592_2GHZ_DEF_RF 518 },rt5592_5ghz_def_rf[] = { 519 RT5592_5GHZ_DEF_RF 520 }; 521 522 static const struct { 523 u_int firstchan; 524 u_int lastchan; 525 uint8_t reg; 526 uint8_t val; 527 } rt5592_chan_5ghz[] = { 528 RT5592_CHAN_5GHZ 529 }; 530 531 static int 532 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 533 size_t *sizep) 534 { 535 firmware_handle_t fh; 536 int error; 537 538 if ((error = firmware_open(dname, iname, &fh)) != 0) 539 return error; 540 *sizep = firmware_get_size(fh); 541 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 542 firmware_close(fh); 543 return ENOMEM; 544 } 545 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 546 firmware_free(*ucodep, *sizep); 547 firmware_close(fh); 548 549 return error; 550 } 551 552 static int 553 run_match(device_t parent, cfdata_t match, void *aux) 554 { 555 struct usb_attach_arg *uaa = aux; 556 557 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 558 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 559 } 560 561 static void 562 run_attach(device_t parent, device_t self, void *aux) 563 { 564 struct run_softc *sc = device_private(self); 565 struct usb_attach_arg *uaa = aux; 566 struct ieee80211com *ic = &sc->sc_ic; 567 struct ifnet *ifp = &sc->sc_if; 568 usb_interface_descriptor_t *id; 569 usb_endpoint_descriptor_t *ed; 570 char *devinfop; 571 int i, nrx, ntx, ntries, error; 572 uint32_t ver; 573 574 aprint_naive("\n"); 575 aprint_normal("\n"); 576 577 sc->sc_dev = self; 578 sc->sc_udev = uaa->uaa_device; 579 580 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 581 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 582 usbd_devinfo_free(devinfop); 583 584 error = usbd_set_config_no(sc->sc_udev, 1, 0); 585 if (error != 0) { 586 aprint_error_dev(sc->sc_dev, "failed to set configuration" 587 ", err=%s\n", usbd_errstr(error)); 588 return; 589 } 590 591 /* get the first interface handle */ 592 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 593 if (error != 0) { 594 aprint_error_dev(sc->sc_dev, 595 "could not get interface handle\n"); 596 return; 597 } 598 599 /* 600 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 601 * and 6 for TX (4 EDCAs + HCCA + Prio). 602 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 603 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 604 */ 605 nrx = ntx = 0; 606 id = usbd_get_interface_descriptor(sc->sc_iface); 607 for (i = 0; i < id->bNumEndpoints; i++) { 608 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 609 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 610 continue; 611 612 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 613 sc->rxq.pipe_no = ed->bEndpointAddress; 614 nrx++; 615 } else if (ntx < RUN_MAXEPOUT) { 616 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 617 ntx++; 618 } 619 } 620 /* make sure we've got them all */ 621 if (nrx < 1 || ntx < RUN_MAXEPOUT) { 622 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 623 return; 624 } 625 626 usb_init_task(&sc->sc_task, run_task, sc, 0); 627 callout_init(&sc->scan_to, 0); 628 callout_setfunc(&sc->scan_to, run_next_scan, sc); 629 callout_init(&sc->calib_to, 0); 630 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 631 632 sc->amrr.amrr_min_success_threshold = 1; 633 sc->amrr.amrr_max_success_threshold = 10; 634 635 /* wait for the chip to settle */ 636 for (ntries = 0; ntries < 100; ntries++) { 637 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 638 return; 639 if (ver != 0 && ver != 0xffffffff) 640 break; 641 DELAY(10); 642 } 643 if (ntries == 100) { 644 aprint_error_dev(sc->sc_dev, 645 "timeout waiting for NIC to initialize\n"); 646 return; 647 } 648 sc->mac_ver = ver >> 16; 649 sc->mac_rev = ver & 0xffff; 650 651 /* retrieve RF rev. no and various other things from EEPROM */ 652 run_read_eeprom(sc); 653 654 aprint_verbose_dev(sc->sc_dev, 655 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 656 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 657 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 658 659 ic->ic_ifp = ifp; 660 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 661 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 662 ic->ic_state = IEEE80211_S_INIT; 663 664 /* set device capabilities */ 665 ic->ic_caps = 666 IEEE80211_C_MONITOR | /* monitor mode supported */ 667 #ifndef IEEE80211_STA_ONLY 668 IEEE80211_C_IBSS | /* IBSS mode supported */ 669 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 670 #endif 671 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 672 IEEE80211_C_SHSLOT | /* short slot time supported */ 673 #ifdef RUN_HWCRYPTO 674 IEEE80211_C_WEP | /* WEP */ 675 IEEE80211_C_TKIP | /* TKIP */ 676 IEEE80211_C_AES_CCM | /* AES CCMP */ 677 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 678 #endif 679 IEEE80211_C_WME | /* WME */ 680 IEEE80211_C_WPA; /* WPA/RSN */ 681 682 if (sc->rf_rev == RT2860_RF_2750 || 683 sc->rf_rev == RT2860_RF_2850 || 684 sc->rf_rev == RT3070_RF_3052 || 685 sc->rf_rev == RT3070_RF_3053 || 686 sc->rf_rev == RT5592_RF_5592) { 687 /* set supported .11a rates */ 688 ic->ic_sup_rates[IEEE80211_MODE_11A] = 689 ieee80211_std_rateset_11a; 690 691 /* set supported .11a channels */ 692 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 693 uint8_t chan = rt2860_rf2850[i].chan; 694 ic->ic_channels[chan].ic_freq = 695 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 696 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 697 } 698 } 699 700 /* set supported .11b and .11g rates */ 701 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 702 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 703 704 /* set supported .11b and .11g channels (1 through 14) */ 705 for (i = 1; i <= 14; i++) { 706 ic->ic_channels[i].ic_freq = 707 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 708 ic->ic_channels[i].ic_flags = 709 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 710 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 711 } 712 713 ifp->if_softc = sc; 714 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 715 ifp->if_init = run_init; 716 ifp->if_ioctl = run_ioctl; 717 ifp->if_start = run_start; 718 ifp->if_watchdog = run_watchdog; 719 IFQ_SET_READY(&ifp->if_snd); 720 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 721 722 if_attach(ifp); 723 ieee80211_ifattach(ic); 724 ic->ic_node_alloc = run_node_alloc; 725 ic->ic_newassoc = run_newassoc; 726 ic->ic_updateslot = run_updateslot; 727 ic->ic_wme.wme_update = run_updateedca; 728 #ifdef RUN_HWCRYPTO 729 ic->ic_crypto.cs_key_set = run_set_key; 730 ic->ic_crypto.cs_key_delete = run_delete_key; 731 #endif 732 /* override state transition machine */ 733 sc->sc_newstate = ic->ic_newstate; 734 ic->ic_newstate = run_newstate; 735 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 736 737 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 738 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 739 &sc->sc_drvbpf); 740 741 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 742 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 743 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 744 745 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 746 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 747 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 748 749 ieee80211_announce(ic); 750 751 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 752 753 if (!pmf_device_register(self, NULL, NULL)) 754 aprint_error_dev(self, "couldn't establish power handler\n"); 755 } 756 757 static int 758 run_detach(device_t self, int flags) 759 { 760 struct run_softc *sc = device_private(self); 761 struct ifnet *ifp = &sc->sc_if; 762 struct ieee80211com *ic = &sc->sc_ic; 763 int s; 764 765 if (ifp->if_softc == NULL) 766 return 0; 767 768 pmf_device_deregister(self); 769 770 s = splusb(); 771 772 sc->sc_flags |= RUN_DETACHING; 773 774 if (ifp->if_flags & IFF_RUNNING) { 775 run_stop(ifp, 0); 776 callout_halt(&sc->scan_to, NULL); 777 callout_halt(&sc->calib_to, NULL); 778 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 779 NULL); 780 } 781 782 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 783 bpf_detach(ifp); 784 ieee80211_ifdetach(ic); 785 if_detach(ifp); 786 787 splx(s); 788 789 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 790 791 callout_stop(&sc->scan_to); 792 callout_stop(&sc->calib_to); 793 794 callout_destroy(&sc->scan_to); 795 callout_destroy(&sc->calib_to); 796 797 return 0; 798 } 799 800 static int 801 run_activate(device_t self, enum devact act) 802 { 803 struct run_softc *sc = device_private(self); 804 805 switch (act) { 806 case DVACT_DEACTIVATE: 807 if_deactivate(sc->sc_ic.ic_ifp); 808 return 0; 809 default: 810 return EOPNOTSUPP; 811 } 812 } 813 814 static int 815 run_alloc_rx_ring(struct run_softc *sc) 816 { 817 struct run_rx_ring *rxq = &sc->rxq; 818 int i, error; 819 820 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 821 if (error != 0) 822 goto fail; 823 824 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 825 struct run_rx_data *data = &rxq->data[i]; 826 827 data->sc = sc; /* backpointer for callbacks */ 828 829 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 830 0, 0, &data->xfer); 831 if (error) 832 goto fail; 833 834 data->buf = usbd_get_buffer(data->xfer); 835 } 836 if (error != 0) 837 fail: run_free_rx_ring(sc); 838 return error; 839 } 840 841 static void 842 run_free_rx_ring(struct run_softc *sc) 843 { 844 struct run_rx_ring *rxq = &sc->rxq; 845 int i; 846 847 if (rxq->pipeh != NULL) { 848 usbd_abort_pipe(rxq->pipeh); 849 } 850 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 851 if (rxq->data[i].xfer != NULL) 852 usbd_destroy_xfer(rxq->data[i].xfer); 853 rxq->data[i].xfer = NULL; 854 } 855 if (rxq->pipeh != NULL) { 856 usbd_close_pipe(rxq->pipeh); 857 rxq->pipeh = NULL; 858 } 859 } 860 861 static int 862 run_alloc_tx_ring(struct run_softc *sc, int qid) 863 { 864 struct run_tx_ring *txq = &sc->txq[qid]; 865 int i, error; 866 uint16_t txwisize; 867 868 txwisize = sizeof(struct rt2860_txwi); 869 if (sc->mac_ver == 0x5592) 870 txwisize += sizeof(uint32_t); 871 872 txq->cur = txq->queued = 0; 873 874 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 875 if (error != 0) 876 goto fail; 877 878 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 879 struct run_tx_data *data = &txq->data[i]; 880 881 data->sc = sc; /* backpointer for callbacks */ 882 data->qid = qid; 883 884 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 885 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 886 if (error) 887 goto fail; 888 889 data->buf = usbd_get_buffer(data->xfer); 890 /* zeroize the TXD + TXWI part */ 891 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 892 } 893 if (error != 0) 894 fail: run_free_tx_ring(sc, qid); 895 return error; 896 } 897 898 static void 899 run_free_tx_ring(struct run_softc *sc, int qid) 900 { 901 struct run_tx_ring *txq = &sc->txq[qid]; 902 int i; 903 904 if (txq->pipeh != NULL) { 905 usbd_abort_pipe(txq->pipeh); 906 usbd_close_pipe(txq->pipeh); 907 txq->pipeh = NULL; 908 } 909 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 910 if (txq->data[i].xfer != NULL) 911 usbd_destroy_xfer(txq->data[i].xfer); 912 txq->data[i].xfer = NULL; 913 } 914 } 915 916 static int 917 run_load_microcode(struct run_softc *sc) 918 { 919 usb_device_request_t req; 920 const char *fwname; 921 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 922 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 923 uint32_t tmp; 924 int ntries, error; 925 926 /* RT3071/RT3072 use a different firmware */ 927 if (sc->mac_ver != 0x2860 && 928 sc->mac_ver != 0x2872 && 929 sc->mac_ver != 0x3070) 930 fwname = "run-rt3071"; 931 else 932 fwname = "run-rt2870"; 933 934 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 935 device_printf(sc->sc_dev, 936 "error %d, could not read firmware %s\n", error, fwname); 937 return error; 938 } 939 if (size != 4096) { 940 device_printf(sc->sc_dev, 941 "invalid firmware size (should be 4KB)\n"); 942 firmware_free(ucode, size); 943 return EINVAL; 944 } 945 946 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 947 /* write microcode image */ 948 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 949 firmware_free(ucode, size); 950 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 951 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 952 953 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 954 req.bRequest = RT2870_RESET; 955 USETW(req.wValue, 8); 956 USETW(req.wIndex, 0); 957 USETW(req.wLength, 0); 958 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 959 return error; 960 961 usbd_delay_ms(sc->sc_udev, 10); 962 run_write(sc, RT2860_H2M_BBPAGENT, 0); 963 run_write(sc, RT2860_H2M_MAILBOX, 0); 964 run_write(sc, RT2860_H2M_INTSRC, 0); 965 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 966 return error; 967 968 /* wait until microcontroller is ready */ 969 for (ntries = 0; ntries < 1000; ntries++) { 970 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 971 return error; 972 if (tmp & RT2860_MCU_READY) 973 break; 974 usbd_delay_ms(sc->sc_udev, 10); 975 } 976 if (ntries == 1000) { 977 device_printf(sc->sc_dev, 978 "timeout waiting for MCU to initialize\n"); 979 return ETIMEDOUT; 980 } 981 982 sc->sc_flags |= RUN_FWLOADED; 983 984 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 985 return 0; 986 } 987 988 static int 989 run_reset(struct run_softc *sc) 990 { 991 usb_device_request_t req; 992 993 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 994 req.bRequest = RT2870_RESET; 995 USETW(req.wValue, 1); 996 USETW(req.wIndex, 0); 997 USETW(req.wLength, 0); 998 return usbd_do_request(sc->sc_udev, &req, NULL); 999 } 1000 1001 static int 1002 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 1003 { 1004 uint32_t tmp; 1005 int error; 1006 1007 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 1008 if (error == 0) 1009 *val = le32toh(tmp); 1010 else 1011 *val = 0xffffffff; 1012 return error; 1013 } 1014 1015 static int 1016 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 1017 { 1018 usb_device_request_t req; 1019 1020 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1021 req.bRequest = RT2870_READ_REGION_1; 1022 USETW(req.wValue, 0); 1023 USETW(req.wIndex, reg); 1024 USETW(req.wLength, len); 1025 return usbd_do_request(sc->sc_udev, &req, buf); 1026 } 1027 1028 static int 1029 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1030 { 1031 usb_device_request_t req; 1032 1033 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1034 req.bRequest = RT2870_WRITE_2; 1035 USETW(req.wValue, val); 1036 USETW(req.wIndex, reg); 1037 USETW(req.wLength, 0); 1038 return usbd_do_request(sc->sc_udev, &req, NULL); 1039 } 1040 1041 static int 1042 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1043 { 1044 int error; 1045 1046 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1047 error = run_write_2(sc, reg + 2, val >> 16); 1048 return error; 1049 } 1050 1051 static int 1052 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1053 int len) 1054 { 1055 #if 1 1056 int i, error = 0; 1057 /* 1058 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1059 * We thus issue multiple WRITE_2 commands instead. 1060 */ 1061 KASSERT((len & 1) == 0); 1062 for (i = 0; i < len && error == 0; i += 2) 1063 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1064 return error; 1065 #else 1066 usb_device_request_t req; 1067 1068 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1069 req.bRequest = RT2870_WRITE_REGION_1; 1070 USETW(req.wValue, 0); 1071 USETW(req.wIndex, reg); 1072 USETW(req.wLength, len); 1073 return usbd_do_request(sc->sc_udev, &req, buf); 1074 #endif 1075 } 1076 1077 static int 1078 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1079 { 1080 int error = 0; 1081 1082 for (; count > 0 && error == 0; count--, reg += 4) 1083 error = run_write(sc, reg, val); 1084 return error; 1085 } 1086 1087 static int 1088 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1089 { 1090 uint32_t tmp; 1091 uint16_t reg; 1092 int error, ntries; 1093 1094 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1095 return error; 1096 1097 if (count == 2) 1098 addr *= 2; 1099 /*- 1100 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1101 * DATA0: F E D C 1102 * DATA1: B A 9 8 1103 * DATA2: 7 6 5 4 1104 * DATA3: 3 2 1 0 1105 */ 1106 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1107 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1108 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1109 for (ntries = 0; ntries < 100; ntries++) { 1110 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1111 return error; 1112 if (!(tmp & RT3070_EFSROM_KICK)) 1113 break; 1114 usbd_delay_ms(sc->sc_udev, 2); 1115 } 1116 if (ntries == 100) 1117 return ETIMEDOUT; 1118 1119 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1120 *val = 0xffff; /* address not found */ 1121 return 0; 1122 } 1123 /* determine to which 32-bit register our 16-bit word belongs */ 1124 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1125 if ((error = run_read(sc, reg, &tmp)) != 0) 1126 return error; 1127 1128 tmp >>= (8 * (addr & 0x3)); 1129 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1130 return 0; 1131 } 1132 1133 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1134 static int 1135 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1136 { 1137 return run_efuse_read(sc, addr, val, 2); 1138 } 1139 1140 static int 1141 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1142 { 1143 usb_device_request_t req; 1144 uint16_t tmp; 1145 int error; 1146 1147 addr *= 2; 1148 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1149 req.bRequest = RT2870_EEPROM_READ; 1150 USETW(req.wValue, 0); 1151 USETW(req.wIndex, addr); 1152 USETW(req.wLength, sizeof(tmp)); 1153 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1154 if (error == 0) 1155 *val = le16toh(tmp); 1156 else 1157 *val = 0xffff; 1158 return error; 1159 } 1160 1161 static __inline int 1162 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1163 { 1164 1165 /* either eFUSE ROM or EEPROM */ 1166 return sc->sc_srom_read(sc, addr, val); 1167 } 1168 1169 static int 1170 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1171 { 1172 uint32_t tmp; 1173 int error, ntries; 1174 1175 for (ntries = 0; ntries < 10; ntries++) { 1176 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1177 return error; 1178 if (!(tmp & RT2860_RF_REG_CTRL)) 1179 break; 1180 } 1181 if (ntries == 10) 1182 return ETIMEDOUT; 1183 1184 /* RF registers are 24-bit on the RT2860 */ 1185 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1186 (val & 0x3fffff) << 2 | (reg & 3); 1187 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1188 } 1189 1190 static int 1191 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1192 { 1193 uint32_t tmp; 1194 int error, ntries; 1195 1196 for (ntries = 0; ntries < 100; ntries++) { 1197 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1198 return error; 1199 if (!(tmp & RT3070_RF_KICK)) 1200 break; 1201 } 1202 if (ntries == 100) 1203 return ETIMEDOUT; 1204 1205 tmp = RT3070_RF_KICK | reg << 8; 1206 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1207 return error; 1208 1209 for (ntries = 0; ntries < 100; ntries++) { 1210 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1211 return error; 1212 if (!(tmp & RT3070_RF_KICK)) 1213 break; 1214 } 1215 if (ntries == 100) 1216 return ETIMEDOUT; 1217 1218 *val = tmp & 0xff; 1219 return 0; 1220 } 1221 1222 static int 1223 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1224 { 1225 uint32_t tmp; 1226 int error, ntries; 1227 1228 for (ntries = 0; ntries < 10; ntries++) { 1229 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1230 return error; 1231 if (!(tmp & RT3070_RF_KICK)) 1232 break; 1233 } 1234 if (ntries == 10) 1235 return ETIMEDOUT; 1236 1237 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1238 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1239 } 1240 1241 static int 1242 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1243 { 1244 uint32_t tmp; 1245 int ntries, error; 1246 1247 for (ntries = 0; ntries < 10; ntries++) { 1248 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1249 return error; 1250 if (!(tmp & RT2860_BBP_CSR_KICK)) 1251 break; 1252 } 1253 if (ntries == 10) 1254 return ETIMEDOUT; 1255 1256 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1257 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1258 return error; 1259 1260 for (ntries = 0; ntries < 10; ntries++) { 1261 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1262 return error; 1263 if (!(tmp & RT2860_BBP_CSR_KICK)) 1264 break; 1265 } 1266 if (ntries == 10) 1267 return ETIMEDOUT; 1268 1269 *val = tmp & 0xff; 1270 return 0; 1271 } 1272 1273 static int 1274 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1275 { 1276 uint32_t tmp; 1277 int ntries, error; 1278 1279 for (ntries = 0; ntries < 10; ntries++) { 1280 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1281 return error; 1282 if (!(tmp & RT2860_BBP_CSR_KICK)) 1283 break; 1284 } 1285 if (ntries == 10) 1286 return ETIMEDOUT; 1287 1288 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1289 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1290 } 1291 1292 /* 1293 * Send a command to the 8051 microcontroller unit. 1294 */ 1295 static int 1296 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1297 { 1298 uint32_t tmp; 1299 int error, ntries; 1300 1301 for (ntries = 0; ntries < 100; ntries++) { 1302 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1303 return error; 1304 if (!(tmp & RT2860_H2M_BUSY)) 1305 break; 1306 } 1307 if (ntries == 100) 1308 return ETIMEDOUT; 1309 1310 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1311 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1312 error = run_write(sc, RT2860_HOST_CMD, cmd); 1313 return error; 1314 } 1315 1316 /* 1317 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1318 * Used to adjust per-rate Tx power registers. 1319 */ 1320 static __inline uint32_t 1321 b4inc(uint32_t b32, int8_t delta) 1322 { 1323 int8_t i, b4; 1324 1325 for (i = 0; i < 8; i++) { 1326 b4 = b32 & 0xf; 1327 b4 += delta; 1328 if (b4 < 0) 1329 b4 = 0; 1330 else if (b4 > 0xf) 1331 b4 = 0xf; 1332 b32 = b32 >> 4 | b4 << 28; 1333 } 1334 return b32; 1335 } 1336 1337 static const char * 1338 run_get_rf(uint16_t rev) 1339 { 1340 switch (rev) { 1341 case RT2860_RF_2820: return "RT2820"; 1342 case RT2860_RF_2850: return "RT2850"; 1343 case RT2860_RF_2720: return "RT2720"; 1344 case RT2860_RF_2750: return "RT2750"; 1345 case RT3070_RF_3020: return "RT3020"; 1346 case RT3070_RF_2020: return "RT2020"; 1347 case RT3070_RF_3021: return "RT3021"; 1348 case RT3070_RF_3022: return "RT3022"; 1349 case RT3070_RF_3052: return "RT3052"; 1350 case RT3070_RF_3053: return "RT3053"; 1351 case RT5592_RF_5592: return "RT5592"; 1352 case RT5390_RF_5370: return "RT5370"; 1353 case RT5390_RF_5372: return "RT5372"; 1354 } 1355 return "unknown"; 1356 } 1357 1358 static void 1359 run_rt3593_get_txpower(struct run_softc *sc) 1360 { 1361 uint16_t addr, val; 1362 int i; 1363 1364 /* Read power settings for 2GHz channels. */ 1365 for (i = 0; i < 14; i += 2) { 1366 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1367 RT2860_EEPROM_PWR2GHZ_BASE1; 1368 run_srom_read(sc, addr + i / 2, &val); 1369 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1370 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1371 1372 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1373 RT2860_EEPROM_PWR2GHZ_BASE2; 1374 run_srom_read(sc, addr + i / 2, &val); 1375 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1376 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1377 1378 if (sc->ntxchains == 3) { 1379 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1380 &val); 1381 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1382 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1383 } 1384 } 1385 /* Fix broken Tx power entries. */ 1386 for (i = 0; i < 14; i++) { 1387 if (sc->txpow1[i] > 31) 1388 sc->txpow1[i] = 5; 1389 if (sc->txpow2[i] > 31) 1390 sc->txpow2[i] = 5; 1391 if (sc->ntxchains == 3) { 1392 if (sc->txpow3[i] > 31) 1393 sc->txpow3[i] = 5; 1394 } 1395 } 1396 /* Read power settings for 5GHz channels. */ 1397 for (i = 0; i < 40; i += 2) { 1398 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1399 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1400 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1401 1402 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1403 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1404 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1405 1406 if (sc->ntxchains == 3) { 1407 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1408 &val); 1409 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1410 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1411 } 1412 } 1413 } 1414 1415 static void 1416 run_get_txpower(struct run_softc *sc) 1417 { 1418 uint16_t val; 1419 int i; 1420 1421 /* Read power settings for 2GHz channels. */ 1422 for (i = 0; i < 14; i += 2) { 1423 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1424 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1425 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1426 1427 if (sc->mac_ver != 0x5390) { 1428 run_srom_read(sc, 1429 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1430 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1431 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1432 } 1433 } 1434 /* Fix broken Tx power entries. */ 1435 for (i = 0; i < 14; i++) { 1436 if (sc->mac_ver >= 0x5390) { 1437 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1438 sc->txpow1[i] = 5; 1439 } else { 1440 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1441 sc->txpow1[i] = 5; 1442 } 1443 if (sc->mac_ver > 0x5390) { 1444 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1445 sc->txpow2[i] = 5; 1446 } else if (sc->mac_ver < 0x5390) { 1447 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1448 sc->txpow2[i] = 5; 1449 } 1450 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1451 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1452 } 1453 /* Read power settings for 5GHz channels. */ 1454 for (i = 0; i < 40; i += 2) { 1455 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1456 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1457 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1458 1459 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1460 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1461 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1462 } 1463 /* Fix broken Tx power entries. */ 1464 for (i = 0; i < 40; i++ ) { 1465 if (sc->mac_ver != 0x5592) { 1466 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1467 sc->txpow1[14 + i] = 5; 1468 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1469 sc->txpow2[14 + i] = 5; 1470 } 1471 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1472 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1473 sc->txpow2[14 + i])); 1474 } 1475 } 1476 1477 static int 1478 run_read_eeprom(struct run_softc *sc) 1479 { 1480 struct ieee80211com *ic = &sc->sc_ic; 1481 int8_t delta_2ghz, delta_5ghz; 1482 uint32_t tmp; 1483 uint16_t val; 1484 int ridx, ant, i; 1485 1486 /* check whether the ROM is eFUSE ROM or EEPROM */ 1487 sc->sc_srom_read = run_eeprom_read_2; 1488 if (sc->mac_ver >= 0x3070) { 1489 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1490 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1491 if (tmp & RT3070_SEL_EFUSE) 1492 sc->sc_srom_read = run_efuse_read_2; 1493 } 1494 1495 /* read ROM version */ 1496 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1497 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1498 1499 /* read MAC address */ 1500 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1501 ic->ic_myaddr[0] = val & 0xff; 1502 ic->ic_myaddr[1] = val >> 8; 1503 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1504 ic->ic_myaddr[2] = val & 0xff; 1505 ic->ic_myaddr[3] = val >> 8; 1506 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1507 ic->ic_myaddr[4] = val & 0xff; 1508 ic->ic_myaddr[5] = val >> 8; 1509 1510 if (sc->mac_ver < 0x3593) { 1511 /* read vendor BBP settings */ 1512 for (i = 0; i < 10; i++) { 1513 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1514 sc->bbp[i].val = val & 0xff; 1515 sc->bbp[i].reg = val >> 8; 1516 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1517 sc->bbp[i].val)); 1518 } 1519 1520 if (sc->mac_ver >= 0x3071) { 1521 /* read vendor RF settings */ 1522 for (i = 0; i < 8; i++) { 1523 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1524 &val); 1525 sc->rf[i].val = val & 0xff; 1526 sc->rf[i].reg = val >> 8; 1527 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1528 sc->rf[i].val)); 1529 } 1530 } 1531 } 1532 1533 /* read RF frequency offset from EEPROM */ 1534 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1535 RT3593_EEPROM_FREQ, &val); 1536 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1537 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1538 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1539 RT3593_EEPROM_FREQ, &val); 1540 if ((val >> 8) != 0xff) { 1541 /* read LEDs operating mode */ 1542 sc->leds = val >> 8; 1543 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1544 RT3593_EEPROM_LED1, &sc->led[0]); 1545 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1546 RT3593_EEPROM_LED2, &sc->led[1]); 1547 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1548 RT3593_EEPROM_LED3, &sc->led[2]); 1549 } else { 1550 /* broken EEPROM, use default settings */ 1551 sc->leds = 0x01; 1552 sc->led[0] = 0x5555; 1553 sc->led[1] = 0x2221; 1554 sc->led[2] = 0x5627; /* differs from RT2860 */ 1555 } 1556 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1557 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1558 1559 /* read RF information */ 1560 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1561 run_srom_read(sc, 0x00, &val); 1562 else 1563 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1564 if (val == 0xffff) { 1565 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1566 if (sc->mac_ver == 0x3572) { 1567 /* default to RF3052 2T2R */ 1568 sc->rf_rev = RT3070_RF_3052; 1569 sc->ntxchains = 2; 1570 sc->nrxchains = 2; 1571 } else if (sc->mac_ver >= 0x3070) { 1572 /* default to RF3020 1T1R */ 1573 sc->rf_rev = RT3070_RF_3020; 1574 sc->ntxchains = 1; 1575 sc->nrxchains = 1; 1576 } else { 1577 /* default to RF2820 1T2R */ 1578 sc->rf_rev = RT2860_RF_2820; 1579 sc->ntxchains = 1; 1580 sc->nrxchains = 2; 1581 } 1582 } else { 1583 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1584 sc->rf_rev = val; 1585 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1586 } else 1587 sc->rf_rev = (val >> 8) & 0xf; 1588 sc->ntxchains = (val >> 4) & 0xf; 1589 sc->nrxchains = val & 0xf; 1590 } 1591 DPRINTF(("EEPROM RF rev=0x%04x chains=%dT%dR\n", 1592 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1593 1594 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1595 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1596 /* check if driver should patch the DAC issue */ 1597 if ((val >> 8) != 0xff) 1598 sc->patch_dac = (val >> 15) & 1; 1599 if ((val & 0xff) != 0xff) { 1600 sc->ext_5ghz_lna = (val >> 3) & 1; 1601 sc->ext_2ghz_lna = (val >> 2) & 1; 1602 /* check if RF supports automatic Tx access gain control */ 1603 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1604 /* check if we have a hardware radio switch */ 1605 sc->rfswitch = val & 1; 1606 } 1607 1608 /* Read Tx power settings. */ 1609 if (sc->mac_ver == 0x3593) 1610 run_rt3593_get_txpower(sc); 1611 else 1612 run_get_txpower(sc); 1613 1614 /* read Tx power compensation for each Tx rate */ 1615 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1616 delta_2ghz = delta_5ghz = 0; 1617 if ((val & 0xff) != 0xff && (val & 0x80)) { 1618 delta_2ghz = val & 0xf; 1619 if (!(val & 0x40)) /* negative number */ 1620 delta_2ghz = -delta_2ghz; 1621 } 1622 val >>= 8; 1623 if ((val & 0xff) != 0xff && (val & 0x80)) { 1624 delta_5ghz = val & 0xf; 1625 if (!(val & 0x40)) /* negative number */ 1626 delta_5ghz = -delta_5ghz; 1627 } 1628 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1629 delta_2ghz, delta_5ghz)); 1630 1631 for (ridx = 0; ridx < 5; ridx++) { 1632 uint32_t reg; 1633 1634 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1635 reg = val; 1636 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1637 reg |= (uint32_t)val << 16; 1638 1639 sc->txpow20mhz[ridx] = reg; 1640 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1641 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1642 1643 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1644 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1645 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1646 } 1647 1648 DPRINTF(("mac_ver %hx\n", sc->mac_ver)); 1649 /* read RSSI offsets and LNA gains from EEPROM */ 1650 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1651 RT3593_EEPROM_RSSI1_2GHZ, &val); 1652 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1653 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1654 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1655 RT3593_EEPROM_RSSI2_2GHZ, &val); 1656 if (sc->mac_ver >= 0x3070) { 1657 if (sc->mac_ver == 0x3593) { 1658 sc->txmixgain_2ghz = 0; 1659 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1660 } else { 1661 /* 1662 * On RT3070 chips (limited to 2 Rx chains), this ROM 1663 * field contains the Tx mixer gain for the 2GHz band. 1664 */ 1665 if ((val & 0xff) != 0xff) 1666 sc->txmixgain_2ghz = val & 0x7; 1667 } 1668 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1669 } else { 1670 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1671 } 1672 if (sc->mac_ver == 0x3593) 1673 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1674 sc->lna[2] = val >> 8; /* channel group 2 */ 1675 1676 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1677 RT3593_EEPROM_RSSI1_5GHZ, &val); 1678 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1679 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1680 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1681 RT3593_EEPROM_RSSI2_5GHZ, &val); 1682 if (sc->mac_ver == 0x3572) { 1683 /* 1684 * On RT3572 chips (limited to 2 Rx chains), this ROM 1685 * field contains the Tx mixer gain for the 5GHz band. 1686 */ 1687 if ((val & 0xff) != 0xff) 1688 sc->txmixgain_5ghz = val & 0x7; 1689 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1690 } else { 1691 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1692 } 1693 if (sc->mac_ver == 0x3593) { 1694 sc->txmixgain_5ghz = 0; 1695 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1696 } 1697 sc->lna[3] = val >> 8; /* channel group 3 */ 1698 1699 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1700 RT3593_EEPROM_LNA, &val); 1701 sc->lna[0] = val & 0xff; /* channel group 0 */ 1702 sc->lna[1] = val >> 8; /* channel group 1 */ 1703 1704 /* fix broken 5GHz LNA entries */ 1705 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1706 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1707 sc->lna[2] = sc->lna[1]; 1708 } 1709 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1710 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1711 sc->lna[3] = sc->lna[1]; 1712 } 1713 1714 /* fix broken RSSI offset entries */ 1715 for (ant = 0; ant < 3; ant++) { 1716 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1717 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1718 ant + 1, sc->rssi_2ghz[ant])); 1719 sc->rssi_2ghz[ant] = 0; 1720 } 1721 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1722 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1723 ant + 1, sc->rssi_5ghz[ant])); 1724 sc->rssi_5ghz[ant] = 0; 1725 } 1726 } 1727 return 0; 1728 } 1729 1730 static struct ieee80211_node * 1731 run_node_alloc(struct ieee80211_node_table *nt) 1732 { 1733 struct run_node *rn = 1734 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1735 return rn ? &rn->ni : NULL; 1736 } 1737 1738 static int 1739 run_media_change(struct ifnet *ifp) 1740 { 1741 struct run_softc *sc = ifp->if_softc; 1742 struct ieee80211com *ic = &sc->sc_ic; 1743 uint8_t rate, ridx; 1744 int error; 1745 1746 error = ieee80211_media_change(ifp); 1747 if (error != ENETRESET) 1748 return error; 1749 1750 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1751 rate = ic->ic_sup_rates[ic->ic_curmode]. 1752 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1753 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1754 if (rt2860_rates[ridx].rate == rate) 1755 break; 1756 sc->fixed_ridx = ridx; 1757 } 1758 1759 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1760 run_init(ifp); 1761 1762 return 0; 1763 } 1764 1765 static void 1766 run_next_scan(void *arg) 1767 { 1768 struct run_softc *sc = arg; 1769 1770 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1771 ieee80211_next_scan(&sc->sc_ic); 1772 } 1773 1774 static void 1775 run_task(void *arg) 1776 { 1777 struct run_softc *sc = arg; 1778 struct run_host_cmd_ring *ring = &sc->cmdq; 1779 struct run_host_cmd *cmd; 1780 int s; 1781 1782 /* process host commands */ 1783 s = splusb(); 1784 while (ring->next != ring->cur) { 1785 cmd = &ring->cmd[ring->next]; 1786 splx(s); 1787 /* callback */ 1788 cmd->cb(sc, cmd->data); 1789 s = splusb(); 1790 ring->queued--; 1791 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1792 } 1793 wakeup(ring); 1794 splx(s); 1795 } 1796 1797 static void 1798 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1799 void *arg, int len) 1800 { 1801 struct run_host_cmd_ring *ring = &sc->cmdq; 1802 struct run_host_cmd *cmd; 1803 int s; 1804 1805 if (sc->sc_flags & RUN_DETACHING) 1806 return; 1807 1808 s = splusb(); 1809 cmd = &ring->cmd[ring->cur]; 1810 cmd->cb = cb; 1811 KASSERT(len <= sizeof(cmd->data)); 1812 memcpy(cmd->data, arg, len); 1813 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1814 1815 /* if there is no pending command already, schedule a task */ 1816 if (++ring->queued == 1) 1817 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1818 splx(s); 1819 } 1820 1821 static int 1822 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1823 { 1824 struct run_softc *sc = ic->ic_ifp->if_softc; 1825 struct run_cmd_newstate cmd; 1826 1827 callout_stop(&sc->scan_to); 1828 callout_stop(&sc->calib_to); 1829 1830 /* do it in a process context */ 1831 cmd.state = nstate; 1832 cmd.arg = arg; 1833 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1834 return 0; 1835 } 1836 1837 static void 1838 run_newstate_cb(struct run_softc *sc, void *arg) 1839 { 1840 struct run_cmd_newstate *cmd = arg; 1841 struct ifnet *ifp = &sc->sc_if; 1842 struct ieee80211com *ic = &sc->sc_ic; 1843 enum ieee80211_state ostate; 1844 struct ieee80211_node *ni; 1845 uint32_t tmp, sta[3]; 1846 uint8_t wcid; 1847 int s; 1848 1849 s = splnet(); 1850 ostate = ic->ic_state; 1851 1852 if (ostate == IEEE80211_S_RUN) { 1853 /* turn link LED off */ 1854 run_set_leds(sc, RT2860_LED_RADIO); 1855 } 1856 1857 switch (cmd->state) { 1858 case IEEE80211_S_INIT: 1859 if (ostate == IEEE80211_S_RUN) { 1860 /* abort TSF synchronization */ 1861 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1862 run_write(sc, RT2860_BCN_TIME_CFG, 1863 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1864 RT2860_TBTT_TIMER_EN)); 1865 } 1866 break; 1867 1868 case IEEE80211_S_SCAN: 1869 run_set_chan(sc, ic->ic_curchan); 1870 callout_schedule(&sc->scan_to, hz / 5); 1871 break; 1872 1873 case IEEE80211_S_AUTH: 1874 case IEEE80211_S_ASSOC: 1875 run_set_chan(sc, ic->ic_curchan); 1876 break; 1877 1878 case IEEE80211_S_RUN: 1879 run_set_chan(sc, ic->ic_curchan); 1880 1881 ni = ic->ic_bss; 1882 1883 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1884 run_updateslot(ifp); 1885 run_enable_mrr(sc); 1886 run_set_txpreamble(sc); 1887 run_set_basicrates(sc); 1888 run_set_bssid(sc, ni->ni_bssid); 1889 } 1890 #ifndef IEEE80211_STA_ONLY 1891 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1892 ic->ic_opmode == IEEE80211_M_IBSS) 1893 (void)run_setup_beacon(sc); 1894 #endif 1895 if (ic->ic_opmode == IEEE80211_M_STA) { 1896 /* add BSS entry to the WCID table */ 1897 wcid = RUN_AID2WCID(ni->ni_associd); 1898 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1899 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1900 1901 /* fake a join to init the tx rate */ 1902 run_newassoc(ni, 1); 1903 } 1904 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1905 run_enable_tsf_sync(sc); 1906 1907 /* clear statistic registers used by AMRR */ 1908 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1909 (uint8_t *)sta, sizeof(sta)); 1910 /* start calibration timer */ 1911 callout_schedule(&sc->calib_to, hz); 1912 } 1913 1914 /* turn link LED on */ 1915 run_set_leds(sc, RT2860_LED_RADIO | 1916 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1917 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1918 break; 1919 } 1920 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1921 splx(s); 1922 } 1923 1924 static int 1925 run_updateedca(struct ieee80211com *ic) 1926 { 1927 1928 /* do it in a process context */ 1929 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1930 return 0; 1931 } 1932 1933 /* ARGSUSED */ 1934 static void 1935 run_updateedca_cb(struct run_softc *sc, void *arg) 1936 { 1937 struct ieee80211com *ic = &sc->sc_ic; 1938 int s, aci; 1939 1940 s = splnet(); 1941 /* update MAC TX configuration registers */ 1942 for (aci = 0; aci < WME_NUM_AC; aci++) { 1943 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1944 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1945 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1946 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1947 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1948 } 1949 1950 /* update SCH/DMA registers too */ 1951 run_write(sc, RT2860_WMM_AIFSN_CFG, 1952 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1953 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1954 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1955 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1956 run_write(sc, RT2860_WMM_CWMIN_CFG, 1957 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1958 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1959 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1960 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1961 run_write(sc, RT2860_WMM_CWMAX_CFG, 1962 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1963 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1964 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1965 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1966 run_write(sc, RT2860_WMM_TXOP0_CFG, 1967 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1968 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1969 run_write(sc, RT2860_WMM_TXOP1_CFG, 1970 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1971 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1972 splx(s); 1973 } 1974 1975 #ifdef RUN_HWCRYPTO 1976 static int 1977 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1978 const uint8_t *mac) 1979 { 1980 struct run_softc *sc = ic->ic_ifp->if_softc; 1981 struct ieee80211_node *ni = ic->ic_bss; 1982 struct run_cmd_key cmd; 1983 1984 /* do it in a process context */ 1985 cmd.key = *k; 1986 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1987 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1988 return 1; 1989 } 1990 1991 static void 1992 run_set_key_cb(struct run_softc *sc, void *arg) 1993 { 1994 #ifndef IEEE80211_STA_ONLY 1995 struct ieee80211com *ic = &sc->sc_ic; 1996 #endif 1997 struct run_cmd_key *cmd = arg; 1998 struct ieee80211_key *k = &cmd->key; 1999 uint32_t attr; 2000 uint16_t base; 2001 uint8_t mode, wcid, iv[8]; 2002 2003 /* map net80211 cipher to RT2860 security mode */ 2004 switch (k->wk_cipher->ic_cipher) { 2005 case IEEE80211_CIPHER_WEP: 2006 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2007 if (k->wk_keylen == 5) 2008 mode = RT2860_MODE_WEP40; 2009 else 2010 mode = RT2860_MODE_WEP104; 2011 break; 2012 case IEEE80211_CIPHER_TKIP: 2013 mode = RT2860_MODE_TKIP; 2014 break; 2015 case IEEE80211_CIPHER_AES_CCM: 2016 mode = RT2860_MODE_AES_CCMP; 2017 break; 2018 default: 2019 return; 2020 } 2021 2022 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2023 wcid = 0; /* NB: update WCID0 for group keys */ 2024 base = RT2860_SKEY(0, k->wk_keyix); 2025 } else { 2026 wcid = RUN_AID2WCID(cmd->associd); 2027 base = RT2860_PKEY(wcid); 2028 } 2029 2030 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2031 run_write_region_1(sc, base, k->wk_key, 16); 2032 #ifndef IEEE80211_STA_ONLY 2033 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2034 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 2035 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 2036 } else 2037 #endif 2038 { 2039 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 2040 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 2041 } 2042 } else { 2043 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2044 run_write_region_1(sc, base, k->wk_key, 2045 (k->wk_keylen + 1) & ~1); 2046 } 2047 2048 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2049 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2050 /* set initial packet number in IV+EIV */ 2051 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2052 memset(iv, 0, sizeof(iv)); 2053 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2054 } else { 2055 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2056 iv[0] = k->wk_keytsc >> 8; 2057 iv[1] = (iv[0] | 0x20) & 0x7f; 2058 iv[2] = k->wk_keytsc; 2059 } else /* CCMP */ { 2060 iv[0] = k->wk_keytsc; 2061 iv[1] = k->wk_keytsc >> 8; 2062 iv[2] = 0; 2063 } 2064 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2065 iv[4] = k->wk_keytsc >> 16; 2066 iv[5] = k->wk_keytsc >> 24; 2067 iv[6] = k->wk_keytsc >> 32; 2068 iv[7] = k->wk_keytsc >> 40; 2069 } 2070 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2071 } 2072 2073 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2074 /* install group key */ 2075 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2076 attr &= ~(0xf << (k->wk_keyix * 4)); 2077 attr |= mode << (k->wk_keyix * 4); 2078 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2079 } else { 2080 /* install pairwise key */ 2081 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2082 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2083 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2084 } 2085 } 2086 2087 static int 2088 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2089 { 2090 struct run_softc *sc = ic->ic_ifp->if_softc; 2091 struct ieee80211_node *ni = ic->ic_bss; 2092 struct run_cmd_key cmd; 2093 2094 /* do it in a process context */ 2095 cmd.key = *k; 2096 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2097 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2098 return 1; 2099 } 2100 2101 static void 2102 run_delete_key_cb(struct run_softc *sc, void *arg) 2103 { 2104 struct run_cmd_key *cmd = arg; 2105 struct ieee80211_key *k = &cmd->key; 2106 uint32_t attr; 2107 uint8_t wcid; 2108 2109 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2110 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2111 2112 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2113 /* remove group key */ 2114 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2115 attr &= ~(0xf << (k->wk_keyix * 4)); 2116 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2117 2118 } else { 2119 /* remove pairwise key */ 2120 wcid = RUN_AID2WCID(cmd->associd); 2121 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2122 attr &= ~0xf; 2123 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2124 } 2125 } 2126 #endif 2127 2128 static void 2129 run_calibrate_to(void *arg) 2130 { 2131 2132 /* do it in a process context */ 2133 run_do_async(arg, run_calibrate_cb, NULL, 0); 2134 /* next timeout will be rescheduled in the calibration task */ 2135 } 2136 2137 /* ARGSUSED */ 2138 static void 2139 run_calibrate_cb(struct run_softc *sc, void *arg) 2140 { 2141 struct ifnet *ifp = &sc->sc_if; 2142 uint32_t sta[3]; 2143 int s, error; 2144 2145 /* read statistic counters (clear on read) and update AMRR state */ 2146 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2147 sizeof(sta)); 2148 if (error != 0) 2149 goto skip; 2150 2151 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2152 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2153 le32toh(sta[0]) & 0xffff)); 2154 2155 s = splnet(); 2156 /* count failed TX as errors */ 2157 ifp->if_oerrors += le32toh(sta[0]) & 0xffff; 2158 2159 sc->amn.amn_retrycnt = 2160 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2161 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2162 2163 sc->amn.amn_txcnt = 2164 sc->amn.amn_retrycnt + 2165 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2166 2167 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2168 splx(s); 2169 2170 skip: callout_schedule(&sc->calib_to, hz); 2171 } 2172 2173 static void 2174 run_newassoc(struct ieee80211_node *ni, int isnew) 2175 { 2176 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2177 struct run_node *rn = (void *)ni; 2178 struct ieee80211_rateset *rs = &ni->ni_rates; 2179 uint8_t rate; 2180 int ridx, i, j; 2181 2182 DPRINTF(("new assoc isnew=%d addr=%s\n", 2183 isnew, ether_sprintf(ni->ni_macaddr))); 2184 2185 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2186 /* start at lowest available bit-rate, AMRR will raise */ 2187 ni->ni_txrate = 0; 2188 2189 for (i = 0; i < rs->rs_nrates; i++) { 2190 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2191 /* convert 802.11 rate to hardware rate index */ 2192 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2193 if (rt2860_rates[ridx].rate == rate) 2194 break; 2195 rn->ridx[i] = ridx; 2196 /* determine rate of control response frames */ 2197 for (j = i; j >= 0; j--) { 2198 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2199 rt2860_rates[rn->ridx[i]].phy == 2200 rt2860_rates[rn->ridx[j]].phy) 2201 break; 2202 } 2203 if (j >= 0) { 2204 rn->ctl_ridx[i] = rn->ridx[j]; 2205 } else { 2206 /* no basic rate found, use mandatory one */ 2207 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2208 } 2209 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2210 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2211 } 2212 } 2213 2214 /* 2215 * Return the Rx chain with the highest RSSI for a given frame. 2216 */ 2217 static __inline uint8_t 2218 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2219 { 2220 uint8_t rxchain = 0; 2221 2222 if (sc->nrxchains > 1) { 2223 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2224 rxchain = 1; 2225 if (sc->nrxchains > 2) 2226 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2227 rxchain = 2; 2228 } 2229 return rxchain; 2230 } 2231 2232 static void 2233 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2234 { 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 struct ifnet *ifp = &sc->sc_if; 2237 struct ieee80211_frame *wh; 2238 struct ieee80211_node *ni; 2239 struct rt2870_rxd *rxd; 2240 struct rt2860_rxwi *rxwi; 2241 struct mbuf *m; 2242 uint32_t flags; 2243 uint16_t len, rxwisize, phy; 2244 uint8_t ant, rssi; 2245 int s; 2246 #ifdef RUN_HWCRYPTO 2247 int decrypted = 0; 2248 #endif 2249 2250 rxwi = (struct rt2860_rxwi *)buf; 2251 rxwisize = sizeof(struct rt2860_rxwi); 2252 if (sc->mac_ver == 0x5592) 2253 rxwisize += sizeof(uint64_t); 2254 else if (sc->mac_ver == 0x3593) 2255 rxwisize += sizeof(uint32_t); 2256 len = le16toh(rxwi->len) & 0xfff; 2257 if (__predict_false(len > dmalen)) { 2258 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2259 return; 2260 } 2261 /* Rx descriptor is located at the end */ 2262 rxd = (struct rt2870_rxd *)(buf + dmalen); 2263 flags = le32toh(rxd->flags); 2264 2265 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2266 ifp->if_ierrors++; 2267 return; 2268 } 2269 2270 wh = (struct ieee80211_frame *)(buf + rxwisize); 2271 2272 if (__predict_false((flags & RT2860_RX_MICERR))) { 2273 /* report MIC failures to net80211 for TKIP */ 2274 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2275 ifp->if_ierrors++; 2276 return; 2277 } 2278 2279 if (flags & RT2860_RX_L2PAD) { 2280 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2281 memmove((uint8_t *)wh + 2, wh, hdrlen); 2282 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2283 } 2284 2285 #ifdef RUN_HWCRYPTO 2286 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2287 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2288 decrypted = 1; 2289 } 2290 #endif 2291 2292 /* could use m_devget but net80211 wants contig mgmt frames */ 2293 MGETHDR(m, M_DONTWAIT, MT_DATA); 2294 if (__predict_false(m == NULL)) { 2295 ifp->if_ierrors++; 2296 return; 2297 } 2298 if (len > MHLEN) { 2299 MCLGET(m, M_DONTWAIT); 2300 if (__predict_false(!(m->m_flags & M_EXT))) { 2301 ifp->if_ierrors++; 2302 m_freem(m); 2303 return; 2304 } 2305 } 2306 /* finalize mbuf */ 2307 m_set_rcvif(m, ifp); 2308 memcpy(mtod(m, void *), wh, len); 2309 m->m_pkthdr.len = m->m_len = len; 2310 2311 ant = run_maxrssi_chain(sc, rxwi); 2312 rssi = rxwi->rssi[ant]; 2313 2314 if (__predict_false(sc->sc_drvbpf != NULL)) { 2315 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2316 2317 tap->wr_flags = 0; 2318 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2319 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2320 tap->wr_antsignal = rssi; 2321 tap->wr_antenna = ant; 2322 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2323 tap->wr_rate = 2; /* in case it can't be found below */ 2324 phy = le16toh(rxwi->phy); 2325 switch (phy & RT2860_PHY_MODE) { 2326 case RT2860_PHY_CCK: 2327 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2328 case 0: tap->wr_rate = 2; break; 2329 case 1: tap->wr_rate = 4; break; 2330 case 2: tap->wr_rate = 11; break; 2331 case 3: tap->wr_rate = 22; break; 2332 } 2333 if (phy & RT2860_PHY_SHPRE) 2334 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2335 break; 2336 case RT2860_PHY_OFDM: 2337 switch (phy & RT2860_PHY_MCS) { 2338 case 0: tap->wr_rate = 12; break; 2339 case 1: tap->wr_rate = 18; break; 2340 case 2: tap->wr_rate = 24; break; 2341 case 3: tap->wr_rate = 36; break; 2342 case 4: tap->wr_rate = 48; break; 2343 case 5: tap->wr_rate = 72; break; 2344 case 6: tap->wr_rate = 96; break; 2345 case 7: tap->wr_rate = 108; break; 2346 } 2347 break; 2348 } 2349 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2350 } 2351 2352 s = splnet(); 2353 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2354 #ifdef RUN_HWCRYPTO 2355 if (decrypted) { 2356 uint32_t icflags = ic->ic_flags; 2357 2358 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2359 ieee80211_input(ic, m, ni, rssi, 0); 2360 ic->ic_flags = icflags; 2361 } else 2362 #endif 2363 ieee80211_input(ic, m, ni, rssi, 0); 2364 2365 /* node is no longer needed */ 2366 ieee80211_free_node(ni); 2367 2368 /* 2369 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2370 * without calling if_start(). 2371 */ 2372 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2373 run_start(ifp); 2374 2375 splx(s); 2376 } 2377 2378 static void 2379 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2380 { 2381 struct run_rx_data *data = priv; 2382 struct run_softc *sc = data->sc; 2383 uint8_t *buf; 2384 uint32_t dmalen; 2385 int xferlen; 2386 uint16_t rxwisize; 2387 2388 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2389 return; 2390 2391 rxwisize = sizeof(struct rt2860_rxwi); 2392 if (sc->mac_ver == 0x5592) 2393 rxwisize += sizeof(uint64_t); 2394 else if (sc->mac_ver == 0x3593) 2395 rxwisize += sizeof(uint32_t); 2396 2397 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2398 DPRINTF(("RX status=%s\n", usbd_errstr(status))); 2399 if (status == USBD_STALLED) 2400 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2401 if (status != USBD_CANCELLED) 2402 goto skip; 2403 return; 2404 } 2405 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2406 2407 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2408 rxwisize + sizeof(struct rt2870_rxd)))) { 2409 DPRINTF(("xfer too short %d\n", xferlen)); 2410 goto skip; 2411 } 2412 2413 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2414 buf = data->buf; 2415 while (xferlen > 8) { 2416 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2417 2418 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2419 (dmalen & 3) != 0)) { 2420 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2421 break; 2422 } 2423 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2424 DPRINTF(("bad DMA length %u > %d\n", 2425 dmalen + 8, xferlen)); 2426 break; 2427 } 2428 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2429 buf += dmalen + 8; 2430 xferlen -= dmalen + 8; 2431 } 2432 2433 skip: /* setup a new transfer */ 2434 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2435 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2436 status = usbd_transfer(xfer); 2437 if (status != USBD_NORMAL_COMPLETION && 2438 status != USBD_IN_PROGRESS) 2439 device_printf(sc->sc_dev, "requeuing rx failed: %s\n", 2440 usbd_errstr(status)); 2441 } 2442 2443 static void 2444 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2445 { 2446 struct run_tx_data *data = priv; 2447 struct run_softc *sc = data->sc; 2448 struct run_tx_ring *txq = &sc->txq[data->qid]; 2449 struct ifnet *ifp = &sc->sc_if; 2450 int s; 2451 2452 s = splnet(); 2453 txq->queued--; 2454 sc->qfullmsk &= ~(1 << data->qid); 2455 2456 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2457 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2458 return; 2459 2460 DPRINTF(("%s: usb error on tx: %s\n", 2461 device_xname(sc->sc_dev), usbd_errstr(status))); 2462 if (status == USBD_STALLED) 2463 usbd_clear_endpoint_stall_async(txq->pipeh); 2464 ifp->if_oerrors++; 2465 splx(s); 2466 return; 2467 } 2468 2469 sc->sc_tx_timer = 0; 2470 ifp->if_opackets++; 2471 ifp->if_flags &= ~IFF_OACTIVE; 2472 run_start(ifp); 2473 splx(s); 2474 } 2475 2476 static int 2477 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2478 { 2479 struct ieee80211com *ic = &sc->sc_ic; 2480 struct run_node *rn = (void *)ni; 2481 struct ieee80211_frame *wh; 2482 #ifndef RUN_HWCRYPTO 2483 struct ieee80211_key *k; 2484 #endif 2485 struct run_tx_ring *ring; 2486 struct run_tx_data *data; 2487 struct rt2870_txd *txd; 2488 struct rt2860_txwi *txwi; 2489 uint16_t qos, dur, mcs; 2490 uint16_t txwisize; 2491 uint8_t type, tid, qid; 2492 int hasqos, ridx, ctl_ridx, xferlen; 2493 uint8_t pad; 2494 usbd_status status; 2495 2496 wh = mtod(m, struct ieee80211_frame *); 2497 2498 #ifndef RUN_HWCRYPTO 2499 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2500 k = ieee80211_crypto_encap(ic, ni, m); 2501 if (k == NULL) { 2502 m_freem(m); 2503 return ENOBUFS; 2504 } 2505 2506 /* packet header may have moved, reset our local pointer */ 2507 wh = mtod(m, struct ieee80211_frame *); 2508 } 2509 #endif 2510 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2511 2512 if ((hasqos = ieee80211_has_qos(wh))) { 2513 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2514 tid = qos & IEEE80211_QOS_TID; 2515 qid = TID_TO_WME_AC(tid); 2516 } else { 2517 qos = 0; 2518 tid = 0; 2519 qid = WME_AC_BE; 2520 } 2521 ring = &sc->txq[qid]; 2522 data = &ring->data[ring->cur]; 2523 2524 /* pickup a rate index */ 2525 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2526 type != IEEE80211_FC0_TYPE_DATA) { 2527 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2528 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2529 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2530 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2531 ridx = sc->fixed_ridx; 2532 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2533 } else { 2534 ridx = rn->ridx[ni->ni_txrate]; 2535 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2536 } 2537 2538 /* get MCS code from rate index */ 2539 mcs = rt2860_rates[ridx].mcs; 2540 2541 txwisize = sizeof(struct rt2860_txwi); 2542 if (sc->mac_ver == 0x5592) 2543 txwisize += sizeof(uint32_t); 2544 xferlen = txwisize + m->m_pkthdr.len; 2545 2546 /* roundup to 32-bit alignment */ 2547 xferlen = (xferlen + 3) & ~3; 2548 2549 txd = (struct rt2870_txd *)data->buf; 2550 txd->flags = RT2860_TX_QSEL_EDCA; 2551 txd->len = htole16(xferlen); 2552 2553 /* 2554 * Ether both are true or both are false, the header 2555 * are nicely aligned to 32-bit. So, no L2 padding. 2556 */ 2557 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2558 pad = 0; 2559 else 2560 pad = 2; 2561 2562 /* setup TX Wireless Information */ 2563 txwi = (struct rt2860_txwi *)(txd + 1); 2564 txwi->flags = 0; 2565 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2566 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2567 RUN_AID2WCID(ni->ni_associd) : 0xff; 2568 txwi->len = htole16(m->m_pkthdr.len - pad); 2569 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2570 txwi->phy = htole16(RT2860_PHY_CCK); 2571 if (ridx != RT2860_RIDX_CCK1 && 2572 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2573 mcs |= RT2860_PHY_SHPRE; 2574 } else 2575 mcs |= RT2860_PHY_OFDM; 2576 txwi->phy = htole16(mcs); 2577 2578 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2579 2580 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2581 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2582 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2583 txwi->xflags |= RT2860_TX_ACK; 2584 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2585 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2586 else 2587 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2588 *(uint16_t *)wh->i_dur = htole16(dur); 2589 } 2590 2591 #ifndef IEEE80211_STA_ONLY 2592 /* ask MAC to insert timestamp into probe responses */ 2593 if ((wh->i_fc[0] & 2594 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2595 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2596 /* NOTE: beacons do not pass through tx_data() */ 2597 txwi->flags |= RT2860_TX_TS; 2598 #endif 2599 2600 if (__predict_false(sc->sc_drvbpf != NULL)) { 2601 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2602 2603 tap->wt_flags = 0; 2604 tap->wt_rate = rt2860_rates[ridx].rate; 2605 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2606 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2607 tap->wt_hwqueue = qid; 2608 if (mcs & RT2860_PHY_SHPRE) 2609 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2610 2611 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2612 } 2613 2614 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2615 m_freem(m); 2616 2617 xferlen += sizeof(*txd) + 4; 2618 2619 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2620 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2621 status = usbd_transfer(data->xfer); 2622 if (__predict_false(status != USBD_IN_PROGRESS && 2623 status != USBD_NORMAL_COMPLETION)) { 2624 device_printf(sc->sc_dev, "queuing tx failed: %s\n", 2625 usbd_errstr(status)); 2626 return EIO; 2627 } 2628 2629 ieee80211_free_node(ni); 2630 2631 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2632 if (++ring->queued >= RUN_TX_RING_COUNT) 2633 sc->qfullmsk |= 1 << qid; 2634 2635 return 0; 2636 } 2637 2638 static void 2639 run_start(struct ifnet *ifp) 2640 { 2641 struct run_softc *sc = ifp->if_softc; 2642 struct ieee80211com *ic = &sc->sc_ic; 2643 struct ether_header *eh; 2644 struct ieee80211_node *ni; 2645 struct mbuf *m; 2646 2647 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2648 return; 2649 2650 for (;;) { 2651 if (sc->qfullmsk != 0) { 2652 ifp->if_flags |= IFF_OACTIVE; 2653 break; 2654 } 2655 /* send pending management frames first */ 2656 IF_DEQUEUE(&ic->ic_mgtq, m); 2657 if (m != NULL) { 2658 ni = M_GETCTX(m, struct ieee80211_node *); 2659 M_CLEARCTX(m); 2660 goto sendit; 2661 } 2662 if (ic->ic_state != IEEE80211_S_RUN) 2663 break; 2664 2665 /* encapsulate and send data frames */ 2666 IFQ_DEQUEUE(&ifp->if_snd, m); 2667 if (m == NULL) 2668 break; 2669 if (m->m_len < (int)sizeof(*eh) && 2670 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2671 ifp->if_oerrors++; 2672 continue; 2673 } 2674 2675 eh = mtod(m, struct ether_header *); 2676 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2677 if (ni == NULL) { 2678 m_freem(m); 2679 ifp->if_oerrors++; 2680 continue; 2681 } 2682 2683 bpf_mtap(ifp, m, BPF_D_OUT); 2684 2685 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2686 ieee80211_free_node(ni); 2687 ifp->if_oerrors++; 2688 continue; 2689 } 2690 sendit: 2691 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2692 2693 if (run_tx(sc, m, ni) != 0) { 2694 ieee80211_free_node(ni); 2695 ifp->if_oerrors++; 2696 continue; 2697 } 2698 2699 sc->sc_tx_timer = 5; 2700 ifp->if_timer = 1; 2701 } 2702 } 2703 2704 static void 2705 run_watchdog(struct ifnet *ifp) 2706 { 2707 struct run_softc *sc = ifp->if_softc; 2708 struct ieee80211com *ic = &sc->sc_ic; 2709 2710 ifp->if_timer = 0; 2711 2712 if (sc->sc_tx_timer > 0) { 2713 if (--sc->sc_tx_timer == 0) { 2714 device_printf(sc->sc_dev, "device timeout\n"); 2715 /* run_init(ifp); XXX needs a process context! */ 2716 ifp->if_oerrors++; 2717 return; 2718 } 2719 ifp->if_timer = 1; 2720 } 2721 2722 ieee80211_watchdog(ic); 2723 } 2724 2725 static int 2726 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2727 { 2728 struct run_softc *sc = ifp->if_softc; 2729 struct ieee80211com *ic = &sc->sc_ic; 2730 int s, error = 0; 2731 2732 s = splnet(); 2733 2734 switch (cmd) { 2735 case SIOCSIFFLAGS: 2736 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2737 break; 2738 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2739 case IFF_UP|IFF_RUNNING: 2740 break; 2741 case IFF_UP: 2742 run_init(ifp); 2743 break; 2744 case IFF_RUNNING: 2745 run_stop(ifp, 1); 2746 break; 2747 case 0: 2748 break; 2749 } 2750 break; 2751 2752 case SIOCADDMULTI: 2753 case SIOCDELMULTI: 2754 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2755 /* setup multicast filter, etc */ 2756 error = 0; 2757 } 2758 break; 2759 2760 default: 2761 error = ieee80211_ioctl(ic, cmd, data); 2762 break; 2763 } 2764 2765 if (error == ENETRESET) { 2766 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2767 (IFF_UP | IFF_RUNNING)) { 2768 run_init(ifp); 2769 } 2770 error = 0; 2771 } 2772 2773 splx(s); 2774 2775 return error; 2776 } 2777 2778 static void 2779 run_select_chan_group(struct run_softc *sc, int group) 2780 { 2781 uint32_t tmp; 2782 uint8_t agc; 2783 2784 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2785 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2786 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2787 if (sc->mac_ver < 0x3572) 2788 run_bbp_write(sc, 86, 0x00); 2789 2790 if (sc->mac_ver == 0x3593) { 2791 run_bbp_write(sc, 77, 0x98); 2792 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2793 } 2794 2795 if (group == 0) { 2796 if (sc->ext_2ghz_lna) { 2797 if (sc->mac_ver >= 0x5390) 2798 run_bbp_write(sc, 75, 0x52); 2799 else { 2800 run_bbp_write(sc, 82, 0x62); 2801 run_bbp_write(sc, 75, 0x46); 2802 } 2803 } else { 2804 if (sc->mac_ver == 0x5592) { 2805 run_bbp_write(sc, 79, 0x1c); 2806 run_bbp_write(sc, 80, 0x0e); 2807 run_bbp_write(sc, 81, 0x3a); 2808 run_bbp_write(sc, 82, 0x62); 2809 2810 run_bbp_write(sc, 195, 0x80); 2811 run_bbp_write(sc, 196, 0xe0); 2812 run_bbp_write(sc, 195, 0x81); 2813 run_bbp_write(sc, 196, 0x1f); 2814 run_bbp_write(sc, 195, 0x82); 2815 run_bbp_write(sc, 196, 0x38); 2816 run_bbp_write(sc, 195, 0x83); 2817 run_bbp_write(sc, 196, 0x32); 2818 run_bbp_write(sc, 195, 0x85); 2819 run_bbp_write(sc, 196, 0x28); 2820 run_bbp_write(sc, 195, 0x86); 2821 run_bbp_write(sc, 196, 0x19); 2822 } else if (sc->mac_ver >= 0x5390) { 2823 run_bbp_write(sc, 75, 0x50); 2824 } else { 2825 run_bbp_write(sc, 82, 2826 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2827 run_bbp_write(sc, 75, 0x50); 2828 } 2829 } 2830 } else { 2831 if (sc->mac_ver == 0x5592) { 2832 run_bbp_write(sc, 79, 0x18); 2833 run_bbp_write(sc, 80, 0x08); 2834 run_bbp_write(sc, 81, 0x38); 2835 run_bbp_write(sc, 82, 0x92); 2836 2837 run_bbp_write(sc, 195, 0x80); 2838 run_bbp_write(sc, 196, 0xf0); 2839 run_bbp_write(sc, 195, 0x81); 2840 run_bbp_write(sc, 196, 0x1e); 2841 run_bbp_write(sc, 195, 0x82); 2842 run_bbp_write(sc, 196, 0x28); 2843 run_bbp_write(sc, 195, 0x83); 2844 run_bbp_write(sc, 196, 0x20); 2845 run_bbp_write(sc, 195, 0x85); 2846 run_bbp_write(sc, 196, 0x7f); 2847 run_bbp_write(sc, 195, 0x86); 2848 run_bbp_write(sc, 196, 0x7f); 2849 } else if (sc->mac_ver == 0x3572) 2850 run_bbp_write(sc, 82, 0x94); 2851 else 2852 run_bbp_write(sc, 82, 2853 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2854 if (sc->ext_5ghz_lna) 2855 run_bbp_write(sc, 75, 0x46); 2856 else 2857 run_bbp_write(sc, 75, 0x50); 2858 } 2859 2860 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2861 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2862 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2863 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2864 2865 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2866 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2867 if (sc->mac_ver == 0x3593) 2868 tmp |= RT3593_LNA_PE_G2_EN | RT3593_LNA_PE_A2_EN; 2869 if (sc->nrxchains > 1) 2870 tmp |= RT2860_LNA_PE1_EN; 2871 if (group == 0) { /* 2GHz */ 2872 tmp |= RT2860_PA_PE_G0_EN; 2873 if (sc->ntxchains > 1) 2874 tmp |= RT2860_PA_PE_G1_EN; 2875 } else { /* 5GHz */ 2876 tmp |= RT2860_PA_PE_A0_EN; 2877 if (sc->ntxchains > 1) 2878 tmp |= RT2860_PA_PE_A1_EN; 2879 if (sc->mac_ver == 0x3593) { 2880 if (sc->ntxchains > 2) 2881 tmp |= RT3593_PA_PE_G2_EN; 2882 } 2883 } 2884 if (sc->mac_ver == 0x3572) { 2885 run_rt3070_rf_write(sc, 8, 0x00); 2886 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2887 run_rt3070_rf_write(sc, 8, 0x80); 2888 } else 2889 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2890 2891 if (sc->mac_ver == 0x5592) { 2892 run_bbp_write(sc, 195, 0x8d); 2893 run_bbp_write(sc, 196, 0x1a); 2894 } 2895 2896 if (sc->mac_ver == 0x3593) { 2897 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2898 tmp &= ~0x01010000; 2899 if (group == 0) 2900 tmp |= 0x00010000; 2901 tmp = (tmp & ~0x00009090) | 0x00000090; 2902 run_write(sc, RT2860_GPIO_CTRL, tmp); 2903 } 2904 2905 /* set initial AGC value */ 2906 if (group == 0) { /* 2GHz band */ 2907 if (sc->mac_ver >= 0x3070) 2908 agc = 0x1c + sc->lna[0] * 2; 2909 else 2910 agc = 0x2e + sc->lna[0]; 2911 } else { /* 5GHz band */ 2912 if (sc->mac_ver == 0x3572) 2913 agc = 0x22 + (sc->lna[group] * 5) / 3; 2914 else 2915 agc = 0x32 + (sc->lna[group] * 5) / 3; 2916 } 2917 run_set_agc(sc, agc); 2918 } 2919 2920 static void 2921 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2922 { 2923 const struct rfprog *rfprog = rt2860_rf2850; 2924 uint32_t r2, r3, r4; 2925 int8_t txpow1, txpow2; 2926 int i; 2927 2928 /* find the settings for this channel (we know it exists) */ 2929 for (i = 0; rfprog[i].chan != chan; i++); 2930 2931 r2 = rfprog[i].r2; 2932 if (sc->ntxchains == 1) 2933 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2934 if (sc->nrxchains == 1) 2935 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2936 else if (sc->nrxchains == 2) 2937 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2938 2939 /* use Tx power values from EEPROM */ 2940 txpow1 = sc->txpow1[i]; 2941 txpow2 = sc->txpow2[i]; 2942 if (chan > 14) { 2943 if (txpow1 >= 0) 2944 txpow1 = txpow1 << 1 | 1; 2945 else 2946 txpow1 = (7 + txpow1) << 1; 2947 if (txpow2 >= 0) 2948 txpow2 = txpow2 << 1 | 1; 2949 else 2950 txpow2 = (7 + txpow2) << 1; 2951 } 2952 r3 = rfprog[i].r3 | txpow1 << 7; 2953 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2954 2955 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2956 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2957 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2958 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2959 2960 usbd_delay_ms(sc->sc_udev, 10); 2961 2962 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2963 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2964 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2965 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2966 2967 usbd_delay_ms(sc->sc_udev, 10); 2968 2969 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2970 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2971 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2972 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2973 } 2974 2975 static void 2976 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2977 { 2978 int8_t txpow1, txpow2; 2979 uint8_t rf; 2980 int i; 2981 2982 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2983 2984 /* find the settings for this channel (we know it exists) */ 2985 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2986 continue; 2987 2988 /* use Tx power values from EEPROM */ 2989 txpow1 = sc->txpow1[i]; 2990 txpow2 = sc->txpow2[i]; 2991 2992 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2993 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2994 run_rt3070_rf_read(sc, 6, &rf); 2995 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2996 run_rt3070_rf_write(sc, 6, rf); 2997 2998 /* set Tx0 power */ 2999 run_rt3070_rf_read(sc, 12, &rf); 3000 rf = (rf & ~0x1f) | txpow1; 3001 run_rt3070_rf_write(sc, 12, rf); 3002 3003 /* set Tx1 power */ 3004 run_rt3070_rf_read(sc, 13, &rf); 3005 rf = (rf & ~0x1f) | txpow2; 3006 run_rt3070_rf_write(sc, 13, rf); 3007 3008 run_rt3070_rf_read(sc, 1, &rf); 3009 rf &= ~0xfc; 3010 if (sc->ntxchains == 1) 3011 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3012 else if (sc->ntxchains == 2) 3013 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3014 if (sc->nrxchains == 1) 3015 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3016 else if (sc->nrxchains == 2) 3017 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3018 run_rt3070_rf_write(sc, 1, rf); 3019 3020 /* set RF offset */ 3021 run_rt3070_rf_read(sc, 23, &rf); 3022 rf = (rf & ~0x7f) | sc->freq; 3023 run_rt3070_rf_write(sc, 23, rf); 3024 3025 /* program RF filter */ 3026 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 3027 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3028 run_rt3070_rf_write(sc, 24, rf); 3029 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3030 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3031 run_rt3070_rf_write(sc, 31, rf); 3032 3033 /* enable RF tuning */ 3034 run_rt3070_rf_read(sc, 7, &rf); 3035 run_rt3070_rf_write(sc, 7, rf | 0x01); 3036 } 3037 3038 static void 3039 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3040 { 3041 int8_t txpow1, txpow2; 3042 uint32_t tmp; 3043 uint8_t rf; 3044 int i; 3045 3046 /* find the settings for this channel (we know it exists) */ 3047 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3048 3049 /* use Tx power values from EEPROM */ 3050 txpow1 = sc->txpow1[i]; 3051 txpow2 = sc->txpow2[i]; 3052 3053 if (chan <= 14) { 3054 run_bbp_write(sc, 25, sc->bbp25); 3055 run_bbp_write(sc, 26, sc->bbp26); 3056 } else { 3057 /* enable IQ phase correction */ 3058 run_bbp_write(sc, 25, 0x09); 3059 run_bbp_write(sc, 26, 0xff); 3060 } 3061 3062 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3063 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3064 run_rt3070_rf_read(sc, 6, &rf); 3065 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3066 rf |= (chan <= 14) ? 0x08 : 0x04; 3067 run_rt3070_rf_write(sc, 6, rf); 3068 3069 /* set PLL mode */ 3070 run_rt3070_rf_read(sc, 5, &rf); 3071 rf &= ~(0x08 | 0x04); 3072 rf |= (chan <= 14) ? 0x04 : 0x08; 3073 run_rt3070_rf_write(sc, 5, rf); 3074 3075 /* set Tx power for chain 0 */ 3076 if (chan <= 14) 3077 rf = 0x60 | txpow1; 3078 else 3079 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3080 run_rt3070_rf_write(sc, 12, rf); 3081 3082 /* set Tx power for chain 1 */ 3083 if (chan <= 14) 3084 rf = 0x60 | txpow2; 3085 else 3086 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3087 run_rt3070_rf_write(sc, 13, rf); 3088 3089 /* set Tx/Rx streams */ 3090 run_rt3070_rf_read(sc, 1, &rf); 3091 rf &= ~0xfc; 3092 if (sc->ntxchains == 1) 3093 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3094 else if (sc->ntxchains == 2) 3095 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3096 if (sc->nrxchains == 1) 3097 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3098 else if (sc->nrxchains == 2) 3099 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3100 run_rt3070_rf_write(sc, 1, rf); 3101 3102 /* set RF offset */ 3103 run_rt3070_rf_read(sc, 23, &rf); 3104 rf = (rf & ~0x7f) | sc->freq; 3105 run_rt3070_rf_write(sc, 23, rf); 3106 3107 /* program RF filter */ 3108 rf = sc->rf24_20mhz; 3109 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3110 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3111 3112 /* enable RF tuning */ 3113 run_rt3070_rf_read(sc, 7, &rf); 3114 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3115 run_rt3070_rf_write(sc, 7, rf); 3116 3117 /* TSSI */ 3118 rf = (chan <= 14) ? 0xc3 : 0xc0; 3119 run_rt3070_rf_write(sc, 9, rf); 3120 3121 /* set loop filter 1 */ 3122 run_rt3070_rf_write(sc, 10, 0xf1); 3123 /* set loop filter 2 */ 3124 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3125 3126 /* set tx_mx2_ic */ 3127 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3128 /* set tx_mx1_ic */ 3129 if (chan <= 14) 3130 rf = 0x48 | sc->txmixgain_2ghz; 3131 else 3132 rf = 0x78 | sc->txmixgain_5ghz; 3133 run_rt3070_rf_write(sc, 16, rf); 3134 3135 /* set tx_lo1 */ 3136 run_rt3070_rf_write(sc, 17, 0x23); 3137 /* set tx_lo2 */ 3138 if (chan <= 14) 3139 rf = 0x93; 3140 else if (chan <= 64) 3141 rf = 0xb7; 3142 else if (chan <= 128) 3143 rf = 0x74; 3144 else 3145 rf = 0x72; 3146 run_rt3070_rf_write(sc, 19, rf); 3147 3148 /* set rx_lo1 */ 3149 if (chan <= 14) 3150 rf = 0xb3; 3151 else if (chan <= 64) 3152 rf = 0xf6; 3153 else if (chan <= 128) 3154 rf = 0xf4; 3155 else 3156 rf = 0xf3; 3157 run_rt3070_rf_write(sc, 20, rf); 3158 3159 /* set pfd_delay */ 3160 if (chan <= 14) 3161 rf = 0x15; 3162 else if (chan <= 64) 3163 rf = 0x3d; 3164 else 3165 rf = 0x01; 3166 run_rt3070_rf_write(sc, 25, rf); 3167 3168 /* set rx_lo2 */ 3169 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3170 /* set ldo_rf_vc */ 3171 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3172 /* set drv_cc */ 3173 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3174 3175 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3176 tmp &= ~0x8080; 3177 if (chan <= 14) 3178 tmp |= 0x80; 3179 run_write(sc, RT2860_GPIO_CTRL, tmp); 3180 3181 /* enable RF tuning */ 3182 run_rt3070_rf_read(sc, 7, &rf); 3183 run_rt3070_rf_write(sc, 7, rf | 0x01); 3184 3185 usbd_delay_ms(sc->sc_udev, 2); 3186 } 3187 3188 static void 3189 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3190 { 3191 int8_t txpow1, txpow2, txpow3; 3192 uint8_t h20mhz, rf; 3193 int i; 3194 3195 /* find the settings for this channel (we know it exists) */ 3196 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3197 3198 /* use Tx power values from EEPROM */ 3199 txpow1 = sc->txpow1[i]; 3200 txpow2 = sc->txpow2[i]; 3201 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3202 3203 if (chan <= 14) { 3204 run_bbp_write(sc, 25, sc->bbp25); 3205 run_bbp_write(sc, 26, sc->bbp26); 3206 } else { 3207 /* Enable IQ phase correction. */ 3208 run_bbp_write(sc, 25, 0x09); 3209 run_bbp_write(sc, 26, 0xff); 3210 } 3211 3212 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3213 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3214 run_rt3070_rf_read(sc, 11, &rf); 3215 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3216 run_rt3070_rf_write(sc, 11, rf); 3217 3218 /* Set pll_idoh. */ 3219 run_rt3070_rf_read(sc, 11, &rf); 3220 rf &= ~0x4c; 3221 rf |= (chan <= 14) ? 0x44 : 0x48; 3222 run_rt3070_rf_write(sc, 11, rf); 3223 3224 if (chan <= 14) 3225 rf = txpow1 & 0x1f; 3226 else 3227 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3228 run_rt3070_rf_write(sc, 53, rf); 3229 3230 if (chan <= 14) 3231 rf = txpow2 & 0x1f; 3232 else 3233 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3234 run_rt3070_rf_write(sc, 55, rf); 3235 3236 if (chan <= 14) 3237 rf = txpow3 & 0x1f; 3238 else 3239 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3240 run_rt3070_rf_write(sc, 54, rf); 3241 3242 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3243 if (sc->ntxchains == 3) 3244 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3245 else 3246 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3247 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3248 run_rt3070_rf_write(sc, 1, rf); 3249 3250 run_adjust_freq_offset(sc); 3251 3252 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3253 3254 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3255 run_rt3070_rf_read(sc, 30, &rf); 3256 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3257 run_rt3070_rf_write(sc, 30, rf); 3258 3259 run_rt3070_rf_read(sc, 36, &rf); 3260 if (chan <= 14) 3261 rf |= 0x80; 3262 else 3263 rf &= ~0x80; 3264 run_rt3070_rf_write(sc, 36, rf); 3265 3266 /* Set vcolo_bs. */ 3267 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3268 /* Set pfd_delay. */ 3269 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3270 3271 /* Set vco bias current control. */ 3272 run_rt3070_rf_read(sc, 6, &rf); 3273 rf &= ~0xc0; 3274 if (chan <= 14) 3275 rf |= 0x40; 3276 else if (chan <= 128) 3277 rf |= 0x80; 3278 else 3279 rf |= 0x40; 3280 run_rt3070_rf_write(sc, 6, rf); 3281 3282 run_rt3070_rf_read(sc, 30, &rf); 3283 rf = (rf & ~0x18) | 0x10; 3284 run_rt3070_rf_write(sc, 30, rf); 3285 3286 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3287 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3288 3289 run_rt3070_rf_read(sc, 51, &rf); 3290 rf = (rf & ~0x03) | 0x01; 3291 run_rt3070_rf_write(sc, 51, rf); 3292 /* Set tx_mx1_cc. */ 3293 run_rt3070_rf_read(sc, 51, &rf); 3294 rf &= ~0x1c; 3295 rf |= (chan <= 14) ? 0x14 : 0x10; 3296 run_rt3070_rf_write(sc, 51, rf); 3297 /* Set tx_mx1_ic. */ 3298 run_rt3070_rf_read(sc, 51, &rf); 3299 rf &= ~0xe0; 3300 rf |= (chan <= 14) ? 0x60 : 0x40; 3301 run_rt3070_rf_write(sc, 51, rf); 3302 /* Set tx_lo1_ic. */ 3303 run_rt3070_rf_read(sc, 49, &rf); 3304 rf &= ~0x1c; 3305 rf |= (chan <= 14) ? 0x0c : 0x08; 3306 run_rt3070_rf_write(sc, 49, rf); 3307 /* Set tx_lo1_en. */ 3308 run_rt3070_rf_read(sc, 50, &rf); 3309 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3310 /* Set drv_cc. */ 3311 run_rt3070_rf_read(sc, 57, &rf); 3312 rf &= ~0xfc; 3313 rf |= (chan <= 14) ? 0x6c : 0x3c; 3314 run_rt3070_rf_write(sc, 57, rf); 3315 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3316 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3317 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3318 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3319 /* Enable VCO calibration. */ 3320 run_rt3070_rf_read(sc, 3, &rf); 3321 rf &= ~RT5390_VCOCAL; 3322 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3323 run_rt3070_rf_write(sc, 3, rf); 3324 3325 if (chan <= 14) 3326 rf = 0x23; 3327 else if (chan <= 64) 3328 rf = 0x36; 3329 else if (chan <= 128) 3330 rf = 0x32; 3331 else 3332 rf = 0x30; 3333 run_rt3070_rf_write(sc, 39, rf); 3334 if (chan <= 14) 3335 rf = 0xbb; 3336 else if (chan <= 64) 3337 rf = 0xeb; 3338 else if (chan <= 128) 3339 rf = 0xb3; 3340 else 3341 rf = 0x9b; 3342 run_rt3070_rf_write(sc, 45, rf); 3343 3344 /* Set FEQ/AEQ control. */ 3345 run_bbp_write(sc, 105, 0x34); 3346 } 3347 3348 static void 3349 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3350 { 3351 int8_t txpow1, txpow2; 3352 uint8_t rf; 3353 int i; 3354 3355 /* find the settings for this channel (we know it exists) */ 3356 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3357 3358 /* use Tx power values from EEPROM */ 3359 txpow1 = sc->txpow1[i]; 3360 txpow2 = sc->txpow2[i]; 3361 3362 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3363 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3364 run_rt3070_rf_read(sc, 11, &rf); 3365 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3366 run_rt3070_rf_write(sc, 11, rf); 3367 3368 run_rt3070_rf_read(sc, 49, &rf); 3369 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3370 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3371 if ((rf & 0x3f) > 0x27) 3372 rf = (rf & ~0x3f) | 0x27; 3373 run_rt3070_rf_write(sc, 49, rf); 3374 3375 if (sc->mac_ver == 0x5392) { 3376 run_rt3070_rf_read(sc, 50, &rf); 3377 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3378 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3379 if ((rf & 0x3f) > 0x27) 3380 rf = (rf & ~0x3f) | 0x27; 3381 run_rt3070_rf_write(sc, 50, rf); 3382 } 3383 3384 run_rt3070_rf_read(sc, 1, &rf); 3385 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3386 if (sc->mac_ver == 0x5392) 3387 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3388 run_rt3070_rf_write(sc, 1, rf); 3389 3390 if (sc->mac_ver != 0x5392) { 3391 run_rt3070_rf_read(sc, 2, &rf); 3392 rf |= 0x80; 3393 run_rt3070_rf_write(sc, 2, rf); 3394 usbd_delay_ms(sc->sc_udev, 10); 3395 rf &= 0x7f; 3396 run_rt3070_rf_write(sc, 2, rf); 3397 } 3398 3399 run_adjust_freq_offset(sc); 3400 3401 if (sc->mac_ver == 0x5392) { 3402 /* Fix for RT5392C. */ 3403 if (sc->mac_rev >= 0x0223) { 3404 if (chan <= 4) 3405 rf = 0x0f; 3406 else if (chan >= 5 && chan <= 7) 3407 rf = 0x0e; 3408 else 3409 rf = 0x0d; 3410 run_rt3070_rf_write(sc, 23, rf); 3411 3412 if (chan <= 4) 3413 rf = 0x0c; 3414 else if (chan == 5) 3415 rf = 0x0b; 3416 else if (chan >= 6 && chan <= 7) 3417 rf = 0x0a; 3418 else if (chan >= 8 && chan <= 10) 3419 rf = 0x09; 3420 else 3421 rf = 0x08; 3422 run_rt3070_rf_write(sc, 59, rf); 3423 } else { 3424 if (chan <= 11) 3425 rf = 0x0f; 3426 else 3427 rf = 0x0b; 3428 run_rt3070_rf_write(sc, 59, rf); 3429 } 3430 } else { 3431 /* Fix for RT5390F. */ 3432 if (sc->mac_rev >= 0x0502) { 3433 if (chan <= 11) 3434 rf = 0x43; 3435 else 3436 rf = 0x23; 3437 run_rt3070_rf_write(sc, 55, rf); 3438 3439 if (chan <= 11) 3440 rf = 0x0f; 3441 else if (chan == 12) 3442 rf = 0x0d; 3443 else 3444 rf = 0x0b; 3445 run_rt3070_rf_write(sc, 59, rf); 3446 } else { 3447 run_rt3070_rf_write(sc, 55, 0x44); 3448 run_rt3070_rf_write(sc, 59, 0x8f); 3449 } 3450 } 3451 3452 /* Enable VCO calibration. */ 3453 run_rt3070_rf_read(sc, 3, &rf); 3454 rf |= RT5390_VCOCAL; 3455 run_rt3070_rf_write(sc, 3, rf); 3456 } 3457 3458 static void 3459 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3460 { 3461 const struct rt5592_freqs *freqs; 3462 uint32_t tmp; 3463 uint8_t reg, rf, txpow_bound; 3464 int8_t txpow1, txpow2; 3465 int i; 3466 3467 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3468 freqs = (tmp & RT5592_SEL_XTAL) ? 3469 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3470 3471 /* find the settings for this channel (we know it exists) */ 3472 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3473 3474 /* use Tx power values from EEPROM */ 3475 txpow1 = sc->txpow1[i]; 3476 txpow2 = sc->txpow2[i]; 3477 3478 run_read(sc, RT3070_LDO_CFG0, &tmp); 3479 tmp &= ~0x1c000000; 3480 if (chan > 14) 3481 tmp |= 0x14000000; 3482 run_write(sc, RT3070_LDO_CFG0, tmp); 3483 3484 /* N setting. */ 3485 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3486 run_rt3070_rf_read(sc, 9, &rf); 3487 rf &= ~(1 << 4); 3488 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3489 run_rt3070_rf_write(sc, 9, rf); 3490 3491 /* K setting. */ 3492 run_rt3070_rf_read(sc, 9, &rf); 3493 rf &= ~0x0f; 3494 rf |= (freqs->k & 0x0f); 3495 run_rt3070_rf_write(sc, 9, rf); 3496 3497 /* Mode setting. */ 3498 run_rt3070_rf_read(sc, 11, &rf); 3499 rf &= ~0x0c; 3500 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3501 run_rt3070_rf_write(sc, 11, rf); 3502 run_rt3070_rf_read(sc, 9, &rf); 3503 rf &= ~(1 << 7); 3504 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3505 run_rt3070_rf_write(sc, 9, rf); 3506 3507 /* R setting. */ 3508 run_rt3070_rf_read(sc, 11, &rf); 3509 rf &= ~0x03; 3510 rf |= (freqs->r - 0x1); 3511 run_rt3070_rf_write(sc, 11, rf); 3512 3513 if (chan <= 14) { 3514 /* Initialize RF registers for 2GHZ. */ 3515 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3516 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3517 rt5592_2ghz_def_rf[i].val); 3518 } 3519 3520 rf = (chan <= 10) ? 0x07 : 0x06; 3521 run_rt3070_rf_write(sc, 23, rf); 3522 run_rt3070_rf_write(sc, 59, rf); 3523 3524 run_rt3070_rf_write(sc, 55, 0x43); 3525 3526 /* 3527 * RF R49/R50 Tx power ALC code. 3528 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3529 */ 3530 reg = 2; 3531 txpow_bound = 0x27; 3532 } else { 3533 /* Initialize RF registers for 5GHZ. */ 3534 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3535 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3536 rt5592_5ghz_def_rf[i].val); 3537 } 3538 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3539 if (chan >= rt5592_chan_5ghz[i].firstchan && 3540 chan <= rt5592_chan_5ghz[i].lastchan) { 3541 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3542 rt5592_chan_5ghz[i].val); 3543 } 3544 } 3545 3546 /* 3547 * RF R49/R50 Tx power ALC code. 3548 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3549 */ 3550 reg = 3; 3551 txpow_bound = 0x2b; 3552 } 3553 3554 /* RF R49 ch0 Tx power ALC code. */ 3555 run_rt3070_rf_read(sc, 49, &rf); 3556 rf &= ~0xc0; 3557 rf |= (reg << 6); 3558 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3559 if ((rf & 0x3f) > txpow_bound) 3560 rf = (rf & ~0x3f) | txpow_bound; 3561 run_rt3070_rf_write(sc, 49, rf); 3562 3563 /* RF R50 ch1 Tx power ALC code. */ 3564 run_rt3070_rf_read(sc, 50, &rf); 3565 rf &= ~(1 << 7 | 1 << 6); 3566 rf |= (reg << 6); 3567 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3568 if ((rf & 0x3f) > txpow_bound) 3569 rf = (rf & ~0x3f) | txpow_bound; 3570 run_rt3070_rf_write(sc, 50, rf); 3571 3572 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3573 run_rt3070_rf_read(sc, 1, &rf); 3574 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3575 if (sc->ntxchains > 1) 3576 rf |= RT3070_TX1_PD; 3577 if (sc->nrxchains > 1) 3578 rf |= RT3070_RX1_PD; 3579 run_rt3070_rf_write(sc, 1, rf); 3580 3581 run_rt3070_rf_write(sc, 6, 0xe4); 3582 3583 run_rt3070_rf_write(sc, 30, 0x10); 3584 run_rt3070_rf_write(sc, 31, 0x80); 3585 run_rt3070_rf_write(sc, 32, 0x80); 3586 3587 run_adjust_freq_offset(sc); 3588 3589 /* Enable VCO calibration. */ 3590 run_rt3070_rf_read(sc, 3, &rf); 3591 rf |= RT5390_VCOCAL; 3592 run_rt3070_rf_write(sc, 3, rf); 3593 } 3594 3595 static void 3596 run_iq_calib(struct run_softc *sc, u_int chan) 3597 { 3598 uint16_t val; 3599 3600 /* Tx0 IQ gain. */ 3601 run_bbp_write(sc, 158, 0x2c); 3602 if (chan <= 14) 3603 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3604 else if (chan <= 64) { 3605 run_efuse_read(sc, 3606 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3607 &val, 1); 3608 } else if (chan <= 138) { 3609 run_efuse_read(sc, 3610 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3611 &val, 1); 3612 } else if (chan <= 165) { 3613 run_efuse_read(sc, 3614 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3615 &val, 1); 3616 } else 3617 val = 0; 3618 run_bbp_write(sc, 159, val); 3619 3620 /* Tx0 IQ phase. */ 3621 run_bbp_write(sc, 158, 0x2d); 3622 if (chan <= 14) { 3623 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3624 &val, 1); 3625 } else if (chan <= 64) { 3626 run_efuse_read(sc, 3627 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3628 &val, 1); 3629 } else if (chan <= 138) { 3630 run_efuse_read(sc, 3631 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3632 &val, 1); 3633 } else if (chan <= 165) { 3634 run_efuse_read(sc, 3635 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3636 &val, 1); 3637 } else 3638 val = 0; 3639 run_bbp_write(sc, 159, val); 3640 3641 /* Tx1 IQ gain. */ 3642 run_bbp_write(sc, 158, 0x4a); 3643 if (chan <= 14) { 3644 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3645 &val, 1); 3646 } else if (chan <= 64) { 3647 run_efuse_read(sc, 3648 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3649 &val, 1); 3650 } else if (chan <= 138) { 3651 run_efuse_read(sc, 3652 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3653 &val, 1); 3654 } else if (chan <= 165) { 3655 run_efuse_read(sc, 3656 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3657 &val, 1); 3658 } else 3659 val = 0; 3660 run_bbp_write(sc, 159, val); 3661 3662 /* Tx1 IQ phase. */ 3663 run_bbp_write(sc, 158, 0x4b); 3664 if (chan <= 14) { 3665 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3666 &val, 1); 3667 } else if (chan <= 64) { 3668 run_efuse_read(sc, 3669 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3670 &val, 1); 3671 } else if (chan <= 138) { 3672 run_efuse_read(sc, 3673 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3674 &val, 1); 3675 } else if (chan <= 165) { 3676 run_efuse_read(sc, 3677 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3678 &val, 1); 3679 } else 3680 val = 0; 3681 run_bbp_write(sc, 159, val); 3682 3683 /* RF IQ compensation control. */ 3684 run_bbp_write(sc, 158, 0x04); 3685 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3686 &val, 1); 3687 run_bbp_write(sc, 159, val); 3688 3689 /* RF IQ imbalance compensation control. */ 3690 run_bbp_write(sc, 158, 0x03); 3691 run_efuse_read(sc, 3692 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3693 run_bbp_write(sc, 159, val); 3694 } 3695 3696 static void 3697 run_set_agc(struct run_softc *sc, uint8_t agc) 3698 { 3699 uint8_t bbp; 3700 3701 if (sc->mac_ver == 0x3572) { 3702 run_bbp_read(sc, 27, &bbp); 3703 bbp &= ~(0x3 << 5); 3704 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3705 run_bbp_write(sc, 66, agc); 3706 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3707 run_bbp_write(sc, 66, agc); 3708 } else 3709 run_bbp_write(sc, 66, agc); 3710 } 3711 3712 static void 3713 run_set_rx_antenna(struct run_softc *sc, int aux) 3714 { 3715 uint32_t tmp; 3716 uint8_t bbp152; 3717 3718 if (aux) { 3719 if (sc->rf_rev == RT5390_RF_5370) { 3720 run_bbp_read(sc, 152, &bbp152); 3721 bbp152 &= ~0x80; 3722 run_bbp_write(sc, 152, bbp152); 3723 } else { 3724 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3725 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3726 tmp &= ~0x0808; 3727 tmp |= 0x08; 3728 run_write(sc, RT2860_GPIO_CTRL, tmp); 3729 } 3730 } else { 3731 if (sc->rf_rev == RT5390_RF_5370) { 3732 run_bbp_read(sc, 152, &bbp152); 3733 bbp152 |= 0x80; 3734 run_bbp_write(sc, 152, bbp152); 3735 } else { 3736 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3737 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3738 tmp &= ~0x0808; 3739 run_write(sc, RT2860_GPIO_CTRL, tmp); 3740 } 3741 } 3742 } 3743 3744 static int 3745 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3746 { 3747 struct ieee80211com *ic = &sc->sc_ic; 3748 u_int chan, group; 3749 3750 chan = ieee80211_chan2ieee(ic, c); 3751 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3752 return EINVAL; 3753 3754 if (sc->mac_ver == 0x5592) 3755 run_rt5592_set_chan(sc, chan); 3756 else if (sc->mac_ver >= 0x5390) 3757 run_rt5390_set_chan(sc, chan); 3758 else if (sc->mac_ver == 0x3593) 3759 run_rt3593_set_chan(sc, chan); 3760 else if (sc->mac_ver == 0x3572) 3761 run_rt3572_set_chan(sc, chan); 3762 else if (sc->mac_ver >= 0x3070) 3763 run_rt3070_set_chan(sc, chan); 3764 else 3765 run_rt2870_set_chan(sc, chan); 3766 3767 /* determine channel group */ 3768 if (chan <= 14) 3769 group = 0; 3770 else if (chan <= 64) 3771 group = 1; 3772 else if (chan <= 128) 3773 group = 2; 3774 else 3775 group = 3; 3776 3777 /* XXX necessary only when group has changed! */ 3778 run_select_chan_group(sc, group); 3779 3780 usbd_delay_ms(sc->sc_udev, 10); 3781 3782 /* Perform IQ calibration. */ 3783 if (sc->mac_ver >= 0x5392) 3784 run_iq_calib(sc, chan); 3785 3786 return 0; 3787 } 3788 3789 static void 3790 run_updateprot(struct run_softc *sc) 3791 { 3792 struct ieee80211com *ic = &sc->sc_ic; 3793 uint32_t tmp; 3794 3795 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3796 /* setup protection frame rate (MCS code) */ 3797 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3798 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3799 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3800 3801 /* CCK frames don't require protection */ 3802 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3803 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3804 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3805 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3806 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3807 tmp |= RT2860_PROT_CTRL_CTS; 3808 } 3809 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3810 } 3811 3812 static void 3813 run_enable_tsf_sync(struct run_softc *sc) 3814 { 3815 struct ieee80211com *ic = &sc->sc_ic; 3816 uint32_t tmp; 3817 3818 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3819 tmp &= ~0x1fffff; 3820 tmp |= ic->ic_bss->ni_intval * 16; 3821 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3822 if (ic->ic_opmode == IEEE80211_M_STA) { 3823 /* 3824 * Local TSF is always updated with remote TSF on beacon 3825 * reception. 3826 */ 3827 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3828 } 3829 #ifndef IEEE80211_STA_ONLY 3830 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3831 tmp |= RT2860_BCN_TX_EN; 3832 /* 3833 * Local TSF is updated with remote TSF on beacon reception 3834 * only if the remote TSF is greater than local TSF. 3835 */ 3836 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3837 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3838 tmp |= RT2860_BCN_TX_EN; 3839 /* SYNC with nobody */ 3840 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3841 } 3842 #endif 3843 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3844 } 3845 3846 static void 3847 run_enable_mrr(struct run_softc *sc) 3848 { 3849 #define CCK(mcs) (mcs) 3850 #define OFDM(mcs) (1 << 3 | (mcs)) 3851 run_write(sc, RT2860_LG_FBK_CFG0, 3852 OFDM(6) << 28 | /* 54->48 */ 3853 OFDM(5) << 24 | /* 48->36 */ 3854 OFDM(4) << 20 | /* 36->24 */ 3855 OFDM(3) << 16 | /* 24->18 */ 3856 OFDM(2) << 12 | /* 18->12 */ 3857 OFDM(1) << 8 | /* 12-> 9 */ 3858 OFDM(0) << 4 | /* 9-> 6 */ 3859 OFDM(0)); /* 6-> 6 */ 3860 3861 run_write(sc, RT2860_LG_FBK_CFG1, 3862 CCK(2) << 12 | /* 11->5.5 */ 3863 CCK(1) << 8 | /* 5.5-> 2 */ 3864 CCK(0) << 4 | /* 2-> 1 */ 3865 CCK(0)); /* 1-> 1 */ 3866 #undef OFDM 3867 #undef CCK 3868 } 3869 3870 static void 3871 run_set_txpreamble(struct run_softc *sc) 3872 { 3873 uint32_t tmp; 3874 3875 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3876 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3877 tmp |= RT2860_CCK_SHORT_EN; 3878 else 3879 tmp &= ~RT2860_CCK_SHORT_EN; 3880 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3881 } 3882 3883 static void 3884 run_set_basicrates(struct run_softc *sc) 3885 { 3886 struct ieee80211com *ic = &sc->sc_ic; 3887 3888 /* set basic rates mask */ 3889 if (ic->ic_curmode == IEEE80211_MODE_11B) 3890 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3891 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3892 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3893 else /* 11g */ 3894 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3895 } 3896 3897 static void 3898 run_set_leds(struct run_softc *sc, uint16_t which) 3899 { 3900 3901 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3902 which | (sc->leds & 0x7f)); 3903 } 3904 3905 static void 3906 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3907 { 3908 3909 run_write(sc, RT2860_MAC_BSSID_DW0, 3910 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3911 run_write(sc, RT2860_MAC_BSSID_DW1, 3912 bssid[4] | bssid[5] << 8); 3913 } 3914 3915 static void 3916 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3917 { 3918 3919 run_write(sc, RT2860_MAC_ADDR_DW0, 3920 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3921 run_write(sc, RT2860_MAC_ADDR_DW1, 3922 addr[4] | addr[5] << 8 | 0xff << 16); 3923 } 3924 3925 static void 3926 run_updateslot(struct ifnet *ifp) 3927 { 3928 3929 /* do it in a process context */ 3930 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3931 } 3932 3933 /* ARGSUSED */ 3934 static void 3935 run_updateslot_cb(struct run_softc *sc, void *arg) 3936 { 3937 uint32_t tmp; 3938 3939 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3940 tmp &= ~0xff; 3941 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3942 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3943 } 3944 3945 static int8_t 3946 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3947 { 3948 struct ieee80211com *ic = &sc->sc_ic; 3949 struct ieee80211_channel *c = ic->ic_curchan; 3950 int delta; 3951 3952 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3953 u_int chan = ieee80211_chan2ieee(ic, c); 3954 delta = sc->rssi_5ghz[rxchain]; 3955 3956 /* determine channel group */ 3957 if (chan <= 64) 3958 delta -= sc->lna[1]; 3959 else if (chan <= 128) 3960 delta -= sc->lna[2]; 3961 else 3962 delta -= sc->lna[3]; 3963 } else 3964 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3965 3966 return -12 - delta - rssi; 3967 } 3968 3969 static void 3970 run_rt5390_bbp_init(struct run_softc *sc) 3971 { 3972 u_int i; 3973 uint8_t bbp; 3974 3975 /* Apply maximum likelihood detection for 2 stream case. */ 3976 run_bbp_read(sc, 105, &bbp); 3977 if (sc->nrxchains > 1) 3978 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3979 3980 /* Avoid data lost and CRC error. */ 3981 run_bbp_read(sc, 4, &bbp); 3982 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3983 3984 if (sc->mac_ver == 0x5592) { 3985 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3986 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3987 rt5592_def_bbp[i].val); 3988 } 3989 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3990 run_bbp_write(sc, 195, i + 0x80); 3991 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3992 } 3993 } else { 3994 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3995 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3996 rt5390_def_bbp[i].val); 3997 } 3998 } 3999 if (sc->mac_ver == 0x5392) { 4000 run_bbp_write(sc, 88, 0x90); 4001 run_bbp_write(sc, 95, 0x9a); 4002 run_bbp_write(sc, 98, 0x12); 4003 run_bbp_write(sc, 106, 0x12); 4004 run_bbp_write(sc, 134, 0xd0); 4005 run_bbp_write(sc, 135, 0xf6); 4006 run_bbp_write(sc, 148, 0x84); 4007 } 4008 4009 run_bbp_read(sc, 152, &bbp); 4010 run_bbp_write(sc, 152, bbp | 0x80); 4011 4012 /* Fix BBP254 for RT5592C. */ 4013 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 4014 run_bbp_read(sc, 254, &bbp); 4015 run_bbp_write(sc, 254, bbp | 0x80); 4016 } 4017 4018 /* Disable hardware antenna diversity. */ 4019 if (sc->mac_ver == 0x5390) 4020 run_bbp_write(sc, 154, 0); 4021 4022 /* Initialize Rx CCK/OFDM frequency offset report. */ 4023 run_bbp_write(sc, 142, 1); 4024 run_bbp_write(sc, 143, 57); 4025 } 4026 4027 static int 4028 run_bbp_init(struct run_softc *sc) 4029 { 4030 int i, error, ntries; 4031 uint8_t bbp0; 4032 4033 /* wait for BBP to wake up */ 4034 for (ntries = 0; ntries < 20; ntries++) { 4035 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 4036 return error; 4037 if (bbp0 != 0 && bbp0 != 0xff) 4038 break; 4039 } 4040 if (ntries == 20) 4041 return ETIMEDOUT; 4042 4043 /* initialize BBP registers to default values */ 4044 if (sc->mac_ver >= 0x5390) 4045 run_rt5390_bbp_init(sc); 4046 else { 4047 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 4048 run_bbp_write(sc, rt2860_def_bbp[i].reg, 4049 rt2860_def_bbp[i].val); 4050 } 4051 } 4052 4053 if (sc->mac_ver == 0x3593) { 4054 run_bbp_write(sc, 79, 0x13); 4055 run_bbp_write(sc, 80, 0x05); 4056 run_bbp_write(sc, 81, 0x33); 4057 run_bbp_write(sc, 86, 0x46); 4058 run_bbp_write(sc, 137, 0x0f); 4059 } 4060 4061 /* fix BBP84 for RT2860E */ 4062 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 4063 run_bbp_write(sc, 84, 0x19); 4064 4065 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 4066 sc->mac_ver != 0x5592)) { 4067 run_bbp_write(sc, 79, 0x13); 4068 run_bbp_write(sc, 80, 0x05); 4069 run_bbp_write(sc, 81, 0x33); 4070 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 4071 run_bbp_write(sc, 69, 0x16); 4072 run_bbp_write(sc, 73, 0x12); 4073 } 4074 return 0; 4075 } 4076 4077 static int 4078 run_rt3070_rf_init(struct run_softc *sc) 4079 { 4080 uint32_t tmp; 4081 uint8_t rf, target, bbp4; 4082 int i; 4083 4084 run_rt3070_rf_read(sc, 30, &rf); 4085 /* toggle RF R30 bit 7 */ 4086 run_rt3070_rf_write(sc, 30, rf | 0x80); 4087 usbd_delay_ms(sc->sc_udev, 10); 4088 run_rt3070_rf_write(sc, 30, rf & ~0x80); 4089 4090 /* initialize RF registers to default value */ 4091 if (sc->mac_ver == 0x3572) { 4092 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 4093 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 4094 rt3572_def_rf[i].val); 4095 } 4096 } else { 4097 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 4098 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 4099 rt3070_def_rf[i].val); 4100 } 4101 } 4102 if (sc->mac_ver == 0x3572) { 4103 run_rt3070_rf_read(sc, 6, &rf); 4104 run_rt3070_rf_write(sc, 6, rf | 0x40); 4105 run_rt3070_rf_write(sc, 31, 0x14); 4106 4107 run_read(sc, RT3070_LDO_CFG0, &tmp); 4108 tmp &= ~0x1f000000; 4109 if (sc->mac_rev < 0x0211 && sc->patch_dac) 4110 tmp |= 0x0d000000; /* 1.3V */ 4111 else 4112 tmp |= 0x01000000; /* 1.2V */ 4113 run_write(sc, RT3070_LDO_CFG0, tmp); 4114 } else if (sc->mac_ver == 0x3071) { 4115 run_rt3070_rf_read(sc, 6, &rf); 4116 run_rt3070_rf_write(sc, 6, rf | 0x40); 4117 run_rt3070_rf_write(sc, 31, 0x14); 4118 4119 run_read(sc, RT3070_LDO_CFG0, &tmp); 4120 tmp &= ~0x1f000000; 4121 if (sc->mac_rev < 0x0211) 4122 tmp |= 0x0d000000; /* 1.35V */ 4123 else 4124 tmp |= 0x01000000; /* 1.2V */ 4125 run_write(sc, RT3070_LDO_CFG0, tmp); 4126 4127 /* patch LNA_PE_G1 */ 4128 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4129 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 4130 } else if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 4131 /* 4132 * Change voltage from 1.2V to 1.35V for RT3070. 4133 * The DAC issue (RT3070_LD0_CFG0) has been fixed 4134 * in RT3070(F). 4135 */ 4136 run_read(sc, RT3070_LDO_CFG0, &tmp); 4137 tmp = (tmp & ~0x0f000000) | 0x0d000000; 4138 run_write(sc, RT3070_LDO_CFG0, tmp); 4139 } 4140 4141 /* select 20MHz bandwidth */ 4142 run_rt3070_rf_read(sc, 31, &rf); 4143 run_rt3070_rf_write(sc, 31, rf & ~0x20); 4144 4145 /* calibrate filter for 20MHz bandwidth */ 4146 sc->rf24_20mhz = 0x1f; /* default value */ 4147 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 4148 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 4149 4150 /* select 40MHz bandwidth */ 4151 run_bbp_read(sc, 4, &bbp4); 4152 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 4153 run_rt3070_rf_read(sc, 31, &rf); 4154 run_rt3070_rf_write(sc, 31, rf | 0x20); 4155 4156 /* calibrate filter for 40MHz bandwidth */ 4157 sc->rf24_40mhz = 0x2f; /* default value */ 4158 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4159 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4160 4161 /* go back to 20MHz bandwidth */ 4162 run_bbp_read(sc, 4, &bbp4); 4163 run_bbp_write(sc, 4, bbp4 & ~0x18); 4164 4165 if (sc->mac_ver == 0x3572) { 4166 /* save default BBP registers 25 and 26 values */ 4167 run_bbp_read(sc, 25, &sc->bbp25); 4168 run_bbp_read(sc, 26, &sc->bbp26); 4169 } else if (sc->mac_rev < 0x0211) 4170 run_rt3070_rf_write(sc, 27, 0x03); 4171 4172 run_read(sc, RT3070_OPT_14, &tmp); 4173 run_write(sc, RT3070_OPT_14, tmp | 1); 4174 4175 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4176 run_rt3070_rf_read(sc, 17, &rf); 4177 rf &= ~RT3070_TX_LO1; 4178 if ((sc->mac_ver == 0x3070 || 4179 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4180 !sc->ext_2ghz_lna) 4181 rf |= 0x20; /* fix for long range Rx issue */ 4182 if (sc->txmixgain_2ghz >= 1) 4183 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4184 run_rt3070_rf_write(sc, 17, rf); 4185 } 4186 if (sc->mac_ver == 0x3071) { 4187 run_rt3070_rf_read(sc, 1, &rf); 4188 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4189 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4190 run_rt3070_rf_write(sc, 1, rf); 4191 4192 run_rt3070_rf_read(sc, 15, &rf); 4193 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4194 4195 run_rt3070_rf_read(sc, 20, &rf); 4196 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4197 4198 run_rt3070_rf_read(sc, 21, &rf); 4199 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4200 } 4201 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4202 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4203 run_rt3070_rf_read(sc, 27, &rf); 4204 rf &= ~0x77; 4205 if (sc->mac_rev < 0x0211) 4206 rf |= 0x03; 4207 run_rt3070_rf_write(sc, 27, rf); 4208 } 4209 return 0; 4210 } 4211 4212 static int 4213 run_rt3593_rf_init(struct run_softc *sc) 4214 { 4215 uint32_t tmp; 4216 uint8_t rf; 4217 int i; 4218 4219 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4220 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4221 tmp &= ~(1 << 4 | 1 << 7); 4222 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4223 4224 /* Initialize RF registers to default value. */ 4225 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4226 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4227 rt3593_def_rf[i].val); 4228 } 4229 4230 /* Toggle RF R2 to initiate calibration. */ 4231 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4232 4233 /* Initialize RF frequency offset. */ 4234 run_adjust_freq_offset(sc); 4235 4236 run_rt3070_rf_read(sc, 18, &rf); 4237 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4238 4239 /* 4240 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4241 * decrease voltage back to 1.2V. 4242 */ 4243 run_read(sc, RT3070_LDO_CFG0, &tmp); 4244 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4245 run_write(sc, RT3070_LDO_CFG0, tmp); 4246 usbd_delay_ms(sc->sc_udev, 1); 4247 tmp = (tmp & ~0x1f000000) | 0x01000000; 4248 run_write(sc, RT3070_LDO_CFG0, tmp); 4249 4250 sc->rf24_20mhz = 0x1f; 4251 sc->rf24_40mhz = 0x2f; 4252 4253 /* Save default BBP registers 25 and 26 values. */ 4254 run_bbp_read(sc, 25, &sc->bbp25); 4255 run_bbp_read(sc, 26, &sc->bbp26); 4256 4257 run_read(sc, RT3070_OPT_14, &tmp); 4258 run_write(sc, RT3070_OPT_14, tmp | 1); 4259 return 0; 4260 } 4261 4262 static int 4263 run_rt5390_rf_init(struct run_softc *sc) 4264 { 4265 uint32_t tmp; 4266 uint8_t rf; 4267 int i; 4268 4269 /* Toggle RF R2 to initiate calibration. */ 4270 if (sc->mac_ver == 0x5390) { 4271 run_rt3070_rf_read(sc, 2, &rf); 4272 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4273 usbd_delay_ms(sc->sc_udev, 10); 4274 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4275 } else { 4276 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4277 usbd_delay_ms(sc->sc_udev, 10); 4278 } 4279 4280 /* Initialize RF registers to default value. */ 4281 if (sc->mac_ver == 0x5592) { 4282 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4283 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4284 rt5592_def_rf[i].val); 4285 } 4286 /* Initialize RF frequency offset. */ 4287 run_adjust_freq_offset(sc); 4288 } else if (sc->mac_ver == 0x5392) { 4289 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4290 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4291 rt5392_def_rf[i].val); 4292 } 4293 if (sc->mac_rev >= 0x0223) { 4294 run_rt3070_rf_write(sc, 23, 0x0f); 4295 run_rt3070_rf_write(sc, 24, 0x3e); 4296 run_rt3070_rf_write(sc, 51, 0x32); 4297 run_rt3070_rf_write(sc, 53, 0x22); 4298 run_rt3070_rf_write(sc, 56, 0xc1); 4299 run_rt3070_rf_write(sc, 59, 0x0f); 4300 } 4301 } else { 4302 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4303 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4304 rt5390_def_rf[i].val); 4305 } 4306 if (sc->mac_rev >= 0x0502) { 4307 run_rt3070_rf_write(sc, 6, 0xe0); 4308 run_rt3070_rf_write(sc, 25, 0x80); 4309 run_rt3070_rf_write(sc, 46, 0x73); 4310 run_rt3070_rf_write(sc, 53, 0x00); 4311 run_rt3070_rf_write(sc, 56, 0x42); 4312 run_rt3070_rf_write(sc, 61, 0xd1); 4313 } 4314 } 4315 4316 sc->rf24_20mhz = 0x1f; /* default value */ 4317 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4318 4319 if (sc->mac_rev < 0x0211) 4320 run_rt3070_rf_write(sc, 27, 0x3); 4321 4322 run_read(sc, RT3070_OPT_14, &tmp); 4323 run_write(sc, RT3070_OPT_14, tmp | 1); 4324 return 0; 4325 } 4326 4327 static int 4328 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4329 uint8_t *val) 4330 { 4331 uint8_t rf22, rf24; 4332 uint8_t bbp55_pb, bbp55_sb, delta; 4333 int ntries; 4334 4335 /* program filter */ 4336 run_rt3070_rf_read(sc, 24, &rf24); 4337 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4338 run_rt3070_rf_write(sc, 24, rf24); 4339 4340 /* enable baseband loopback mode */ 4341 run_rt3070_rf_read(sc, 22, &rf22); 4342 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4343 4344 /* set power and frequency of passband test tone */ 4345 run_bbp_write(sc, 24, 0x00); 4346 for (ntries = 0; ntries < 100; ntries++) { 4347 /* transmit test tone */ 4348 run_bbp_write(sc, 25, 0x90); 4349 usbd_delay_ms(sc->sc_udev, 10); 4350 /* read received power */ 4351 run_bbp_read(sc, 55, &bbp55_pb); 4352 if (bbp55_pb != 0) 4353 break; 4354 } 4355 if (ntries == 100) 4356 return ETIMEDOUT; 4357 4358 /* set power and frequency of stopband test tone */ 4359 run_bbp_write(sc, 24, 0x06); 4360 for (ntries = 0; ntries < 100; ntries++) { 4361 /* transmit test tone */ 4362 run_bbp_write(sc, 25, 0x90); 4363 usbd_delay_ms(sc->sc_udev, 10); 4364 /* read received power */ 4365 run_bbp_read(sc, 55, &bbp55_sb); 4366 4367 delta = bbp55_pb - bbp55_sb; 4368 if (delta > target) 4369 break; 4370 4371 /* reprogram filter */ 4372 rf24++; 4373 run_rt3070_rf_write(sc, 24, rf24); 4374 } 4375 if (ntries < 100) { 4376 if (rf24 != init) 4377 rf24--; /* backtrack */ 4378 *val = rf24; 4379 run_rt3070_rf_write(sc, 24, rf24); 4380 } 4381 4382 /* restore initial state */ 4383 run_bbp_write(sc, 24, 0x00); 4384 4385 /* disable baseband loopback mode */ 4386 run_rt3070_rf_read(sc, 22, &rf22); 4387 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4388 4389 return 0; 4390 } 4391 4392 static void 4393 run_rt3070_rf_setup(struct run_softc *sc) 4394 { 4395 uint8_t bbp, rf; 4396 int i; 4397 4398 if (sc->mac_ver == 0x3572) { 4399 /* enable DC filter */ 4400 if (sc->mac_rev >= 0x0201) 4401 run_bbp_write(sc, 103, 0xc0); 4402 4403 run_bbp_read(sc, 138, &bbp); 4404 if (sc->ntxchains == 1) 4405 bbp |= 0x20; /* turn off DAC1 */ 4406 if (sc->nrxchains == 1) 4407 bbp &= ~0x02; /* turn off ADC1 */ 4408 run_bbp_write(sc, 138, bbp); 4409 4410 if (sc->mac_rev >= 0x0211) { 4411 /* improve power consumption */ 4412 run_bbp_read(sc, 31, &bbp); 4413 run_bbp_write(sc, 31, bbp & ~0x03); 4414 } 4415 4416 run_rt3070_rf_read(sc, 16, &rf); 4417 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4418 run_rt3070_rf_write(sc, 16, rf); 4419 } else if (sc->mac_ver == 0x3071) { 4420 /* enable DC filter */ 4421 if (sc->mac_rev >= 0x0201) 4422 run_bbp_write(sc, 103, 0xc0); 4423 4424 run_bbp_read(sc, 138, &bbp); 4425 if (sc->ntxchains == 1) 4426 bbp |= 0x20; /* turn off DAC1 */ 4427 if (sc->nrxchains == 1) 4428 bbp &= ~0x02; /* turn off ADC1 */ 4429 run_bbp_write(sc, 138, bbp); 4430 4431 if (sc->mac_rev >= 0x0211) { 4432 /* improve power consumption */ 4433 run_bbp_read(sc, 31, &bbp); 4434 run_bbp_write(sc, 31, bbp & ~0x03); 4435 } 4436 4437 run_write(sc, RT2860_TX_SW_CFG1, 0); 4438 if (sc->mac_rev < 0x0211) { 4439 run_write(sc, RT2860_TX_SW_CFG2, 4440 sc->patch_dac ? 0x2c : 0x0f); 4441 } else 4442 run_write(sc, RT2860_TX_SW_CFG2, 0); 4443 } else if (sc->mac_ver == 0x3070) { 4444 if (sc->mac_rev >= 0x0201) { 4445 /* enable DC filter */ 4446 run_bbp_write(sc, 103, 0xc0); 4447 4448 /* improve power consumption */ 4449 run_bbp_read(sc, 31, &bbp); 4450 run_bbp_write(sc, 31, bbp & ~0x03); 4451 } 4452 4453 if (sc->mac_rev < 0x0211) { 4454 run_write(sc, RT2860_TX_SW_CFG1, 0); 4455 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4456 } else 4457 run_write(sc, RT2860_TX_SW_CFG2, 0); 4458 } 4459 4460 /* initialize RF registers from ROM for >=RT3071*/ 4461 if (sc->mac_ver >= 0x3071) { 4462 for (i = 0; i < 10; i++) { 4463 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4464 continue; 4465 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4466 } 4467 } 4468 } 4469 4470 static void 4471 run_rt3593_rf_setup(struct run_softc *sc) 4472 { 4473 uint8_t bbp, rf; 4474 4475 if (sc->mac_rev >= 0x0211) { 4476 /* Enable DC filter. */ 4477 run_bbp_write(sc, 103, 0xc0); 4478 } 4479 run_write(sc, RT2860_TX_SW_CFG1, 0); 4480 if (sc->mac_rev < 0x0211) { 4481 run_write(sc, RT2860_TX_SW_CFG2, 4482 sc->patch_dac ? 0x2c : 0x0f); 4483 } else 4484 run_write(sc, RT2860_TX_SW_CFG2, 0); 4485 4486 run_rt3070_rf_read(sc, 50, &rf); 4487 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4488 4489 run_rt3070_rf_read(sc, 51, &rf); 4490 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4491 ((sc->txmixgain_2ghz & 0x07) << 2); 4492 run_rt3070_rf_write(sc, 51, rf); 4493 4494 run_rt3070_rf_read(sc, 38, &rf); 4495 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4496 4497 run_rt3070_rf_read(sc, 39, &rf); 4498 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4499 4500 run_rt3070_rf_read(sc, 1, &rf); 4501 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4502 4503 run_rt3070_rf_read(sc, 30, &rf); 4504 rf = (rf & ~0x18) | 0x10; 4505 run_rt3070_rf_write(sc, 30, rf); 4506 4507 /* Apply maximum likelihood detection for 2 stream case. */ 4508 run_bbp_read(sc, 105, &bbp); 4509 if (sc->nrxchains > 1) 4510 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4511 4512 /* Avoid data lost and CRC error. */ 4513 run_bbp_read(sc, 4, &bbp); 4514 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4515 4516 run_bbp_write(sc, 92, 0x02); 4517 run_bbp_write(sc, 82, 0x82); 4518 run_bbp_write(sc, 106, 0x05); 4519 run_bbp_write(sc, 104, 0x92); 4520 run_bbp_write(sc, 88, 0x90); 4521 run_bbp_write(sc, 148, 0xc8); 4522 run_bbp_write(sc, 47, 0x48); 4523 run_bbp_write(sc, 120, 0x50); 4524 4525 run_bbp_write(sc, 163, 0x9d); 4526 4527 /* SNR mapping. */ 4528 run_bbp_write(sc, 142, 0x06); 4529 run_bbp_write(sc, 143, 0xa0); 4530 run_bbp_write(sc, 142, 0x07); 4531 run_bbp_write(sc, 143, 0xa1); 4532 run_bbp_write(sc, 142, 0x08); 4533 run_bbp_write(sc, 143, 0xa2); 4534 4535 run_bbp_write(sc, 31, 0x08); 4536 run_bbp_write(sc, 68, 0x0b); 4537 run_bbp_write(sc, 105, 0x04); 4538 } 4539 4540 static void 4541 run_rt5390_rf_setup(struct run_softc *sc) 4542 { 4543 uint8_t bbp, rf; 4544 4545 if (sc->mac_rev >= 0x0211) { 4546 /* Enable DC filter. */ 4547 run_bbp_write(sc, 103, 0xc0); 4548 4549 if (sc->mac_ver != 0x5592) { 4550 /* Improve power consumption. */ 4551 run_bbp_read(sc, 31, &bbp); 4552 run_bbp_write(sc, 31, bbp & ~0x03); 4553 } 4554 } 4555 4556 run_bbp_read(sc, 138, &bbp); 4557 if (sc->ntxchains == 1) 4558 bbp |= 0x20; /* turn off DAC1 */ 4559 if (sc->nrxchains == 1) 4560 bbp &= ~0x02; /* turn off ADC1 */ 4561 run_bbp_write(sc, 138, bbp); 4562 4563 run_rt3070_rf_read(sc, 38, &rf); 4564 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4565 4566 run_rt3070_rf_read(sc, 39, &rf); 4567 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4568 4569 /* Avoid data lost and CRC error. */ 4570 run_bbp_read(sc, 4, &bbp); 4571 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4572 4573 run_rt3070_rf_read(sc, 30, &rf); 4574 rf = (rf & ~0x18) | 0x10; 4575 run_rt3070_rf_write(sc, 30, rf); 4576 4577 if (sc->mac_ver != 0x5592) { 4578 run_write(sc, RT2860_TX_SW_CFG1, 0); 4579 if (sc->mac_rev < 0x0211) { 4580 run_write(sc, RT2860_TX_SW_CFG2, 4581 sc->patch_dac ? 0x2c : 0x0f); 4582 } else 4583 run_write(sc, RT2860_TX_SW_CFG2, 0); 4584 } 4585 } 4586 4587 static int 4588 run_txrx_enable(struct run_softc *sc) 4589 { 4590 uint32_t tmp; 4591 int error, ntries; 4592 4593 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4594 for (ntries = 0; ntries < 200; ntries++) { 4595 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4596 return error; 4597 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4598 break; 4599 usbd_delay_ms(sc->sc_udev, 50); 4600 } 4601 if (ntries == 200) 4602 return ETIMEDOUT; 4603 4604 usbd_delay_ms(sc->sc_udev, 50); 4605 4606 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4607 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4608 4609 /* enable Rx bulk aggregation (set timeout and limit) */ 4610 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4611 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4612 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4613 4614 /* set Rx filter */ 4615 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4616 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4617 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4618 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4619 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4620 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4621 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4622 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4623 } 4624 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4625 4626 run_write(sc, RT2860_MAC_SYS_CTRL, 4627 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4628 4629 return 0; 4630 } 4631 4632 static int 4633 run_adjust_freq_offset(struct run_softc *sc) 4634 { 4635 uint8_t rf, tmp; 4636 4637 run_rt3070_rf_read(sc, 17, &rf); 4638 tmp = rf; 4639 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4640 rf = MIN(rf, 0x5f); 4641 4642 if (tmp != rf) 4643 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4644 4645 return 0; 4646 } 4647 4648 static int 4649 run_init(struct ifnet *ifp) 4650 { 4651 struct run_softc *sc = ifp->if_softc; 4652 struct ieee80211com *ic = &sc->sc_ic; 4653 uint32_t tmp; 4654 uint8_t bbp1, bbp3; 4655 int i, error, qid, ridx, ntries; 4656 usbd_status status; 4657 4658 for (ntries = 0; ntries < 100; ntries++) { 4659 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4660 goto fail; 4661 if (tmp != 0 && tmp != 0xffffffff) 4662 break; 4663 usbd_delay_ms(sc->sc_udev, 10); 4664 } 4665 if (ntries == 100) { 4666 error = ETIMEDOUT; 4667 goto fail; 4668 } 4669 4670 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4671 (error = run_load_microcode(sc)) != 0) { 4672 device_printf(sc->sc_dev, 4673 "could not load 8051 microcode\n"); 4674 goto fail; 4675 } 4676 4677 if (ifp->if_flags & IFF_RUNNING) 4678 run_stop(ifp, 0); 4679 4680 /* init host command ring */ 4681 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4682 4683 /* init Tx rings (4 EDCAs) */ 4684 for (qid = 0; qid < 4; qid++) { 4685 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4686 goto fail; 4687 } 4688 /* init Rx ring */ 4689 if ((error = run_alloc_rx_ring(sc)) != 0) 4690 goto fail; 4691 4692 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4693 run_set_macaddr(sc, ic->ic_myaddr); 4694 4695 for (ntries = 0; ntries < 100; ntries++) { 4696 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4697 goto fail; 4698 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4699 break; 4700 usbd_delay_ms(sc->sc_udev, 10); 4701 } 4702 if (ntries == 100) { 4703 device_printf(sc->sc_dev, 4704 "timeout waiting for DMA engine\n"); 4705 error = ETIMEDOUT; 4706 goto fail; 4707 } 4708 tmp &= 0xff0; 4709 tmp |= RT2860_TX_WB_DDONE; 4710 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4711 4712 /* turn off PME_OEN to solve high-current issue */ 4713 run_read(sc, RT2860_SYS_CTRL, &tmp); 4714 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4715 4716 run_write(sc, RT2860_MAC_SYS_CTRL, 4717 RT2860_BBP_HRST | RT2860_MAC_SRST); 4718 run_write(sc, RT2860_USB_DMA_CFG, 0); 4719 4720 if ((error = run_reset(sc)) != 0) { 4721 device_printf(sc->sc_dev, "could not reset chipset\n"); 4722 goto fail; 4723 } 4724 4725 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4726 4727 /* init Tx power for all Tx rates (from EEPROM) */ 4728 for (ridx = 0; ridx < 5; ridx++) { 4729 if (sc->txpow20mhz[ridx] == 0xffffffff) 4730 continue; 4731 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4732 } 4733 4734 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4735 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4736 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4737 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4738 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4739 4740 if (sc->mac_ver >= 0x5390) { 4741 run_write(sc, RT2860_TX_SW_CFG0, 4742 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4743 if (sc->mac_ver >= 0x5392) { 4744 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4745 if (sc->mac_ver == 0x5592) { 4746 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4747 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4748 } else { 4749 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4750 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4751 } 4752 } 4753 } else if (sc->mac_ver >= 0x3593) { 4754 run_write(sc, RT2860_TX_SW_CFG0, 4755 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4756 } else if (sc->mac_ver >= 0x3070) { 4757 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4758 run_write(sc, RT2860_TX_SW_CFG0, 4759 4 << RT2860_DLY_PAPE_EN_SHIFT); 4760 } 4761 4762 /* wait while MAC is busy */ 4763 for (ntries = 0; ntries < 100; ntries++) { 4764 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4765 goto fail; 4766 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4767 break; 4768 DELAY(1000); 4769 } 4770 if (ntries == 100) { 4771 error = ETIMEDOUT; 4772 goto fail; 4773 } 4774 4775 /* clear Host to MCU mailbox */ 4776 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4777 run_write(sc, RT2860_H2M_MAILBOX, 0); 4778 usbd_delay_ms(sc->sc_udev, 10); 4779 4780 if ((error = run_bbp_init(sc)) != 0) { 4781 device_printf(sc->sc_dev, "could not initialize BBP\n"); 4782 goto fail; 4783 } 4784 4785 /* abort TSF synchronization */ 4786 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4787 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4788 RT2860_TBTT_TIMER_EN); 4789 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4790 4791 /* clear RX WCID search table */ 4792 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4793 /* clear Pair-wise key table */ 4794 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4795 /* clear IV/EIV table */ 4796 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4797 /* clear WCID attribute table */ 4798 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4799 /* clear shared key table */ 4800 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4801 /* clear shared key mode */ 4802 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4803 4804 /* clear RX WCID search table */ 4805 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4806 /* clear WCID attribute table */ 4807 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4808 4809 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4810 tmp = (tmp & ~0xff) | 0x1e; 4811 run_write(sc, RT2860_US_CYC_CNT, tmp); 4812 4813 if (sc->mac_rev != 0x0101) 4814 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4815 4816 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4817 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4818 4819 /* write vendor-specific BBP values (from EEPROM) */ 4820 if (sc->mac_ver < 0x3593) { 4821 for (i = 0; i < 10; i++) { 4822 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4823 continue; 4824 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4825 } 4826 } 4827 4828 /* select Main antenna for 1T1R devices */ 4829 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4830 run_set_rx_antenna(sc, 0); 4831 4832 /* send LEDs operating mode to microcontroller */ 4833 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4834 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4835 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4836 4837 if (sc->mac_ver >= 0x5390) 4838 run_rt5390_rf_init(sc); 4839 else if (sc->mac_ver == 0x3593) 4840 run_rt3593_rf_init(sc); 4841 else if (sc->mac_ver >= 0x3070) 4842 run_rt3070_rf_init(sc); 4843 4844 /* disable non-existing Rx chains */ 4845 run_bbp_read(sc, 3, &bbp3); 4846 bbp3 &= ~(1 << 3 | 1 << 4); 4847 if (sc->nrxchains == 2) 4848 bbp3 |= 1 << 3; 4849 else if (sc->nrxchains == 3) 4850 bbp3 |= 1 << 4; 4851 run_bbp_write(sc, 3, bbp3); 4852 4853 /* disable non-existing Tx chains */ 4854 run_bbp_read(sc, 1, &bbp1); 4855 if (sc->ntxchains == 1) 4856 bbp1 &= ~(1 << 3 | 1 << 4); 4857 run_bbp_write(sc, 1, bbp1); 4858 4859 if (sc->mac_ver >= 0x5390) 4860 run_rt5390_rf_setup(sc); 4861 else if (sc->mac_ver == 0x3593) 4862 run_rt3593_rf_setup(sc); 4863 else if (sc->mac_ver >= 0x3070) 4864 run_rt3070_rf_setup(sc); 4865 4866 /* select default channel */ 4867 run_set_chan(sc, ic->ic_curchan); 4868 4869 /* setup initial protection mode */ 4870 run_updateprot(sc); 4871 4872 /* turn radio LED on */ 4873 run_set_leds(sc, RT2860_LED_RADIO); 4874 4875 #ifdef RUN_HWCRYPTO 4876 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4877 /* install WEP keys */ 4878 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4879 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4880 NULL); 4881 } 4882 #endif 4883 4884 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4885 struct run_rx_data *data = &sc->rxq.data[i]; 4886 4887 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4888 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4889 status = usbd_transfer(data->xfer); 4890 if (status != USBD_NORMAL_COMPLETION && 4891 status != USBD_IN_PROGRESS) { 4892 device_printf(sc->sc_dev, "queuing rx failed: %s\n", 4893 usbd_errstr(status)); 4894 error = EIO; 4895 goto fail; 4896 } 4897 } 4898 4899 if ((error = run_txrx_enable(sc)) != 0) 4900 goto fail; 4901 4902 ifp->if_flags &= ~IFF_OACTIVE; 4903 ifp->if_flags |= IFF_RUNNING; 4904 4905 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4906 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4907 else 4908 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4909 4910 if (error != 0) 4911 fail: run_stop(ifp, 1); 4912 return error; 4913 } 4914 4915 static void 4916 run_stop(struct ifnet *ifp, int disable) 4917 { 4918 struct run_softc *sc = ifp->if_softc; 4919 struct ieee80211com *ic = &sc->sc_ic; 4920 uint32_t tmp; 4921 int ntries, qid; 4922 4923 if (ifp->if_flags & IFF_RUNNING) 4924 run_set_leds(sc, 0); /* turn all LEDs off */ 4925 4926 sc->sc_tx_timer = 0; 4927 ifp->if_timer = 0; 4928 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4929 4930 callout_stop(&sc->scan_to); 4931 callout_stop(&sc->calib_to); 4932 4933 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4934 /* wait for all queued asynchronous commands to complete */ 4935 while (sc->cmdq.queued > 0) 4936 tsleep(&sc->cmdq, 0, "cmdq", 0); 4937 4938 /* disable Tx/Rx */ 4939 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4940 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4941 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4942 4943 /* wait for pending Tx to complete */ 4944 for (ntries = 0; ntries < 100; ntries++) { 4945 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4946 break; 4947 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4948 break; 4949 } 4950 DELAY(1000); 4951 run_write(sc, RT2860_USB_DMA_CFG, 0); 4952 4953 /* reset adapter */ 4954 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4955 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4956 4957 /* reset Tx and Rx rings */ 4958 sc->qfullmsk = 0; 4959 for (qid = 0; qid < 4; qid++) 4960 run_free_tx_ring(sc, qid); 4961 run_free_rx_ring(sc); 4962 } 4963 4964 #ifndef IEEE80211_STA_ONLY 4965 static int 4966 run_setup_beacon(struct run_softc *sc) 4967 { 4968 struct ieee80211com *ic = &sc->sc_ic; 4969 struct rt2860_txwi txwi; 4970 struct mbuf *m; 4971 uint16_t txwisize; 4972 int ridx; 4973 4974 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4975 return ENOBUFS; 4976 4977 memset(&txwi, 0, sizeof(txwi)); 4978 txwi.wcid = 0xff; 4979 txwi.len = htole16(m->m_pkthdr.len); 4980 /* send beacons at the lowest available rate */ 4981 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4982 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4983 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4984 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4985 txwi.phy |= htole16(RT2860_PHY_OFDM); 4986 txwi.txop = RT2860_TX_TXOP_HT; 4987 txwi.flags = RT2860_TX_TS; 4988 4989 txwisize = (sc->mac_ver == 0x5592) ? 4990 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4991 run_write_region_1(sc, RT2860_BCN_BASE(0), 4992 (uint8_t *)&txwi, txwisize); 4993 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4994 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4995 4996 m_freem(m); 4997 4998 return 0; 4999 } 5000 #endif 5001 5002 MODULE(MODULE_CLASS_DRIVER, if_run, NULL); 5003 5004 #ifdef _MODULE 5005 #include "ioconf.c" 5006 #endif 5007 5008 static int 5009 if_run_modcmd(modcmd_t cmd, void *arg) 5010 { 5011 int error = 0; 5012 5013 switch (cmd) { 5014 case MODULE_CMD_INIT: 5015 #ifdef _MODULE 5016 error = config_init_component(cfdriver_ioconf_run, 5017 cfattach_ioconf_run, cfdata_ioconf_run); 5018 #endif 5019 return error; 5020 case MODULE_CMD_FINI: 5021 #ifdef _MODULE 5022 error = config_fini_component(cfdriver_ioconf_run, 5023 cfattach_ioconf_run, cfdata_ioconf_run); 5024 #endif 5025 return error; 5026 default: 5027 return ENOTTY; 5028 } 5029 } 5030