1 /* $NetBSD: if_run.c,v 1.39 2020/03/15 23:04:51 thorpej Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.39 2020/03/15 23:04:51 thorpej Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 #include <sys/atomic.h> 45 46 #include <sys/bus.h> 47 #include <machine/endian.h> 48 #include <sys/intr.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/firmload.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usbdi_util.h> 68 #include <dev/usb/usbdevs.h> 69 70 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 71 #include <dev/usb/if_runvar.h> 72 73 #ifdef RUN_DEBUG 74 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 76 int run_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 83 84 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 85 static const struct usb_devno run_devs[] = { 86 USB_ID(ABOCOM, RT2770), 87 USB_ID(ABOCOM, RT2870), 88 USB_ID(ABOCOM, RT3070), 89 USB_ID(ABOCOM, RT3071), 90 USB_ID(ABOCOM, RT3072), 91 USB_ID(ABOCOM2, RT2870_1), 92 USB_ID(ACCTON, RT2770), 93 USB_ID(ACCTON, RT2870_1), 94 USB_ID(ACCTON, RT2870_2), 95 USB_ID(ACCTON, RT2870_3), 96 USB_ID(ACCTON, RT2870_4), 97 USB_ID(ACCTON, RT2870_5), 98 USB_ID(ACCTON, RT3070), 99 USB_ID(ACCTON, RT3070_1), 100 USB_ID(ACCTON, RT3070_2), 101 USB_ID(ACCTON, RT3070_3), 102 USB_ID(ACCTON, RT3070_4), 103 USB_ID(ACCTON, RT3070_5), 104 USB_ID(ACCTON, RT3070_6), 105 USB_ID(AIRTIES, RT3070), 106 USB_ID(AIRTIES, RT3070_2), 107 USB_ID(ALLWIN, RT2070), 108 USB_ID(ALLWIN, RT2770), 109 USB_ID(ALLWIN, RT2870), 110 USB_ID(ALLWIN, RT3070), 111 USB_ID(ALLWIN, RT3071), 112 USB_ID(ALLWIN, RT3072), 113 USB_ID(ALLWIN, RT3572), 114 USB_ID(AMIGO, RT2870_1), 115 USB_ID(AMIGO, RT2870_2), 116 USB_ID(AMIT, CGWLUSB2GNR), 117 USB_ID(AMIT, RT2870_1), 118 USB_ID(AMIT2, RT2870), 119 USB_ID(ASUSTEK, RT2870_1), 120 USB_ID(ASUSTEK, RT2870_2), 121 USB_ID(ASUSTEK, RT2870_3), 122 USB_ID(ASUSTEK, RT2870_4), 123 USB_ID(ASUSTEK, RT2870_5), 124 USB_ID(ASUSTEK, RT3070), 125 USB_ID(ASUSTEK, RT3070_1), 126 USB_ID(ASUSTEK, USBN53), 127 USB_ID(ASUSTEK, USBN66), 128 USB_ID(ASUSTEK2, USBN11), 129 USB_ID(AZUREWAVE, RT2870_1), 130 USB_ID(AZUREWAVE, RT2870_2), 131 USB_ID(AZUREWAVE, RT3070), 132 USB_ID(AZUREWAVE, RT3070_2), 133 USB_ID(AZUREWAVE, RT3070_3), 134 USB_ID(AZUREWAVE, RT3070_4), 135 USB_ID(AZUREWAVE, RT3070_5), 136 USB_ID(BELKIN, F5D8053V3), 137 USB_ID(BELKIN, F5D8055), 138 USB_ID(BELKIN, F5D8055V2), 139 USB_ID(BELKIN, F6D4050V1), 140 USB_ID(BELKIN, F6D4050V2), 141 USB_ID(BELKIN, F7D1101V2), 142 USB_ID(BELKIN, RT2870_1), 143 USB_ID(BELKIN, RT2870_2), 144 USB_ID(BELKIN, RTL8192CU_2), 145 USB_ID(BEWAN, RT3070), 146 USB_ID(CISCOLINKSYS, AE1000), 147 USB_ID(CISCOLINKSYS, AM10), 148 USB_ID(CISCOLINKSYS2, RT3070), 149 USB_ID(CISCOLINKSYS3, RT3070), 150 USB_ID(CONCEPTRONIC, RT2870_1), 151 USB_ID(CONCEPTRONIC, RT2870_2), 152 USB_ID(CONCEPTRONIC, RT2870_3), 153 USB_ID(CONCEPTRONIC, RT2870_4), 154 USB_ID(CONCEPTRONIC, RT2870_5), 155 USB_ID(CONCEPTRONIC, RT2870_6), 156 USB_ID(CONCEPTRONIC, RT2870_7), 157 USB_ID(CONCEPTRONIC, RT2870_8), 158 USB_ID(CONCEPTRONIC, RT3070_1), 159 USB_ID(CONCEPTRONIC, RT3070_2), 160 USB_ID(CONCEPTRONIC, RT3070_3), 161 USB_ID(COREGA, CGWLUSB300GNM), 162 USB_ID(COREGA, RT2870_1), 163 USB_ID(COREGA, RT2870_2), 164 USB_ID(COREGA, RT2870_3), 165 USB_ID(COREGA, RT3070), 166 USB_ID(CYBERTAN, RT2870), 167 USB_ID(DLINK, RT2870), 168 USB_ID(DLINK, RT3072), 169 USB_ID(DLINK, DWA127), 170 USB_ID(DLINK, DWA140B3), 171 USB_ID(DLINK, DWA160B2), 172 USB_ID(DLINK, DWA162), 173 USB_ID(DLINK2, DWA130), 174 USB_ID(DLINK2, RT2870_1), 175 USB_ID(DLINK2, RT2870_2), 176 USB_ID(DLINK2, RT3070_1), 177 USB_ID(DLINK2, RT3070_2), 178 USB_ID(DLINK2, RT3070_3), 179 USB_ID(DLINK2, RT3070_4), 180 USB_ID(DLINK2, RT3070_5), 181 USB_ID(DLINK2, RT3072), 182 USB_ID(DLINK2, RT3072_1), 183 USB_ID(DVICO, RT3070), 184 USB_ID(EDIMAX, EW7717), 185 USB_ID(EDIMAX, EW7718), 186 USB_ID(EDIMAX, EW7722UTN), 187 USB_ID(EDIMAX, RT2870_1), 188 USB_ID(ENCORE, RT3070), 189 USB_ID(ENCORE, RT3070_2), 190 USB_ID(ENCORE, RT3070_3), 191 USB_ID(GIGABYTE, GNWB31N), 192 USB_ID(GIGABYTE, GNWB32L), 193 USB_ID(GIGABYTE, RT2870_1), 194 USB_ID(GIGASET, RT3070_1), 195 USB_ID(GIGASET, RT3070_2), 196 USB_ID(GUILLEMOT, HWNU300), 197 USB_ID(HAWKING, HWUN2), 198 USB_ID(HAWKING, RT2870_1), 199 USB_ID(HAWKING, RT2870_2), 200 USB_ID(HAWKING, RT2870_3), 201 USB_ID(HAWKING, RT2870_4), 202 USB_ID(HAWKING, RT2870_5), 203 USB_ID(HAWKING, RT3070), 204 USB_ID(IODATA, RT3072_1), 205 USB_ID(IODATA, RT3072_2), 206 USB_ID(IODATA, RT3072_3), 207 USB_ID(IODATA, RT3072_4), 208 USB_ID(LINKSYS4, RT3070), 209 USB_ID(LINKSYS4, WUSB100), 210 USB_ID(LINKSYS4, WUSB54GC_3), 211 USB_ID(LINKSYS4, WUSB600N), 212 USB_ID(LINKSYS4, WUSB600NV2), 213 USB_ID(LOGITEC, LANW300NU2), 214 USB_ID(LOGITEC, LANW300NU2S), 215 USB_ID(LOGITEC, LAN_W300ANU2), 216 USB_ID(LOGITEC, LAN_W450ANU2E), 217 USB_ID(LOGITEC, RT2870_1), 218 USB_ID(LOGITEC, RT2870_2), 219 USB_ID(LOGITEC, RT2870_3), 220 USB_ID(LOGITEC, RT3020), 221 USB_ID(MELCO, RT2870_1), 222 USB_ID(MELCO, RT2870_2), 223 USB_ID(MELCO, WLIUCAG300N), 224 USB_ID(MELCO, WLIUCG300N), 225 USB_ID(MELCO, WLIUCG301N), 226 USB_ID(MELCO, WLIUCGN), 227 USB_ID(MELCO, WLIUCGNHP), 228 USB_ID(MELCO, WLIUCGNM), 229 USB_ID(MELCO, WLIUCGNM2T), 230 USB_ID(MOTOROLA4, RT2770), 231 USB_ID(MOTOROLA4, RT3070), 232 USB_ID(MSI, RT3070), 233 USB_ID(MSI, RT3070_2), 234 USB_ID(MSI, RT3070_3), 235 USB_ID(MSI, RT3070_4), 236 USB_ID(MSI, RT3070_5), 237 USB_ID(MSI, RT3070_6), 238 USB_ID(MSI, RT3070_7), 239 USB_ID(MSI, RT3070_8), 240 USB_ID(MSI, RT3070_9), 241 USB_ID(MSI, RT3070_10), 242 USB_ID(MSI, RT3070_11), 243 USB_ID(MSI, RT3070_12), 244 USB_ID(MSI, RT3070_13), 245 USB_ID(MSI, RT3070_14), 246 USB_ID(MSI, RT3070_15), 247 USB_ID(OVISLINK, RT3071), 248 USB_ID(OVISLINK, RT3072), 249 USB_ID(PARA, RT3070), 250 USB_ID(PEGATRON, RT2870), 251 USB_ID(PEGATRON, RT3070), 252 USB_ID(PEGATRON, RT3070_2), 253 USB_ID(PEGATRON, RT3070_3), 254 USB_ID(PEGATRON, RT3072), 255 USB_ID(PHILIPS, RT2870), 256 USB_ID(PLANEX2, GWUS300MINIS), 257 USB_ID(PLANEX2, GWUSMICRO300), 258 USB_ID(PLANEX2, GWUSMICRON), 259 USB_ID(PLANEX2, GWUS300MINIX), 260 USB_ID(PLANEX2, RT3070), 261 USB_ID(QCOM, RT2870), 262 USB_ID(QUANTA, RT3070), 263 USB_ID(RALINK, RT2070), 264 USB_ID(RALINK, RT2770), 265 USB_ID(RALINK, RT2870), 266 USB_ID(RALINK, RT3070), 267 USB_ID(RALINK, RT3071), 268 USB_ID(RALINK, RT3072), 269 USB_ID(RALINK, RT3370), 270 USB_ID(RALINK, RT3572), 271 USB_ID(RALINK, RT3573), 272 USB_ID(RALINK, RT5370), 273 USB_ID(RALINK, RT5572), 274 USB_ID(RALINK, RT8070), 275 USB_ID(SAMSUNG, RT2870_1), 276 USB_ID(SENAO, RT2870_1), 277 USB_ID(SENAO, RT2870_2), 278 USB_ID(SENAO, RT2870_3), 279 USB_ID(SENAO, RT2870_4), 280 USB_ID(SENAO, RT3070), 281 USB_ID(SENAO, RT3071), 282 USB_ID(SENAO, RT3072), 283 USB_ID(SENAO, RT3072_2), 284 USB_ID(SENAO, RT3072_3), 285 USB_ID(SENAO, RT3072_4), 286 USB_ID(SENAO, RT3072_5), 287 USB_ID(SITECOMEU, RT2870_1), 288 USB_ID(SITECOMEU, RT2870_2), 289 USB_ID(SITECOMEU, RT2870_3), 290 USB_ID(SITECOMEU, RT3070_1), 291 USB_ID(SITECOMEU, RT3070_3), 292 USB_ID(SITECOMEU, RT3072_3), 293 USB_ID(SITECOMEU, RT3072_4), 294 USB_ID(SITECOMEU, RT3072_5), 295 USB_ID(SITECOMEU, RT3072_6), 296 USB_ID(SITECOMEU, WL302), 297 USB_ID(SITECOMEU, WL315), 298 USB_ID(SITECOMEU, WL321), 299 USB_ID(SITECOMEU, WL324), 300 USB_ID(SITECOMEU, WL329), 301 USB_ID(SITECOMEU, WL343), 302 USB_ID(SITECOMEU, WL344), 303 USB_ID(SITECOMEU, WL345), 304 USB_ID(SITECOMEU, WL349V4), 305 USB_ID(SITECOMEU, WL608), 306 USB_ID(SITECOMEU, WLA4000), 307 USB_ID(SITECOMEU, WLA5000), 308 USB_ID(SPARKLAN, RT2870_1), 309 USB_ID(SPARKLAN, RT2870_2), 310 USB_ID(SPARKLAN, RT3070), 311 USB_ID(SWEEX2, LW153), 312 USB_ID(SWEEX2, LW303), 313 USB_ID(SWEEX2, LW313), 314 USB_ID(TOSHIBA, RT3070), 315 USB_ID(UMEDIA, RT2870_1), 316 USB_ID(UMEDIA, TEW645UB), 317 USB_ID(ZCOM, RT2870_1), 318 USB_ID(ZCOM, RT2870_2), 319 USB_ID(ZINWELL, RT2870_1), 320 USB_ID(ZINWELL, RT2870_2), 321 USB_ID(ZINWELL, RT3070), 322 USB_ID(ZINWELL, RT3072), 323 USB_ID(ZINWELL, RT3072_2), 324 USB_ID(ZYXEL, NWD2105), 325 USB_ID(ZYXEL, NWD211AN), 326 USB_ID(ZYXEL, RT2870_1), 327 USB_ID(ZYXEL, RT2870_2), 328 USB_ID(ZYXEL, RT3070), 329 }; 330 331 static int run_match(device_t, cfdata_t, void *); 332 static void run_attach(device_t, device_t, void *); 333 static int run_detach(device_t, int); 334 static int run_activate(device_t, enum devact); 335 336 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 337 run_match, run_attach, run_detach, run_activate); 338 339 static int run_alloc_rx_ring(struct run_softc *); 340 static void run_free_rx_ring(struct run_softc *); 341 static int run_alloc_tx_ring(struct run_softc *, int); 342 static void run_free_tx_ring(struct run_softc *, int); 343 static int run_load_microcode(struct run_softc *); 344 static int run_reset(struct run_softc *); 345 static int run_read(struct run_softc *, uint16_t, uint32_t *); 346 static int run_read_region_1(struct run_softc *, uint16_t, 347 uint8_t *, int); 348 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 349 static int run_write(struct run_softc *, uint16_t, uint32_t); 350 static int run_write_region_1(struct run_softc *, uint16_t, 351 const uint8_t *, int); 352 static int run_set_region_4(struct run_softc *, uint16_t, 353 uint32_t, int); 354 static int run_efuse_read(struct run_softc *, uint16_t, 355 uint16_t *, int); 356 static int run_efuse_read_2(struct run_softc *, uint16_t, 357 uint16_t *); 358 static int run_eeprom_read_2(struct run_softc *, uint16_t, 359 uint16_t *); 360 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 361 uint32_t); 362 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 363 uint8_t *); 364 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 365 uint8_t); 366 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 367 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 368 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 369 static const char * run_get_rf(uint16_t); 370 static void run_rt3593_get_txpower(struct run_softc *); 371 static void run_get_txpower(struct run_softc *); 372 static int run_read_eeprom(struct run_softc *); 373 static struct ieee80211_node * 374 run_node_alloc(struct ieee80211_node_table *); 375 static int run_media_change(struct ifnet *); 376 static void run_next_scan(void *); 377 static void run_task(void *); 378 static void run_do_async(struct run_softc *, 379 void (*)(struct run_softc *, void *), void *, int); 380 static int run_newstate(struct ieee80211com *, 381 enum ieee80211_state, int); 382 static void run_newstate_cb(struct run_softc *, void *); 383 static int run_updateedca(struct ieee80211com *); 384 static void run_updateedca_cb(struct run_softc *, void *); 385 #ifdef RUN_HWCRYPTO 386 static int run_set_key(struct ieee80211com *, 387 const struct ieee80211_key *, const uint8_t *); 388 static void run_set_key_cb(struct run_softc *, void *); 389 static int run_delete_key(struct ieee80211com *, 390 const struct ieee80211_key *); 391 static void run_delete_key_cb(struct run_softc *, void *); 392 #endif 393 static void run_calibrate_to(void *); 394 static void run_calibrate_cb(struct run_softc *, void *); 395 static void run_newassoc(struct ieee80211_node *, int); 396 static void run_rx_frame(struct run_softc *, uint8_t *, int); 397 static void run_rxeof(struct usbd_xfer *, void *, 398 usbd_status); 399 static void run_txeof(struct usbd_xfer *, void *, 400 usbd_status); 401 static int run_tx(struct run_softc *, struct mbuf *, 402 struct ieee80211_node *); 403 static void run_start(struct ifnet *); 404 static void run_watchdog(struct ifnet *); 405 static int run_ioctl(struct ifnet *, u_long, void *); 406 static void run_select_chan_group(struct run_softc *, int); 407 static void run_iq_calib(struct run_softc *, u_int); 408 static void run_set_agc(struct run_softc *, uint8_t); 409 static void run_set_rx_antenna(struct run_softc *, int); 410 static void run_rt2870_set_chan(struct run_softc *, u_int); 411 static void run_rt3070_set_chan(struct run_softc *, u_int); 412 static void run_rt3572_set_chan(struct run_softc *, u_int); 413 static void run_rt3593_set_chan(struct run_softc *, u_int); 414 static void run_rt5390_set_chan(struct run_softc *, u_int); 415 static void run_rt5592_set_chan(struct run_softc *, u_int); 416 static int run_set_chan(struct run_softc *, 417 struct ieee80211_channel *); 418 static void run_updateprot(struct run_softc *); 419 static void run_enable_tsf_sync(struct run_softc *); 420 static void run_enable_mrr(struct run_softc *); 421 static void run_set_txpreamble(struct run_softc *); 422 static void run_set_basicrates(struct run_softc *); 423 static void run_set_leds(struct run_softc *, uint16_t); 424 static void run_set_bssid(struct run_softc *, const uint8_t *); 425 static void run_set_macaddr(struct run_softc *, const uint8_t *); 426 static void run_updateslot(struct ifnet *); 427 static void run_updateslot_cb(struct run_softc *, void *); 428 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 429 static void run_rt5390_bbp_init(struct run_softc *); 430 static int run_bbp_init(struct run_softc *); 431 static int run_rt3070_rf_init(struct run_softc *); 432 static int run_rt3593_rf_init(struct run_softc *); 433 static int run_rt5390_rf_init(struct run_softc *); 434 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 435 uint8_t, uint8_t *); 436 static void run_rt3070_rf_setup(struct run_softc *); 437 static void run_rt3593_rf_setup(struct run_softc *); 438 static void run_rt5390_rf_setup(struct run_softc *); 439 static int run_txrx_enable(struct run_softc *); 440 static int run_adjust_freq_offset(struct run_softc *); 441 static int run_init(struct ifnet *); 442 static void run_stop(struct ifnet *, int); 443 #ifndef IEEE80211_STA_ONLY 444 static int run_setup_beacon(struct run_softc *); 445 #endif 446 447 static const struct { 448 uint32_t reg; 449 uint32_t val; 450 } rt2870_def_mac[] = { 451 RT2870_DEF_MAC 452 }; 453 454 static const struct { 455 uint8_t reg; 456 uint8_t val; 457 } rt2860_def_bbp[] = { 458 RT2860_DEF_BBP 459 }, rt5390_def_bbp[] = { 460 RT5390_DEF_BBP 461 }, rt5592_def_bbp[] = { 462 RT5592_DEF_BBP 463 }; 464 465 /* 466 * Default values for BBP register R196 for RT5592. 467 */ 468 static const uint8_t rt5592_bbp_r196[] = { 469 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 470 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 471 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 472 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 473 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 474 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 476 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 477 0x2e, 0x36, 0x30, 0x6e 478 }; 479 480 static const struct rfprog { 481 uint8_t chan; 482 uint32_t r1, r2, r3, r4; 483 } rt2860_rf2850[] = { 484 RT2860_RF2850 485 }; 486 487 static const struct { 488 uint8_t n, r, k; 489 } rt3070_freqs[] = { 490 RT3070_RF3052 491 }; 492 493 static const struct rt5592_freqs { 494 uint16_t n; 495 uint8_t k, m, r; 496 } rt5592_freqs_20mhz[] = { 497 RT5592_RF5592_20MHZ 498 },rt5592_freqs_40mhz[] = { 499 RT5592_RF5592_40MHZ 500 }; 501 502 static const struct { 503 uint8_t reg; 504 uint8_t val; 505 } rt3070_def_rf[] = { 506 RT3070_DEF_RF 507 }, rt3572_def_rf[] = { 508 RT3572_DEF_RF 509 },rt3593_def_rf[] = { 510 RT3593_DEF_RF 511 },rt5390_def_rf[] = { 512 RT5390_DEF_RF 513 },rt5392_def_rf[] = { 514 RT5392_DEF_RF 515 },rt5592_def_rf[] = { 516 RT5592_DEF_RF 517 },rt5592_2ghz_def_rf[] = { 518 RT5592_2GHZ_DEF_RF 519 },rt5592_5ghz_def_rf[] = { 520 RT5592_5GHZ_DEF_RF 521 }; 522 523 static const struct { 524 u_int firstchan; 525 u_int lastchan; 526 uint8_t reg; 527 uint8_t val; 528 } rt5592_chan_5ghz[] = { 529 RT5592_CHAN_5GHZ 530 }; 531 532 static int 533 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 534 size_t *sizep) 535 { 536 firmware_handle_t fh; 537 int error; 538 539 if ((error = firmware_open(dname, iname, &fh)) != 0) 540 return error; 541 *sizep = firmware_get_size(fh); 542 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 543 firmware_close(fh); 544 return ENOMEM; 545 } 546 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 547 firmware_free(*ucodep, *sizep); 548 firmware_close(fh); 549 550 return error; 551 } 552 553 static int 554 run_match(device_t parent, cfdata_t match, void *aux) 555 { 556 struct usb_attach_arg *uaa = aux; 557 558 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 559 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 560 } 561 562 static void 563 run_attach(device_t parent, device_t self, void *aux) 564 { 565 struct run_softc *sc = device_private(self); 566 struct usb_attach_arg *uaa = aux; 567 struct ieee80211com *ic = &sc->sc_ic; 568 struct ifnet *ifp = &sc->sc_if; 569 usb_interface_descriptor_t *id; 570 usb_endpoint_descriptor_t *ed; 571 char *devinfop; 572 int i, nrx, ntx, ntries, error; 573 uint32_t ver; 574 575 aprint_naive("\n"); 576 aprint_normal("\n"); 577 578 sc->sc_dev = self; 579 sc->sc_udev = uaa->uaa_device; 580 581 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 582 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 583 usbd_devinfo_free(devinfop); 584 585 error = usbd_set_config_no(sc->sc_udev, 1, 0); 586 if (error != 0) { 587 aprint_error_dev(sc->sc_dev, "failed to set configuration" 588 ", err=%s\n", usbd_errstr(error)); 589 return; 590 } 591 592 /* get the first interface handle */ 593 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 594 if (error != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "could not get interface handle\n"); 597 return; 598 } 599 600 /* 601 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 602 * and 6 for TX (4 EDCAs + HCCA + Prio). 603 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 604 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 605 */ 606 nrx = ntx = 0; 607 id = usbd_get_interface_descriptor(sc->sc_iface); 608 for (i = 0; i < id->bNumEndpoints; i++) { 609 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 610 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 611 continue; 612 613 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 614 sc->rxq.pipe_no = ed->bEndpointAddress; 615 nrx++; 616 } else if (ntx < RUN_MAXEPOUT) { 617 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 618 ntx++; 619 } 620 } 621 /* make sure we've got them all */ 622 if (nrx < 1 || ntx < RUN_MAXEPOUT) { 623 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 624 return; 625 } 626 627 usb_init_task(&sc->sc_task, run_task, sc, 0); 628 callout_init(&sc->scan_to, 0); 629 callout_setfunc(&sc->scan_to, run_next_scan, sc); 630 callout_init(&sc->calib_to, 0); 631 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 632 633 sc->amrr.amrr_min_success_threshold = 1; 634 sc->amrr.amrr_max_success_threshold = 10; 635 636 /* wait for the chip to settle */ 637 for (ntries = 0; ntries < 100; ntries++) { 638 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 639 return; 640 if (ver != 0 && ver != 0xffffffff) 641 break; 642 DELAY(10); 643 } 644 if (ntries == 100) { 645 aprint_error_dev(sc->sc_dev, 646 "timeout waiting for NIC to initialize\n"); 647 return; 648 } 649 sc->mac_ver = ver >> 16; 650 sc->mac_rev = ver & 0xffff; 651 652 /* retrieve RF rev. no and various other things from EEPROM */ 653 run_read_eeprom(sc); 654 655 aprint_verbose_dev(sc->sc_dev, 656 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 657 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 658 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 659 660 ic->ic_ifp = ifp; 661 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 662 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 663 ic->ic_state = IEEE80211_S_INIT; 664 665 /* set device capabilities */ 666 ic->ic_caps = 667 IEEE80211_C_MONITOR | /* monitor mode supported */ 668 #ifndef IEEE80211_STA_ONLY 669 IEEE80211_C_IBSS | /* IBSS mode supported */ 670 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 671 #endif 672 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 673 IEEE80211_C_SHSLOT | /* short slot time supported */ 674 #ifdef RUN_HWCRYPTO 675 IEEE80211_C_WEP | /* WEP */ 676 IEEE80211_C_TKIP | /* TKIP */ 677 IEEE80211_C_AES_CCM | /* AES CCMP */ 678 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 679 #endif 680 IEEE80211_C_WME | /* WME */ 681 IEEE80211_C_WPA; /* WPA/RSN */ 682 683 if (sc->rf_rev == RT2860_RF_2750 || 684 sc->rf_rev == RT2860_RF_2850 || 685 sc->rf_rev == RT3070_RF_3052 || 686 sc->rf_rev == RT3070_RF_3053 || 687 sc->rf_rev == RT5592_RF_5592) { 688 /* set supported .11a rates */ 689 ic->ic_sup_rates[IEEE80211_MODE_11A] = 690 ieee80211_std_rateset_11a; 691 692 /* set supported .11a channels */ 693 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 694 uint8_t chan = rt2860_rf2850[i].chan; 695 ic->ic_channels[chan].ic_freq = 696 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 697 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 698 } 699 } 700 701 /* set supported .11b and .11g rates */ 702 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 703 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 704 705 /* set supported .11b and .11g channels (1 through 14) */ 706 for (i = 1; i <= 14; i++) { 707 ic->ic_channels[i].ic_freq = 708 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 709 ic->ic_channels[i].ic_flags = 710 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 711 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 712 } 713 714 ifp->if_softc = sc; 715 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 716 ifp->if_init = run_init; 717 ifp->if_ioctl = run_ioctl; 718 ifp->if_start = run_start; 719 ifp->if_watchdog = run_watchdog; 720 IFQ_SET_READY(&ifp->if_snd); 721 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 722 723 if_attach(ifp); 724 ieee80211_ifattach(ic); 725 ic->ic_node_alloc = run_node_alloc; 726 ic->ic_newassoc = run_newassoc; 727 ic->ic_updateslot = run_updateslot; 728 ic->ic_wme.wme_update = run_updateedca; 729 #ifdef RUN_HWCRYPTO 730 ic->ic_crypto.cs_key_set = run_set_key; 731 ic->ic_crypto.cs_key_delete = run_delete_key; 732 #endif 733 /* override state transition machine */ 734 sc->sc_newstate = ic->ic_newstate; 735 ic->ic_newstate = run_newstate; 736 737 /* XXX media locking needs revisiting */ 738 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 739 ieee80211_media_init_with_lock(ic, 740 run_media_change, ieee80211_media_status, &sc->sc_media_mtx); 741 742 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 743 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 744 &sc->sc_drvbpf); 745 746 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 747 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 748 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 749 750 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 751 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 752 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 753 754 ieee80211_announce(ic); 755 756 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 757 758 if (!pmf_device_register(self, NULL, NULL)) 759 aprint_error_dev(self, "couldn't establish power handler\n"); 760 } 761 762 static int 763 run_detach(device_t self, int flags) 764 { 765 struct run_softc *sc = device_private(self); 766 struct ifnet *ifp = &sc->sc_if; 767 struct ieee80211com *ic = &sc->sc_ic; 768 int s; 769 770 if (ifp->if_softc == NULL) 771 return 0; 772 773 pmf_device_deregister(self); 774 775 s = splusb(); 776 777 sc->sc_flags |= RUN_DETACHING; 778 779 if (ifp->if_flags & IFF_RUNNING) { 780 run_stop(ifp, 0); 781 callout_halt(&sc->scan_to, NULL); 782 callout_halt(&sc->calib_to, NULL); 783 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 784 NULL); 785 } 786 787 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 788 bpf_detach(ifp); 789 ieee80211_ifdetach(ic); 790 if_detach(ifp); 791 792 splx(s); 793 794 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 795 796 callout_stop(&sc->scan_to); 797 callout_stop(&sc->calib_to); 798 799 callout_destroy(&sc->scan_to); 800 callout_destroy(&sc->calib_to); 801 802 return 0; 803 } 804 805 static int 806 run_activate(device_t self, enum devact act) 807 { 808 struct run_softc *sc = device_private(self); 809 810 switch (act) { 811 case DVACT_DEACTIVATE: 812 if_deactivate(sc->sc_ic.ic_ifp); 813 return 0; 814 default: 815 return EOPNOTSUPP; 816 } 817 } 818 819 static int 820 run_alloc_rx_ring(struct run_softc *sc) 821 { 822 struct run_rx_ring *rxq = &sc->rxq; 823 int i, error; 824 825 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 826 if (error != 0) 827 goto fail; 828 829 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 830 struct run_rx_data *data = &rxq->data[i]; 831 832 data->sc = sc; /* backpointer for callbacks */ 833 834 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 835 0, 0, &data->xfer); 836 if (error) 837 goto fail; 838 839 data->buf = usbd_get_buffer(data->xfer); 840 } 841 if (error != 0) 842 fail: run_free_rx_ring(sc); 843 return error; 844 } 845 846 static void 847 run_free_rx_ring(struct run_softc *sc) 848 { 849 struct run_rx_ring *rxq = &sc->rxq; 850 int i; 851 852 if (rxq->pipeh != NULL) { 853 usbd_abort_pipe(rxq->pipeh); 854 } 855 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 856 if (rxq->data[i].xfer != NULL) 857 usbd_destroy_xfer(rxq->data[i].xfer); 858 rxq->data[i].xfer = NULL; 859 } 860 if (rxq->pipeh != NULL) { 861 usbd_close_pipe(rxq->pipeh); 862 rxq->pipeh = NULL; 863 } 864 } 865 866 static int 867 run_alloc_tx_ring(struct run_softc *sc, int qid) 868 { 869 struct run_tx_ring *txq = &sc->txq[qid]; 870 int i, error; 871 uint16_t txwisize; 872 873 txwisize = sizeof(struct rt2860_txwi); 874 if (sc->mac_ver == 0x5592) 875 txwisize += sizeof(uint32_t); 876 877 txq->cur = txq->queued = 0; 878 879 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 880 if (error != 0) 881 goto fail; 882 883 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 884 struct run_tx_data *data = &txq->data[i]; 885 886 data->sc = sc; /* backpointer for callbacks */ 887 data->qid = qid; 888 889 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 890 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 891 if (error) 892 goto fail; 893 894 data->buf = usbd_get_buffer(data->xfer); 895 /* zeroize the TXD + TXWI part */ 896 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 897 } 898 if (error != 0) 899 fail: run_free_tx_ring(sc, qid); 900 return error; 901 } 902 903 static void 904 run_free_tx_ring(struct run_softc *sc, int qid) 905 { 906 struct run_tx_ring *txq = &sc->txq[qid]; 907 int i; 908 909 if (txq->pipeh != NULL) { 910 usbd_abort_pipe(txq->pipeh); 911 usbd_close_pipe(txq->pipeh); 912 txq->pipeh = NULL; 913 } 914 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 915 if (txq->data[i].xfer != NULL) 916 usbd_destroy_xfer(txq->data[i].xfer); 917 txq->data[i].xfer = NULL; 918 } 919 } 920 921 static int 922 run_load_microcode(struct run_softc *sc) 923 { 924 usb_device_request_t req; 925 const char *fwname; 926 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 927 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 928 uint32_t tmp; 929 int ntries, error; 930 931 /* RT3071/RT3072 use a different firmware */ 932 if (sc->mac_ver != 0x2860 && 933 sc->mac_ver != 0x2872 && 934 sc->mac_ver != 0x3070) 935 fwname = "run-rt3071"; 936 else 937 fwname = "run-rt2870"; 938 939 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 940 device_printf(sc->sc_dev, 941 "error %d, could not read firmware %s\n", error, fwname); 942 return error; 943 } 944 if (size != 4096) { 945 device_printf(sc->sc_dev, 946 "invalid firmware size (should be 4KB)\n"); 947 firmware_free(ucode, size); 948 return EINVAL; 949 } 950 951 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 952 /* write microcode image */ 953 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 954 firmware_free(ucode, size); 955 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 956 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 957 958 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 959 req.bRequest = RT2870_RESET; 960 USETW(req.wValue, 8); 961 USETW(req.wIndex, 0); 962 USETW(req.wLength, 0); 963 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 964 return error; 965 966 usbd_delay_ms(sc->sc_udev, 10); 967 run_write(sc, RT2860_H2M_BBPAGENT, 0); 968 run_write(sc, RT2860_H2M_MAILBOX, 0); 969 run_write(sc, RT2860_H2M_INTSRC, 0); 970 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 971 return error; 972 973 /* wait until microcontroller is ready */ 974 for (ntries = 0; ntries < 1000; ntries++) { 975 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 976 return error; 977 if (tmp & RT2860_MCU_READY) 978 break; 979 usbd_delay_ms(sc->sc_udev, 10); 980 } 981 if (ntries == 1000) { 982 device_printf(sc->sc_dev, 983 "timeout waiting for MCU to initialize\n"); 984 return ETIMEDOUT; 985 } 986 987 sc->sc_flags |= RUN_FWLOADED; 988 989 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 990 return 0; 991 } 992 993 static int 994 run_reset(struct run_softc *sc) 995 { 996 usb_device_request_t req; 997 998 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 999 req.bRequest = RT2870_RESET; 1000 USETW(req.wValue, 1); 1001 USETW(req.wIndex, 0); 1002 USETW(req.wLength, 0); 1003 return usbd_do_request(sc->sc_udev, &req, NULL); 1004 } 1005 1006 static int 1007 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 1008 { 1009 uint32_t tmp; 1010 int error; 1011 1012 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 1013 if (error == 0) 1014 *val = le32toh(tmp); 1015 else 1016 *val = 0xffffffff; 1017 return error; 1018 } 1019 1020 static int 1021 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 1022 { 1023 usb_device_request_t req; 1024 1025 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1026 req.bRequest = RT2870_READ_REGION_1; 1027 USETW(req.wValue, 0); 1028 USETW(req.wIndex, reg); 1029 USETW(req.wLength, len); 1030 return usbd_do_request(sc->sc_udev, &req, buf); 1031 } 1032 1033 static int 1034 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1035 { 1036 usb_device_request_t req; 1037 1038 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1039 req.bRequest = RT2870_WRITE_2; 1040 USETW(req.wValue, val); 1041 USETW(req.wIndex, reg); 1042 USETW(req.wLength, 0); 1043 return usbd_do_request(sc->sc_udev, &req, NULL); 1044 } 1045 1046 static int 1047 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1048 { 1049 int error; 1050 1051 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1052 error = run_write_2(sc, reg + 2, val >> 16); 1053 return error; 1054 } 1055 1056 static int 1057 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1058 int len) 1059 { 1060 #if 1 1061 int i, error = 0; 1062 /* 1063 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1064 * We thus issue multiple WRITE_2 commands instead. 1065 */ 1066 KASSERT((len & 1) == 0); 1067 for (i = 0; i < len && error == 0; i += 2) 1068 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1069 return error; 1070 #else 1071 usb_device_request_t req; 1072 1073 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1074 req.bRequest = RT2870_WRITE_REGION_1; 1075 USETW(req.wValue, 0); 1076 USETW(req.wIndex, reg); 1077 USETW(req.wLength, len); 1078 return usbd_do_request(sc->sc_udev, &req, __UNCONST(buf)); 1079 #endif 1080 } 1081 1082 static int 1083 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1084 { 1085 int error = 0; 1086 1087 for (; count > 0 && error == 0; count--, reg += 4) 1088 error = run_write(sc, reg, val); 1089 return error; 1090 } 1091 1092 static int 1093 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1094 { 1095 uint32_t tmp; 1096 uint16_t reg; 1097 int error, ntries; 1098 1099 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1100 return error; 1101 1102 if (count == 2) 1103 addr *= 2; 1104 /*- 1105 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1106 * DATA0: F E D C 1107 * DATA1: B A 9 8 1108 * DATA2: 7 6 5 4 1109 * DATA3: 3 2 1 0 1110 */ 1111 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1112 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1113 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1114 for (ntries = 0; ntries < 100; ntries++) { 1115 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1116 return error; 1117 if (!(tmp & RT3070_EFSROM_KICK)) 1118 break; 1119 usbd_delay_ms(sc->sc_udev, 2); 1120 } 1121 if (ntries == 100) 1122 return ETIMEDOUT; 1123 1124 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1125 *val = 0xffff; /* address not found */ 1126 return 0; 1127 } 1128 /* determine to which 32-bit register our 16-bit word belongs */ 1129 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1130 if ((error = run_read(sc, reg, &tmp)) != 0) 1131 return error; 1132 1133 tmp >>= (8 * (addr & 0x3)); 1134 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1135 return 0; 1136 } 1137 1138 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1139 static int 1140 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1141 { 1142 return run_efuse_read(sc, addr, val, 2); 1143 } 1144 1145 static int 1146 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1147 { 1148 usb_device_request_t req; 1149 uint16_t tmp; 1150 int error; 1151 1152 addr *= 2; 1153 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1154 req.bRequest = RT2870_EEPROM_READ; 1155 USETW(req.wValue, 0); 1156 USETW(req.wIndex, addr); 1157 USETW(req.wLength, sizeof(tmp)); 1158 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1159 if (error == 0) 1160 *val = le16toh(tmp); 1161 else 1162 *val = 0xffff; 1163 return error; 1164 } 1165 1166 static __inline int 1167 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1168 { 1169 1170 /* either eFUSE ROM or EEPROM */ 1171 return sc->sc_srom_read(sc, addr, val); 1172 } 1173 1174 static int 1175 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1176 { 1177 uint32_t tmp; 1178 int error, ntries; 1179 1180 for (ntries = 0; ntries < 10; ntries++) { 1181 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1182 return error; 1183 if (!(tmp & RT2860_RF_REG_CTRL)) 1184 break; 1185 } 1186 if (ntries == 10) 1187 return ETIMEDOUT; 1188 1189 /* RF registers are 24-bit on the RT2860 */ 1190 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1191 (val & 0x3fffff) << 2 | (reg & 3); 1192 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1193 } 1194 1195 static int 1196 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1197 { 1198 uint32_t tmp; 1199 int error, ntries; 1200 1201 for (ntries = 0; ntries < 100; ntries++) { 1202 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1203 return error; 1204 if (!(tmp & RT3070_RF_KICK)) 1205 break; 1206 } 1207 if (ntries == 100) 1208 return ETIMEDOUT; 1209 1210 tmp = RT3070_RF_KICK | reg << 8; 1211 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1212 return error; 1213 1214 for (ntries = 0; ntries < 100; ntries++) { 1215 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1216 return error; 1217 if (!(tmp & RT3070_RF_KICK)) 1218 break; 1219 } 1220 if (ntries == 100) 1221 return ETIMEDOUT; 1222 1223 *val = tmp & 0xff; 1224 return 0; 1225 } 1226 1227 static int 1228 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1229 { 1230 uint32_t tmp; 1231 int error, ntries; 1232 1233 for (ntries = 0; ntries < 10; ntries++) { 1234 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1235 return error; 1236 if (!(tmp & RT3070_RF_KICK)) 1237 break; 1238 } 1239 if (ntries == 10) 1240 return ETIMEDOUT; 1241 1242 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1243 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1244 } 1245 1246 static int 1247 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1248 { 1249 uint32_t tmp; 1250 int ntries, error; 1251 1252 for (ntries = 0; ntries < 10; ntries++) { 1253 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1254 return error; 1255 if (!(tmp & RT2860_BBP_CSR_KICK)) 1256 break; 1257 } 1258 if (ntries == 10) 1259 return ETIMEDOUT; 1260 1261 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1262 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1263 return error; 1264 1265 for (ntries = 0; ntries < 10; ntries++) { 1266 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1267 return error; 1268 if (!(tmp & RT2860_BBP_CSR_KICK)) 1269 break; 1270 } 1271 if (ntries == 10) 1272 return ETIMEDOUT; 1273 1274 *val = tmp & 0xff; 1275 return 0; 1276 } 1277 1278 static int 1279 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1280 { 1281 uint32_t tmp; 1282 int ntries, error; 1283 1284 for (ntries = 0; ntries < 10; ntries++) { 1285 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1286 return error; 1287 if (!(tmp & RT2860_BBP_CSR_KICK)) 1288 break; 1289 } 1290 if (ntries == 10) 1291 return ETIMEDOUT; 1292 1293 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1294 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1295 } 1296 1297 /* 1298 * Send a command to the 8051 microcontroller unit. 1299 */ 1300 static int 1301 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1302 { 1303 uint32_t tmp; 1304 int error, ntries; 1305 1306 for (ntries = 0; ntries < 100; ntries++) { 1307 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1308 return error; 1309 if (!(tmp & RT2860_H2M_BUSY)) 1310 break; 1311 } 1312 if (ntries == 100) 1313 return ETIMEDOUT; 1314 1315 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1316 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1317 error = run_write(sc, RT2860_HOST_CMD, cmd); 1318 return error; 1319 } 1320 1321 /* 1322 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1323 * Used to adjust per-rate Tx power registers. 1324 */ 1325 static __inline uint32_t 1326 b4inc(uint32_t b32, int8_t delta) 1327 { 1328 int8_t i, b4; 1329 1330 for (i = 0; i < 8; i++) { 1331 b4 = b32 & 0xf; 1332 b4 += delta; 1333 if (b4 < 0) 1334 b4 = 0; 1335 else if (b4 > 0xf) 1336 b4 = 0xf; 1337 b32 = b32 >> 4 | b4 << 28; 1338 } 1339 return b32; 1340 } 1341 1342 static const char * 1343 run_get_rf(uint16_t rev) 1344 { 1345 switch (rev) { 1346 case RT2860_RF_2820: return "RT2820"; 1347 case RT2860_RF_2850: return "RT2850"; 1348 case RT2860_RF_2720: return "RT2720"; 1349 case RT2860_RF_2750: return "RT2750"; 1350 case RT3070_RF_3020: return "RT3020"; 1351 case RT3070_RF_2020: return "RT2020"; 1352 case RT3070_RF_3021: return "RT3021"; 1353 case RT3070_RF_3022: return "RT3022"; 1354 case RT3070_RF_3052: return "RT3052"; 1355 case RT3070_RF_3053: return "RT3053"; 1356 case RT5592_RF_5592: return "RT5592"; 1357 case RT5390_RF_5370: return "RT5370"; 1358 case RT5390_RF_5372: return "RT5372"; 1359 } 1360 return "unknown"; 1361 } 1362 1363 static void 1364 run_rt3593_get_txpower(struct run_softc *sc) 1365 { 1366 uint16_t addr, val; 1367 int i; 1368 1369 /* Read power settings for 2GHz channels. */ 1370 for (i = 0; i < 14; i += 2) { 1371 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1372 RT2860_EEPROM_PWR2GHZ_BASE1; 1373 run_srom_read(sc, addr + i / 2, &val); 1374 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1375 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1376 1377 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1378 RT2860_EEPROM_PWR2GHZ_BASE2; 1379 run_srom_read(sc, addr + i / 2, &val); 1380 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1381 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1382 1383 if (sc->ntxchains == 3) { 1384 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1385 &val); 1386 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1387 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1388 } 1389 } 1390 /* Fix broken Tx power entries. */ 1391 for (i = 0; i < 14; i++) { 1392 if (sc->txpow1[i] > 31) 1393 sc->txpow1[i] = 5; 1394 if (sc->txpow2[i] > 31) 1395 sc->txpow2[i] = 5; 1396 if (sc->ntxchains == 3) { 1397 if (sc->txpow3[i] > 31) 1398 sc->txpow3[i] = 5; 1399 } 1400 } 1401 /* Read power settings for 5GHz channels. */ 1402 for (i = 0; i < 40; i += 2) { 1403 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1404 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1405 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1406 1407 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1408 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1409 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1410 1411 if (sc->ntxchains == 3) { 1412 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1413 &val); 1414 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1415 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1416 } 1417 } 1418 } 1419 1420 static void 1421 run_get_txpower(struct run_softc *sc) 1422 { 1423 uint16_t val; 1424 int i; 1425 1426 /* Read power settings for 2GHz channels. */ 1427 for (i = 0; i < 14; i += 2) { 1428 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1429 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1430 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1431 1432 if (sc->mac_ver != 0x5390) { 1433 run_srom_read(sc, 1434 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1435 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1436 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1437 } 1438 } 1439 /* Fix broken Tx power entries. */ 1440 for (i = 0; i < 14; i++) { 1441 if (sc->mac_ver >= 0x5390) { 1442 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1443 sc->txpow1[i] = 5; 1444 } else { 1445 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1446 sc->txpow1[i] = 5; 1447 } 1448 if (sc->mac_ver > 0x5390) { 1449 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1450 sc->txpow2[i] = 5; 1451 } else if (sc->mac_ver < 0x5390) { 1452 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1453 sc->txpow2[i] = 5; 1454 } 1455 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1456 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1457 } 1458 /* Read power settings for 5GHz channels. */ 1459 for (i = 0; i < 40; i += 2) { 1460 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1461 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1462 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1463 1464 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1465 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1466 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1467 } 1468 /* Fix broken Tx power entries. */ 1469 for (i = 0; i < 40; i++ ) { 1470 if (sc->mac_ver != 0x5592) { 1471 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1472 sc->txpow1[14 + i] = 5; 1473 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1474 sc->txpow2[14 + i] = 5; 1475 } 1476 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1477 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1478 sc->txpow2[14 + i])); 1479 } 1480 } 1481 1482 static int 1483 run_read_eeprom(struct run_softc *sc) 1484 { 1485 struct ieee80211com *ic = &sc->sc_ic; 1486 int8_t delta_2ghz, delta_5ghz; 1487 uint32_t tmp; 1488 uint16_t val; 1489 int ridx, ant, i; 1490 1491 /* check whether the ROM is eFUSE ROM or EEPROM */ 1492 sc->sc_srom_read = run_eeprom_read_2; 1493 if (sc->mac_ver >= 0x3070) { 1494 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1495 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1496 if (tmp & RT3070_SEL_EFUSE) 1497 sc->sc_srom_read = run_efuse_read_2; 1498 } 1499 1500 /* read ROM version */ 1501 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1502 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1503 1504 /* read MAC address */ 1505 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1506 ic->ic_myaddr[0] = val & 0xff; 1507 ic->ic_myaddr[1] = val >> 8; 1508 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1509 ic->ic_myaddr[2] = val & 0xff; 1510 ic->ic_myaddr[3] = val >> 8; 1511 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1512 ic->ic_myaddr[4] = val & 0xff; 1513 ic->ic_myaddr[5] = val >> 8; 1514 1515 if (sc->mac_ver < 0x3593) { 1516 /* read vendor BBP settings */ 1517 for (i = 0; i < 10; i++) { 1518 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1519 sc->bbp[i].val = val & 0xff; 1520 sc->bbp[i].reg = val >> 8; 1521 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1522 sc->bbp[i].val)); 1523 } 1524 1525 if (sc->mac_ver >= 0x3071) { 1526 /* read vendor RF settings */ 1527 for (i = 0; i < 8; i++) { 1528 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1529 &val); 1530 sc->rf[i].val = val & 0xff; 1531 sc->rf[i].reg = val >> 8; 1532 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1533 sc->rf[i].val)); 1534 } 1535 } 1536 } 1537 1538 /* read RF frequency offset from EEPROM */ 1539 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1540 RT3593_EEPROM_FREQ, &val); 1541 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1542 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1543 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1544 RT3593_EEPROM_FREQ, &val); 1545 if ((val >> 8) != 0xff) { 1546 /* read LEDs operating mode */ 1547 sc->leds = val >> 8; 1548 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1549 RT3593_EEPROM_LED1, &sc->led[0]); 1550 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1551 RT3593_EEPROM_LED2, &sc->led[1]); 1552 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1553 RT3593_EEPROM_LED3, &sc->led[2]); 1554 } else { 1555 /* broken EEPROM, use default settings */ 1556 sc->leds = 0x01; 1557 sc->led[0] = 0x5555; 1558 sc->led[1] = 0x2221; 1559 sc->led[2] = 0x5627; /* differs from RT2860 */ 1560 } 1561 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1562 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1563 1564 /* read RF information */ 1565 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1566 run_srom_read(sc, 0x00, &val); 1567 else 1568 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1569 if (val == 0xffff) { 1570 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1571 if (sc->mac_ver == 0x3572) { 1572 /* default to RF3052 2T2R */ 1573 sc->rf_rev = RT3070_RF_3052; 1574 sc->ntxchains = 2; 1575 sc->nrxchains = 2; 1576 } else if (sc->mac_ver >= 0x3070) { 1577 /* default to RF3020 1T1R */ 1578 sc->rf_rev = RT3070_RF_3020; 1579 sc->ntxchains = 1; 1580 sc->nrxchains = 1; 1581 } else { 1582 /* default to RF2820 1T2R */ 1583 sc->rf_rev = RT2860_RF_2820; 1584 sc->ntxchains = 1; 1585 sc->nrxchains = 2; 1586 } 1587 } else { 1588 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1589 sc->rf_rev = val; 1590 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1591 } else 1592 sc->rf_rev = (val >> 8) & 0xf; 1593 sc->ntxchains = (val >> 4) & 0xf; 1594 sc->nrxchains = val & 0xf; 1595 } 1596 DPRINTF(("EEPROM RF rev=0x%04x chains=%dT%dR\n", 1597 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1598 1599 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1600 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1601 /* check if driver should patch the DAC issue */ 1602 if ((val >> 8) != 0xff) 1603 sc->patch_dac = (val >> 15) & 1; 1604 if ((val & 0xff) != 0xff) { 1605 sc->ext_5ghz_lna = (val >> 3) & 1; 1606 sc->ext_2ghz_lna = (val >> 2) & 1; 1607 /* check if RF supports automatic Tx access gain control */ 1608 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1609 /* check if we have a hardware radio switch */ 1610 sc->rfswitch = val & 1; 1611 } 1612 1613 /* Read Tx power settings. */ 1614 if (sc->mac_ver == 0x3593) 1615 run_rt3593_get_txpower(sc); 1616 else 1617 run_get_txpower(sc); 1618 1619 /* read Tx power compensation for each Tx rate */ 1620 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1621 delta_2ghz = delta_5ghz = 0; 1622 if ((val & 0xff) != 0xff && (val & 0x80)) { 1623 delta_2ghz = val & 0xf; 1624 if (!(val & 0x40)) /* negative number */ 1625 delta_2ghz = -delta_2ghz; 1626 } 1627 val >>= 8; 1628 if ((val & 0xff) != 0xff && (val & 0x80)) { 1629 delta_5ghz = val & 0xf; 1630 if (!(val & 0x40)) /* negative number */ 1631 delta_5ghz = -delta_5ghz; 1632 } 1633 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1634 delta_2ghz, delta_5ghz)); 1635 1636 for (ridx = 0; ridx < 5; ridx++) { 1637 uint32_t reg; 1638 1639 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1640 reg = val; 1641 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1642 reg |= (uint32_t)val << 16; 1643 1644 sc->txpow20mhz[ridx] = reg; 1645 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1646 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1647 1648 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1649 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1650 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1651 } 1652 1653 DPRINTF(("mac_ver %hx\n", sc->mac_ver)); 1654 /* read RSSI offsets and LNA gains from EEPROM */ 1655 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1656 RT3593_EEPROM_RSSI1_2GHZ, &val); 1657 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1658 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1659 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1660 RT3593_EEPROM_RSSI2_2GHZ, &val); 1661 if (sc->mac_ver >= 0x3070) { 1662 if (sc->mac_ver == 0x3593) { 1663 sc->txmixgain_2ghz = 0; 1664 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1665 } else { 1666 /* 1667 * On RT3070 chips (limited to 2 Rx chains), this ROM 1668 * field contains the Tx mixer gain for the 2GHz band. 1669 */ 1670 if ((val & 0xff) != 0xff) 1671 sc->txmixgain_2ghz = val & 0x7; 1672 } 1673 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1674 } else { 1675 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1676 } 1677 if (sc->mac_ver == 0x3593) 1678 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1679 sc->lna[2] = val >> 8; /* channel group 2 */ 1680 1681 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1682 RT3593_EEPROM_RSSI1_5GHZ, &val); 1683 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1684 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1685 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1686 RT3593_EEPROM_RSSI2_5GHZ, &val); 1687 if (sc->mac_ver == 0x3572) { 1688 /* 1689 * On RT3572 chips (limited to 2 Rx chains), this ROM 1690 * field contains the Tx mixer gain for the 5GHz band. 1691 */ 1692 if ((val & 0xff) != 0xff) 1693 sc->txmixgain_5ghz = val & 0x7; 1694 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1695 } else { 1696 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1697 } 1698 if (sc->mac_ver == 0x3593) { 1699 sc->txmixgain_5ghz = 0; 1700 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1701 } 1702 sc->lna[3] = val >> 8; /* channel group 3 */ 1703 1704 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1705 RT3593_EEPROM_LNA, &val); 1706 sc->lna[0] = val & 0xff; /* channel group 0 */ 1707 sc->lna[1] = val >> 8; /* channel group 1 */ 1708 1709 /* fix broken 5GHz LNA entries */ 1710 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1711 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1712 sc->lna[2] = sc->lna[1]; 1713 } 1714 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1715 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1716 sc->lna[3] = sc->lna[1]; 1717 } 1718 1719 /* fix broken RSSI offset entries */ 1720 for (ant = 0; ant < 3; ant++) { 1721 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1722 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1723 ant + 1, sc->rssi_2ghz[ant])); 1724 sc->rssi_2ghz[ant] = 0; 1725 } 1726 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1727 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1728 ant + 1, sc->rssi_5ghz[ant])); 1729 sc->rssi_5ghz[ant] = 0; 1730 } 1731 } 1732 return 0; 1733 } 1734 1735 static struct ieee80211_node * 1736 run_node_alloc(struct ieee80211_node_table *nt) 1737 { 1738 struct run_node *rn = 1739 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1740 return rn ? &rn->ni : NULL; 1741 } 1742 1743 static int 1744 run_media_change(struct ifnet *ifp) 1745 { 1746 struct run_softc *sc = ifp->if_softc; 1747 struct ieee80211com *ic = &sc->sc_ic; 1748 uint8_t rate, ridx; 1749 int error; 1750 1751 error = ieee80211_media_change(ifp); 1752 if (error != ENETRESET) 1753 return error; 1754 1755 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1756 rate = ic->ic_sup_rates[ic->ic_curmode]. 1757 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1758 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1759 if (rt2860_rates[ridx].rate == rate) 1760 break; 1761 sc->fixed_ridx = ridx; 1762 } 1763 1764 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1765 run_init(ifp); 1766 1767 return 0; 1768 } 1769 1770 static void 1771 run_next_scan(void *arg) 1772 { 1773 struct run_softc *sc = arg; 1774 1775 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1776 ieee80211_next_scan(&sc->sc_ic); 1777 } 1778 1779 static void 1780 run_task(void *arg) 1781 { 1782 struct run_softc *sc = arg; 1783 struct run_host_cmd_ring *ring = &sc->cmdq; 1784 struct run_host_cmd *cmd; 1785 int s; 1786 1787 /* process host commands */ 1788 s = splusb(); 1789 while (ring->next != ring->cur) { 1790 cmd = &ring->cmd[ring->next]; 1791 splx(s); 1792 membar_consumer(); 1793 /* callback */ 1794 cmd->cb(sc, cmd->data); 1795 s = splusb(); 1796 atomic_dec_uint(&ring->queued); 1797 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1798 } 1799 wakeup(ring); 1800 splx(s); 1801 } 1802 1803 static void 1804 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1805 void *arg, int len) 1806 { 1807 struct run_host_cmd_ring *ring = &sc->cmdq; 1808 struct run_host_cmd *cmd; 1809 int s; 1810 1811 if (sc->sc_flags & RUN_DETACHING) 1812 return; 1813 1814 s = splusb(); 1815 cmd = &ring->cmd[ring->cur]; 1816 cmd->cb = cb; 1817 KASSERT(len <= sizeof(cmd->data)); 1818 memcpy(cmd->data, arg, len); 1819 membar_producer(); 1820 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1821 1822 /* if there is no pending command already, schedule a task */ 1823 if (atomic_inc_uint_nv(&ring->queued) == 1) 1824 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1825 splx(s); 1826 } 1827 1828 static int 1829 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1830 { 1831 struct run_softc *sc = ic->ic_ifp->if_softc; 1832 struct run_cmd_newstate cmd; 1833 1834 callout_stop(&sc->scan_to); 1835 callout_stop(&sc->calib_to); 1836 1837 /* do it in a process context */ 1838 cmd.state = nstate; 1839 cmd.arg = arg; 1840 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1841 return 0; 1842 } 1843 1844 static void 1845 run_newstate_cb(struct run_softc *sc, void *arg) 1846 { 1847 struct run_cmd_newstate *cmd = arg; 1848 struct ifnet *ifp = &sc->sc_if; 1849 struct ieee80211com *ic = &sc->sc_ic; 1850 enum ieee80211_state ostate; 1851 struct ieee80211_node *ni; 1852 uint32_t tmp, sta[3]; 1853 uint8_t wcid; 1854 int s; 1855 1856 s = splnet(); 1857 ostate = ic->ic_state; 1858 1859 if (ostate == IEEE80211_S_RUN) { 1860 /* turn link LED off */ 1861 run_set_leds(sc, RT2860_LED_RADIO); 1862 } 1863 1864 switch (cmd->state) { 1865 case IEEE80211_S_INIT: 1866 if (ostate == IEEE80211_S_RUN) { 1867 /* abort TSF synchronization */ 1868 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1869 run_write(sc, RT2860_BCN_TIME_CFG, 1870 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1871 RT2860_TBTT_TIMER_EN)); 1872 } 1873 break; 1874 1875 case IEEE80211_S_SCAN: 1876 run_set_chan(sc, ic->ic_curchan); 1877 callout_schedule(&sc->scan_to, hz / 5); 1878 break; 1879 1880 case IEEE80211_S_AUTH: 1881 case IEEE80211_S_ASSOC: 1882 run_set_chan(sc, ic->ic_curchan); 1883 break; 1884 1885 case IEEE80211_S_RUN: 1886 run_set_chan(sc, ic->ic_curchan); 1887 1888 ni = ic->ic_bss; 1889 1890 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1891 run_updateslot(ifp); 1892 run_enable_mrr(sc); 1893 run_set_txpreamble(sc); 1894 run_set_basicrates(sc); 1895 run_set_bssid(sc, ni->ni_bssid); 1896 } 1897 #ifndef IEEE80211_STA_ONLY 1898 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1899 ic->ic_opmode == IEEE80211_M_IBSS) 1900 (void)run_setup_beacon(sc); 1901 #endif 1902 if (ic->ic_opmode == IEEE80211_M_STA) { 1903 /* add BSS entry to the WCID table */ 1904 wcid = RUN_AID2WCID(ni->ni_associd); 1905 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1906 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1907 1908 /* fake a join to init the tx rate */ 1909 run_newassoc(ni, 1); 1910 } 1911 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1912 run_enable_tsf_sync(sc); 1913 1914 /* clear statistic registers used by AMRR */ 1915 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1916 (uint8_t *)sta, sizeof(sta)); 1917 /* start calibration timer */ 1918 callout_schedule(&sc->calib_to, hz); 1919 } 1920 1921 /* turn link LED on */ 1922 run_set_leds(sc, RT2860_LED_RADIO | 1923 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1924 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1925 break; 1926 } 1927 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1928 splx(s); 1929 } 1930 1931 static int 1932 run_updateedca(struct ieee80211com *ic) 1933 { 1934 1935 /* do it in a process context */ 1936 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1937 return 0; 1938 } 1939 1940 /* ARGSUSED */ 1941 static void 1942 run_updateedca_cb(struct run_softc *sc, void *arg) 1943 { 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 int s, aci; 1946 1947 s = splnet(); 1948 /* update MAC TX configuration registers */ 1949 for (aci = 0; aci < WME_NUM_AC; aci++) { 1950 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1951 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1952 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1953 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1954 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1955 } 1956 1957 /* update SCH/DMA registers too */ 1958 run_write(sc, RT2860_WMM_AIFSN_CFG, 1959 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1960 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1961 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1962 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1963 run_write(sc, RT2860_WMM_CWMIN_CFG, 1964 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1965 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1966 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1967 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1968 run_write(sc, RT2860_WMM_CWMAX_CFG, 1969 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1970 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1971 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1972 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1973 run_write(sc, RT2860_WMM_TXOP0_CFG, 1974 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1975 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1976 run_write(sc, RT2860_WMM_TXOP1_CFG, 1977 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1978 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1979 splx(s); 1980 } 1981 1982 #ifdef RUN_HWCRYPTO 1983 static int 1984 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1985 const uint8_t *mac) 1986 { 1987 struct run_softc *sc = ic->ic_ifp->if_softc; 1988 struct ieee80211_node *ni = ic->ic_bss; 1989 struct run_cmd_key cmd; 1990 1991 /* do it in a process context */ 1992 cmd.key = *k; 1993 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1994 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1995 return 1; 1996 } 1997 1998 static void 1999 run_set_key_cb(struct run_softc *sc, void *arg) 2000 { 2001 #ifndef IEEE80211_STA_ONLY 2002 struct ieee80211com *ic = &sc->sc_ic; 2003 #endif 2004 struct run_cmd_key *cmd = arg; 2005 struct ieee80211_key *k = &cmd->key; 2006 uint32_t attr; 2007 uint16_t base; 2008 uint8_t mode, wcid, iv[8]; 2009 2010 /* map net80211 cipher to RT2860 security mode */ 2011 switch (k->wk_cipher->ic_cipher) { 2012 case IEEE80211_CIPHER_WEP: 2013 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2014 if (k->wk_keylen == 5) 2015 mode = RT2860_MODE_WEP40; 2016 else 2017 mode = RT2860_MODE_WEP104; 2018 break; 2019 case IEEE80211_CIPHER_TKIP: 2020 mode = RT2860_MODE_TKIP; 2021 break; 2022 case IEEE80211_CIPHER_AES_CCM: 2023 mode = RT2860_MODE_AES_CCMP; 2024 break; 2025 default: 2026 return; 2027 } 2028 2029 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2030 wcid = 0; /* NB: update WCID0 for group keys */ 2031 base = RT2860_SKEY(0, k->wk_keyix); 2032 } else { 2033 wcid = RUN_AID2WCID(cmd->associd); 2034 base = RT2860_PKEY(wcid); 2035 } 2036 2037 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2038 run_write_region_1(sc, base, k->wk_key, 16); 2039 #ifndef IEEE80211_STA_ONLY 2040 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2041 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 2042 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 2043 } else 2044 #endif 2045 { 2046 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 2047 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 2048 } 2049 } else { 2050 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2051 run_write_region_1(sc, base, k->wk_key, 2052 (k->wk_keylen + 1) & ~1); 2053 } 2054 2055 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2056 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2057 /* set initial packet number in IV+EIV */ 2058 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2059 memset(iv, 0, sizeof(iv)); 2060 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2061 } else { 2062 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2063 iv[0] = k->wk_keytsc >> 8; 2064 iv[1] = (iv[0] | 0x20) & 0x7f; 2065 iv[2] = k->wk_keytsc; 2066 } else /* CCMP */ { 2067 iv[0] = k->wk_keytsc; 2068 iv[1] = k->wk_keytsc >> 8; 2069 iv[2] = 0; 2070 } 2071 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2072 iv[4] = k->wk_keytsc >> 16; 2073 iv[5] = k->wk_keytsc >> 24; 2074 iv[6] = k->wk_keytsc >> 32; 2075 iv[7] = k->wk_keytsc >> 40; 2076 } 2077 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2078 } 2079 2080 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2081 /* install group key */ 2082 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2083 attr &= ~(0xf << (k->wk_keyix * 4)); 2084 attr |= mode << (k->wk_keyix * 4); 2085 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2086 } else { 2087 /* install pairwise key */ 2088 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2089 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2090 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2091 } 2092 } 2093 2094 static int 2095 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2096 { 2097 struct run_softc *sc = ic->ic_ifp->if_softc; 2098 struct ieee80211_node *ni = ic->ic_bss; 2099 struct run_cmd_key cmd; 2100 2101 /* do it in a process context */ 2102 cmd.key = *k; 2103 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2104 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2105 return 1; 2106 } 2107 2108 static void 2109 run_delete_key_cb(struct run_softc *sc, void *arg) 2110 { 2111 struct run_cmd_key *cmd = arg; 2112 struct ieee80211_key *k = &cmd->key; 2113 uint32_t attr; 2114 uint8_t wcid; 2115 2116 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2117 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2118 2119 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2120 /* remove group key */ 2121 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2122 attr &= ~(0xf << (k->wk_keyix * 4)); 2123 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2124 2125 } else { 2126 /* remove pairwise key */ 2127 wcid = RUN_AID2WCID(cmd->associd); 2128 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2129 attr &= ~0xf; 2130 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2131 } 2132 } 2133 #endif 2134 2135 static void 2136 run_calibrate_to(void *arg) 2137 { 2138 2139 /* do it in a process context */ 2140 run_do_async(arg, run_calibrate_cb, NULL, 0); 2141 /* next timeout will be rescheduled in the calibration task */ 2142 } 2143 2144 /* ARGSUSED */ 2145 static void 2146 run_calibrate_cb(struct run_softc *sc, void *arg) 2147 { 2148 struct ifnet *ifp = &sc->sc_if; 2149 uint32_t sta[3]; 2150 int s, error; 2151 2152 /* read statistic counters (clear on read) and update AMRR state */ 2153 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2154 sizeof(sta)); 2155 if (error != 0) 2156 goto skip; 2157 2158 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2159 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2160 le32toh(sta[0]) & 0xffff)); 2161 2162 s = splnet(); 2163 /* count failed TX as errors */ 2164 if_statadd(ifp, if_oerrors, le32toh(sta[0]) & 0xffff); 2165 2166 sc->amn.amn_retrycnt = 2167 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2168 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2169 2170 sc->amn.amn_txcnt = 2171 sc->amn.amn_retrycnt + 2172 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2173 2174 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2175 splx(s); 2176 2177 skip: callout_schedule(&sc->calib_to, hz); 2178 } 2179 2180 static void 2181 run_newassoc(struct ieee80211_node *ni, int isnew) 2182 { 2183 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2184 struct run_node *rn = (void *)ni; 2185 struct ieee80211_rateset *rs = &ni->ni_rates; 2186 uint8_t rate; 2187 int ridx, i, j; 2188 2189 DPRINTF(("new assoc isnew=%d addr=%s\n", 2190 isnew, ether_sprintf(ni->ni_macaddr))); 2191 2192 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2193 /* start at lowest available bit-rate, AMRR will raise */ 2194 ni->ni_txrate = 0; 2195 2196 for (i = 0; i < rs->rs_nrates; i++) { 2197 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2198 /* convert 802.11 rate to hardware rate index */ 2199 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2200 if (rt2860_rates[ridx].rate == rate) 2201 break; 2202 rn->ridx[i] = ridx; 2203 /* determine rate of control response frames */ 2204 for (j = i; j >= 0; j--) { 2205 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2206 rt2860_rates[rn->ridx[i]].phy == 2207 rt2860_rates[rn->ridx[j]].phy) 2208 break; 2209 } 2210 if (j >= 0) { 2211 rn->ctl_ridx[i] = rn->ridx[j]; 2212 } else { 2213 /* no basic rate found, use mandatory one */ 2214 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2215 } 2216 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2217 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2218 } 2219 } 2220 2221 /* 2222 * Return the Rx chain with the highest RSSI for a given frame. 2223 */ 2224 static __inline uint8_t 2225 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2226 { 2227 uint8_t rxchain = 0; 2228 2229 if (sc->nrxchains > 1) { 2230 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2231 rxchain = 1; 2232 if (sc->nrxchains > 2) 2233 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2234 rxchain = 2; 2235 } 2236 return rxchain; 2237 } 2238 2239 static void 2240 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2241 { 2242 struct ieee80211com *ic = &sc->sc_ic; 2243 struct ifnet *ifp = &sc->sc_if; 2244 struct ieee80211_frame *wh; 2245 struct ieee80211_node *ni; 2246 struct rt2870_rxd *rxd; 2247 struct rt2860_rxwi *rxwi; 2248 struct mbuf *m; 2249 uint32_t flags; 2250 uint16_t len, rxwisize, phy; 2251 uint8_t ant, rssi; 2252 int s; 2253 #ifdef RUN_HWCRYPTO 2254 int decrypted = 0; 2255 #endif 2256 2257 rxwi = (struct rt2860_rxwi *)buf; 2258 rxwisize = sizeof(struct rt2860_rxwi); 2259 if (sc->mac_ver == 0x5592) 2260 rxwisize += sizeof(uint64_t); 2261 else if (sc->mac_ver == 0x3593) 2262 rxwisize += sizeof(uint32_t); 2263 len = le16toh(rxwi->len) & 0xfff; 2264 if (__predict_false(len > dmalen)) { 2265 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2266 return; 2267 } 2268 /* Rx descriptor is located at the end */ 2269 rxd = (struct rt2870_rxd *)(buf + dmalen); 2270 flags = le32toh(rxd->flags); 2271 2272 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2273 if_statinc(ifp, if_ierrors); 2274 return; 2275 } 2276 2277 wh = (struct ieee80211_frame *)(buf + rxwisize); 2278 2279 if (__predict_false((flags & RT2860_RX_MICERR))) { 2280 /* report MIC failures to net80211 for TKIP */ 2281 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2282 if_statinc(ifp, if_ierrors); 2283 return; 2284 } 2285 2286 if (flags & RT2860_RX_L2PAD) { 2287 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2288 memmove((uint8_t *)wh + 2, wh, hdrlen); 2289 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2290 } 2291 2292 #ifdef RUN_HWCRYPTO 2293 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2294 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2295 decrypted = 1; 2296 } 2297 #endif 2298 2299 /* could use m_devget but net80211 wants contig mgmt frames */ 2300 MGETHDR(m, M_DONTWAIT, MT_DATA); 2301 if (__predict_false(m == NULL)) { 2302 if_statinc(ifp, if_ierrors); 2303 return; 2304 } 2305 if (len > MHLEN) { 2306 MCLGET(m, M_DONTWAIT); 2307 if (__predict_false(!(m->m_flags & M_EXT))) { 2308 if_statinc(ifp, if_ierrors); 2309 m_freem(m); 2310 return; 2311 } 2312 } 2313 /* finalize mbuf */ 2314 m_set_rcvif(m, ifp); 2315 memcpy(mtod(m, void *), wh, len); 2316 m->m_pkthdr.len = m->m_len = len; 2317 2318 ant = run_maxrssi_chain(sc, rxwi); 2319 rssi = rxwi->rssi[ant]; 2320 2321 if (__predict_false(sc->sc_drvbpf != NULL)) { 2322 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2323 2324 tap->wr_flags = 0; 2325 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2326 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2327 tap->wr_antsignal = rssi; 2328 tap->wr_antenna = ant; 2329 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2330 tap->wr_rate = 2; /* in case it can't be found below */ 2331 phy = le16toh(rxwi->phy); 2332 switch (phy & RT2860_PHY_MODE) { 2333 case RT2860_PHY_CCK: 2334 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2335 case 0: tap->wr_rate = 2; break; 2336 case 1: tap->wr_rate = 4; break; 2337 case 2: tap->wr_rate = 11; break; 2338 case 3: tap->wr_rate = 22; break; 2339 } 2340 if (phy & RT2860_PHY_SHPRE) 2341 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2342 break; 2343 case RT2860_PHY_OFDM: 2344 switch (phy & RT2860_PHY_MCS) { 2345 case 0: tap->wr_rate = 12; break; 2346 case 1: tap->wr_rate = 18; break; 2347 case 2: tap->wr_rate = 24; break; 2348 case 3: tap->wr_rate = 36; break; 2349 case 4: tap->wr_rate = 48; break; 2350 case 5: tap->wr_rate = 72; break; 2351 case 6: tap->wr_rate = 96; break; 2352 case 7: tap->wr_rate = 108; break; 2353 } 2354 break; 2355 } 2356 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2357 } 2358 2359 s = splnet(); 2360 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2361 #ifdef RUN_HWCRYPTO 2362 if (decrypted) { 2363 uint32_t icflags = ic->ic_flags; 2364 2365 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2366 ieee80211_input(ic, m, ni, rssi, 0); 2367 ic->ic_flags = icflags; 2368 } else 2369 #endif 2370 ieee80211_input(ic, m, ni, rssi, 0); 2371 2372 /* node is no longer needed */ 2373 ieee80211_free_node(ni); 2374 2375 /* 2376 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2377 * without calling if_start(). 2378 */ 2379 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2380 run_start(ifp); 2381 2382 splx(s); 2383 } 2384 2385 static void 2386 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2387 { 2388 struct run_rx_data *data = priv; 2389 struct run_softc *sc = data->sc; 2390 uint8_t *buf; 2391 uint32_t dmalen; 2392 int xferlen; 2393 uint16_t rxwisize; 2394 2395 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2396 return; 2397 2398 rxwisize = sizeof(struct rt2860_rxwi); 2399 if (sc->mac_ver == 0x5592) 2400 rxwisize += sizeof(uint64_t); 2401 else if (sc->mac_ver == 0x3593) 2402 rxwisize += sizeof(uint32_t); 2403 2404 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2405 DPRINTF(("RX status=%s\n", usbd_errstr(status))); 2406 if (status == USBD_STALLED) 2407 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2408 if (status != USBD_CANCELLED) 2409 goto skip; 2410 return; 2411 } 2412 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2413 2414 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2415 rxwisize + sizeof(struct rt2870_rxd)))) { 2416 DPRINTF(("xfer too short %d\n", xferlen)); 2417 goto skip; 2418 } 2419 2420 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2421 buf = data->buf; 2422 while (xferlen > 8) { 2423 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2424 2425 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2426 (dmalen & 3) != 0)) { 2427 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2428 break; 2429 } 2430 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2431 DPRINTF(("bad DMA length %u > %d\n", 2432 dmalen + 8, xferlen)); 2433 break; 2434 } 2435 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2436 buf += dmalen + 8; 2437 xferlen -= dmalen + 8; 2438 } 2439 2440 skip: /* setup a new transfer */ 2441 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2442 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2443 status = usbd_transfer(xfer); 2444 if (status != USBD_NORMAL_COMPLETION && 2445 status != USBD_IN_PROGRESS) 2446 device_printf(sc->sc_dev, "requeuing rx failed: %s\n", 2447 usbd_errstr(status)); 2448 } 2449 2450 static void 2451 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2452 { 2453 struct run_tx_data *data = priv; 2454 struct run_softc *sc = data->sc; 2455 struct run_tx_ring *txq = &sc->txq[data->qid]; 2456 struct ifnet *ifp = &sc->sc_if; 2457 int s; 2458 2459 s = splnet(); 2460 txq->queued--; 2461 sc->qfullmsk &= ~(1 << data->qid); 2462 2463 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2464 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2465 return; 2466 2467 DPRINTF(("%s: usb error on tx: %s\n", 2468 device_xname(sc->sc_dev), usbd_errstr(status))); 2469 if (status == USBD_STALLED) 2470 usbd_clear_endpoint_stall_async(txq->pipeh); 2471 if_statinc(ifp, if_oerrors); 2472 splx(s); 2473 return; 2474 } 2475 2476 sc->sc_tx_timer = 0; 2477 if_statinc(ifp, if_opackets); 2478 ifp->if_flags &= ~IFF_OACTIVE; 2479 run_start(ifp); 2480 splx(s); 2481 } 2482 2483 static int 2484 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2485 { 2486 struct ieee80211com *ic = &sc->sc_ic; 2487 struct run_node *rn = (void *)ni; 2488 struct ieee80211_frame *wh; 2489 #ifndef RUN_HWCRYPTO 2490 struct ieee80211_key *k; 2491 #endif 2492 struct run_tx_ring *ring; 2493 struct run_tx_data *data; 2494 struct rt2870_txd *txd; 2495 struct rt2860_txwi *txwi; 2496 uint16_t qos, dur, mcs; 2497 uint16_t txwisize; 2498 uint8_t type, tid, qid; 2499 int hasqos, ridx, ctl_ridx, xferlen; 2500 uint8_t pad; 2501 usbd_status status; 2502 2503 wh = mtod(m, struct ieee80211_frame *); 2504 2505 #ifndef RUN_HWCRYPTO 2506 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2507 k = ieee80211_crypto_encap(ic, ni, m); 2508 if (k == NULL) { 2509 m_freem(m); 2510 return ENOBUFS; 2511 } 2512 2513 /* packet header may have moved, reset our local pointer */ 2514 wh = mtod(m, struct ieee80211_frame *); 2515 } 2516 #endif 2517 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2518 2519 if ((hasqos = ieee80211_has_qos(wh))) { 2520 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2521 tid = qos & IEEE80211_QOS_TID; 2522 qid = TID_TO_WME_AC(tid); 2523 } else { 2524 qos = 0; 2525 tid = 0; 2526 qid = WME_AC_BE; 2527 } 2528 ring = &sc->txq[qid]; 2529 data = &ring->data[ring->cur]; 2530 2531 /* pickup a rate index */ 2532 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2533 type != IEEE80211_FC0_TYPE_DATA) { 2534 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2535 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2536 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2537 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2538 ridx = sc->fixed_ridx; 2539 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2540 } else { 2541 ridx = rn->ridx[ni->ni_txrate]; 2542 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2543 } 2544 2545 /* get MCS code from rate index */ 2546 mcs = rt2860_rates[ridx].mcs; 2547 2548 txwisize = sizeof(struct rt2860_txwi); 2549 if (sc->mac_ver == 0x5592) 2550 txwisize += sizeof(uint32_t); 2551 xferlen = txwisize + m->m_pkthdr.len; 2552 2553 /* roundup to 32-bit alignment */ 2554 xferlen = (xferlen + 3) & ~3; 2555 2556 txd = (struct rt2870_txd *)data->buf; 2557 txd->flags = RT2860_TX_QSEL_EDCA; 2558 txd->len = htole16(xferlen); 2559 2560 /* 2561 * Ether both are true or both are false, the header 2562 * are nicely aligned to 32-bit. So, no L2 padding. 2563 */ 2564 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2565 pad = 0; 2566 else 2567 pad = 2; 2568 2569 /* setup TX Wireless Information */ 2570 txwi = (struct rt2860_txwi *)(txd + 1); 2571 txwi->flags = 0; 2572 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2573 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2574 RUN_AID2WCID(ni->ni_associd) : 0xff; 2575 txwi->len = htole16(m->m_pkthdr.len - pad); 2576 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2577 txwi->phy = htole16(RT2860_PHY_CCK); 2578 if (ridx != RT2860_RIDX_CCK1 && 2579 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2580 mcs |= RT2860_PHY_SHPRE; 2581 } else 2582 mcs |= RT2860_PHY_OFDM; 2583 txwi->phy = htole16(mcs); 2584 2585 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2586 2587 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2588 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2589 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2590 txwi->xflags |= RT2860_TX_ACK; 2591 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2592 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2593 else 2594 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2595 *(uint16_t *)wh->i_dur = htole16(dur); 2596 } 2597 2598 #ifndef IEEE80211_STA_ONLY 2599 /* ask MAC to insert timestamp into probe responses */ 2600 if ((wh->i_fc[0] & 2601 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2602 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2603 /* NOTE: beacons do not pass through tx_data() */ 2604 txwi->flags |= RT2860_TX_TS; 2605 #endif 2606 2607 if (__predict_false(sc->sc_drvbpf != NULL)) { 2608 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2609 2610 tap->wt_flags = 0; 2611 tap->wt_rate = rt2860_rates[ridx].rate; 2612 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2613 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2614 tap->wt_hwqueue = qid; 2615 if (mcs & RT2860_PHY_SHPRE) 2616 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2617 2618 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2619 } 2620 2621 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2622 m_freem(m); 2623 2624 xferlen += sizeof(*txd) + 4; 2625 2626 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2627 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2628 status = usbd_transfer(data->xfer); 2629 if (__predict_false(status != USBD_IN_PROGRESS && 2630 status != USBD_NORMAL_COMPLETION)) { 2631 device_printf(sc->sc_dev, "queuing tx failed: %s\n", 2632 usbd_errstr(status)); 2633 return EIO; 2634 } 2635 2636 ieee80211_free_node(ni); 2637 2638 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2639 if (++ring->queued >= RUN_TX_RING_COUNT) 2640 sc->qfullmsk |= 1 << qid; 2641 2642 return 0; 2643 } 2644 2645 static void 2646 run_start(struct ifnet *ifp) 2647 { 2648 struct run_softc *sc = ifp->if_softc; 2649 struct ieee80211com *ic = &sc->sc_ic; 2650 struct ether_header *eh; 2651 struct ieee80211_node *ni; 2652 struct mbuf *m; 2653 2654 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2655 return; 2656 2657 for (;;) { 2658 if (sc->qfullmsk != 0) { 2659 ifp->if_flags |= IFF_OACTIVE; 2660 break; 2661 } 2662 /* send pending management frames first */ 2663 IF_DEQUEUE(&ic->ic_mgtq, m); 2664 if (m != NULL) { 2665 ni = M_GETCTX(m, struct ieee80211_node *); 2666 M_CLEARCTX(m); 2667 goto sendit; 2668 } 2669 if (ic->ic_state != IEEE80211_S_RUN) 2670 break; 2671 2672 /* encapsulate and send data frames */ 2673 IFQ_DEQUEUE(&ifp->if_snd, m); 2674 if (m == NULL) 2675 break; 2676 if (m->m_len < (int)sizeof(*eh) && 2677 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2678 if_statinc(ifp, if_oerrors); 2679 continue; 2680 } 2681 2682 eh = mtod(m, struct ether_header *); 2683 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2684 if (ni == NULL) { 2685 m_freem(m); 2686 if_statinc(ifp, if_oerrors); 2687 continue; 2688 } 2689 2690 bpf_mtap(ifp, m, BPF_D_OUT); 2691 2692 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2693 ieee80211_free_node(ni); 2694 if_statinc(ifp, if_oerrors); 2695 continue; 2696 } 2697 sendit: 2698 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2699 2700 if (run_tx(sc, m, ni) != 0) { 2701 ieee80211_free_node(ni); 2702 if_statinc(ifp, if_oerrors); 2703 continue; 2704 } 2705 2706 sc->sc_tx_timer = 5; 2707 ifp->if_timer = 1; 2708 } 2709 } 2710 2711 static void 2712 run_watchdog(struct ifnet *ifp) 2713 { 2714 struct run_softc *sc = ifp->if_softc; 2715 struct ieee80211com *ic = &sc->sc_ic; 2716 2717 ifp->if_timer = 0; 2718 2719 if (sc->sc_tx_timer > 0) { 2720 if (--sc->sc_tx_timer == 0) { 2721 device_printf(sc->sc_dev, "device timeout\n"); 2722 /* run_init(ifp); XXX needs a process context! */ 2723 if_statinc(ifp, if_oerrors); 2724 return; 2725 } 2726 ifp->if_timer = 1; 2727 } 2728 2729 ieee80211_watchdog(ic); 2730 } 2731 2732 static int 2733 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2734 { 2735 struct run_softc *sc = ifp->if_softc; 2736 struct ieee80211com *ic = &sc->sc_ic; 2737 int s, error = 0; 2738 2739 s = splnet(); 2740 2741 switch (cmd) { 2742 case SIOCSIFFLAGS: 2743 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2744 break; 2745 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2746 case IFF_UP|IFF_RUNNING: 2747 break; 2748 case IFF_UP: 2749 run_init(ifp); 2750 break; 2751 case IFF_RUNNING: 2752 run_stop(ifp, 1); 2753 break; 2754 case 0: 2755 break; 2756 } 2757 break; 2758 2759 case SIOCADDMULTI: 2760 case SIOCDELMULTI: 2761 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2762 /* setup multicast filter, etc */ 2763 error = 0; 2764 } 2765 break; 2766 2767 default: 2768 error = ieee80211_ioctl(ic, cmd, data); 2769 break; 2770 } 2771 2772 if (error == ENETRESET) { 2773 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2774 (IFF_UP | IFF_RUNNING)) { 2775 run_init(ifp); 2776 } 2777 error = 0; 2778 } 2779 2780 splx(s); 2781 2782 return error; 2783 } 2784 2785 static void 2786 run_select_chan_group(struct run_softc *sc, int group) 2787 { 2788 uint32_t tmp; 2789 uint8_t agc; 2790 2791 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2792 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2793 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2794 if (sc->mac_ver < 0x3572) 2795 run_bbp_write(sc, 86, 0x00); 2796 2797 if (sc->mac_ver == 0x3593) { 2798 run_bbp_write(sc, 77, 0x98); 2799 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2800 } 2801 2802 if (group == 0) { 2803 if (sc->ext_2ghz_lna) { 2804 if (sc->mac_ver >= 0x5390) 2805 run_bbp_write(sc, 75, 0x52); 2806 else { 2807 run_bbp_write(sc, 82, 0x62); 2808 run_bbp_write(sc, 75, 0x46); 2809 } 2810 } else { 2811 if (sc->mac_ver == 0x5592) { 2812 run_bbp_write(sc, 79, 0x1c); 2813 run_bbp_write(sc, 80, 0x0e); 2814 run_bbp_write(sc, 81, 0x3a); 2815 run_bbp_write(sc, 82, 0x62); 2816 2817 run_bbp_write(sc, 195, 0x80); 2818 run_bbp_write(sc, 196, 0xe0); 2819 run_bbp_write(sc, 195, 0x81); 2820 run_bbp_write(sc, 196, 0x1f); 2821 run_bbp_write(sc, 195, 0x82); 2822 run_bbp_write(sc, 196, 0x38); 2823 run_bbp_write(sc, 195, 0x83); 2824 run_bbp_write(sc, 196, 0x32); 2825 run_bbp_write(sc, 195, 0x85); 2826 run_bbp_write(sc, 196, 0x28); 2827 run_bbp_write(sc, 195, 0x86); 2828 run_bbp_write(sc, 196, 0x19); 2829 } else if (sc->mac_ver >= 0x5390) { 2830 run_bbp_write(sc, 75, 0x50); 2831 } else { 2832 run_bbp_write(sc, 82, 2833 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2834 run_bbp_write(sc, 75, 0x50); 2835 } 2836 } 2837 } else { 2838 if (sc->mac_ver == 0x5592) { 2839 run_bbp_write(sc, 79, 0x18); 2840 run_bbp_write(sc, 80, 0x08); 2841 run_bbp_write(sc, 81, 0x38); 2842 run_bbp_write(sc, 82, 0x92); 2843 2844 run_bbp_write(sc, 195, 0x80); 2845 run_bbp_write(sc, 196, 0xf0); 2846 run_bbp_write(sc, 195, 0x81); 2847 run_bbp_write(sc, 196, 0x1e); 2848 run_bbp_write(sc, 195, 0x82); 2849 run_bbp_write(sc, 196, 0x28); 2850 run_bbp_write(sc, 195, 0x83); 2851 run_bbp_write(sc, 196, 0x20); 2852 run_bbp_write(sc, 195, 0x85); 2853 run_bbp_write(sc, 196, 0x7f); 2854 run_bbp_write(sc, 195, 0x86); 2855 run_bbp_write(sc, 196, 0x7f); 2856 } else if (sc->mac_ver == 0x3572) 2857 run_bbp_write(sc, 82, 0x94); 2858 else 2859 run_bbp_write(sc, 82, 2860 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2861 if (sc->ext_5ghz_lna) 2862 run_bbp_write(sc, 75, 0x46); 2863 else 2864 run_bbp_write(sc, 75, 0x50); 2865 } 2866 2867 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2868 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2869 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2870 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2871 2872 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2873 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2874 if (sc->mac_ver == 0x3593) 2875 tmp |= RT3593_LNA_PE_G2_EN | RT3593_LNA_PE_A2_EN; 2876 if (sc->nrxchains > 1) 2877 tmp |= RT2860_LNA_PE1_EN; 2878 if (group == 0) { /* 2GHz */ 2879 tmp |= RT2860_PA_PE_G0_EN; 2880 if (sc->ntxchains > 1) 2881 tmp |= RT2860_PA_PE_G1_EN; 2882 } else { /* 5GHz */ 2883 tmp |= RT2860_PA_PE_A0_EN; 2884 if (sc->ntxchains > 1) 2885 tmp |= RT2860_PA_PE_A1_EN; 2886 if (sc->mac_ver == 0x3593) { 2887 if (sc->ntxchains > 2) 2888 tmp |= RT3593_PA_PE_G2_EN; 2889 } 2890 } 2891 if (sc->mac_ver == 0x3572) { 2892 run_rt3070_rf_write(sc, 8, 0x00); 2893 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2894 run_rt3070_rf_write(sc, 8, 0x80); 2895 } else 2896 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2897 2898 if (sc->mac_ver == 0x5592) { 2899 run_bbp_write(sc, 195, 0x8d); 2900 run_bbp_write(sc, 196, 0x1a); 2901 } 2902 2903 if (sc->mac_ver == 0x3593) { 2904 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2905 tmp &= ~0x01010000; 2906 if (group == 0) 2907 tmp |= 0x00010000; 2908 tmp = (tmp & ~0x00009090) | 0x00000090; 2909 run_write(sc, RT2860_GPIO_CTRL, tmp); 2910 } 2911 2912 /* set initial AGC value */ 2913 if (group == 0) { /* 2GHz band */ 2914 if (sc->mac_ver >= 0x3070) 2915 agc = 0x1c + sc->lna[0] * 2; 2916 else 2917 agc = 0x2e + sc->lna[0]; 2918 } else { /* 5GHz band */ 2919 if (sc->mac_ver == 0x3572) 2920 agc = 0x22 + (sc->lna[group] * 5) / 3; 2921 else 2922 agc = 0x32 + (sc->lna[group] * 5) / 3; 2923 } 2924 run_set_agc(sc, agc); 2925 } 2926 2927 static void 2928 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2929 { 2930 const struct rfprog *rfprog = rt2860_rf2850; 2931 uint32_t r2, r3, r4; 2932 int8_t txpow1, txpow2; 2933 int i; 2934 2935 /* find the settings for this channel (we know it exists) */ 2936 for (i = 0; rfprog[i].chan != chan; i++); 2937 2938 r2 = rfprog[i].r2; 2939 if (sc->ntxchains == 1) 2940 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2941 if (sc->nrxchains == 1) 2942 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2943 else if (sc->nrxchains == 2) 2944 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2945 2946 /* use Tx power values from EEPROM */ 2947 txpow1 = sc->txpow1[i]; 2948 txpow2 = sc->txpow2[i]; 2949 if (chan > 14) { 2950 if (txpow1 >= 0) 2951 txpow1 = txpow1 << 1 | 1; 2952 else 2953 txpow1 = (7 + txpow1) << 1; 2954 if (txpow2 >= 0) 2955 txpow2 = txpow2 << 1 | 1; 2956 else 2957 txpow2 = (7 + txpow2) << 1; 2958 } 2959 r3 = rfprog[i].r3 | txpow1 << 7; 2960 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2961 2962 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2963 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2964 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2965 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2966 2967 usbd_delay_ms(sc->sc_udev, 10); 2968 2969 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2970 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2971 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2972 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2973 2974 usbd_delay_ms(sc->sc_udev, 10); 2975 2976 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2977 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2978 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2979 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2980 } 2981 2982 static void 2983 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2984 { 2985 int8_t txpow1, txpow2; 2986 uint8_t rf; 2987 int i; 2988 2989 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2990 2991 /* find the settings for this channel (we know it exists) */ 2992 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2993 continue; 2994 2995 /* use Tx power values from EEPROM */ 2996 txpow1 = sc->txpow1[i]; 2997 txpow2 = sc->txpow2[i]; 2998 2999 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3000 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3001 run_rt3070_rf_read(sc, 6, &rf); 3002 rf = (rf & ~0x03) | rt3070_freqs[i].r; 3003 run_rt3070_rf_write(sc, 6, rf); 3004 3005 /* set Tx0 power */ 3006 run_rt3070_rf_read(sc, 12, &rf); 3007 rf = (rf & ~0x1f) | txpow1; 3008 run_rt3070_rf_write(sc, 12, rf); 3009 3010 /* set Tx1 power */ 3011 run_rt3070_rf_read(sc, 13, &rf); 3012 rf = (rf & ~0x1f) | txpow2; 3013 run_rt3070_rf_write(sc, 13, rf); 3014 3015 run_rt3070_rf_read(sc, 1, &rf); 3016 rf &= ~0xfc; 3017 if (sc->ntxchains == 1) 3018 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3019 else if (sc->ntxchains == 2) 3020 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3021 if (sc->nrxchains == 1) 3022 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3023 else if (sc->nrxchains == 2) 3024 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3025 run_rt3070_rf_write(sc, 1, rf); 3026 3027 /* set RF offset */ 3028 run_rt3070_rf_read(sc, 23, &rf); 3029 rf = (rf & ~0x7f) | sc->freq; 3030 run_rt3070_rf_write(sc, 23, rf); 3031 3032 /* program RF filter */ 3033 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 3034 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3035 run_rt3070_rf_write(sc, 24, rf); 3036 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3037 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3038 run_rt3070_rf_write(sc, 31, rf); 3039 3040 /* enable RF tuning */ 3041 run_rt3070_rf_read(sc, 7, &rf); 3042 run_rt3070_rf_write(sc, 7, rf | 0x01); 3043 } 3044 3045 static void 3046 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3047 { 3048 int8_t txpow1, txpow2; 3049 uint32_t tmp; 3050 uint8_t rf; 3051 int i; 3052 3053 /* find the settings for this channel (we know it exists) */ 3054 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3055 3056 /* use Tx power values from EEPROM */ 3057 txpow1 = sc->txpow1[i]; 3058 txpow2 = sc->txpow2[i]; 3059 3060 if (chan <= 14) { 3061 run_bbp_write(sc, 25, sc->bbp25); 3062 run_bbp_write(sc, 26, sc->bbp26); 3063 } else { 3064 /* enable IQ phase correction */ 3065 run_bbp_write(sc, 25, 0x09); 3066 run_bbp_write(sc, 26, 0xff); 3067 } 3068 3069 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3070 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3071 run_rt3070_rf_read(sc, 6, &rf); 3072 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3073 rf |= (chan <= 14) ? 0x08 : 0x04; 3074 run_rt3070_rf_write(sc, 6, rf); 3075 3076 /* set PLL mode */ 3077 run_rt3070_rf_read(sc, 5, &rf); 3078 rf &= ~(0x08 | 0x04); 3079 rf |= (chan <= 14) ? 0x04 : 0x08; 3080 run_rt3070_rf_write(sc, 5, rf); 3081 3082 /* set Tx power for chain 0 */ 3083 if (chan <= 14) 3084 rf = 0x60 | txpow1; 3085 else 3086 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3087 run_rt3070_rf_write(sc, 12, rf); 3088 3089 /* set Tx power for chain 1 */ 3090 if (chan <= 14) 3091 rf = 0x60 | txpow2; 3092 else 3093 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3094 run_rt3070_rf_write(sc, 13, rf); 3095 3096 /* set Tx/Rx streams */ 3097 run_rt3070_rf_read(sc, 1, &rf); 3098 rf &= ~0xfc; 3099 if (sc->ntxchains == 1) 3100 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3101 else if (sc->ntxchains == 2) 3102 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3103 if (sc->nrxchains == 1) 3104 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3105 else if (sc->nrxchains == 2) 3106 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3107 run_rt3070_rf_write(sc, 1, rf); 3108 3109 /* set RF offset */ 3110 run_rt3070_rf_read(sc, 23, &rf); 3111 rf = (rf & ~0x7f) | sc->freq; 3112 run_rt3070_rf_write(sc, 23, rf); 3113 3114 /* program RF filter */ 3115 rf = sc->rf24_20mhz; 3116 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3117 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3118 3119 /* enable RF tuning */ 3120 run_rt3070_rf_read(sc, 7, &rf); 3121 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3122 run_rt3070_rf_write(sc, 7, rf); 3123 3124 /* TSSI */ 3125 rf = (chan <= 14) ? 0xc3 : 0xc0; 3126 run_rt3070_rf_write(sc, 9, rf); 3127 3128 /* set loop filter 1 */ 3129 run_rt3070_rf_write(sc, 10, 0xf1); 3130 /* set loop filter 2 */ 3131 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3132 3133 /* set tx_mx2_ic */ 3134 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3135 /* set tx_mx1_ic */ 3136 if (chan <= 14) 3137 rf = 0x48 | sc->txmixgain_2ghz; 3138 else 3139 rf = 0x78 | sc->txmixgain_5ghz; 3140 run_rt3070_rf_write(sc, 16, rf); 3141 3142 /* set tx_lo1 */ 3143 run_rt3070_rf_write(sc, 17, 0x23); 3144 /* set tx_lo2 */ 3145 if (chan <= 14) 3146 rf = 0x93; 3147 else if (chan <= 64) 3148 rf = 0xb7; 3149 else if (chan <= 128) 3150 rf = 0x74; 3151 else 3152 rf = 0x72; 3153 run_rt3070_rf_write(sc, 19, rf); 3154 3155 /* set rx_lo1 */ 3156 if (chan <= 14) 3157 rf = 0xb3; 3158 else if (chan <= 64) 3159 rf = 0xf6; 3160 else if (chan <= 128) 3161 rf = 0xf4; 3162 else 3163 rf = 0xf3; 3164 run_rt3070_rf_write(sc, 20, rf); 3165 3166 /* set pfd_delay */ 3167 if (chan <= 14) 3168 rf = 0x15; 3169 else if (chan <= 64) 3170 rf = 0x3d; 3171 else 3172 rf = 0x01; 3173 run_rt3070_rf_write(sc, 25, rf); 3174 3175 /* set rx_lo2 */ 3176 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3177 /* set ldo_rf_vc */ 3178 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3179 /* set drv_cc */ 3180 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3181 3182 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3183 tmp &= ~0x8080; 3184 if (chan <= 14) 3185 tmp |= 0x80; 3186 run_write(sc, RT2860_GPIO_CTRL, tmp); 3187 3188 /* enable RF tuning */ 3189 run_rt3070_rf_read(sc, 7, &rf); 3190 run_rt3070_rf_write(sc, 7, rf | 0x01); 3191 3192 usbd_delay_ms(sc->sc_udev, 2); 3193 } 3194 3195 static void 3196 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3197 { 3198 int8_t txpow1, txpow2, txpow3; 3199 uint8_t h20mhz, rf; 3200 int i; 3201 3202 /* find the settings for this channel (we know it exists) */ 3203 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3204 3205 /* use Tx power values from EEPROM */ 3206 txpow1 = sc->txpow1[i]; 3207 txpow2 = sc->txpow2[i]; 3208 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3209 3210 if (chan <= 14) { 3211 run_bbp_write(sc, 25, sc->bbp25); 3212 run_bbp_write(sc, 26, sc->bbp26); 3213 } else { 3214 /* Enable IQ phase correction. */ 3215 run_bbp_write(sc, 25, 0x09); 3216 run_bbp_write(sc, 26, 0xff); 3217 } 3218 3219 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3220 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3221 run_rt3070_rf_read(sc, 11, &rf); 3222 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3223 run_rt3070_rf_write(sc, 11, rf); 3224 3225 /* Set pll_idoh. */ 3226 run_rt3070_rf_read(sc, 11, &rf); 3227 rf &= ~0x4c; 3228 rf |= (chan <= 14) ? 0x44 : 0x48; 3229 run_rt3070_rf_write(sc, 11, rf); 3230 3231 if (chan <= 14) 3232 rf = txpow1 & 0x1f; 3233 else 3234 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3235 run_rt3070_rf_write(sc, 53, rf); 3236 3237 if (chan <= 14) 3238 rf = txpow2 & 0x1f; 3239 else 3240 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3241 run_rt3070_rf_write(sc, 55, rf); 3242 3243 if (chan <= 14) 3244 rf = txpow3 & 0x1f; 3245 else 3246 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3247 run_rt3070_rf_write(sc, 54, rf); 3248 3249 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3250 if (sc->ntxchains == 3) 3251 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3252 else 3253 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3254 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3255 run_rt3070_rf_write(sc, 1, rf); 3256 3257 run_adjust_freq_offset(sc); 3258 3259 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3260 3261 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3262 run_rt3070_rf_read(sc, 30, &rf); 3263 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3264 run_rt3070_rf_write(sc, 30, rf); 3265 3266 run_rt3070_rf_read(sc, 36, &rf); 3267 if (chan <= 14) 3268 rf |= 0x80; 3269 else 3270 rf &= ~0x80; 3271 run_rt3070_rf_write(sc, 36, rf); 3272 3273 /* Set vcolo_bs. */ 3274 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3275 /* Set pfd_delay. */ 3276 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3277 3278 /* Set vco bias current control. */ 3279 run_rt3070_rf_read(sc, 6, &rf); 3280 rf &= ~0xc0; 3281 if (chan <= 14) 3282 rf |= 0x40; 3283 else if (chan <= 128) 3284 rf |= 0x80; 3285 else 3286 rf |= 0x40; 3287 run_rt3070_rf_write(sc, 6, rf); 3288 3289 run_rt3070_rf_read(sc, 30, &rf); 3290 rf = (rf & ~0x18) | 0x10; 3291 run_rt3070_rf_write(sc, 30, rf); 3292 3293 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3294 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3295 3296 run_rt3070_rf_read(sc, 51, &rf); 3297 rf = (rf & ~0x03) | 0x01; 3298 run_rt3070_rf_write(sc, 51, rf); 3299 /* Set tx_mx1_cc. */ 3300 run_rt3070_rf_read(sc, 51, &rf); 3301 rf &= ~0x1c; 3302 rf |= (chan <= 14) ? 0x14 : 0x10; 3303 run_rt3070_rf_write(sc, 51, rf); 3304 /* Set tx_mx1_ic. */ 3305 run_rt3070_rf_read(sc, 51, &rf); 3306 rf &= ~0xe0; 3307 rf |= (chan <= 14) ? 0x60 : 0x40; 3308 run_rt3070_rf_write(sc, 51, rf); 3309 /* Set tx_lo1_ic. */ 3310 run_rt3070_rf_read(sc, 49, &rf); 3311 rf &= ~0x1c; 3312 rf |= (chan <= 14) ? 0x0c : 0x08; 3313 run_rt3070_rf_write(sc, 49, rf); 3314 /* Set tx_lo1_en. */ 3315 run_rt3070_rf_read(sc, 50, &rf); 3316 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3317 /* Set drv_cc. */ 3318 run_rt3070_rf_read(sc, 57, &rf); 3319 rf &= ~0xfc; 3320 rf |= (chan <= 14) ? 0x6c : 0x3c; 3321 run_rt3070_rf_write(sc, 57, rf); 3322 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3323 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3324 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3325 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3326 /* Enable VCO calibration. */ 3327 run_rt3070_rf_read(sc, 3, &rf); 3328 rf &= ~RT5390_VCOCAL; 3329 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3330 run_rt3070_rf_write(sc, 3, rf); 3331 3332 if (chan <= 14) 3333 rf = 0x23; 3334 else if (chan <= 64) 3335 rf = 0x36; 3336 else if (chan <= 128) 3337 rf = 0x32; 3338 else 3339 rf = 0x30; 3340 run_rt3070_rf_write(sc, 39, rf); 3341 if (chan <= 14) 3342 rf = 0xbb; 3343 else if (chan <= 64) 3344 rf = 0xeb; 3345 else if (chan <= 128) 3346 rf = 0xb3; 3347 else 3348 rf = 0x9b; 3349 run_rt3070_rf_write(sc, 45, rf); 3350 3351 /* Set FEQ/AEQ control. */ 3352 run_bbp_write(sc, 105, 0x34); 3353 } 3354 3355 static void 3356 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3357 { 3358 int8_t txpow1, txpow2; 3359 uint8_t rf; 3360 int i; 3361 3362 /* find the settings for this channel (we know it exists) */ 3363 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3364 3365 /* use Tx power values from EEPROM */ 3366 txpow1 = sc->txpow1[i]; 3367 txpow2 = sc->txpow2[i]; 3368 3369 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3370 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3371 run_rt3070_rf_read(sc, 11, &rf); 3372 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3373 run_rt3070_rf_write(sc, 11, rf); 3374 3375 run_rt3070_rf_read(sc, 49, &rf); 3376 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3377 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3378 if ((rf & 0x3f) > 0x27) 3379 rf = (rf & ~0x3f) | 0x27; 3380 run_rt3070_rf_write(sc, 49, rf); 3381 3382 if (sc->mac_ver == 0x5392) { 3383 run_rt3070_rf_read(sc, 50, &rf); 3384 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3385 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3386 if ((rf & 0x3f) > 0x27) 3387 rf = (rf & ~0x3f) | 0x27; 3388 run_rt3070_rf_write(sc, 50, rf); 3389 } 3390 3391 run_rt3070_rf_read(sc, 1, &rf); 3392 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3393 if (sc->mac_ver == 0x5392) 3394 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3395 run_rt3070_rf_write(sc, 1, rf); 3396 3397 if (sc->mac_ver != 0x5392) { 3398 run_rt3070_rf_read(sc, 2, &rf); 3399 rf |= 0x80; 3400 run_rt3070_rf_write(sc, 2, rf); 3401 usbd_delay_ms(sc->sc_udev, 10); 3402 rf &= 0x7f; 3403 run_rt3070_rf_write(sc, 2, rf); 3404 } 3405 3406 run_adjust_freq_offset(sc); 3407 3408 if (sc->mac_ver == 0x5392) { 3409 /* Fix for RT5392C. */ 3410 if (sc->mac_rev >= 0x0223) { 3411 if (chan <= 4) 3412 rf = 0x0f; 3413 else if (chan >= 5 && chan <= 7) 3414 rf = 0x0e; 3415 else 3416 rf = 0x0d; 3417 run_rt3070_rf_write(sc, 23, rf); 3418 3419 if (chan <= 4) 3420 rf = 0x0c; 3421 else if (chan == 5) 3422 rf = 0x0b; 3423 else if (chan >= 6 && chan <= 7) 3424 rf = 0x0a; 3425 else if (chan >= 8 && chan <= 10) 3426 rf = 0x09; 3427 else 3428 rf = 0x08; 3429 run_rt3070_rf_write(sc, 59, rf); 3430 } else { 3431 if (chan <= 11) 3432 rf = 0x0f; 3433 else 3434 rf = 0x0b; 3435 run_rt3070_rf_write(sc, 59, rf); 3436 } 3437 } else { 3438 /* Fix for RT5390F. */ 3439 if (sc->mac_rev >= 0x0502) { 3440 if (chan <= 11) 3441 rf = 0x43; 3442 else 3443 rf = 0x23; 3444 run_rt3070_rf_write(sc, 55, rf); 3445 3446 if (chan <= 11) 3447 rf = 0x0f; 3448 else if (chan == 12) 3449 rf = 0x0d; 3450 else 3451 rf = 0x0b; 3452 run_rt3070_rf_write(sc, 59, rf); 3453 } else { 3454 run_rt3070_rf_write(sc, 55, 0x44); 3455 run_rt3070_rf_write(sc, 59, 0x8f); 3456 } 3457 } 3458 3459 /* Enable VCO calibration. */ 3460 run_rt3070_rf_read(sc, 3, &rf); 3461 rf |= RT5390_VCOCAL; 3462 run_rt3070_rf_write(sc, 3, rf); 3463 } 3464 3465 static void 3466 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3467 { 3468 const struct rt5592_freqs *freqs; 3469 uint32_t tmp; 3470 uint8_t reg, rf, txpow_bound; 3471 int8_t txpow1, txpow2; 3472 int i; 3473 3474 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3475 freqs = (tmp & RT5592_SEL_XTAL) ? 3476 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3477 3478 /* find the settings for this channel (we know it exists) */ 3479 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3480 3481 /* use Tx power values from EEPROM */ 3482 txpow1 = sc->txpow1[i]; 3483 txpow2 = sc->txpow2[i]; 3484 3485 run_read(sc, RT3070_LDO_CFG0, &tmp); 3486 tmp &= ~0x1c000000; 3487 if (chan > 14) 3488 tmp |= 0x14000000; 3489 run_write(sc, RT3070_LDO_CFG0, tmp); 3490 3491 /* N setting. */ 3492 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3493 run_rt3070_rf_read(sc, 9, &rf); 3494 rf &= ~(1 << 4); 3495 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3496 run_rt3070_rf_write(sc, 9, rf); 3497 3498 /* K setting. */ 3499 run_rt3070_rf_read(sc, 9, &rf); 3500 rf &= ~0x0f; 3501 rf |= (freqs->k & 0x0f); 3502 run_rt3070_rf_write(sc, 9, rf); 3503 3504 /* Mode setting. */ 3505 run_rt3070_rf_read(sc, 11, &rf); 3506 rf &= ~0x0c; 3507 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3508 run_rt3070_rf_write(sc, 11, rf); 3509 run_rt3070_rf_read(sc, 9, &rf); 3510 rf &= ~(1 << 7); 3511 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3512 run_rt3070_rf_write(sc, 9, rf); 3513 3514 /* R setting. */ 3515 run_rt3070_rf_read(sc, 11, &rf); 3516 rf &= ~0x03; 3517 rf |= (freqs->r - 0x1); 3518 run_rt3070_rf_write(sc, 11, rf); 3519 3520 if (chan <= 14) { 3521 /* Initialize RF registers for 2GHZ. */ 3522 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3523 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3524 rt5592_2ghz_def_rf[i].val); 3525 } 3526 3527 rf = (chan <= 10) ? 0x07 : 0x06; 3528 run_rt3070_rf_write(sc, 23, rf); 3529 run_rt3070_rf_write(sc, 59, rf); 3530 3531 run_rt3070_rf_write(sc, 55, 0x43); 3532 3533 /* 3534 * RF R49/R50 Tx power ALC code. 3535 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3536 */ 3537 reg = 2; 3538 txpow_bound = 0x27; 3539 } else { 3540 /* Initialize RF registers for 5GHZ. */ 3541 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3542 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3543 rt5592_5ghz_def_rf[i].val); 3544 } 3545 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3546 if (chan >= rt5592_chan_5ghz[i].firstchan && 3547 chan <= rt5592_chan_5ghz[i].lastchan) { 3548 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3549 rt5592_chan_5ghz[i].val); 3550 } 3551 } 3552 3553 /* 3554 * RF R49/R50 Tx power ALC code. 3555 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3556 */ 3557 reg = 3; 3558 txpow_bound = 0x2b; 3559 } 3560 3561 /* RF R49 ch0 Tx power ALC code. */ 3562 run_rt3070_rf_read(sc, 49, &rf); 3563 rf &= ~0xc0; 3564 rf |= (reg << 6); 3565 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3566 if ((rf & 0x3f) > txpow_bound) 3567 rf = (rf & ~0x3f) | txpow_bound; 3568 run_rt3070_rf_write(sc, 49, rf); 3569 3570 /* RF R50 ch1 Tx power ALC code. */ 3571 run_rt3070_rf_read(sc, 50, &rf); 3572 rf &= ~(1 << 7 | 1 << 6); 3573 rf |= (reg << 6); 3574 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3575 if ((rf & 0x3f) > txpow_bound) 3576 rf = (rf & ~0x3f) | txpow_bound; 3577 run_rt3070_rf_write(sc, 50, rf); 3578 3579 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3580 run_rt3070_rf_read(sc, 1, &rf); 3581 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3582 if (sc->ntxchains > 1) 3583 rf |= RT3070_TX1_PD; 3584 if (sc->nrxchains > 1) 3585 rf |= RT3070_RX1_PD; 3586 run_rt3070_rf_write(sc, 1, rf); 3587 3588 run_rt3070_rf_write(sc, 6, 0xe4); 3589 3590 run_rt3070_rf_write(sc, 30, 0x10); 3591 run_rt3070_rf_write(sc, 31, 0x80); 3592 run_rt3070_rf_write(sc, 32, 0x80); 3593 3594 run_adjust_freq_offset(sc); 3595 3596 /* Enable VCO calibration. */ 3597 run_rt3070_rf_read(sc, 3, &rf); 3598 rf |= RT5390_VCOCAL; 3599 run_rt3070_rf_write(sc, 3, rf); 3600 } 3601 3602 static void 3603 run_iq_calib(struct run_softc *sc, u_int chan) 3604 { 3605 uint16_t val; 3606 3607 /* Tx0 IQ gain. */ 3608 run_bbp_write(sc, 158, 0x2c); 3609 if (chan <= 14) 3610 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3611 else if (chan <= 64) { 3612 run_efuse_read(sc, 3613 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3614 &val, 1); 3615 } else if (chan <= 138) { 3616 run_efuse_read(sc, 3617 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3618 &val, 1); 3619 } else if (chan <= 165) { 3620 run_efuse_read(sc, 3621 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3622 &val, 1); 3623 } else 3624 val = 0; 3625 run_bbp_write(sc, 159, val); 3626 3627 /* Tx0 IQ phase. */ 3628 run_bbp_write(sc, 158, 0x2d); 3629 if (chan <= 14) { 3630 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3631 &val, 1); 3632 } else if (chan <= 64) { 3633 run_efuse_read(sc, 3634 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3635 &val, 1); 3636 } else if (chan <= 138) { 3637 run_efuse_read(sc, 3638 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3639 &val, 1); 3640 } else if (chan <= 165) { 3641 run_efuse_read(sc, 3642 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3643 &val, 1); 3644 } else 3645 val = 0; 3646 run_bbp_write(sc, 159, val); 3647 3648 /* Tx1 IQ gain. */ 3649 run_bbp_write(sc, 158, 0x4a); 3650 if (chan <= 14) { 3651 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3652 &val, 1); 3653 } else if (chan <= 64) { 3654 run_efuse_read(sc, 3655 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3656 &val, 1); 3657 } else if (chan <= 138) { 3658 run_efuse_read(sc, 3659 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3660 &val, 1); 3661 } else if (chan <= 165) { 3662 run_efuse_read(sc, 3663 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3664 &val, 1); 3665 } else 3666 val = 0; 3667 run_bbp_write(sc, 159, val); 3668 3669 /* Tx1 IQ phase. */ 3670 run_bbp_write(sc, 158, 0x4b); 3671 if (chan <= 14) { 3672 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3673 &val, 1); 3674 } else if (chan <= 64) { 3675 run_efuse_read(sc, 3676 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3677 &val, 1); 3678 } else if (chan <= 138) { 3679 run_efuse_read(sc, 3680 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3681 &val, 1); 3682 } else if (chan <= 165) { 3683 run_efuse_read(sc, 3684 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3685 &val, 1); 3686 } else 3687 val = 0; 3688 run_bbp_write(sc, 159, val); 3689 3690 /* RF IQ compensation control. */ 3691 run_bbp_write(sc, 158, 0x04); 3692 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3693 &val, 1); 3694 run_bbp_write(sc, 159, val); 3695 3696 /* RF IQ imbalance compensation control. */ 3697 run_bbp_write(sc, 158, 0x03); 3698 run_efuse_read(sc, 3699 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3700 run_bbp_write(sc, 159, val); 3701 } 3702 3703 static void 3704 run_set_agc(struct run_softc *sc, uint8_t agc) 3705 { 3706 uint8_t bbp; 3707 3708 if (sc->mac_ver == 0x3572) { 3709 run_bbp_read(sc, 27, &bbp); 3710 bbp &= ~(0x3 << 5); 3711 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3712 run_bbp_write(sc, 66, agc); 3713 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3714 run_bbp_write(sc, 66, agc); 3715 } else 3716 run_bbp_write(sc, 66, agc); 3717 } 3718 3719 static void 3720 run_set_rx_antenna(struct run_softc *sc, int aux) 3721 { 3722 uint32_t tmp; 3723 uint8_t bbp152; 3724 3725 if (aux) { 3726 if (sc->rf_rev == RT5390_RF_5370) { 3727 run_bbp_read(sc, 152, &bbp152); 3728 bbp152 &= ~0x80; 3729 run_bbp_write(sc, 152, bbp152); 3730 } else { 3731 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3732 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3733 tmp &= ~0x0808; 3734 tmp |= 0x08; 3735 run_write(sc, RT2860_GPIO_CTRL, tmp); 3736 } 3737 } else { 3738 if (sc->rf_rev == RT5390_RF_5370) { 3739 run_bbp_read(sc, 152, &bbp152); 3740 bbp152 |= 0x80; 3741 run_bbp_write(sc, 152, bbp152); 3742 } else { 3743 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3744 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3745 tmp &= ~0x0808; 3746 run_write(sc, RT2860_GPIO_CTRL, tmp); 3747 } 3748 } 3749 } 3750 3751 static int 3752 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3753 { 3754 struct ieee80211com *ic = &sc->sc_ic; 3755 u_int chan, group; 3756 3757 chan = ieee80211_chan2ieee(ic, c); 3758 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3759 return EINVAL; 3760 3761 if (sc->mac_ver == 0x5592) 3762 run_rt5592_set_chan(sc, chan); 3763 else if (sc->mac_ver >= 0x5390) 3764 run_rt5390_set_chan(sc, chan); 3765 else if (sc->mac_ver == 0x3593) 3766 run_rt3593_set_chan(sc, chan); 3767 else if (sc->mac_ver == 0x3572) 3768 run_rt3572_set_chan(sc, chan); 3769 else if (sc->mac_ver >= 0x3070) 3770 run_rt3070_set_chan(sc, chan); 3771 else 3772 run_rt2870_set_chan(sc, chan); 3773 3774 /* determine channel group */ 3775 if (chan <= 14) 3776 group = 0; 3777 else if (chan <= 64) 3778 group = 1; 3779 else if (chan <= 128) 3780 group = 2; 3781 else 3782 group = 3; 3783 3784 /* XXX necessary only when group has changed! */ 3785 run_select_chan_group(sc, group); 3786 3787 usbd_delay_ms(sc->sc_udev, 10); 3788 3789 /* Perform IQ calibration. */ 3790 if (sc->mac_ver >= 0x5392) 3791 run_iq_calib(sc, chan); 3792 3793 return 0; 3794 } 3795 3796 static void 3797 run_updateprot(struct run_softc *sc) 3798 { 3799 struct ieee80211com *ic = &sc->sc_ic; 3800 uint32_t tmp; 3801 3802 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3803 /* setup protection frame rate (MCS code) */ 3804 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3805 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3806 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3807 3808 /* CCK frames don't require protection */ 3809 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3810 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3811 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3812 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3813 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3814 tmp |= RT2860_PROT_CTRL_CTS; 3815 } 3816 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3817 } 3818 3819 static void 3820 run_enable_tsf_sync(struct run_softc *sc) 3821 { 3822 struct ieee80211com *ic = &sc->sc_ic; 3823 uint32_t tmp; 3824 3825 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3826 tmp &= ~0x1fffff; 3827 tmp |= ic->ic_bss->ni_intval * 16; 3828 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3829 if (ic->ic_opmode == IEEE80211_M_STA) { 3830 /* 3831 * Local TSF is always updated with remote TSF on beacon 3832 * reception. 3833 */ 3834 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3835 } 3836 #ifndef IEEE80211_STA_ONLY 3837 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3838 tmp |= RT2860_BCN_TX_EN; 3839 /* 3840 * Local TSF is updated with remote TSF on beacon reception 3841 * only if the remote TSF is greater than local TSF. 3842 */ 3843 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3844 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3845 tmp |= RT2860_BCN_TX_EN; 3846 /* SYNC with nobody */ 3847 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3848 } 3849 #endif 3850 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3851 } 3852 3853 static void 3854 run_enable_mrr(struct run_softc *sc) 3855 { 3856 #define CCK(mcs) (mcs) 3857 #define OFDM(mcs) (1 << 3 | (mcs)) 3858 run_write(sc, RT2860_LG_FBK_CFG0, 3859 OFDM(6) << 28 | /* 54->48 */ 3860 OFDM(5) << 24 | /* 48->36 */ 3861 OFDM(4) << 20 | /* 36->24 */ 3862 OFDM(3) << 16 | /* 24->18 */ 3863 OFDM(2) << 12 | /* 18->12 */ 3864 OFDM(1) << 8 | /* 12-> 9 */ 3865 OFDM(0) << 4 | /* 9-> 6 */ 3866 OFDM(0)); /* 6-> 6 */ 3867 3868 run_write(sc, RT2860_LG_FBK_CFG1, 3869 CCK(2) << 12 | /* 11->5.5 */ 3870 CCK(1) << 8 | /* 5.5-> 2 */ 3871 CCK(0) << 4 | /* 2-> 1 */ 3872 CCK(0)); /* 1-> 1 */ 3873 #undef OFDM 3874 #undef CCK 3875 } 3876 3877 static void 3878 run_set_txpreamble(struct run_softc *sc) 3879 { 3880 uint32_t tmp; 3881 3882 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3883 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3884 tmp |= RT2860_CCK_SHORT_EN; 3885 else 3886 tmp &= ~RT2860_CCK_SHORT_EN; 3887 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3888 } 3889 3890 static void 3891 run_set_basicrates(struct run_softc *sc) 3892 { 3893 struct ieee80211com *ic = &sc->sc_ic; 3894 3895 /* set basic rates mask */ 3896 if (ic->ic_curmode == IEEE80211_MODE_11B) 3897 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3898 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3899 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3900 else /* 11g */ 3901 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3902 } 3903 3904 static void 3905 run_set_leds(struct run_softc *sc, uint16_t which) 3906 { 3907 3908 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3909 which | (sc->leds & 0x7f)); 3910 } 3911 3912 static void 3913 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3914 { 3915 3916 run_write(sc, RT2860_MAC_BSSID_DW0, 3917 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3918 run_write(sc, RT2860_MAC_BSSID_DW1, 3919 bssid[4] | bssid[5] << 8); 3920 } 3921 3922 static void 3923 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3924 { 3925 3926 run_write(sc, RT2860_MAC_ADDR_DW0, 3927 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3928 run_write(sc, RT2860_MAC_ADDR_DW1, 3929 addr[4] | addr[5] << 8 | 0xff << 16); 3930 } 3931 3932 static void 3933 run_updateslot(struct ifnet *ifp) 3934 { 3935 3936 /* do it in a process context */ 3937 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3938 } 3939 3940 /* ARGSUSED */ 3941 static void 3942 run_updateslot_cb(struct run_softc *sc, void *arg) 3943 { 3944 uint32_t tmp; 3945 3946 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3947 tmp &= ~0xff; 3948 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3949 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3950 } 3951 3952 static int8_t 3953 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3954 { 3955 struct ieee80211com *ic = &sc->sc_ic; 3956 struct ieee80211_channel *c = ic->ic_curchan; 3957 int delta; 3958 3959 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3960 u_int chan = ieee80211_chan2ieee(ic, c); 3961 delta = sc->rssi_5ghz[rxchain]; 3962 3963 /* determine channel group */ 3964 if (chan <= 64) 3965 delta -= sc->lna[1]; 3966 else if (chan <= 128) 3967 delta -= sc->lna[2]; 3968 else 3969 delta -= sc->lna[3]; 3970 } else 3971 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3972 3973 return -12 - delta - rssi; 3974 } 3975 3976 static void 3977 run_rt5390_bbp_init(struct run_softc *sc) 3978 { 3979 u_int i; 3980 uint8_t bbp; 3981 3982 /* Apply maximum likelihood detection for 2 stream case. */ 3983 run_bbp_read(sc, 105, &bbp); 3984 if (sc->nrxchains > 1) 3985 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3986 3987 /* Avoid data lost and CRC error. */ 3988 run_bbp_read(sc, 4, &bbp); 3989 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3990 3991 if (sc->mac_ver == 0x5592) { 3992 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3993 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3994 rt5592_def_bbp[i].val); 3995 } 3996 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3997 run_bbp_write(sc, 195, i + 0x80); 3998 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3999 } 4000 } else { 4001 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 4002 run_bbp_write(sc, rt5390_def_bbp[i].reg, 4003 rt5390_def_bbp[i].val); 4004 } 4005 } 4006 if (sc->mac_ver == 0x5392) { 4007 run_bbp_write(sc, 88, 0x90); 4008 run_bbp_write(sc, 95, 0x9a); 4009 run_bbp_write(sc, 98, 0x12); 4010 run_bbp_write(sc, 106, 0x12); 4011 run_bbp_write(sc, 134, 0xd0); 4012 run_bbp_write(sc, 135, 0xf6); 4013 run_bbp_write(sc, 148, 0x84); 4014 } 4015 4016 run_bbp_read(sc, 152, &bbp); 4017 run_bbp_write(sc, 152, bbp | 0x80); 4018 4019 /* Fix BBP254 for RT5592C. */ 4020 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 4021 run_bbp_read(sc, 254, &bbp); 4022 run_bbp_write(sc, 254, bbp | 0x80); 4023 } 4024 4025 /* Disable hardware antenna diversity. */ 4026 if (sc->mac_ver == 0x5390) 4027 run_bbp_write(sc, 154, 0); 4028 4029 /* Initialize Rx CCK/OFDM frequency offset report. */ 4030 run_bbp_write(sc, 142, 1); 4031 run_bbp_write(sc, 143, 57); 4032 } 4033 4034 static int 4035 run_bbp_init(struct run_softc *sc) 4036 { 4037 int i, error, ntries; 4038 uint8_t bbp0; 4039 4040 /* wait for BBP to wake up */ 4041 for (ntries = 0; ntries < 20; ntries++) { 4042 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 4043 return error; 4044 if (bbp0 != 0 && bbp0 != 0xff) 4045 break; 4046 } 4047 if (ntries == 20) 4048 return ETIMEDOUT; 4049 4050 /* initialize BBP registers to default values */ 4051 if (sc->mac_ver >= 0x5390) 4052 run_rt5390_bbp_init(sc); 4053 else { 4054 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 4055 run_bbp_write(sc, rt2860_def_bbp[i].reg, 4056 rt2860_def_bbp[i].val); 4057 } 4058 } 4059 4060 if (sc->mac_ver == 0x3593) { 4061 run_bbp_write(sc, 79, 0x13); 4062 run_bbp_write(sc, 80, 0x05); 4063 run_bbp_write(sc, 81, 0x33); 4064 run_bbp_write(sc, 86, 0x46); 4065 run_bbp_write(sc, 137, 0x0f); 4066 } 4067 4068 /* fix BBP84 for RT2860E */ 4069 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 4070 run_bbp_write(sc, 84, 0x19); 4071 4072 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 4073 sc->mac_ver != 0x5592)) { 4074 run_bbp_write(sc, 79, 0x13); 4075 run_bbp_write(sc, 80, 0x05); 4076 run_bbp_write(sc, 81, 0x33); 4077 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 4078 run_bbp_write(sc, 69, 0x16); 4079 run_bbp_write(sc, 73, 0x12); 4080 } 4081 return 0; 4082 } 4083 4084 static int 4085 run_rt3070_rf_init(struct run_softc *sc) 4086 { 4087 uint32_t tmp; 4088 uint8_t rf, target, bbp4; 4089 int i; 4090 4091 run_rt3070_rf_read(sc, 30, &rf); 4092 /* toggle RF R30 bit 7 */ 4093 run_rt3070_rf_write(sc, 30, rf | 0x80); 4094 usbd_delay_ms(sc->sc_udev, 10); 4095 run_rt3070_rf_write(sc, 30, rf & ~0x80); 4096 4097 /* initialize RF registers to default value */ 4098 if (sc->mac_ver == 0x3572) { 4099 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 4100 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 4101 rt3572_def_rf[i].val); 4102 } 4103 } else { 4104 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 4105 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 4106 rt3070_def_rf[i].val); 4107 } 4108 } 4109 if (sc->mac_ver == 0x3572) { 4110 run_rt3070_rf_read(sc, 6, &rf); 4111 run_rt3070_rf_write(sc, 6, rf | 0x40); 4112 run_rt3070_rf_write(sc, 31, 0x14); 4113 4114 run_read(sc, RT3070_LDO_CFG0, &tmp); 4115 tmp &= ~0x1f000000; 4116 if (sc->mac_rev < 0x0211 && sc->patch_dac) 4117 tmp |= 0x0d000000; /* 1.3V */ 4118 else 4119 tmp |= 0x01000000; /* 1.2V */ 4120 run_write(sc, RT3070_LDO_CFG0, tmp); 4121 } else if (sc->mac_ver == 0x3071) { 4122 run_rt3070_rf_read(sc, 6, &rf); 4123 run_rt3070_rf_write(sc, 6, rf | 0x40); 4124 run_rt3070_rf_write(sc, 31, 0x14); 4125 4126 run_read(sc, RT3070_LDO_CFG0, &tmp); 4127 tmp &= ~0x1f000000; 4128 if (sc->mac_rev < 0x0211) 4129 tmp |= 0x0d000000; /* 1.35V */ 4130 else 4131 tmp |= 0x01000000; /* 1.2V */ 4132 run_write(sc, RT3070_LDO_CFG0, tmp); 4133 4134 /* patch LNA_PE_G1 */ 4135 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4136 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 4137 } else if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 4138 /* 4139 * Change voltage from 1.2V to 1.35V for RT3070. 4140 * The DAC issue (RT3070_LD0_CFG0) has been fixed 4141 * in RT3070(F). 4142 */ 4143 run_read(sc, RT3070_LDO_CFG0, &tmp); 4144 tmp = (tmp & ~0x0f000000) | 0x0d000000; 4145 run_write(sc, RT3070_LDO_CFG0, tmp); 4146 } 4147 4148 /* select 20MHz bandwidth */ 4149 run_rt3070_rf_read(sc, 31, &rf); 4150 run_rt3070_rf_write(sc, 31, rf & ~0x20); 4151 4152 /* calibrate filter for 20MHz bandwidth */ 4153 sc->rf24_20mhz = 0x1f; /* default value */ 4154 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 4155 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 4156 4157 /* select 40MHz bandwidth */ 4158 run_bbp_read(sc, 4, &bbp4); 4159 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 4160 run_rt3070_rf_read(sc, 31, &rf); 4161 run_rt3070_rf_write(sc, 31, rf | 0x20); 4162 4163 /* calibrate filter for 40MHz bandwidth */ 4164 sc->rf24_40mhz = 0x2f; /* default value */ 4165 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4166 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4167 4168 /* go back to 20MHz bandwidth */ 4169 run_bbp_read(sc, 4, &bbp4); 4170 run_bbp_write(sc, 4, bbp4 & ~0x18); 4171 4172 if (sc->mac_ver == 0x3572) { 4173 /* save default BBP registers 25 and 26 values */ 4174 run_bbp_read(sc, 25, &sc->bbp25); 4175 run_bbp_read(sc, 26, &sc->bbp26); 4176 } else if (sc->mac_rev < 0x0211) 4177 run_rt3070_rf_write(sc, 27, 0x03); 4178 4179 run_read(sc, RT3070_OPT_14, &tmp); 4180 run_write(sc, RT3070_OPT_14, tmp | 1); 4181 4182 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4183 run_rt3070_rf_read(sc, 17, &rf); 4184 rf &= ~RT3070_TX_LO1; 4185 if ((sc->mac_ver == 0x3070 || 4186 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4187 !sc->ext_2ghz_lna) 4188 rf |= 0x20; /* fix for long range Rx issue */ 4189 if (sc->txmixgain_2ghz >= 1) 4190 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4191 run_rt3070_rf_write(sc, 17, rf); 4192 } 4193 if (sc->mac_ver == 0x3071) { 4194 run_rt3070_rf_read(sc, 1, &rf); 4195 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4196 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4197 run_rt3070_rf_write(sc, 1, rf); 4198 4199 run_rt3070_rf_read(sc, 15, &rf); 4200 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4201 4202 run_rt3070_rf_read(sc, 20, &rf); 4203 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4204 4205 run_rt3070_rf_read(sc, 21, &rf); 4206 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4207 } 4208 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4209 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4210 run_rt3070_rf_read(sc, 27, &rf); 4211 rf &= ~0x77; 4212 if (sc->mac_rev < 0x0211) 4213 rf |= 0x03; 4214 run_rt3070_rf_write(sc, 27, rf); 4215 } 4216 return 0; 4217 } 4218 4219 static int 4220 run_rt3593_rf_init(struct run_softc *sc) 4221 { 4222 uint32_t tmp; 4223 uint8_t rf; 4224 int i; 4225 4226 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4227 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4228 tmp &= ~(1 << 4 | 1 << 7); 4229 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4230 4231 /* Initialize RF registers to default value. */ 4232 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4233 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4234 rt3593_def_rf[i].val); 4235 } 4236 4237 /* Toggle RF R2 to initiate calibration. */ 4238 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4239 4240 /* Initialize RF frequency offset. */ 4241 run_adjust_freq_offset(sc); 4242 4243 run_rt3070_rf_read(sc, 18, &rf); 4244 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4245 4246 /* 4247 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4248 * decrease voltage back to 1.2V. 4249 */ 4250 run_read(sc, RT3070_LDO_CFG0, &tmp); 4251 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4252 run_write(sc, RT3070_LDO_CFG0, tmp); 4253 usbd_delay_ms(sc->sc_udev, 1); 4254 tmp = (tmp & ~0x1f000000) | 0x01000000; 4255 run_write(sc, RT3070_LDO_CFG0, tmp); 4256 4257 sc->rf24_20mhz = 0x1f; 4258 sc->rf24_40mhz = 0x2f; 4259 4260 /* Save default BBP registers 25 and 26 values. */ 4261 run_bbp_read(sc, 25, &sc->bbp25); 4262 run_bbp_read(sc, 26, &sc->bbp26); 4263 4264 run_read(sc, RT3070_OPT_14, &tmp); 4265 run_write(sc, RT3070_OPT_14, tmp | 1); 4266 return 0; 4267 } 4268 4269 static int 4270 run_rt5390_rf_init(struct run_softc *sc) 4271 { 4272 uint32_t tmp; 4273 uint8_t rf; 4274 int i; 4275 4276 /* Toggle RF R2 to initiate calibration. */ 4277 if (sc->mac_ver == 0x5390) { 4278 run_rt3070_rf_read(sc, 2, &rf); 4279 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4280 usbd_delay_ms(sc->sc_udev, 10); 4281 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4282 } else { 4283 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4284 usbd_delay_ms(sc->sc_udev, 10); 4285 } 4286 4287 /* Initialize RF registers to default value. */ 4288 if (sc->mac_ver == 0x5592) { 4289 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4290 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4291 rt5592_def_rf[i].val); 4292 } 4293 /* Initialize RF frequency offset. */ 4294 run_adjust_freq_offset(sc); 4295 } else if (sc->mac_ver == 0x5392) { 4296 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4297 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4298 rt5392_def_rf[i].val); 4299 } 4300 if (sc->mac_rev >= 0x0223) { 4301 run_rt3070_rf_write(sc, 23, 0x0f); 4302 run_rt3070_rf_write(sc, 24, 0x3e); 4303 run_rt3070_rf_write(sc, 51, 0x32); 4304 run_rt3070_rf_write(sc, 53, 0x22); 4305 run_rt3070_rf_write(sc, 56, 0xc1); 4306 run_rt3070_rf_write(sc, 59, 0x0f); 4307 } 4308 } else { 4309 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4310 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4311 rt5390_def_rf[i].val); 4312 } 4313 if (sc->mac_rev >= 0x0502) { 4314 run_rt3070_rf_write(sc, 6, 0xe0); 4315 run_rt3070_rf_write(sc, 25, 0x80); 4316 run_rt3070_rf_write(sc, 46, 0x73); 4317 run_rt3070_rf_write(sc, 53, 0x00); 4318 run_rt3070_rf_write(sc, 56, 0x42); 4319 run_rt3070_rf_write(sc, 61, 0xd1); 4320 } 4321 } 4322 4323 sc->rf24_20mhz = 0x1f; /* default value */ 4324 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4325 4326 if (sc->mac_rev < 0x0211) 4327 run_rt3070_rf_write(sc, 27, 0x3); 4328 4329 run_read(sc, RT3070_OPT_14, &tmp); 4330 run_write(sc, RT3070_OPT_14, tmp | 1); 4331 return 0; 4332 } 4333 4334 static int 4335 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4336 uint8_t *val) 4337 { 4338 uint8_t rf22, rf24; 4339 uint8_t bbp55_pb, bbp55_sb, delta; 4340 int ntries; 4341 4342 /* program filter */ 4343 run_rt3070_rf_read(sc, 24, &rf24); 4344 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4345 run_rt3070_rf_write(sc, 24, rf24); 4346 4347 /* enable baseband loopback mode */ 4348 run_rt3070_rf_read(sc, 22, &rf22); 4349 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4350 4351 /* set power and frequency of passband test tone */ 4352 run_bbp_write(sc, 24, 0x00); 4353 for (ntries = 0; ntries < 100; ntries++) { 4354 /* transmit test tone */ 4355 run_bbp_write(sc, 25, 0x90); 4356 usbd_delay_ms(sc->sc_udev, 10); 4357 /* read received power */ 4358 run_bbp_read(sc, 55, &bbp55_pb); 4359 if (bbp55_pb != 0) 4360 break; 4361 } 4362 if (ntries == 100) 4363 return ETIMEDOUT; 4364 4365 /* set power and frequency of stopband test tone */ 4366 run_bbp_write(sc, 24, 0x06); 4367 for (ntries = 0; ntries < 100; ntries++) { 4368 /* transmit test tone */ 4369 run_bbp_write(sc, 25, 0x90); 4370 usbd_delay_ms(sc->sc_udev, 10); 4371 /* read received power */ 4372 run_bbp_read(sc, 55, &bbp55_sb); 4373 4374 delta = bbp55_pb - bbp55_sb; 4375 if (delta > target) 4376 break; 4377 4378 /* reprogram filter */ 4379 rf24++; 4380 run_rt3070_rf_write(sc, 24, rf24); 4381 } 4382 if (ntries < 100) { 4383 if (rf24 != init) 4384 rf24--; /* backtrack */ 4385 *val = rf24; 4386 run_rt3070_rf_write(sc, 24, rf24); 4387 } 4388 4389 /* restore initial state */ 4390 run_bbp_write(sc, 24, 0x00); 4391 4392 /* disable baseband loopback mode */ 4393 run_rt3070_rf_read(sc, 22, &rf22); 4394 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4395 4396 return 0; 4397 } 4398 4399 static void 4400 run_rt3070_rf_setup(struct run_softc *sc) 4401 { 4402 uint8_t bbp, rf; 4403 int i; 4404 4405 if (sc->mac_ver == 0x3572) { 4406 /* enable DC filter */ 4407 if (sc->mac_rev >= 0x0201) 4408 run_bbp_write(sc, 103, 0xc0); 4409 4410 run_bbp_read(sc, 138, &bbp); 4411 if (sc->ntxchains == 1) 4412 bbp |= 0x20; /* turn off DAC1 */ 4413 if (sc->nrxchains == 1) 4414 bbp &= ~0x02; /* turn off ADC1 */ 4415 run_bbp_write(sc, 138, bbp); 4416 4417 if (sc->mac_rev >= 0x0211) { 4418 /* improve power consumption */ 4419 run_bbp_read(sc, 31, &bbp); 4420 run_bbp_write(sc, 31, bbp & ~0x03); 4421 } 4422 4423 run_rt3070_rf_read(sc, 16, &rf); 4424 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4425 run_rt3070_rf_write(sc, 16, rf); 4426 } else if (sc->mac_ver == 0x3071) { 4427 /* enable DC filter */ 4428 if (sc->mac_rev >= 0x0201) 4429 run_bbp_write(sc, 103, 0xc0); 4430 4431 run_bbp_read(sc, 138, &bbp); 4432 if (sc->ntxchains == 1) 4433 bbp |= 0x20; /* turn off DAC1 */ 4434 if (sc->nrxchains == 1) 4435 bbp &= ~0x02; /* turn off ADC1 */ 4436 run_bbp_write(sc, 138, bbp); 4437 4438 if (sc->mac_rev >= 0x0211) { 4439 /* improve power consumption */ 4440 run_bbp_read(sc, 31, &bbp); 4441 run_bbp_write(sc, 31, bbp & ~0x03); 4442 } 4443 4444 run_write(sc, RT2860_TX_SW_CFG1, 0); 4445 if (sc->mac_rev < 0x0211) { 4446 run_write(sc, RT2860_TX_SW_CFG2, 4447 sc->patch_dac ? 0x2c : 0x0f); 4448 } else 4449 run_write(sc, RT2860_TX_SW_CFG2, 0); 4450 } else if (sc->mac_ver == 0x3070) { 4451 if (sc->mac_rev >= 0x0201) { 4452 /* enable DC filter */ 4453 run_bbp_write(sc, 103, 0xc0); 4454 4455 /* improve power consumption */ 4456 run_bbp_read(sc, 31, &bbp); 4457 run_bbp_write(sc, 31, bbp & ~0x03); 4458 } 4459 4460 if (sc->mac_rev < 0x0211) { 4461 run_write(sc, RT2860_TX_SW_CFG1, 0); 4462 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4463 } else 4464 run_write(sc, RT2860_TX_SW_CFG2, 0); 4465 } 4466 4467 /* initialize RF registers from ROM for >=RT3071*/ 4468 if (sc->mac_ver >= 0x3071) { 4469 for (i = 0; i < 10; i++) { 4470 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4471 continue; 4472 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4473 } 4474 } 4475 } 4476 4477 static void 4478 run_rt3593_rf_setup(struct run_softc *sc) 4479 { 4480 uint8_t bbp, rf; 4481 4482 if (sc->mac_rev >= 0x0211) { 4483 /* Enable DC filter. */ 4484 run_bbp_write(sc, 103, 0xc0); 4485 } 4486 run_write(sc, RT2860_TX_SW_CFG1, 0); 4487 if (sc->mac_rev < 0x0211) { 4488 run_write(sc, RT2860_TX_SW_CFG2, 4489 sc->patch_dac ? 0x2c : 0x0f); 4490 } else 4491 run_write(sc, RT2860_TX_SW_CFG2, 0); 4492 4493 run_rt3070_rf_read(sc, 50, &rf); 4494 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4495 4496 run_rt3070_rf_read(sc, 51, &rf); 4497 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4498 ((sc->txmixgain_2ghz & 0x07) << 2); 4499 run_rt3070_rf_write(sc, 51, rf); 4500 4501 run_rt3070_rf_read(sc, 38, &rf); 4502 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4503 4504 run_rt3070_rf_read(sc, 39, &rf); 4505 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4506 4507 run_rt3070_rf_read(sc, 1, &rf); 4508 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4509 4510 run_rt3070_rf_read(sc, 30, &rf); 4511 rf = (rf & ~0x18) | 0x10; 4512 run_rt3070_rf_write(sc, 30, rf); 4513 4514 /* Apply maximum likelihood detection for 2 stream case. */ 4515 run_bbp_read(sc, 105, &bbp); 4516 if (sc->nrxchains > 1) 4517 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4518 4519 /* Avoid data lost and CRC error. */ 4520 run_bbp_read(sc, 4, &bbp); 4521 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4522 4523 run_bbp_write(sc, 92, 0x02); 4524 run_bbp_write(sc, 82, 0x82); 4525 run_bbp_write(sc, 106, 0x05); 4526 run_bbp_write(sc, 104, 0x92); 4527 run_bbp_write(sc, 88, 0x90); 4528 run_bbp_write(sc, 148, 0xc8); 4529 run_bbp_write(sc, 47, 0x48); 4530 run_bbp_write(sc, 120, 0x50); 4531 4532 run_bbp_write(sc, 163, 0x9d); 4533 4534 /* SNR mapping. */ 4535 run_bbp_write(sc, 142, 0x06); 4536 run_bbp_write(sc, 143, 0xa0); 4537 run_bbp_write(sc, 142, 0x07); 4538 run_bbp_write(sc, 143, 0xa1); 4539 run_bbp_write(sc, 142, 0x08); 4540 run_bbp_write(sc, 143, 0xa2); 4541 4542 run_bbp_write(sc, 31, 0x08); 4543 run_bbp_write(sc, 68, 0x0b); 4544 run_bbp_write(sc, 105, 0x04); 4545 } 4546 4547 static void 4548 run_rt5390_rf_setup(struct run_softc *sc) 4549 { 4550 uint8_t bbp, rf; 4551 4552 if (sc->mac_rev >= 0x0211) { 4553 /* Enable DC filter. */ 4554 run_bbp_write(sc, 103, 0xc0); 4555 4556 if (sc->mac_ver != 0x5592) { 4557 /* Improve power consumption. */ 4558 run_bbp_read(sc, 31, &bbp); 4559 run_bbp_write(sc, 31, bbp & ~0x03); 4560 } 4561 } 4562 4563 run_bbp_read(sc, 138, &bbp); 4564 if (sc->ntxchains == 1) 4565 bbp |= 0x20; /* turn off DAC1 */ 4566 if (sc->nrxchains == 1) 4567 bbp &= ~0x02; /* turn off ADC1 */ 4568 run_bbp_write(sc, 138, bbp); 4569 4570 run_rt3070_rf_read(sc, 38, &rf); 4571 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4572 4573 run_rt3070_rf_read(sc, 39, &rf); 4574 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4575 4576 /* Avoid data lost and CRC error. */ 4577 run_bbp_read(sc, 4, &bbp); 4578 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4579 4580 run_rt3070_rf_read(sc, 30, &rf); 4581 rf = (rf & ~0x18) | 0x10; 4582 run_rt3070_rf_write(sc, 30, rf); 4583 4584 if (sc->mac_ver != 0x5592) { 4585 run_write(sc, RT2860_TX_SW_CFG1, 0); 4586 if (sc->mac_rev < 0x0211) { 4587 run_write(sc, RT2860_TX_SW_CFG2, 4588 sc->patch_dac ? 0x2c : 0x0f); 4589 } else 4590 run_write(sc, RT2860_TX_SW_CFG2, 0); 4591 } 4592 } 4593 4594 static int 4595 run_txrx_enable(struct run_softc *sc) 4596 { 4597 uint32_t tmp; 4598 int error, ntries; 4599 4600 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4601 for (ntries = 0; ntries < 200; ntries++) { 4602 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4603 return error; 4604 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4605 break; 4606 usbd_delay_ms(sc->sc_udev, 50); 4607 } 4608 if (ntries == 200) 4609 return ETIMEDOUT; 4610 4611 usbd_delay_ms(sc->sc_udev, 50); 4612 4613 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4614 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4615 4616 /* enable Rx bulk aggregation (set timeout and limit) */ 4617 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4618 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4619 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4620 4621 /* set Rx filter */ 4622 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4623 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4624 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4625 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4626 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4627 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4628 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4629 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4630 } 4631 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4632 4633 run_write(sc, RT2860_MAC_SYS_CTRL, 4634 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4635 4636 return 0; 4637 } 4638 4639 static int 4640 run_adjust_freq_offset(struct run_softc *sc) 4641 { 4642 uint8_t rf, tmp; 4643 4644 run_rt3070_rf_read(sc, 17, &rf); 4645 tmp = rf; 4646 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4647 rf = MIN(rf, 0x5f); 4648 4649 if (tmp != rf) 4650 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4651 4652 return 0; 4653 } 4654 4655 static int 4656 run_init(struct ifnet *ifp) 4657 { 4658 struct run_softc *sc = ifp->if_softc; 4659 struct ieee80211com *ic = &sc->sc_ic; 4660 uint32_t tmp; 4661 uint8_t bbp1, bbp3; 4662 int i, error, qid, ridx, ntries; 4663 usbd_status status; 4664 4665 for (ntries = 0; ntries < 100; ntries++) { 4666 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4667 goto fail; 4668 if (tmp != 0 && tmp != 0xffffffff) 4669 break; 4670 usbd_delay_ms(sc->sc_udev, 10); 4671 } 4672 if (ntries == 100) { 4673 error = ETIMEDOUT; 4674 goto fail; 4675 } 4676 4677 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4678 (error = run_load_microcode(sc)) != 0) { 4679 device_printf(sc->sc_dev, 4680 "could not load 8051 microcode\n"); 4681 goto fail; 4682 } 4683 4684 if (ifp->if_flags & IFF_RUNNING) 4685 run_stop(ifp, 0); 4686 4687 /* init host command ring */ 4688 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4689 4690 /* init Tx rings (4 EDCAs) */ 4691 for (qid = 0; qid < 4; qid++) { 4692 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4693 goto fail; 4694 } 4695 /* init Rx ring */ 4696 if ((error = run_alloc_rx_ring(sc)) != 0) 4697 goto fail; 4698 4699 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4700 run_set_macaddr(sc, ic->ic_myaddr); 4701 4702 for (ntries = 0; ntries < 100; ntries++) { 4703 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4704 goto fail; 4705 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4706 break; 4707 usbd_delay_ms(sc->sc_udev, 10); 4708 } 4709 if (ntries == 100) { 4710 device_printf(sc->sc_dev, 4711 "timeout waiting for DMA engine\n"); 4712 error = ETIMEDOUT; 4713 goto fail; 4714 } 4715 tmp &= 0xff0; 4716 tmp |= RT2860_TX_WB_DDONE; 4717 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4718 4719 /* turn off PME_OEN to solve high-current issue */ 4720 run_read(sc, RT2860_SYS_CTRL, &tmp); 4721 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4722 4723 run_write(sc, RT2860_MAC_SYS_CTRL, 4724 RT2860_BBP_HRST | RT2860_MAC_SRST); 4725 run_write(sc, RT2860_USB_DMA_CFG, 0); 4726 4727 if ((error = run_reset(sc)) != 0) { 4728 device_printf(sc->sc_dev, "could not reset chipset\n"); 4729 goto fail; 4730 } 4731 4732 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4733 4734 /* init Tx power for all Tx rates (from EEPROM) */ 4735 for (ridx = 0; ridx < 5; ridx++) { 4736 if (sc->txpow20mhz[ridx] == 0xffffffff) 4737 continue; 4738 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4739 } 4740 4741 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4742 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4743 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4744 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4745 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4746 4747 if (sc->mac_ver >= 0x5390) { 4748 run_write(sc, RT2860_TX_SW_CFG0, 4749 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4750 if (sc->mac_ver >= 0x5392) { 4751 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4752 if (sc->mac_ver == 0x5592) { 4753 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4754 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4755 } else { 4756 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4757 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4758 } 4759 } 4760 } else if (sc->mac_ver >= 0x3593) { 4761 run_write(sc, RT2860_TX_SW_CFG0, 4762 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4763 } else if (sc->mac_ver >= 0x3070) { 4764 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4765 run_write(sc, RT2860_TX_SW_CFG0, 4766 4 << RT2860_DLY_PAPE_EN_SHIFT); 4767 } 4768 4769 /* wait while MAC is busy */ 4770 for (ntries = 0; ntries < 100; ntries++) { 4771 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4772 goto fail; 4773 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4774 break; 4775 DELAY(1000); 4776 } 4777 if (ntries == 100) { 4778 error = ETIMEDOUT; 4779 goto fail; 4780 } 4781 4782 /* clear Host to MCU mailbox */ 4783 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4784 run_write(sc, RT2860_H2M_MAILBOX, 0); 4785 usbd_delay_ms(sc->sc_udev, 10); 4786 4787 if ((error = run_bbp_init(sc)) != 0) { 4788 device_printf(sc->sc_dev, "could not initialize BBP\n"); 4789 goto fail; 4790 } 4791 4792 /* abort TSF synchronization */ 4793 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4794 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4795 RT2860_TBTT_TIMER_EN); 4796 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4797 4798 /* clear RX WCID search table */ 4799 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4800 /* clear Pair-wise key table */ 4801 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4802 /* clear IV/EIV table */ 4803 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4804 /* clear WCID attribute table */ 4805 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4806 /* clear shared key table */ 4807 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4808 /* clear shared key mode */ 4809 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4810 4811 /* clear RX WCID search table */ 4812 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4813 /* clear WCID attribute table */ 4814 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4815 4816 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4817 tmp = (tmp & ~0xff) | 0x1e; 4818 run_write(sc, RT2860_US_CYC_CNT, tmp); 4819 4820 if (sc->mac_rev != 0x0101) 4821 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4822 4823 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4824 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4825 4826 /* write vendor-specific BBP values (from EEPROM) */ 4827 if (sc->mac_ver < 0x3593) { 4828 for (i = 0; i < 10; i++) { 4829 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4830 continue; 4831 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4832 } 4833 } 4834 4835 /* select Main antenna for 1T1R devices */ 4836 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4837 run_set_rx_antenna(sc, 0); 4838 4839 /* send LEDs operating mode to microcontroller */ 4840 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4841 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4842 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4843 4844 if (sc->mac_ver >= 0x5390) 4845 run_rt5390_rf_init(sc); 4846 else if (sc->mac_ver == 0x3593) 4847 run_rt3593_rf_init(sc); 4848 else if (sc->mac_ver >= 0x3070) 4849 run_rt3070_rf_init(sc); 4850 4851 /* disable non-existing Rx chains */ 4852 run_bbp_read(sc, 3, &bbp3); 4853 bbp3 &= ~(1 << 3 | 1 << 4); 4854 if (sc->nrxchains == 2) 4855 bbp3 |= 1 << 3; 4856 else if (sc->nrxchains == 3) 4857 bbp3 |= 1 << 4; 4858 run_bbp_write(sc, 3, bbp3); 4859 4860 /* disable non-existing Tx chains */ 4861 run_bbp_read(sc, 1, &bbp1); 4862 if (sc->ntxchains == 1) 4863 bbp1 &= ~(1 << 3 | 1 << 4); 4864 run_bbp_write(sc, 1, bbp1); 4865 4866 if (sc->mac_ver >= 0x5390) 4867 run_rt5390_rf_setup(sc); 4868 else if (sc->mac_ver == 0x3593) 4869 run_rt3593_rf_setup(sc); 4870 else if (sc->mac_ver >= 0x3070) 4871 run_rt3070_rf_setup(sc); 4872 4873 /* select default channel */ 4874 run_set_chan(sc, ic->ic_curchan); 4875 4876 /* setup initial protection mode */ 4877 run_updateprot(sc); 4878 4879 /* turn radio LED on */ 4880 run_set_leds(sc, RT2860_LED_RADIO); 4881 4882 #ifdef RUN_HWCRYPTO 4883 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4884 /* install WEP keys */ 4885 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4886 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4887 NULL); 4888 } 4889 #endif 4890 4891 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4892 struct run_rx_data *data = &sc->rxq.data[i]; 4893 4894 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4895 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4896 status = usbd_transfer(data->xfer); 4897 if (status != USBD_NORMAL_COMPLETION && 4898 status != USBD_IN_PROGRESS) { 4899 device_printf(sc->sc_dev, "queuing rx failed: %s\n", 4900 usbd_errstr(status)); 4901 error = EIO; 4902 goto fail; 4903 } 4904 } 4905 4906 if ((error = run_txrx_enable(sc)) != 0) 4907 goto fail; 4908 4909 ifp->if_flags &= ~IFF_OACTIVE; 4910 ifp->if_flags |= IFF_RUNNING; 4911 4912 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4913 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4914 else 4915 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4916 4917 if (error != 0) 4918 fail: run_stop(ifp, 1); 4919 return error; 4920 } 4921 4922 static void 4923 run_stop(struct ifnet *ifp, int disable) 4924 { 4925 struct run_softc *sc = ifp->if_softc; 4926 struct ieee80211com *ic = &sc->sc_ic; 4927 uint32_t tmp; 4928 int ntries, qid; 4929 4930 if (ifp->if_flags & IFF_RUNNING) 4931 run_set_leds(sc, 0); /* turn all LEDs off */ 4932 4933 sc->sc_tx_timer = 0; 4934 ifp->if_timer = 0; 4935 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4936 4937 callout_stop(&sc->scan_to); 4938 callout_stop(&sc->calib_to); 4939 4940 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4941 /* wait for all queued asynchronous commands to complete */ 4942 while (sc->cmdq.queued > 0) 4943 tsleep(&sc->cmdq, 0, "cmdq", 0); 4944 4945 /* disable Tx/Rx */ 4946 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4947 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4948 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4949 4950 /* wait for pending Tx to complete */ 4951 for (ntries = 0; ntries < 100; ntries++) { 4952 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4953 break; 4954 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4955 break; 4956 } 4957 DELAY(1000); 4958 run_write(sc, RT2860_USB_DMA_CFG, 0); 4959 4960 /* reset adapter */ 4961 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4962 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4963 4964 /* reset Tx and Rx rings */ 4965 sc->qfullmsk = 0; 4966 for (qid = 0; qid < 4; qid++) 4967 run_free_tx_ring(sc, qid); 4968 run_free_rx_ring(sc); 4969 } 4970 4971 #ifndef IEEE80211_STA_ONLY 4972 static int 4973 run_setup_beacon(struct run_softc *sc) 4974 { 4975 struct ieee80211com *ic = &sc->sc_ic; 4976 struct rt2860_txwi txwi; 4977 struct mbuf *m; 4978 uint16_t txwisize; 4979 int ridx; 4980 4981 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4982 return ENOBUFS; 4983 4984 memset(&txwi, 0, sizeof(txwi)); 4985 txwi.wcid = 0xff; 4986 txwi.len = htole16(m->m_pkthdr.len); 4987 /* send beacons at the lowest available rate */ 4988 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4989 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4990 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4991 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4992 txwi.phy |= htole16(RT2860_PHY_OFDM); 4993 txwi.txop = RT2860_TX_TXOP_HT; 4994 txwi.flags = RT2860_TX_TS; 4995 4996 txwisize = (sc->mac_ver == 0x5592) ? 4997 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4998 run_write_region_1(sc, RT2860_BCN_BASE(0), 4999 (uint8_t *)&txwi, txwisize); 5000 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 5001 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 5002 5003 m_freem(m); 5004 5005 return 0; 5006 } 5007 #endif 5008 5009 MODULE(MODULE_CLASS_DRIVER, if_run, NULL); 5010 5011 #ifdef _MODULE 5012 #include "ioconf.c" 5013 #endif 5014 5015 static int 5016 if_run_modcmd(modcmd_t cmd, void *arg) 5017 { 5018 int error = 0; 5019 5020 switch (cmd) { 5021 case MODULE_CMD_INIT: 5022 #ifdef _MODULE 5023 error = config_init_component(cfdriver_ioconf_run, 5024 cfattach_ioconf_run, cfdata_ioconf_run); 5025 #endif 5026 return error; 5027 case MODULE_CMD_FINI: 5028 #ifdef _MODULE 5029 error = config_fini_component(cfdriver_ioconf_run, 5030 cfattach_ioconf_run, cfdata_ioconf_run); 5031 #endif 5032 return error; 5033 default: 5034 return ENOTTY; 5035 } 5036 } 5037