1 /* $NetBSD: if_mue.c,v 1.50 2019/05/29 09:04:01 mlelstv Exp $ */ 2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2018 Kevin Lo <kevlo@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */ 21 22 #include <sys/cdefs.h> 23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.50 2019/05/29 09:04:01 mlelstv Exp $"); 24 25 #ifdef _KERNEL_OPT 26 #include "opt_usb.h" 27 #include "opt_inet.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/mutex.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/socket.h> 39 40 #include <sys/device.h> 41 42 #include <sys/rndsource.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 49 #include <net/bpf.h> 50 51 #include <netinet/if_inarp.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> /* XXX for struct ip */ 54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdi_util.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usbdevs.h> 64 65 #include <dev/usb/if_muereg.h> 66 #include <dev/usb/if_muevar.h> 67 68 #define MUE_PRINTF(sc, fmt, args...) \ 69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args); 70 71 #ifdef USB_DEBUG 72 int muedebug = 0; 73 #define DPRINTF(sc, fmt, args...) \ 74 do { \ 75 if (muedebug) \ 76 MUE_PRINTF(sc, fmt, ##args); \ 77 } while (0 /* CONSTCOND */) 78 #else 79 #define DPRINTF(sc, fmt, args...) __nothing 80 #endif 81 82 /* 83 * Various supported device vendors/products. 84 */ 85 struct mue_type { 86 struct usb_devno mue_dev; 87 uint16_t mue_flags; 88 #define LAN7500 0x0001 /* LAN7500 */ 89 }; 90 91 const struct mue_type mue_devs[] = { 92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 }, 93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 }, 94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 }, 95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 }, 96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 } 97 }; 98 99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \ 100 uaa->uaa_vendor, uaa->uaa_product)) 101 102 #define MUE_ENADDR_LO(enaddr) \ 103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0]) 104 #define MUE_ENADDR_HI(enaddr) \ 105 ((enaddr[5] << 8) | enaddr[4]) 106 107 static int mue_match(device_t, cfdata_t, void *); 108 static void mue_attach(device_t, device_t, void *); 109 static int mue_detach(device_t, int); 110 static int mue_activate(device_t, enum devact); 111 112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t); 113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t); 114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t, 115 uint32_t, uint32_t); 116 117 static void mue_lock_mii(struct mue_softc *); 118 static void mue_unlock_mii(struct mue_softc *); 119 120 static int mue_miibus_readreg(device_t, int, int, uint16_t *); 121 static int mue_miibus_writereg(device_t, int, int, uint16_t); 122 static void mue_miibus_statchg(struct ifnet *); 123 static int mue_ifmedia_upd(struct ifnet *); 124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *); 127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int); 128 static bool mue_eeprom_present(struct mue_softc *sc); 129 130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int); 131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int); 132 133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t, 134 uint32_t, uint32_t *); 135 136 static void mue_init_ltm(struct mue_softc *); 137 138 static int mue_chip_init(struct mue_softc *); 139 140 static void mue_set_macaddr(struct mue_softc *); 141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t); 142 143 static int mue_rx_list_init(struct mue_softc *); 144 static int mue_tx_list_init(struct mue_softc *); 145 static int mue_open_pipes(struct mue_softc *); 146 static void mue_startup_rx_pipes(struct mue_softc *); 147 148 static int mue_encap(struct mue_softc *, struct mbuf *, int); 149 static int mue_prepare_tso(struct mue_softc *, struct mbuf *); 150 151 static void mue_setmulti(struct mue_softc *); 152 static void mue_sethwcsum(struct mue_softc *); 153 static void mue_setmtu(struct mue_softc *); 154 155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status); 156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status); 157 158 static int mue_init(struct ifnet *); 159 static int mue_ioctl(struct ifnet *, u_long, void *); 160 static void mue_watchdog(struct ifnet *); 161 static void mue_reset(struct mue_softc *); 162 static void mue_start(struct ifnet *); 163 static void mue_stop(struct ifnet *, int); 164 static void mue_tick(void *); 165 static void mue_tick_task(void *); 166 167 static struct mbuf *mue_newbuf(void); 168 169 #define MUE_SETBIT(sc, reg, x) \ 170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x)) 171 172 #define MUE_CLRBIT(sc, reg, x) \ 173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x)) 174 175 #define MUE_WAIT_SET(sc, reg, set, fail) \ 176 mue_wait_for_bits(sc, reg, set, ~0, fail) 177 178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \ 179 mue_wait_for_bits(sc, reg, 0, clear, fail) 180 181 #define ETHER_IS_VALID(addr) \ 182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) 183 184 #define ETHER_IS_ZERO(addr) \ 185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 186 187 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach, 188 mue_detach, mue_activate); 189 190 static uint32_t 191 mue_csr_read(struct mue_softc *sc, uint32_t reg) 192 { 193 usb_device_request_t req; 194 usbd_status err; 195 uDWord val; 196 197 if (sc->mue_dying) 198 return 0; 199 200 USETDW(val, 0); 201 req.bmRequestType = UT_READ_VENDOR_DEVICE; 202 req.bRequest = MUE_UR_READREG; 203 USETW(req.wValue, 0); 204 USETW(req.wIndex, reg); 205 USETW(req.wLength, 4); 206 207 err = usbd_do_request(sc->mue_udev, &req, &val); 208 if (err) { 209 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err)); 210 return 0; 211 } 212 213 return UGETDW(val); 214 } 215 216 static int 217 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval) 218 { 219 usb_device_request_t req; 220 usbd_status err; 221 uDWord val; 222 223 if (sc->mue_dying) 224 return 0; 225 226 USETDW(val, aval); 227 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 228 req.bRequest = MUE_UR_WRITEREG; 229 USETW(req.wValue, 0); 230 USETW(req.wIndex, reg); 231 USETW(req.wLength, 4); 232 233 err = usbd_do_request(sc->mue_udev, &req, &val); 234 if (err) { 235 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err)); 236 return -1; 237 } 238 239 return 0; 240 } 241 242 static int 243 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg, 244 uint32_t set, uint32_t clear, uint32_t fail) 245 { 246 uint32_t val; 247 int ntries; 248 249 for (ntries = 0; ntries < 1000; ntries++) { 250 val = mue_csr_read(sc, reg); 251 if ((val & set) || !(val & clear)) 252 return 0; 253 if (val & fail) 254 return 1; 255 usbd_delay_ms(sc->mue_udev, 1); 256 } 257 258 return 1; 259 } 260 261 /* 262 * Get exclusive access to the MII registers. 263 */ 264 static void 265 mue_lock_mii(struct mue_softc *sc) 266 { 267 sc->mue_refcnt++; 268 mutex_enter(&sc->mue_mii_lock); 269 } 270 271 static void 272 mue_unlock_mii(struct mue_softc *sc) 273 { 274 mutex_exit(&sc->mue_mii_lock); 275 if (--sc->mue_refcnt < 0) 276 usb_detach_wakeupold(sc->mue_dev); 277 } 278 279 static int 280 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 281 { 282 struct mue_softc *sc = device_private(dev); 283 uint32_t data; 284 int rv = 0; 285 286 if (sc->mue_dying) { 287 DPRINTF(sc, "dying\n"); 288 return -1; 289 } 290 291 if (sc->mue_phyno != phy) 292 return -1; 293 294 mue_lock_mii(sc); 295 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 296 mue_unlock_mii(sc); 297 MUE_PRINTF(sc, "not ready\n"); 298 return -1; 299 } 300 301 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ | 302 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 303 MUE_MII_ACCESS_PHYADDR(phy)); 304 305 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 306 MUE_PRINTF(sc, "timed out\n"); 307 rv = ETIMEDOUT; 308 goto out; 309 } 310 311 data = mue_csr_read(sc, MUE_MII_DATA); 312 *val = data & 0xffff; 313 314 out: 315 mue_unlock_mii(sc); 316 return rv; 317 } 318 319 static int 320 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 321 { 322 struct mue_softc *sc = device_private(dev); 323 int rv = 0; 324 325 if (sc->mue_dying) { 326 DPRINTF(sc, "dying\n"); 327 return -1; 328 } 329 330 if (sc->mue_phyno != phy) { 331 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n", 332 sc->mue_phyno, phy); 333 return -1; 334 } 335 336 mue_lock_mii(sc); 337 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 338 MUE_PRINTF(sc, "not ready\n"); 339 rv = EBUSY; 340 goto out; 341 } 342 343 mue_csr_write(sc, MUE_MII_DATA, val); 344 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE | 345 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) | 346 MUE_MII_ACCESS_PHYADDR(phy)); 347 348 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) { 349 MUE_PRINTF(sc, "timed out\n"); 350 rv = ETIMEDOUT; 351 } 352 out: 353 mue_unlock_mii(sc); 354 return rv; 355 } 356 357 static void 358 mue_miibus_statchg(struct ifnet *ifp) 359 { 360 struct mue_softc *sc; 361 struct mii_data *mii; 362 uint32_t flow, threshold; 363 364 if (ifp == NULL) { 365 printf("%s: ifp not ready\n", __func__); 366 return; 367 } 368 369 sc = ifp->if_softc; 370 mii = GET_MII(sc); 371 372 if ((ifp->if_flags & IFF_RUNNING) == 0) { 373 DPRINTF(sc, "not running\n"); 374 return; 375 } 376 377 if (mii == NULL) { 378 DPRINTF(sc, "mii not ready\n"); 379 return; 380 } 381 382 sc->mue_link = 0; 383 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 384 (IFM_ACTIVE | IFM_AVALID)) { 385 switch (IFM_SUBTYPE(mii->mii_media_active)) { 386 case IFM_10_T: 387 case IFM_100_TX: 388 case IFM_1000_T: 389 sc->mue_link++; 390 break; 391 default: 392 break; 393 } 394 } 395 396 /* Lost link, do nothing. */ 397 if (sc->mue_link == 0) { 398 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status); 399 return; 400 } 401 402 if (!(sc->mue_flags & LAN7500)) { 403 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) { 404 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 405 /* Disable U2 and enable U1. */ 406 MUE_CLRBIT(sc, MUE_USB_CFG1, 407 MUE_USB_CFG1_DEV_U2_INIT_EN); 408 MUE_SETBIT(sc, MUE_USB_CFG1, 409 MUE_USB_CFG1_DEV_U1_INIT_EN); 410 } else { 411 /* Enable U1 and U2. */ 412 MUE_SETBIT(sc, MUE_USB_CFG1, 413 MUE_USB_CFG1_DEV_U1_INIT_EN | 414 MUE_USB_CFG1_DEV_U2_INIT_EN); 415 } 416 } 417 } 418 419 flow = 0; 420 /* XXX Linux does not check IFM_FDX flag for 7800. */ 421 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 422 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 423 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME; 424 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 425 flow |= MUE_FLOW_RX_FCEN; 426 } 427 428 /* XXX Magic numbers taken from Linux driver. */ 429 if (sc->mue_flags & LAN7500) 430 threshold = 0x820; 431 else 432 switch (sc->mue_udev->ud_speed) { 433 case USB_SPEED_SUPER: 434 threshold = 0x817; 435 break; 436 case USB_SPEED_HIGH: 437 threshold = 0x211; 438 break; 439 default: 440 threshold = 0; 441 break; 442 } 443 444 /* Threshold value should be set before enabling flow. */ 445 mue_csr_write(sc, (sc->mue_flags & LAN7500) ? 446 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold); 447 mue_csr_write(sc, MUE_FLOW, flow); 448 449 DPRINTF(sc, "done\n"); 450 } 451 452 /* 453 * Set media options. 454 */ 455 static int 456 mue_ifmedia_upd(struct ifnet *ifp) 457 { 458 struct mue_softc *sc = ifp->if_softc; 459 struct mii_data *mii = GET_MII(sc); 460 461 sc->mue_link = 0; /* XXX */ 462 463 if (mii->mii_instance) { 464 struct mii_softc *miisc; 465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 466 mii_phy_reset(miisc); 467 } 468 return mii_mediachg(mii); 469 } 470 471 /* 472 * Report current media status. 473 */ 474 static void 475 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 476 { 477 struct mue_softc *sc = ifp->if_softc; 478 struct mii_data *mii = GET_MII(sc); 479 480 mii_pollstat(mii); 481 ifmr->ifm_active = mii->mii_media_active; 482 ifmr->ifm_status = mii->mii_media_status; 483 } 484 485 static uint8_t 486 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest) 487 { 488 uint32_t val; 489 490 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) { 491 MUE_PRINTF(sc, "not ready\n"); 492 return ETIMEDOUT; 493 } 494 495 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0); 496 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY | 497 off); 498 499 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 500 MUE_E2P_CMD_TIMEOUT)) { 501 MUE_PRINTF(sc, "timed out\n"); 502 return ETIMEDOUT; 503 } 504 505 val = mue_csr_read(sc, MUE_E2P_DATA); 506 *dest = val & 0xff; 507 508 return 0; 509 } 510 511 static int 512 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt) 513 { 514 uint32_t val = 0; /* XXX gcc */ 515 uint8_t byte; 516 int i, err = 0; 517 518 /* 519 * EEPROM pins are muxed with the LED function on LAN7800 device. 520 */ 521 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) { 522 val = mue_csr_read(sc, MUE_HW_CFG); 523 mue_csr_write(sc, MUE_HW_CFG, 524 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN)); 525 } 526 527 for (i = 0; i < cnt; i++) { 528 err = mue_eeprom_getbyte(sc, off + i, &byte); 529 if (err) 530 break; 531 *(dest + i) = byte; 532 } 533 534 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) 535 mue_csr_write(sc, MUE_HW_CFG, val); 536 537 return err ? 1 : 0; 538 } 539 540 static bool 541 mue_eeprom_present(struct mue_softc *sc) 542 { 543 uint32_t val; 544 uint8_t sig; 545 int ret; 546 547 if (sc->mue_flags & LAN7500) { 548 val = mue_csr_read(sc, MUE_E2P_CMD); 549 return val & MUE_E2P_CMD_LOADED; 550 } else { 551 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1); 552 return (ret == 0) && (sig == MUE_E2P_IND); 553 } 554 } 555 556 static int 557 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt) 558 { 559 uint32_t val; 560 int i, err; 561 562 val = mue_csr_read(sc, MUE_OTP_PWR_DN); 563 564 /* Checking if bit is set. */ 565 if (val & MUE_OTP_PWR_DN_PWRDN_N) { 566 /* Clear it, then wait for it to be cleared. */ 567 mue_csr_write(sc, MUE_OTP_PWR_DN, 0); 568 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N, 569 0); 570 if (err) { 571 MUE_PRINTF(sc, "not ready\n"); 572 return 1; 573 } 574 } 575 576 /* Start reading the bytes, one at a time. */ 577 for (i = 0; i < cnt; i++) { 578 mue_csr_write(sc, MUE_OTP_ADDR1, 579 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK); 580 mue_csr_write(sc, MUE_OTP_ADDR2, 581 ((off + i) & MUE_OTP_ADDR2_MASK)); 582 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ); 583 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO); 584 585 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0); 586 if (err) { 587 MUE_PRINTF(sc, "timed out\n"); 588 return 1; 589 } 590 val = mue_csr_read(sc, MUE_OTP_RD_DATA); 591 *(dest + i) = (uint8_t)(val & 0xff); 592 } 593 594 return 0; 595 } 596 597 static int 598 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt) 599 { 600 uint8_t sig; 601 int err; 602 603 if (sc->mue_flags & LAN7500) 604 return 1; 605 606 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1); 607 if (err) 608 return 1; 609 switch (sig) { 610 case MUE_OTP_IND_1: 611 break; 612 case MUE_OTP_IND_2: 613 off += 0x100; 614 break; 615 default: 616 DPRINTF(sc, "OTP not found\n"); 617 return 1; 618 } 619 err = mue_read_otp_raw(sc, dest, off, cnt); 620 return err; 621 } 622 623 static void 624 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr, 625 uint32_t cnt, uint32_t *data) 626 { 627 uint32_t i; 628 629 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) { 630 MUE_PRINTF(sc, "not ready\n"); 631 return; 632 } 633 634 mue_csr_write(sc, MUE_DP_SEL, 635 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel); 636 637 for (i = 0; i < cnt; i++) { 638 mue_csr_write(sc, MUE_DP_ADDR, addr + i); 639 mue_csr_write(sc, MUE_DP_DATA, data[i]); 640 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE); 641 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) { 642 MUE_PRINTF(sc, "timed out\n"); 643 return; 644 } 645 } 646 } 647 648 static void 649 mue_init_ltm(struct mue_softc *sc) 650 { 651 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 }; 652 uint8_t temp[2]; 653 size_t i; 654 655 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) { 656 if (mue_eeprom_present(sc) && 657 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) { 658 if (temp[0] != sizeof(idx)) { 659 DPRINTF(sc, "EEPROM: unexpected size\n"); 660 goto done; 661 } 662 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1, 663 sizeof(idx))) { 664 DPRINTF(sc, "EEPROM: failed to read\n"); 665 goto done; 666 } 667 DPRINTF(sc, "success\n"); 668 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) { 669 if (temp[0] != sizeof(idx)) { 670 DPRINTF(sc, "OTP: unexpected size\n"); 671 goto done; 672 } 673 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1, 674 sizeof(idx))) { 675 DPRINTF(sc, "OTP: failed to read\n"); 676 goto done; 677 } 678 DPRINTF(sc, "success\n"); 679 } else 680 DPRINTF(sc, "nothing to do\n"); 681 } else 682 DPRINTF(sc, "nothing to do\n"); 683 done: 684 for (i = 0; i < __arraycount(idx); i++) 685 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]); 686 } 687 688 static int 689 mue_chip_init(struct mue_softc *sc) 690 { 691 uint32_t val; 692 693 if ((sc->mue_flags & LAN7500) && 694 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) { 695 MUE_PRINTF(sc, "not ready\n"); 696 return ETIMEDOUT; 697 } 698 699 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST); 700 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) { 701 MUE_PRINTF(sc, "timed out\n"); 702 return ETIMEDOUT; 703 } 704 705 /* Respond to the IN token with a NAK. */ 706 if (sc->mue_flags & LAN7500) 707 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR); 708 else 709 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR); 710 711 if (sc->mue_flags & LAN7500) { 712 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH) 713 val = MUE_7500_HS_RX_BUFSIZE / 714 MUE_HS_USB_PKT_SIZE; 715 else 716 val = MUE_7500_FS_RX_BUFSIZE / 717 MUE_FS_USB_PKT_SIZE; 718 mue_csr_write(sc, MUE_7500_BURST_CAP, val); 719 mue_csr_write(sc, MUE_7500_BULKIN_DELAY, 720 MUE_7500_DEFAULT_BULKIN_DELAY); 721 722 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF); 723 724 /* Set FIFO sizes. */ 725 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512; 726 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val); 727 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512; 728 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val); 729 } else { 730 /* Init LTM. */ 731 mue_init_ltm(sc); 732 733 val = MUE_7800_RX_BUFSIZE; 734 switch (sc->mue_udev->ud_speed) { 735 case USB_SPEED_SUPER: 736 val /= MUE_SS_USB_PKT_SIZE; 737 break; 738 case USB_SPEED_HIGH: 739 val /= MUE_HS_USB_PKT_SIZE; 740 break; 741 default: 742 val /= MUE_FS_USB_PKT_SIZE; 743 break; 744 } 745 mue_csr_write(sc, MUE_7800_BURST_CAP, val); 746 mue_csr_write(sc, MUE_7800_BULKIN_DELAY, 747 MUE_7800_DEFAULT_BULKIN_DELAY); 748 749 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF); 750 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE); 751 752 /* 753 * Set FCL's RX and TX FIFO sizes: according to data sheet this 754 * is already the default value. But we initialize it to the 755 * same value anyways, as that's what the Linux driver does. 756 */ 757 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512; 758 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val); 759 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512; 760 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val); 761 } 762 763 /* Enabling interrupts. */ 764 mue_csr_write(sc, MUE_INT_STATUS, ~0); 765 766 mue_csr_write(sc, (sc->mue_flags & LAN7500) ? 767 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0); 768 mue_csr_write(sc, MUE_FLOW, 0); 769 770 /* Reset PHY. */ 771 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST); 772 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) { 773 MUE_PRINTF(sc, "PHY not ready\n"); 774 return ETIMEDOUT; 775 } 776 777 /* LAN7801 only has RGMII mode. */ 778 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801) 779 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN); 780 781 if ((sc->mue_flags & LAN7500) || 782 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 && 783 !mue_eeprom_present(sc))) { 784 /* Allow MAC to detect speed and duplex from PHY. */ 785 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED | 786 MUE_MAC_CR_AUTO_DUPLEX); 787 } 788 789 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN); 790 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ? 791 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN); 792 793 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ? 794 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN); 795 796 /* Set default GPIO/LED settings only if no EEPROM is detected. */ 797 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) { 798 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL); 799 MUE_SETBIT(sc, MUE_LED_CFG, 800 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL); 801 } 802 803 /* XXX We assume two LEDs at least when EEPROM is missing. */ 804 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 && 805 !mue_eeprom_present(sc)) 806 MUE_SETBIT(sc, MUE_HW_CFG, 807 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN); 808 809 return 0; 810 } 811 812 static void 813 mue_set_macaddr(struct mue_softc *sc) 814 { 815 struct ifnet *ifp = GET_IFP(sc); 816 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 817 uint32_t lo, hi; 818 819 lo = MUE_ENADDR_LO(enaddr); 820 hi = MUE_ENADDR_HI(enaddr); 821 822 mue_csr_write(sc, MUE_RX_ADDRL, lo); 823 mue_csr_write(sc, MUE_RX_ADDRH, hi); 824 } 825 826 static int 827 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict) 828 { 829 prop_data_t eaprop; 830 uint32_t low, high; 831 832 if (!(sc->mue_flags & LAN7500)) { 833 low = mue_csr_read(sc, MUE_RX_ADDRL); 834 high = mue_csr_read(sc, MUE_RX_ADDRH); 835 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff); 836 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff); 837 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff); 838 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff); 839 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff); 840 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff); 841 if (ETHER_IS_VALID(sc->mue_enaddr)) 842 return 0; 843 else 844 DPRINTF(sc, "registers: %s\n", 845 ether_sprintf(sc->mue_enaddr)); 846 } 847 848 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr, 849 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) { 850 if (ETHER_IS_VALID(sc->mue_enaddr)) 851 return 0; 852 else 853 DPRINTF(sc, "EEPROM: %s\n", 854 ether_sprintf(sc->mue_enaddr)); 855 } 856 857 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET, 858 ETHER_ADDR_LEN) == 0) { 859 if (ETHER_IS_VALID(sc->mue_enaddr)) 860 return 0; 861 else 862 DPRINTF(sc, "OTP: %s\n", 863 ether_sprintf(sc->mue_enaddr)); 864 } 865 866 /* 867 * Other MD methods. This should be tried only if other methods fail. 868 * Otherwise, MAC address for internal device can be assinged to 869 * external devices on Raspberry Pi, for example. 870 */ 871 eaprop = prop_dictionary_get(dict, "mac-address"); 872 if (eaprop != NULL) { 873 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA); 874 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN); 875 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop), 876 ETHER_ADDR_LEN); 877 if (ETHER_IS_VALID(sc->mue_enaddr)) 878 return 0; 879 else 880 DPRINTF(sc, "prop_dictionary_get: %s\n", 881 ether_sprintf(sc->mue_enaddr)); 882 } 883 884 return 1; 885 } 886 887 888 /* 889 * Probe for a Microchip chip. 890 */ 891 static int 892 mue_match(device_t parent, cfdata_t match, void *aux) 893 { 894 struct usb_attach_arg *uaa = aux; 895 896 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 897 } 898 899 static void 900 mue_attach(device_t parent, device_t self, void *aux) 901 { 902 struct mue_softc *sc = device_private(self); 903 prop_dictionary_t dict = device_properties(self); 904 struct usb_attach_arg *uaa = aux; 905 struct usbd_device *dev = uaa->uaa_device; 906 usb_interface_descriptor_t *id; 907 usb_endpoint_descriptor_t *ed; 908 char *devinfop; 909 struct mii_data *mii; 910 struct ifnet *ifp; 911 usbd_status err; 912 const char *descr; 913 uint8_t i; 914 int s; 915 916 aprint_naive("\n"); 917 aprint_normal("\n"); 918 919 sc->mue_dev = self; 920 sc->mue_udev = dev; 921 922 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0); 923 aprint_normal_dev(self, "%s\n", devinfop); 924 usbd_devinfo_free(devinfop); 925 926 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE); 927 mutex_init(&sc->mue_usb_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 928 929 #define MUE_CONFIG_NO 1 930 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1); 931 if (err) { 932 aprint_error_dev(self, "failed to set configuration: %s\n", 933 usbd_errstr(err)); 934 return; 935 } 936 937 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0); 938 939 #define MUE_IFACE_IDX 0 940 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface); 941 if (err) { 942 aprint_error_dev(self, "failed to get interface handle: %s\n", 943 usbd_errstr(err)); 944 return; 945 } 946 947 sc->mue_product = uaa->uaa_product; 948 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags; 949 950 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV); 951 952 /* Decide on what our bufsize will be. */ 953 if (sc->mue_flags & LAN7500) { 954 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ? 955 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE; 956 sc->mue_rx_list_cnt = 1; 957 sc->mue_tx_list_cnt = 1; 958 } else { 959 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE; 960 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT; 961 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT; 962 } 963 sc->mue_txbufsz = MUE_TX_BUFSIZE; 964 965 /* Find endpoints. */ 966 id = usbd_get_interface_descriptor(sc->mue_iface); 967 for (i = 0; i < id->bNumEndpoints; i++) { 968 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i); 969 if (ed == NULL) { 970 aprint_error_dev(self, "failed to get ep %hhd\n", i); 971 return; 972 } 973 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 974 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 975 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress; 976 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 977 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 978 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress; 979 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 980 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) { 981 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress; 982 } 983 } 984 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0); 985 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0); 986 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0); 987 988 s = splnet(); 989 990 sc->mue_phyno = 1; 991 992 if (mue_chip_init(sc)) { 993 aprint_error_dev(self, "failed to initialize chip\n"); 994 splx(s); 995 return; 996 } 997 998 /* A Microchip chip was detected. Inform the world. */ 999 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800"; 1000 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr, 1001 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID), 1002 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV)); 1003 1004 if (mue_get_macaddr(sc, dict)) { 1005 aprint_error_dev(self, "failed to read MAC address\n"); 1006 splx(s); 1007 return; 1008 } 1009 1010 aprint_normal_dev(self, "Ethernet address %s\n", 1011 ether_sprintf(sc->mue_enaddr)); 1012 1013 /* Initialize interface info.*/ 1014 ifp = GET_IFP(sc); 1015 ifp->if_softc = sc; 1016 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ); 1017 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1018 ifp->if_init = mue_init; 1019 ifp->if_ioctl = mue_ioctl; 1020 ifp->if_start = mue_start; 1021 ifp->if_stop = mue_stop; 1022 ifp->if_watchdog = mue_watchdog; 1023 1024 IFQ_SET_READY(&ifp->if_snd); 1025 1026 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 | 1027 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1028 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1029 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1030 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 1031 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 1032 1033 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1034 #if 0 /* XXX not yet */ 1035 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 1036 #endif 1037 1038 /* Initialize MII/media info. */ 1039 mii = GET_MII(sc); 1040 mii->mii_ifp = ifp; 1041 mii->mii_readreg = mue_miibus_readreg; 1042 mii->mii_writereg = mue_miibus_writereg; 1043 mii->mii_statchg = mue_miibus_statchg; 1044 mii->mii_flags = MIIF_AUTOTSLEEP; 1045 1046 sc->mue_ec.ec_mii = mii; 1047 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts); 1048 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1049 1050 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1051 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1052 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1053 } else 1054 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1055 1056 /* Attach the interface. */ 1057 if_attach(ifp); 1058 ether_ifattach(ifp, sc->mue_enaddr); 1059 1060 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev), 1061 RND_TYPE_NET, RND_FLAG_DEFAULT); 1062 1063 callout_init(&sc->mue_stat_ch, 0); 1064 1065 splx(s); 1066 1067 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev); 1068 } 1069 1070 static int 1071 mue_detach(device_t self, int flags) 1072 { 1073 struct mue_softc *sc = device_private(self); 1074 struct ifnet *ifp = GET_IFP(sc); 1075 size_t i; 1076 int s; 1077 1078 sc->mue_dying = true; 1079 1080 callout_halt(&sc->mue_stat_ch, NULL); 1081 1082 for (i = 0; i < __arraycount(sc->mue_ep); i++) 1083 if (sc->mue_ep[i] != NULL) 1084 usbd_abort_pipe(sc->mue_ep[i]); 1085 1086 /* 1087 * Remove any pending tasks. They cannot be executing because they run 1088 * in the same thread as detach. 1089 */ 1090 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER, 1091 NULL); 1092 1093 s = splusb(); 1094 1095 if (ifp->if_flags & IFF_RUNNING) 1096 mue_stop(ifp, 1); 1097 1098 callout_destroy(&sc->mue_stat_ch); 1099 rnd_detach_source(&sc->mue_rnd_source); 1100 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1101 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY); 1102 if (ifp->if_softc != NULL) { 1103 ether_ifdetach(ifp); 1104 if_detach(ifp); 1105 } 1106 1107 if (--sc->mue_refcnt >= 0) { 1108 /* Wait for processes to go away. */ 1109 usb_detach_waitold(sc->mue_dev); 1110 } 1111 splx(s); 1112 1113 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev); 1114 1115 mutex_destroy(&sc->mue_mii_lock); 1116 mutex_destroy(&sc->mue_usb_lock); 1117 1118 return 0; 1119 } 1120 1121 static int 1122 mue_activate(device_t self, enum devact act) 1123 { 1124 struct mue_softc *sc = device_private(self); 1125 struct ifnet *ifp = GET_IFP(sc); 1126 1127 switch (act) { 1128 case DVACT_DEACTIVATE: 1129 if_deactivate(ifp); 1130 sc->mue_dying = true; 1131 return 0; 1132 default: 1133 return EOPNOTSUPP; 1134 } 1135 return 0; 1136 } 1137 1138 static int 1139 mue_rx_list_init(struct mue_softc *sc) 1140 { 1141 struct mue_cdata *cd; 1142 struct mue_chain *c; 1143 size_t i; 1144 int err; 1145 1146 cd = &sc->mue_cdata; 1147 for (i = 0; i < sc->mue_rx_list_cnt; i++) { 1148 c = &cd->mue_rx_chain[i]; 1149 c->mue_sc = sc; 1150 if (c->mue_xfer == NULL) { 1151 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX], 1152 sc->mue_rxbufsz, 0, 0, &c->mue_xfer); 1153 if (err) 1154 return err; 1155 c->mue_buf = usbd_get_buffer(c->mue_xfer); 1156 } 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int 1163 mue_tx_list_init(struct mue_softc *sc) 1164 { 1165 struct mue_cdata *cd; 1166 struct mue_chain *c; 1167 size_t i; 1168 int err; 1169 1170 cd = &sc->mue_cdata; 1171 for (i = 0; i < sc->mue_tx_list_cnt; i++) { 1172 c = &cd->mue_tx_chain[i]; 1173 c->mue_sc = sc; 1174 if (c->mue_xfer == NULL) { 1175 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX], 1176 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0, 1177 &c->mue_xfer); 1178 if (err) 1179 return err; 1180 c->mue_buf = usbd_get_buffer(c->mue_xfer); 1181 } 1182 } 1183 1184 cd->mue_tx_prod = 0; 1185 cd->mue_tx_cnt = 0; 1186 1187 return 0; 1188 } 1189 1190 static int 1191 mue_open_pipes(struct mue_softc *sc) 1192 { 1193 usbd_status err; 1194 1195 /* Open RX and TX pipes. */ 1196 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX], 1197 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]); 1198 if (err) { 1199 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err)); 1200 return EIO; 1201 } 1202 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX], 1203 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]); 1204 if (err) { 1205 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err)); 1206 return EIO; 1207 } 1208 return 0; 1209 } 1210 1211 static void 1212 mue_startup_rx_pipes(struct mue_softc *sc) 1213 { 1214 struct mue_chain *c; 1215 size_t i; 1216 1217 /* Start up the receive pipe. */ 1218 for (i = 0; i < sc->mue_rx_list_cnt; i++) { 1219 c = &sc->mue_cdata.mue_rx_chain[i]; 1220 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz, 1221 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof); 1222 usbd_transfer(c->mue_xfer); 1223 } 1224 } 1225 1226 static int 1227 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx) 1228 { 1229 struct ifnet *ifp = GET_IFP(sc); 1230 struct mue_chain *c; 1231 usbd_status err; 1232 struct mue_txbuf_hdr hdr; 1233 uint32_t tx_cmd_a, tx_cmd_b; 1234 int csum, len, rv; 1235 bool tso, ipe, tpe; 1236 1237 csum = m->m_pkthdr.csum_flags; 1238 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6); 1239 ipe = csum & M_CSUM_IPv4; 1240 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 | 1241 M_CSUM_TCPv6 | M_CSUM_UDPv6); 1242 1243 len = m->m_pkthdr.len; 1244 if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) || 1245 ( tso && len > MUE_TSO_FRAME_LEN))) { 1246 MUE_PRINTF(sc, "packet length %d\n too long", len); 1247 return EINVAL; 1248 } 1249 1250 c = &sc->mue_cdata.mue_tx_chain[idx]; 1251 1252 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0); 1253 tx_cmd_a = len | MUE_TX_CMD_A_FCS; 1254 1255 if (tso) { 1256 tx_cmd_a |= MUE_TX_CMD_A_LSO; 1257 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN)) 1258 tx_cmd_b = m->m_pkthdr.segsz; 1259 else 1260 tx_cmd_b = MUE_TX_MSS_MIN; 1261 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT; 1262 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0); 1263 rv = mue_prepare_tso(sc, m); 1264 if (__predict_false(rv)) 1265 return rv; 1266 } else { 1267 if (ipe) 1268 tx_cmd_a |= MUE_TX_CMD_A_IPE; 1269 if (tpe) 1270 tx_cmd_a |= MUE_TX_CMD_A_TPE; 1271 tx_cmd_b = 0; 1272 } 1273 1274 hdr.tx_cmd_a = htole32(tx_cmd_a); 1275 hdr.tx_cmd_b = htole32(tx_cmd_b); 1276 1277 memcpy(c->mue_buf, &hdr, sizeof(hdr)); 1278 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr)); 1279 1280 if (__predict_false(c->mue_xfer == NULL)) 1281 return EIO; /* XXX plugged out or down */ 1282 1283 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr), 1284 USBD_FORCE_SHORT_XFER, 10000, mue_txeof); 1285 1286 /* Transmit */ 1287 err = usbd_transfer(c->mue_xfer); 1288 if (__predict_false(err != USBD_IN_PROGRESS)) { 1289 MUE_PRINTF(sc, "%s\n", usbd_errstr(err)); 1290 mue_stop(ifp, 0); 1291 return EIO; 1292 } 1293 1294 return 0; 1295 } 1296 1297 /* 1298 * L3 length field should be cleared. 1299 */ 1300 static int 1301 mue_prepare_tso(struct mue_softc *sc, struct mbuf *m) 1302 { 1303 struct ether_header *eh; 1304 struct ip *ip; 1305 struct ip6_hdr *ip6; 1306 uint16_t type, len = 0; 1307 int off; 1308 1309 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1310 eh = mtod(m, struct ether_header *); 1311 type = eh->ether_type; 1312 } else 1313 m_copydata(m, offsetof(struct ether_header, ether_type), 1314 sizeof(type), &type); 1315 switch (type = htons(type)) { 1316 case ETHERTYPE_IP: 1317 case ETHERTYPE_IPV6: 1318 off = ETHER_HDR_LEN; 1319 break; 1320 case ETHERTYPE_VLAN: 1321 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1322 break; 1323 default: 1324 if (usbd_ratecheck(&sc->mue_tx_notice)) 1325 MUE_PRINTF(sc, "dropping invalid frame " 1326 "type 0x%04hx csum_flags 0x%08x\n", 1327 type, m->m_pkthdr.csum_flags); 1328 return EINVAL; 1329 } 1330 1331 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1332 if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) { 1333 ip = (void *)(mtod(m, char *) + off); 1334 ip->ip_len = 0; 1335 } else 1336 m_copyback(m, off + offsetof(struct ip, ip_len), 1337 sizeof(len), &len); 1338 } else { 1339 if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) { 1340 ip6 = (void *)(mtod(m, char *) + off); 1341 ip6->ip6_plen = 0; 1342 } else 1343 m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen), 1344 sizeof(len), &len); 1345 } 1346 return 0; 1347 } 1348 1349 static void 1350 mue_setmulti(struct mue_softc *sc) 1351 { 1352 struct ethercom *ec = &sc->mue_ec; 1353 struct ifnet *ifp = GET_IFP(sc); 1354 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1355 struct ether_multi *enm; 1356 struct ether_multistep step; 1357 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2]; 1358 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN]; 1359 uint32_t reg, rxfilt, h, hireg, loreg; 1360 size_t i; 1361 1362 if (sc->mue_dying) 1363 return; 1364 1365 /* Clear perfect filter and hash tables. */ 1366 memset(pfiltbl, 0, sizeof(pfiltbl)); 1367 memset(hashtbl, 0, sizeof(hashtbl)); 1368 1369 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL; 1370 rxfilt = mue_csr_read(sc, reg); 1371 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH | 1372 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST); 1373 1374 /* Always accept broadcast frames. */ 1375 rxfilt |= MUE_RFE_CTL_BROADCAST; 1376 1377 if (ifp->if_flags & IFF_PROMISC) { 1378 rxfilt |= MUE_RFE_CTL_UNICAST; 1379 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST; 1380 ifp->if_flags |= IFF_ALLMULTI; 1381 if (ifp->if_flags & IFF_PROMISC) 1382 DPRINTF(sc, "promisc\n"); 1383 else 1384 DPRINTF(sc, "allmulti\n"); 1385 } else { 1386 /* Now program new ones. */ 1387 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID; 1388 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr); 1389 i = 1; 1390 ETHER_LOCK(ec); 1391 ETHER_FIRST_MULTI(step, ec, enm); 1392 while (enm != NULL) { 1393 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1394 ETHER_ADDR_LEN)) { 1395 memset(pfiltbl, 0, sizeof(pfiltbl)); 1396 memset(hashtbl, 0, sizeof(hashtbl)); 1397 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH; 1398 ETHER_UNLOCK(ec); 1399 goto allmulti; 1400 } 1401 if (i < MUE_NUM_ADDR_FILTX) { 1402 /* Use perfect address table if possible. */ 1403 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) | 1404 MUE_ADDR_FILTX_VALID; 1405 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo); 1406 } else { 1407 /* Otherwise, use hash table. */ 1408 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH; 1409 h = (ether_crc32_be(enm->enm_addrlo, 1410 ETHER_ADDR_LEN) >> 23) & 0x1ff; 1411 hashtbl[h / 32] |= 1 << (h % 32); 1412 } 1413 i++; 1414 ETHER_NEXT_MULTI(step, enm); 1415 } 1416 ETHER_UNLOCK(ec); 1417 rxfilt |= MUE_RFE_CTL_PERFECT; 1418 ifp->if_flags &= ~IFF_ALLMULTI; 1419 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) 1420 DPRINTF(sc, "perfect filter and hash tables\n"); 1421 else 1422 DPRINTF(sc, "perfect filter\n"); 1423 } 1424 1425 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) { 1426 hireg = (sc->mue_flags & LAN7500) ? 1427 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i); 1428 loreg = hireg + 4; 1429 mue_csr_write(sc, hireg, 0); 1430 mue_csr_write(sc, loreg, pfiltbl[i][1]); 1431 mue_csr_write(sc, hireg, pfiltbl[i][0]); 1432 } 1433 1434 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN, 1435 MUE_DP_SEL_VHF_HASH_LEN, hashtbl); 1436 1437 mue_csr_write(sc, reg, rxfilt); 1438 } 1439 1440 static void 1441 mue_sethwcsum(struct mue_softc *sc) 1442 { 1443 struct ifnet *ifp = GET_IFP(sc); 1444 uint32_t reg, val; 1445 1446 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL; 1447 val = mue_csr_read(sc, reg); 1448 1449 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 1450 DPRINTF(sc, "RX IPv4 hwcsum enabled\n"); 1451 val |= MUE_RFE_CTL_IP_COE; 1452 } else { 1453 DPRINTF(sc, "RX IPv4 hwcsum disabled\n"); 1454 val &= ~MUE_RFE_CTL_IP_COE; 1455 } 1456 1457 if (ifp->if_capenable & 1458 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1459 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 1460 DPRINTF(sc, "RX L4 hwcsum enabled\n"); 1461 val |= MUE_RFE_CTL_TCPUDP_COE; 1462 } else { 1463 DPRINTF(sc, "RX L4 hwcsum disabled\n"); 1464 val &= ~MUE_RFE_CTL_TCPUDP_COE; 1465 } 1466 1467 val &= ~MUE_RFE_CTL_VLAN_FILTER; 1468 1469 mue_csr_write(sc, reg, val); 1470 } 1471 1472 static void 1473 mue_setmtu(struct mue_softc *sc) 1474 { 1475 struct ifnet *ifp = GET_IFP(sc); 1476 uint32_t val; 1477 1478 /* Set the maximum frame size. */ 1479 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN); 1480 val = mue_csr_read(sc, MUE_MAC_RX); 1481 val &= ~MUE_MAC_RX_MAX_SIZE_MASK; 1482 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu)); 1483 mue_csr_write(sc, MUE_MAC_RX, val); 1484 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN); 1485 } 1486 1487 static void 1488 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1489 { 1490 struct mue_chain *c = (struct mue_chain *)priv; 1491 struct mue_softc *sc = c->mue_sc; 1492 struct ifnet *ifp = GET_IFP(sc); 1493 struct mbuf *m; 1494 struct mue_rxbuf_hdr *hdrp; 1495 uint32_t rx_cmd_a, totlen; 1496 uint16_t pktlen; 1497 int s; 1498 int csum; 1499 char *buf = c->mue_buf; 1500 bool v6; 1501 1502 if (__predict_false(sc->mue_dying)) { 1503 DPRINTF(sc, "dying\n"); 1504 return; 1505 } 1506 1507 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1508 DPRINTF(sc, "%s\n", usbd_errstr(status)); 1509 if (status == USBD_INVAL) 1510 return; /* XXX plugged out or down */ 1511 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1512 return; 1513 if (usbd_ratecheck(&sc->mue_rx_notice)) 1514 MUE_PRINTF(sc, "%s\n", usbd_errstr(status)); 1515 if (status == USBD_STALLED) 1516 usbd_clear_endpoint_stall_async( 1517 sc->mue_ep[MUE_ENDPT_RX]); 1518 goto done; 1519 } 1520 1521 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL); 1522 1523 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u", 1524 totlen, sc->mue_rxbufsz); 1525 1526 do { 1527 if (__predict_false(totlen < sizeof(*hdrp))) { 1528 MUE_PRINTF(sc, "packet length %u too short\n", totlen); 1529 ifp->if_ierrors++; 1530 goto done; 1531 } 1532 1533 hdrp = (struct mue_rxbuf_hdr *)buf; 1534 rx_cmd_a = le32toh(hdrp->rx_cmd_a); 1535 1536 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) { 1537 /* 1538 * We cannot use MUE_RX_CMD_A_RED bit here; 1539 * it is turned on in the cases of L3/L4 1540 * checksum errors which we handle below. 1541 */ 1542 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a); 1543 ifp->if_ierrors++; 1544 goto done; 1545 } 1546 1547 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK); 1548 if (sc->mue_flags & LAN7500) 1549 pktlen -= 2; 1550 1551 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN || 1552 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */ 1553 pktlen + sizeof(*hdrp) > totlen)) { 1554 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen); 1555 ifp->if_ierrors++; 1556 goto done; 1557 } 1558 1559 m = mue_newbuf(); 1560 if (__predict_false(m == NULL)) { 1561 MUE_PRINTF(sc, "failed to allocate mbuf\n"); 1562 ifp->if_ierrors++; 1563 goto done; 1564 } 1565 1566 m_set_rcvif(m, ifp); 1567 m->m_pkthdr.len = m->m_len = pktlen; 1568 m->m_flags |= M_HASFCS; 1569 1570 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) { 1571 csum = 0; 1572 } else { 1573 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV; 1574 switch (rx_cmd_a & MUE_RX_CMD_A_PID) { 1575 case MUE_RX_CMD_A_PID_TCP: 1576 csum = v6 ? 1577 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4; 1578 break; 1579 case MUE_RX_CMD_A_PID_UDP: 1580 csum = v6 ? 1581 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4; 1582 break; 1583 case MUE_RX_CMD_A_PID_IP: 1584 csum = v6 ? 0 : M_CSUM_IPv4; 1585 break; 1586 default: 1587 csum = 0; 1588 break; 1589 } 1590 csum &= ifp->if_csum_flags_rx; 1591 if (__predict_false((csum & M_CSUM_IPv4) && 1592 (rx_cmd_a & MUE_RX_CMD_A_ICE))) 1593 csum |= M_CSUM_IPv4_BAD; 1594 if (__predict_false((csum & ~M_CSUM_IPv4) && 1595 (rx_cmd_a & MUE_RX_CMD_A_TCE))) 1596 csum |= M_CSUM_TCP_UDP_BAD; 1597 } 1598 m->m_pkthdr.csum_flags = csum; 1599 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen); 1600 1601 /* Attention: sizeof(hdr) = 10 */ 1602 pktlen = roundup(pktlen + sizeof(*hdrp), 4); 1603 if (pktlen > totlen) 1604 pktlen = totlen; 1605 totlen -= pktlen; 1606 buf += pktlen; 1607 1608 s = splnet(); 1609 if_percpuq_enqueue(ifp->if_percpuq, m); 1610 splx(s); 1611 } while (totlen > 0); 1612 1613 done: 1614 /* Setup new transfer. */ 1615 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz, 1616 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof); 1617 usbd_transfer(xfer); 1618 } 1619 1620 static void 1621 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1622 { 1623 struct mue_chain *c = priv; 1624 struct mue_softc *sc = c->mue_sc; 1625 struct mue_cdata *cd = &sc->mue_cdata; 1626 struct ifnet *ifp = GET_IFP(sc); 1627 int s; 1628 1629 if (__predict_false(sc->mue_dying)) 1630 return; 1631 1632 s = splnet(); 1633 KASSERT(cd->mue_tx_cnt > 0); 1634 cd->mue_tx_cnt--; 1635 ifp->if_timer = 0; 1636 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1637 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1638 splx(s); 1639 return; 1640 } 1641 ifp->if_oerrors++; 1642 if (usbd_ratecheck(&sc->mue_tx_notice)) 1643 MUE_PRINTF(sc, "%s\n", usbd_errstr(status)); 1644 if (status == USBD_STALLED) 1645 usbd_clear_endpoint_stall_async( 1646 sc->mue_ep[MUE_ENDPT_TX]); 1647 splx(s); 1648 ifp->if_flags &= ~IFF_OACTIVE; 1649 return; 1650 } 1651 1652 ifp->if_flags &= ~IFF_OACTIVE; 1653 1654 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1655 mue_start(ifp); 1656 1657 ifp->if_opackets++; 1658 splx(s); 1659 } 1660 1661 static int 1662 mue_init(struct ifnet *ifp) 1663 { 1664 struct mue_softc *sc = ifp->if_softc; 1665 int s; 1666 1667 if (sc->mue_dying) { 1668 DPRINTF(sc, "dying\n"); 1669 return EIO; 1670 } 1671 1672 s = splnet(); 1673 1674 /* Cancel pending I/O and free all TX/RX buffers. */ 1675 if (ifp->if_flags & IFF_RUNNING) 1676 mue_stop(ifp, 1); 1677 1678 mue_reset(sc); 1679 1680 /* Set MAC address. */ 1681 mue_set_macaddr(sc); 1682 1683 /* Load the multicast filter. */ 1684 mue_setmulti(sc); 1685 1686 /* TCP/UDP checksum offload engines. */ 1687 mue_sethwcsum(sc); 1688 1689 /* Set MTU. */ 1690 mue_setmtu(sc); 1691 1692 if (mue_open_pipes(sc)) { 1693 splx(s); 1694 return EIO; 1695 } 1696 1697 /* Init RX ring. */ 1698 if (mue_rx_list_init(sc)) { 1699 MUE_PRINTF(sc, "failed to init rx list\n"); 1700 splx(s); 1701 return ENOBUFS; 1702 } 1703 1704 /* Init TX ring. */ 1705 if (mue_tx_list_init(sc)) { 1706 MUE_PRINTF(sc, "failed to init tx list\n"); 1707 splx(s); 1708 return ENOBUFS; 1709 } 1710 1711 mue_startup_rx_pipes(sc); 1712 1713 ifp->if_flags |= IFF_RUNNING; 1714 ifp->if_flags &= ~IFF_OACTIVE; 1715 1716 splx(s); 1717 1718 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc); 1719 1720 return 0; 1721 } 1722 1723 static int 1724 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1725 { 1726 struct mue_softc *sc = ifp->if_softc; 1727 int s, error = 0; 1728 1729 s = splnet(); 1730 1731 switch (cmd) { 1732 case SIOCSIFFLAGS: 1733 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1734 break; 1735 1736 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1737 case IFF_RUNNING: 1738 mue_stop(ifp, 1); 1739 break; 1740 case IFF_UP: 1741 mue_init(ifp); 1742 break; 1743 case IFF_UP | IFF_RUNNING: 1744 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC) 1745 mue_setmulti(sc); 1746 else 1747 mue_init(ifp); 1748 break; 1749 } 1750 sc->mue_if_flags = ifp->if_flags; 1751 break; 1752 default: 1753 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1754 break; 1755 error = 0; 1756 switch (cmd) { 1757 case SIOCADDMULTI: 1758 case SIOCDELMULTI: 1759 mue_setmulti(sc); 1760 break; 1761 case SIOCSIFCAP: 1762 mue_sethwcsum(sc); 1763 break; 1764 case SIOCSIFMTU: 1765 mue_setmtu(sc); 1766 break; 1767 default: 1768 break; 1769 } 1770 break; 1771 } 1772 splx(s); 1773 1774 return error; 1775 } 1776 1777 static void 1778 mue_watchdog(struct ifnet *ifp) 1779 { 1780 struct mue_softc *sc = ifp->if_softc; 1781 struct mue_chain *c; 1782 usbd_status stat; 1783 int s; 1784 1785 ifp->if_oerrors++; 1786 MUE_PRINTF(sc, "timed out\n"); 1787 1788 s = splusb(); 1789 c = &sc->mue_cdata.mue_tx_chain[0]; 1790 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat); 1791 mue_txeof(c->mue_xfer, c, stat); 1792 1793 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1794 mue_start(ifp); 1795 splx(s); 1796 } 1797 1798 static void 1799 mue_reset(struct mue_softc *sc) 1800 { 1801 if (sc->mue_dying) 1802 return; 1803 1804 /* Wait a little while for the chip to get its brains in order. */ 1805 usbd_delay_ms(sc->mue_udev, 1); 1806 1807 // mue_chip_init(sc); /* XXX */ 1808 } 1809 1810 static void 1811 mue_start(struct ifnet *ifp) 1812 { 1813 struct mue_softc *sc = ifp->if_softc; 1814 struct mbuf *m; 1815 struct mue_cdata *cd = &sc->mue_cdata; 1816 int idx; 1817 1818 if (__predict_false(!sc->mue_link)) { 1819 DPRINTF(sc, "no link\n"); 1820 return; 1821 } 1822 1823 if (__predict_false((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) 1824 != IFF_RUNNING)) { 1825 DPRINTF(sc, "not ready\n"); 1826 return; 1827 } 1828 1829 mutex_enter(&sc->mue_usb_lock); 1830 1831 idx = cd->mue_tx_prod; 1832 while (cd->mue_tx_cnt < (int)sc->mue_tx_list_cnt) { 1833 IFQ_POLL(&ifp->if_snd, m); 1834 if (m == NULL) 1835 break; 1836 1837 if (__predict_false(mue_encap(sc, m, idx))) { 1838 ifp->if_oerrors++; 1839 break; 1840 } 1841 IFQ_DEQUEUE(&ifp->if_snd, m); 1842 1843 bpf_mtap(ifp, m, BPF_D_OUT); 1844 m_freem(m); 1845 1846 cd->mue_tx_cnt++; 1847 idx = (idx + 1) % sc->mue_tx_list_cnt; 1848 } 1849 cd->mue_tx_prod = idx; 1850 1851 if (cd->mue_tx_cnt >= (int)sc->mue_tx_list_cnt) 1852 ifp->if_flags |= IFF_OACTIVE; 1853 1854 mutex_exit(&sc->mue_usb_lock); 1855 1856 /* Set a timeout in case the chip goes out to lunch. */ 1857 ifp->if_timer = 5; 1858 } 1859 1860 static void 1861 mue_stop(struct ifnet *ifp, int disable __unused) 1862 { 1863 struct mue_softc *sc = ifp->if_softc; 1864 struct mue_chain *c; 1865 usbd_status err; 1866 size_t i; 1867 1868 mue_reset(sc); 1869 1870 ifp->if_timer = 0; 1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1872 1873 callout_stop(&sc->mue_stat_ch); 1874 sc->mue_link = 0; 1875 1876 /* Stop transfers. */ 1877 for (i = 0; i < __arraycount(sc->mue_ep); i++) 1878 if (sc->mue_ep[i] != NULL) { 1879 err = usbd_abort_pipe(sc->mue_ep[i]); 1880 if (err) 1881 MUE_PRINTF(sc, "abort pipe %zu: %s\n", 1882 i, usbd_errstr(err)); 1883 } 1884 1885 /* Free RX resources. */ 1886 for (i = 0; i < sc->mue_rx_list_cnt; i++) { 1887 c = &sc->mue_cdata.mue_rx_chain[i]; 1888 if (c->mue_xfer != NULL) { 1889 usbd_destroy_xfer(c->mue_xfer); 1890 c->mue_xfer = NULL; 1891 } 1892 } 1893 1894 /* Free TX resources. */ 1895 for (i = 0; i < sc->mue_tx_list_cnt; i++) { 1896 c = &sc->mue_cdata.mue_tx_chain[i]; 1897 if (c->mue_xfer != NULL) { 1898 usbd_destroy_xfer(c->mue_xfer); 1899 c->mue_xfer = NULL; 1900 } 1901 } 1902 1903 /* Close pipes */ 1904 for (i = 0; i < __arraycount(sc->mue_ep); i++) 1905 if (sc->mue_ep[i] != NULL) { 1906 err = usbd_close_pipe(sc->mue_ep[i]); 1907 if (err) 1908 MUE_PRINTF(sc, "close pipe %zu: %s\n", 1909 i, usbd_errstr(err)); 1910 sc->mue_ep[i] = NULL; 1911 } 1912 1913 DPRINTF(sc, "done\n"); 1914 } 1915 1916 static void 1917 mue_tick(void *xsc) 1918 { 1919 struct mue_softc *sc = xsc; 1920 1921 if (sc == NULL) 1922 return; 1923 1924 if (sc->mue_dying) 1925 return; 1926 1927 /* Perform periodic stuff in process context. */ 1928 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER); 1929 } 1930 1931 static void 1932 mue_tick_task(void *xsc) 1933 { 1934 struct mue_softc *sc = xsc; 1935 struct ifnet *ifp; 1936 struct mii_data *mii; 1937 int s; 1938 1939 if (sc == NULL) 1940 return; 1941 1942 if (sc->mue_dying) 1943 return; 1944 1945 ifp = GET_IFP(sc); 1946 mii = GET_MII(sc); 1947 1948 s = splnet(); 1949 mii_tick(mii); 1950 if (sc->mue_link == 0) 1951 mue_miibus_statchg(ifp); 1952 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc); 1953 splx(s); 1954 } 1955 1956 static struct mbuf * 1957 mue_newbuf(void) 1958 { 1959 struct mbuf *m; 1960 1961 MGETHDR(m, M_DONTWAIT, MT_DATA); 1962 if (__predict_false(m == NULL)) 1963 return NULL; 1964 1965 MCLGET(m, M_DONTWAIT); 1966 if (__predict_false(!(m->m_flags & M_EXT))) { 1967 m_freem(m); 1968 return NULL; 1969 } 1970 1971 m_adj(m, ETHER_ALIGN); 1972 1973 return m; 1974 } 1975