1 /* $NetBSD: if_axe.c,v 1.129 2020/03/01 12:23:12 nisimura Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul@windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul@windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.129 2020/03/01 12:23:12 nisimura Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX178 | AX772 | AX772A | AX772B)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AXE_IS_172(un) (AXE_IS_178_FAMILY(un) == 0) 133 134 #define AX_RXCSUM \ 135 (IFCAP_CSUM_IPv4_Rx | \ 136 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 137 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 138 139 #define AX_TXCSUM \ 140 (IFCAP_CSUM_IPv4_Tx | \ 141 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 142 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 143 144 /* 145 * AXE_178_MAX_FRAME_BURST 146 * max frame burst size for Ax88178 and Ax88772 147 * 0 2048 bytes 148 * 1 4096 bytes 149 * 2 8192 bytes 150 * 3 16384 bytes 151 * use the largest your system can handle without USB stalling. 152 * 153 * NB: 88772 parts appear to generate lots of input errors with 154 * a 2K rx buffer and 8K is only slightly faster than 4K on an 155 * EHCI port on a T42 so change at your own risk. 156 */ 157 #define AXE_178_MAX_FRAME_BURST 1 158 159 160 #ifdef USB_DEBUG 161 #ifndef AXE_DEBUG 162 #define axedebug 0 163 #else 164 static int axedebug = 0; 165 166 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 167 { 168 int err; 169 const struct sysctlnode *rnode; 170 const struct sysctlnode *cnode; 171 172 err = sysctl_createv(clog, 0, NULL, &rnode, 173 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 174 SYSCTL_DESCR("axe global controls"), 175 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 176 177 if (err) 178 goto fail; 179 180 /* control debugging printfs */ 181 err = sysctl_createv(clog, 0, &rnode, &cnode, 182 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 183 "debug", SYSCTL_DESCR("Enable debugging output"), 184 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 185 if (err) 186 goto fail; 187 188 return; 189 fail: 190 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 191 } 192 193 #endif /* AXE_DEBUG */ 194 #endif /* USB_DEBUG */ 195 196 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 197 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 198 #define AXEHIST_FUNC() USBHIST_FUNC() 199 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 200 201 /* 202 * Various supported device vendors/products. 203 */ 204 static const struct axe_type axe_devs[] = { 205 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000 }, 0 }, 206 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2 }, 0 }, 207 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172 }, 0 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772 }, AX772 }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A }, AX772 }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B }, AX772B }, 212 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1 }, AX772B }, 213 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178 }, AX178 }, 214 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T }, 0 }, 215 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 216 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR }, 0}, 217 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2 }, AX772A }, 218 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0 }, 219 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100 }, 0 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 221 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 222 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 223 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E }, 0 }, 224 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 225 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1 }, 0 }, 226 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 227 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9 }, AX772B }, 228 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M }, 0 }, 229 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 230 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2 }, AX178 }, 231 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT }, AX178 }, 232 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX }, 0 }, 233 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A }, AX772 }, 234 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120 }, 0 }, 235 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 236 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 237 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029 }, 0 }, 238 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 239 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 240 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL }, 0 }, 241 }; 242 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 243 244 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 245 { 0x8000, 0x8001, 2048 }, 246 { 0x8100, 0x8147, 4096 }, 247 { 0x8200, 0x81EB, 6144 }, 248 { 0x8300, 0x83D7, 8192 }, 249 { 0x8400, 0x851E, 16384 }, 250 { 0x8500, 0x8666, 20480 }, 251 { 0x8600, 0x87AE, 24576 }, 252 { 0x8700, 0x8A3D, 32768 } 253 }; 254 255 static int axe_match(device_t, cfdata_t, void *); 256 static void axe_attach(device_t, device_t, void *); 257 258 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 259 axe_match, axe_attach, usbnet_detach, usbnet_activate); 260 261 static void axe_stop(struct ifnet *, int); 262 static int axe_ioctl(struct ifnet *, u_long, void *); 263 static int axe_init(struct ifnet *); 264 static int axe_mii_read_reg(struct usbnet *, int, int, uint16_t *); 265 static int axe_mii_write_reg(struct usbnet *, int, int, uint16_t); 266 static void axe_mii_statchg(struct ifnet *); 267 static void axe_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 268 static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *, 269 struct usbnet_chain *); 270 271 static void axe_ax88178_init(struct axe_softc *); 272 static void axe_ax88772_init(struct axe_softc *); 273 static void axe_ax88772a_init(struct axe_softc *); 274 static void axe_ax88772b_init(struct axe_softc *); 275 276 static const struct usbnet_ops axe_ops = { 277 .uno_stop = axe_stop, 278 .uno_ioctl = axe_ioctl, 279 .uno_read_reg = axe_mii_read_reg, 280 .uno_write_reg = axe_mii_write_reg, 281 .uno_statchg = axe_mii_statchg, 282 .uno_tx_prepare = axe_tx_prepare, 283 .uno_rx_loop = axe_rx_loop, 284 .uno_init = axe_init, 285 }; 286 287 static usbd_status 288 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 289 { 290 AXEHIST_FUNC(); AXEHIST_CALLED(); 291 struct usbnet * const un = &sc->axe_un; 292 usb_device_request_t req; 293 usbd_status err; 294 295 usbnet_isowned_mii(un); 296 297 if (usbnet_isdying(un)) 298 return -1; 299 300 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 301 302 if (AXE_CMD_DIR(cmd)) 303 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 304 else 305 req.bmRequestType = UT_READ_VENDOR_DEVICE; 306 req.bRequest = AXE_CMD_CMD(cmd); 307 USETW(req.wValue, val); 308 USETW(req.wIndex, index); 309 USETW(req.wLength, AXE_CMD_LEN(cmd)); 310 311 err = usbd_do_request(un->un_udev, &req, buf); 312 if (err) 313 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 314 315 return err; 316 } 317 318 static int 319 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 320 { 321 AXEHIST_FUNC(); AXEHIST_CALLED(); 322 struct axe_softc * const sc = usbnet_softc(un); 323 usbd_status err; 324 uint16_t data; 325 326 DPRINTFN(30, "phy %#jx reg %#jx\n", phy, reg, 0, 0); 327 328 if (un->un_phyno != phy) 329 return EINVAL; 330 331 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 332 333 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 334 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 335 336 if (err) { 337 aprint_error_dev(un->un_dev, "read PHY failed\n"); 338 return EIO; 339 } 340 341 *val = le16toh(data); 342 if (AXE_IS_772(un) && reg == MII_BMSR) { 343 /* 344 * BMSR of AX88772 indicates that it supports extended 345 * capability but the extended status register is 346 * reserved for embedded ethernet PHY. So clear the 347 * extended capability bit of BMSR. 348 */ 349 *val &= ~BMSR_EXTCAP; 350 } 351 352 DPRINTFN(30, "phy %#jx reg %#jx val %#jx", phy, reg, *val, 0); 353 354 return 0; 355 } 356 357 static int 358 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 359 { 360 struct axe_softc * const sc = usbnet_softc(un); 361 usbd_status err; 362 uint16_t aval; 363 364 if (un->un_phyno != phy) 365 return EINVAL; 366 367 aval = htole16(val); 368 369 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 370 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 371 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 372 373 if (err) 374 return EIO; 375 return 0; 376 } 377 378 static void 379 axe_mii_statchg(struct ifnet *ifp) 380 { 381 AXEHIST_FUNC(); AXEHIST_CALLED(); 382 383 struct usbnet * const un = ifp->if_softc; 384 struct axe_softc * const sc = usbnet_softc(un); 385 struct mii_data *mii = usbnet_mii(un); 386 int val, err; 387 388 if (usbnet_isdying(un)) 389 return; 390 391 val = 0; 392 if (AXE_IS_172(un)) { 393 if (mii->mii_media_active & IFM_FDX) 394 val |= AXE_MEDIA_FULL_DUPLEX; 395 } else { 396 if (mii->mii_media_active & IFM_FDX) { 397 val |= AXE_MEDIA_FULL_DUPLEX; 398 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 399 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 400 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 401 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 402 } 403 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 404 if (un->un_flags & AX178) 405 val |= AXE_178_MEDIA_ENCK; 406 switch (IFM_SUBTYPE(mii->mii_media_active)) { 407 case IFM_1000_T: 408 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 409 usbnet_set_link(un, true); 410 break; 411 case IFM_100_TX: 412 val |= AXE_178_MEDIA_100TX; 413 usbnet_set_link(un, true); 414 break; 415 case IFM_10_T: 416 usbnet_set_link(un, true); 417 break; 418 } 419 } 420 421 DPRINTF("val=%#jx", val, 0, 0, 0); 422 usbnet_lock_mii(un); 423 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 424 usbnet_unlock_mii(un); 425 if (err) 426 aprint_error_dev(un->un_dev, "media change failed\n"); 427 } 428 429 static void 430 axe_setiff_locked(struct usbnet *un) 431 { 432 AXEHIST_FUNC(); AXEHIST_CALLED(); 433 struct axe_softc * const sc = usbnet_softc(un); 434 struct ifnet * const ifp = usbnet_ifp(un); 435 struct ethercom *ec = usbnet_ec(un); 436 struct ether_multi *enm; 437 struct ether_multistep step; 438 uint32_t h = 0; 439 uint16_t rxmode; 440 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 441 442 usbnet_isowned_mii(un); 443 444 if (usbnet_isdying(un)) 445 return; 446 447 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 448 aprint_error_dev(un->un_dev, "can't read rxmode"); 449 return; 450 } 451 rxmode = le16toh(rxmode); 452 453 rxmode &= 454 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | AXE_RXCMD_MULTICAST); 455 456 if (ifp->if_flags & IFF_PROMISC) { 457 ifp->if_flags |= IFF_ALLMULTI; 458 goto allmulti; 459 } 460 ifp->if_flags &= ~IFF_ALLMULTI; 461 462 /* Now program new ones */ 463 ETHER_LOCK(ec); 464 ETHER_FIRST_MULTI(step, ec, enm); 465 while (enm != NULL) { 466 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 467 ETHER_ADDR_LEN) != 0) { 468 ETHER_UNLOCK(ec); 469 ifp->if_flags |= IFF_ALLMULTI; 470 goto allmulti; 471 } 472 473 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 474 hashtbl[h >> 3] |= 1U << (h & 7); 475 ETHER_NEXT_MULTI(step, enm); 476 } 477 ETHER_UNLOCK(ec); 478 479 rxmode |= AXE_RXCMD_MULTICAST; /* activate mcast hash filter */ 480 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 481 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 482 return; 483 484 allmulti: 485 if (ifp->if_flags & IFF_PROMISC) 486 rxmode |= AXE_RXCMD_PROMISC; /* run promisc. mode */ 487 rxmode |= AXE_RXCMD_ALLMULTI; /* accept all mcast frames */ 488 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 489 } 490 491 static void 492 axe_setiff(struct usbnet *un) 493 { 494 usbnet_lock_mii(un); 495 axe_setiff_locked(un); 496 usbnet_unlock_mii(un); 497 } 498 499 static void 500 axe_ax_init(struct usbnet *un) 501 { 502 struct axe_softc * const sc = usbnet_softc(un); 503 504 int cmd = AXE_178_CMD_READ_NODEID; 505 506 if (un->un_flags & AX178) { 507 axe_ax88178_init(sc); 508 } else if (un->un_flags & AX772) { 509 axe_ax88772_init(sc); 510 } else if (un->un_flags & AX772A) { 511 axe_ax88772a_init(sc); 512 } else if (un->un_flags & AX772B) { 513 axe_ax88772b_init(sc); 514 return; 515 } else { 516 cmd = AXE_172_CMD_READ_NODEID; 517 } 518 519 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 520 aprint_error_dev(un->un_dev, 521 "failed to read ethernet address\n"); 522 } 523 } 524 525 526 static void 527 axe_reset(struct usbnet *un) 528 { 529 530 usbnet_isowned_mii(un); 531 532 if (usbnet_isdying(un)) 533 return; 534 535 /* 536 * softnet_lock can be taken when NET_MPAFE is not defined when calling 537 * if_addr_init -> if_init. This doesn't mix well with the 538 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 539 * can fire during the wait and attempt to take softnet_lock and then 540 * block the softclk thread meaning the wait never ends. 541 */ 542 #ifndef NET_MPSAFE 543 /* XXX What to reset? */ 544 545 /* Wait a little while for the chip to get its brains in order. */ 546 DELAY(1000); 547 #else 548 axe_ax_init(un); 549 #endif 550 } 551 552 static int 553 axe_get_phyno(struct axe_softc *sc, int sel) 554 { 555 int phyno; 556 557 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 558 case PHY_TYPE_100_HOME: 559 /* FALLTHROUGH */ 560 case PHY_TYPE_GIG: 561 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 562 break; 563 case PHY_TYPE_SPECIAL: 564 /* FALLTHROUGH */ 565 case PHY_TYPE_RSVD: 566 /* FALLTHROUGH */ 567 case PHY_TYPE_NON_SUP: 568 /* FALLTHROUGH */ 569 default: 570 phyno = -1; 571 break; 572 } 573 574 return phyno; 575 } 576 577 #define AXE_GPIO_WRITE(x, y) do { \ 578 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 579 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 580 } while (0) 581 582 static void 583 axe_ax88178_init(struct axe_softc *sc) 584 { 585 AXEHIST_FUNC(); AXEHIST_CALLED(); 586 struct usbnet * const un = &sc->axe_un; 587 int gpio0, ledmode, phymode; 588 uint16_t eeprom, val; 589 590 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 591 /* XXX magic */ 592 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 593 eeprom = 0xffff; 594 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 595 596 eeprom = le16toh(eeprom); 597 598 DPRINTF("EEPROM is %#jx", eeprom, 0, 0, 0); 599 600 /* if EEPROM is invalid we have to use to GPIO0 */ 601 if (eeprom == 0xffff) { 602 phymode = AXE_PHY_MODE_MARVELL; 603 gpio0 = 1; 604 ledmode = 0; 605 } else { 606 phymode = eeprom & 0x7f; 607 gpio0 = (eeprom & 0x80) ? 0 : 1; 608 ledmode = eeprom >> 8; 609 } 610 611 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 612 613 /* Program GPIOs depending on PHY hardware. */ 614 switch (phymode) { 615 case AXE_PHY_MODE_MARVELL: 616 if (gpio0 == 1) { 617 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 618 hz / 32); 619 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 620 hz / 32); 621 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 622 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 623 hz / 32); 624 } else { 625 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 626 AXE_GPIO1_EN, hz / 3); 627 if (ledmode == 1) { 628 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 629 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 630 hz / 3); 631 } else { 632 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 633 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 634 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 635 AXE_GPIO2_EN, hz / 4); 636 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 637 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 638 } 639 } 640 break; 641 case AXE_PHY_MODE_CICADA: 642 case AXE_PHY_MODE_CICADA_V2: 643 case AXE_PHY_MODE_CICADA_V2_ASIX: 644 if (gpio0 == 1) 645 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 646 AXE_GPIO0_EN, hz / 32); 647 else 648 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 649 AXE_GPIO1_EN, hz / 32); 650 break; 651 case AXE_PHY_MODE_AGERE: 652 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 653 AXE_GPIO1_EN, hz / 32); 654 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 655 AXE_GPIO2_EN, hz / 32); 656 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 657 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 658 AXE_GPIO2_EN, hz / 32); 659 break; 660 case AXE_PHY_MODE_REALTEK_8211CL: 661 case AXE_PHY_MODE_REALTEK_8211BN: 662 case AXE_PHY_MODE_REALTEK_8251CL: 663 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 664 AXE_GPIO1 | AXE_GPIO1_EN; 665 AXE_GPIO_WRITE(val, hz / 32); 666 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 667 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 668 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 669 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 670 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 671 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 672 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 673 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 674 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 675 } 676 break; 677 default: 678 /* Unknown PHY model or no need to program GPIOs. */ 679 break; 680 } 681 682 /* soft reset */ 683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 684 usbd_delay_ms(un->un_udev, 150); 685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 686 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 687 usbd_delay_ms(un->un_udev, 150); 688 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 689 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 690 usbd_delay_ms(un->un_udev, 10); 691 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 692 } 693 694 static void 695 axe_ax88772_init(struct axe_softc *sc) 696 { 697 AXEHIST_FUNC(); AXEHIST_CALLED(); 698 struct usbnet * const un = &sc->axe_un; 699 700 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 701 usbd_delay_ms(un->un_udev, 40); 702 703 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 704 /* ask for the embedded PHY */ 705 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 706 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 707 usbd_delay_ms(un->un_udev, 10); 708 709 /* power down and reset state, pin reset state */ 710 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 711 usbd_delay_ms(un->un_udev, 60); 712 713 /* power down/reset state, pin operating state */ 714 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 715 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 716 usbd_delay_ms(un->un_udev, 150); 717 718 /* power up, reset */ 719 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 720 721 /* power up, operating */ 722 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 723 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 724 } else { 725 /* ask for external PHY */ 726 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 727 NULL); 728 usbd_delay_ms(un->un_udev, 10); 729 730 /* power down internal PHY */ 731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 732 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 733 } 734 735 usbd_delay_ms(un->un_udev, 150); 736 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 737 } 738 739 static void 740 axe_ax88772_phywake(struct axe_softc *sc) 741 { 742 AXEHIST_FUNC(); AXEHIST_CALLED(); 743 struct usbnet * const un = &sc->axe_un; 744 745 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 746 /* Manually select internal(embedded) PHY - MAC mode. */ 747 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 748 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 749 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 750 } else { 751 /* 752 * Manually select external PHY - MAC mode. 753 * Reverse MII/RMII is for AX88772A PHY mode. 754 */ 755 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 756 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 757 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 758 } 759 760 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 761 AXE_SW_RESET_IPRL, NULL); 762 763 /* T1 = min 500ns everywhere */ 764 usbd_delay_ms(un->un_udev, 150); 765 766 /* Take PHY out of power down. */ 767 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 768 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 769 } else { 770 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 771 } 772 773 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 774 usbd_delay_ms(un->un_udev, 600); 775 776 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 777 778 /* T3 = 500ns everywhere */ 779 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 780 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 781 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 782 } 783 784 static void 785 axe_ax88772a_init(struct axe_softc *sc) 786 { 787 AXEHIST_FUNC(); AXEHIST_CALLED(); 788 789 /* Reload EEPROM. */ 790 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 791 axe_ax88772_phywake(sc); 792 /* Stop MAC. */ 793 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 794 } 795 796 static void 797 axe_ax88772b_init(struct axe_softc *sc) 798 { 799 AXEHIST_FUNC(); AXEHIST_CALLED(); 800 struct usbnet * const un = &sc->axe_un; 801 uint16_t eeprom; 802 int i; 803 804 /* Reload EEPROM. */ 805 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 806 807 /* 808 * Save PHY power saving configuration(high byte) and 809 * clear EEPROM checksum value(low byte). 810 */ 811 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 812 &eeprom)) { 813 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 814 return; 815 } 816 817 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 818 819 /* 820 * Auto-loaded default station address from internal ROM is 821 * 00:00:00:00:00:00 such that an explicit access to EEPROM 822 * is required to get real station address. 823 */ 824 uint8_t *eaddr = un->un_eaddr; 825 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 826 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 827 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 828 aprint_error_dev(un->un_dev, 829 "failed to read eeprom\n"); 830 eeprom = 0; 831 } 832 eeprom = le16toh(eeprom); 833 *eaddr++ = (uint8_t)(eeprom & 0xFF); 834 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 835 } 836 /* Wakeup PHY. */ 837 axe_ax88772_phywake(sc); 838 /* Stop MAC. */ 839 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 840 } 841 842 #undef AXE_GPIO_WRITE 843 844 /* 845 * Probe for a AX88172 chip. 846 */ 847 static int 848 axe_match(device_t parent, cfdata_t match, void *aux) 849 { 850 struct usb_attach_arg *uaa = aux; 851 852 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 853 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 854 } 855 856 /* 857 * Attach the interface. Allocate softc structures, do ifmedia 858 * setup and ethernet/BPF attach. 859 */ 860 static void 861 axe_attach(device_t parent, device_t self, void *aux) 862 { 863 AXEHIST_FUNC(); AXEHIST_CALLED(); 864 USBNET_MII_DECL_DEFAULT(unm); 865 struct axe_softc *sc = device_private(self); 866 struct usbnet * const un = &sc->axe_un; 867 struct usb_attach_arg *uaa = aux; 868 struct usbd_device *dev = uaa->uaa_device; 869 usbd_status err; 870 usb_interface_descriptor_t *id; 871 usb_endpoint_descriptor_t *ed; 872 char *devinfop; 873 unsigned bufsz; 874 int i; 875 876 KASSERT((void *)sc == un); 877 878 aprint_naive("\n"); 879 aprint_normal("\n"); 880 devinfop = usbd_devinfo_alloc(dev, 0); 881 aprint_normal_dev(self, "%s\n", devinfop); 882 usbd_devinfo_free(devinfop); 883 884 un->un_dev = self; 885 un->un_udev = dev; 886 un->un_sc = sc; 887 un->un_ops = &axe_ops; 888 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 889 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 890 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 891 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 892 893 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 894 if (err) { 895 aprint_error_dev(self, "failed to set configuration" 896 ", err=%s\n", usbd_errstr(err)); 897 return; 898 } 899 900 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 901 902 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 903 if (err) { 904 aprint_error_dev(self, "getting interface handle failed\n"); 905 return; 906 } 907 908 id = usbd_get_interface_descriptor(un->un_iface); 909 910 /* decide on what our bufsize will be */ 911 if (AXE_IS_172(un)) 912 bufsz = AXE_172_BUFSZ; 913 else 914 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 915 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 916 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 917 918 un->un_ed[USBNET_ENDPT_RX] = 0; 919 un->un_ed[USBNET_ENDPT_TX] = 0; 920 un->un_ed[USBNET_ENDPT_INTR] = 0; 921 922 /* Find endpoints. */ 923 for (i = 0; i < id->bNumEndpoints; i++) { 924 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 925 if (ed == NULL) { 926 aprint_error_dev(self, "couldn't get ep %d\n", i); 927 return; 928 } 929 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 930 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 931 932 if (dir == UE_DIR_IN && xt == UE_BULK && 933 un->un_ed[USBNET_ENDPT_RX] == 0) { 934 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 935 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 936 un->un_ed[USBNET_ENDPT_TX] == 0) { 937 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 938 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 939 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 940 } 941 } 942 943 /* Set these up now for axe_cmd(). */ 944 usbnet_attach(un, "axedet"); 945 946 /* We need the PHYID for init dance in some cases */ 947 usbnet_lock_mii(un); 948 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 949 aprint_error_dev(self, "failed to read phyaddrs\n"); 950 951 return; 952 } 953 954 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 955 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 956 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 957 if (un->un_phyno == -1) 958 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 959 if (un->un_phyno == -1) { 960 DPRINTF(" no valid PHY address found, assuming PHY address 0", 961 0, 0, 0, 0); 962 un->un_phyno = 0; 963 } 964 965 /* Initialize controller and get station address. */ 966 967 axe_ax_init(un); 968 969 /* 970 * Fetch IPG values. 971 */ 972 if (un->un_flags & (AX772A | AX772B)) { 973 /* Set IPG values. */ 974 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 975 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 976 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 977 } else { 978 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 979 aprint_error_dev(self, "failed to read ipg\n"); 980 usbnet_unlock_mii(un); 981 return; 982 } 983 } 984 985 usbnet_unlock_mii(un); 986 987 if (!AXE_IS_172(un)) 988 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 989 if (un->un_flags & AX772B) { 990 struct ifnet *ifp = usbnet_ifp(un); 991 992 ifp->if_capabilities = 993 IFCAP_CSUM_IPv4_Rx | 994 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 995 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 996 /* 997 * Checksum offloading of AX88772B also works with VLAN 998 * tagged frames but there is no way to take advantage 999 * of the feature because vlan(4) assumes 1000 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1001 * support checksum offloading with VLAN. VLAN hardware 1002 * tagging support of AX88772B is very limited so it's 1003 * not possible to announce IFCAP_VLAN_HWTAGGING. 1004 */ 1005 } 1006 if (un->un_flags & (AX772A | AX772B | AX178)) 1007 unm.un_mii_flags = MIIF_DOPAUSE; 1008 1009 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1010 0, &unm); 1011 } 1012 1013 static void 1014 axe_rx_loop(struct usbnet * un, struct usbnet_chain *c, uint32_t total_len) 1015 { 1016 AXEHIST_FUNC(); AXEHIST_CALLED(); 1017 struct axe_softc * const sc = usbnet_softc(un); 1018 struct ifnet *ifp = usbnet_ifp(un); 1019 uint8_t *buf = c->unc_buf; 1020 1021 do { 1022 u_int pktlen = 0; 1023 u_int rxlen = 0; 1024 int flags = 0; 1025 1026 if ((un->un_flags & AXSTD_FRAME) != 0) { 1027 struct axe_sframe_hdr hdr; 1028 1029 if (total_len < sizeof(hdr)) { 1030 if_statinc(ifp, if_ierrors); 1031 break; 1032 } 1033 1034 memcpy(&hdr, buf, sizeof(hdr)); 1035 1036 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx", 1037 total_len, 1038 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1039 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1040 1041 total_len -= sizeof(hdr); 1042 buf += sizeof(hdr); 1043 1044 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1045 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1046 AXE_RH1M_RXLEN_MASK) { 1047 if_statinc(ifp, if_ierrors); 1048 break; 1049 } 1050 1051 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1052 if (total_len < rxlen) { 1053 pktlen = total_len; 1054 total_len = 0; 1055 } else { 1056 pktlen = rxlen; 1057 rxlen = roundup2(rxlen, 2); 1058 total_len -= rxlen; 1059 } 1060 1061 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1062 struct axe_csum_hdr csum_hdr; 1063 1064 if (total_len < sizeof(csum_hdr)) { 1065 if_statinc(ifp, if_ierrors); 1066 break; 1067 } 1068 1069 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1070 1071 csum_hdr.len = le16toh(csum_hdr.len); 1072 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1073 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1074 1075 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1076 " cstatus %#jx", total_len, 1077 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1078 1079 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1080 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1081 sc->sc_lenmask) { 1082 /* we lost sync */ 1083 if_statinc(ifp, if_ierrors); 1084 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1085 "err", 1086 AXE_CSUM_RXBYTES(csum_hdr.len), 1087 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1088 sc->sc_lenmask, 0); 1089 break; 1090 } 1091 /* 1092 * Get total transferred frame length including 1093 * checksum header. The length should be multiple 1094 * of 4. 1095 */ 1096 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1097 u_int len = sizeof(csum_hdr) + pktlen; 1098 len = (len + 3) & ~3; 1099 if (total_len < len) { 1100 DPRINTFN(20, "total_len %#jx < len %#jx", 1101 total_len, len, 0, 0); 1102 /* invalid length */ 1103 if_statinc(ifp, if_ierrors); 1104 break; 1105 } 1106 buf += sizeof(csum_hdr); 1107 1108 const uint16_t cstatus = csum_hdr.cstatus; 1109 1110 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1111 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1112 flags |= M_CSUM_TCP_UDP_BAD; 1113 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1114 flags |= M_CSUM_IPv4_BAD; 1115 1116 const uint16_t l4type = 1117 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1118 1119 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1120 flags |= M_CSUM_TCPv4; 1121 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1122 flags |= M_CSUM_UDPv4; 1123 } 1124 if (total_len < len) { 1125 pktlen = total_len; 1126 total_len = 0; 1127 } else { 1128 total_len -= len; 1129 rxlen = len - sizeof(csum_hdr); 1130 } 1131 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1132 " rxlen %#jx", total_len, len, pktlen, rxlen); 1133 } else { /* AX172 */ 1134 pktlen = rxlen = total_len; 1135 total_len = 0; 1136 } 1137 1138 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1139 buf += rxlen; 1140 1141 } while (total_len > 0); 1142 1143 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1144 } 1145 1146 static unsigned 1147 axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1148 { 1149 AXEHIST_FUNC(); AXEHIST_CALLED(); 1150 struct axe_sframe_hdr hdr, tlr; 1151 size_t hdr_len = 0, tlr_len = 0; 1152 int length, boundary; 1153 1154 usbnet_isowned_tx(un); 1155 1156 if (!AXE_IS_172(un)) { 1157 /* 1158 * Copy the mbuf data into a contiguous buffer, leaving two 1159 * bytes at the beginning to hold the frame length. 1160 */ 1161 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1162 1163 hdr.len = htole16(m->m_pkthdr.len); 1164 hdr.ilen = ~hdr.len; 1165 hdr_len = sizeof(hdr); 1166 1167 length = hdr_len + m->m_pkthdr.len; 1168 1169 if ((length % boundary) == 0) { 1170 tlr.len = 0x0000; 1171 tlr.ilen = 0xffff; 1172 tlr_len = sizeof(tlr); 1173 } 1174 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1175 length, m->m_pkthdr.len, sizeof(hdr), 0); 1176 } 1177 1178 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1179 return 0; 1180 length = hdr_len + m->m_pkthdr.len + tlr_len; 1181 1182 if (hdr_len) 1183 memcpy(c->unc_buf, &hdr, hdr_len); 1184 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1185 if (tlr_len) 1186 memcpy(c->unc_buf + length - tlr_len, &tlr, tlr_len); 1187 1188 return length; 1189 } 1190 1191 static void 1192 axe_csum_cfg(struct axe_softc *sc) 1193 { 1194 struct usbnet * const un = &sc->axe_un; 1195 struct ifnet * const ifp = usbnet_ifp(un); 1196 uint16_t csum1, csum2; 1197 1198 if ((un->un_flags & AX772B) != 0) { 1199 csum1 = 0; 1200 csum2 = 0; 1201 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1202 csum1 |= AXE_TXCSUM_IP; 1203 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1204 csum1 |= AXE_TXCSUM_TCP; 1205 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1206 csum1 |= AXE_TXCSUM_UDP; 1207 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1208 csum1 |= AXE_TXCSUM_TCPV6; 1209 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1210 csum1 |= AXE_TXCSUM_UDPV6; 1211 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1212 csum1 = 0; 1213 csum2 = 0; 1214 1215 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1216 csum1 |= AXE_RXCSUM_IP; 1217 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1218 csum1 |= AXE_RXCSUM_TCP; 1219 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1220 csum1 |= AXE_RXCSUM_UDP; 1221 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1222 csum1 |= AXE_RXCSUM_TCPV6; 1223 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1224 csum1 |= AXE_RXCSUM_UDPV6; 1225 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1226 } 1227 } 1228 1229 static int 1230 axe_init_locked(struct ifnet *ifp) 1231 { 1232 AXEHIST_FUNC(); AXEHIST_CALLED(); 1233 struct usbnet * const un = ifp->if_softc; 1234 struct axe_softc * const sc = usbnet_softc(un); 1235 int rxmode; 1236 1237 usbnet_isowned(un); 1238 1239 if (usbnet_isdying(un)) 1240 return EIO; 1241 1242 /* Cancel pending I/O */ 1243 usbnet_stop(un, ifp, 1); 1244 1245 usbnet_lock_mii_un_locked(un); 1246 1247 /* Reset the ethernet interface. */ 1248 axe_reset(un); 1249 1250 #if 0 1251 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1252 AX_GPIO_GPO2EN, 5, in_pm); 1253 #endif 1254 /* Set MAC address and transmitter IPG values. */ 1255 if (AXE_IS_172(un)) { 1256 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1257 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1258 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1259 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1260 } else { 1261 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1262 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1263 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1264 1265 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1266 if ((un->un_flags & AX772B) != 0 && 1267 (ifp->if_capenable & AX_RXCSUM) != 0) { 1268 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1269 un->un_flags |= AXCSUM_FRAME; 1270 } else { 1271 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1272 un->un_flags |= AXSTD_FRAME; 1273 } 1274 } 1275 1276 /* Configure TX/RX checksum offloading. */ 1277 axe_csum_cfg(sc); 1278 1279 if (un->un_flags & AX772B) { 1280 /* AX88772B uses different maximum frame burst configuration. */ 1281 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1282 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1283 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1284 } 1285 /* Enable receiver, set RX mode */ 1286 rxmode = (AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1287 if (AXE_IS_172(un)) 1288 rxmode |= AXE_172_RXCMD_UNICAST; 1289 else { 1290 if (un->un_flags & AX772B) { 1291 /* 1292 * Select RX header format type 1. Aligning IP 1293 * header on 4 byte boundary is not needed when 1294 * checksum offloading feature is not used 1295 * because we always copy the received frame in 1296 * RX handler. When RX checksum offloading is 1297 * active, aligning IP header is required to 1298 * reflect actual frame length including RX 1299 * header size. 1300 */ 1301 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1302 if (un->un_flags & AXCSUM_FRAME) 1303 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1304 } else { 1305 /* 1306 * Default Rx buffer size is too small to get 1307 * maximum performance. 1308 */ 1309 #if 0 1310 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1311 /* Largest possible USB buffer size for AX88178 */ 1312 } 1313 #endif 1314 rxmode |= AXE_178_RXCMD_MFB_16384; 1315 } 1316 } 1317 1318 DPRINTF("rxmode %#jx", rxmode, 0, 0, 0); 1319 1320 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1321 1322 /* Accept multicast frame or run promisc. mode */ 1323 axe_setiff_locked(un); 1324 1325 usbnet_unlock_mii_un_locked(un); 1326 1327 return usbnet_init_rx_tx(un); 1328 } 1329 1330 static int 1331 axe_init(struct ifnet *ifp) 1332 { 1333 struct usbnet * const un = ifp->if_softc; 1334 1335 usbnet_lock(un); 1336 int ret = axe_init_locked(ifp); 1337 usbnet_unlock(un); 1338 1339 return ret; 1340 } 1341 1342 static int 1343 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1344 { 1345 struct usbnet * const un = ifp->if_softc; 1346 1347 switch (cmd) { 1348 case SIOCADDMULTI: 1349 case SIOCDELMULTI: 1350 axe_setiff(un); 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static void 1360 axe_stop(struct ifnet *ifp, int disable) 1361 { 1362 struct usbnet * const un = ifp->if_softc; 1363 1364 usbnet_lock_mii_un_locked(un); 1365 axe_reset(un); 1366 usbnet_unlock_mii_un_locked(un); 1367 } 1368 1369 #ifdef _MODULE 1370 #include "ioconf.c" 1371 #endif 1372 1373 USBNET_MODULE(axe) 1374