1 /* $NetBSD: ehcireg.h,v 1.23 2005/11/20 18:36:20 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * The EHCI 0.96 spec can be found at 41 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 42 * and the USB 2.0 spec at 43 * http://www.usb.org/developers/data/usb_20.zip 44 */ 45 46 #ifndef _DEV_PCI_EHCIREG_H_ 47 #define _DEV_PCI_EHCIREG_H_ 48 49 /*** PCI config registers ***/ 50 51 #define PCI_CBMEM 0x10 /* configuration base MEM */ 52 53 #define PCI_INTERFACE_EHCI 0x20 54 55 #define PCI_USBREV 0x60 /* RO USB protocol revision */ 56 #define PCI_USBREV_MASK 0xff 57 #define PCI_USBREV_PRE_1_0 0x00 58 #define PCI_USBREV_1_0 0x10 59 #define PCI_USBREV_1_1 0x11 60 #define PCI_USBREV_2_0 0x20 61 62 #define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */ 63 64 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 65 66 /* Regs at EECP + offset */ 67 #define PCI_EHCI_USBLEGSUP 0x00 68 #define EHCI_LEG_HC_OS_OWNED 0x01000000 69 #define EHCI_LEG_HC_BIOS_OWNED 0x00010000 70 #define PCI_EHCI_USBLEGCTLSTS 0x04 71 72 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff) 73 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff) 74 #define EHCI_CAP_ID_LEGACY 1 75 76 /*** EHCI capability registers ***/ 77 78 #define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */ 79 /* reserved 0x01 */ 80 #define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 81 82 #define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 83 #define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 84 #define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 85 #define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 86 #define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 87 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 88 #define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 89 90 #define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 91 #define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 92 #define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 93 #define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 94 #define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 95 #define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 96 97 #define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */ 98 99 /* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 100 #define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 101 #define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 102 #define EHCI_CMD_ITC_1 0x00010000 103 #define EHCI_CMD_ITC_2 0x00020000 104 #define EHCI_CMD_ITC_4 0x00040000 105 #define EHCI_CMD_ITC_8 0x00080000 106 #define EHCI_CMD_ITC_16 0x00100000 107 #define EHCI_CMD_ITC_32 0x00200000 108 #define EHCI_CMD_ITC_64 0x00400000 109 #define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 110 #define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 111 #define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 112 #define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */ 113 #define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 114 #define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 115 #define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 116 #define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 117 #define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 118 #define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 119 120 #define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 121 #define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 122 #define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 123 #define EHCI_STS_REC 0x00002000 /* RO reclamation */ 124 #define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 125 #define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 126 #define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 127 #define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 128 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 129 #define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 130 #define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 131 #define EHCI_STS_INTRS(x) ((x) & 0x3f) 132 133 #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 134 135 #define EHCI_USBINTR 0x08 /* RW Interrupt register */ 136 #define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */ 137 #define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 138 #define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 139 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 140 #define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 141 #define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 142 143 #define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 144 145 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 146 147 #define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 148 #define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 149 150 #define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 151 #define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 152 153 #define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */ 154 #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 155 #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 156 #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 157 #define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 158 #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 159 #define EHCI_PS_PO 0x00002000 /* RW port owner */ 160 #define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 161 #define EHCI_PS_LS 0x00000c00 /* RO line status */ 162 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 163 #define EHCI_PS_PR 0x00000100 /* RW port reset */ 164 #define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 165 #define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 166 #define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 167 #define EHCI_PS_OCA 0x00000010 /* RO over current active */ 168 #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 169 #define EHCI_PS_PE 0x00000004 /* RW port enable */ 170 #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 171 #define EHCI_PS_CS 0x00000001 /* RO connect status */ 172 #define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) 173 174 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 175 176 #define EHCI_FLALIGN_ALIGN 0x1000 177 #define EHCI_MAX_PORTS 16 /* only 4 bits available in EHCI_HCS_N_PORTS */ 178 179 /* No data structure may cross a page boundary. */ 180 #define EHCI_PAGE_SIZE 0x1000 181 #define EHCI_PAGE(x) ((x) &~ 0xfff) 182 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff) 183 184 typedef u_int32_t ehci_link_t; 185 #define EHCI_LINK_TERMINATE 0x00000001 186 #define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 187 #define EHCI_LINK_ITD 0x0 188 #define EHCI_LINK_QH 0x2 189 #define EHCI_LINK_SITD 0x4 190 #define EHCI_LINK_FSTN 0x6 191 #define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 192 193 typedef u_int32_t ehci_physaddr_t; 194 195 /* Isochronous Transfer Descriptor */ 196 typedef struct { 197 ehci_link_t itd_next; 198 /* XXX many more */ 199 } ehci_itd_t; 200 #define EHCI_ITD_ALIGN 32 201 202 /* Split Transaction Isochronous Transfer Descriptor */ 203 typedef struct { 204 ehci_link_t sitd_next; 205 /* XXX many more */ 206 } ehci_sitd_t; 207 #define EHCI_SITD_ALIGN 32 208 209 /* Queue Element Transfer Descriptor */ 210 #define EHCI_QTD_NBUFFERS 5 211 typedef struct { 212 ehci_link_t qtd_next; 213 ehci_link_t qtd_altnext; 214 u_int32_t qtd_status; 215 #define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) 216 #define EHCI_QTD_SET_STATUS(x) ((x) << 0) 217 #define EHCI_QTD_ACTIVE 0x80 218 #define EHCI_QTD_HALTED 0x40 219 #define EHCI_QTD_BUFERR 0x20 220 #define EHCI_QTD_BABBLE 0x10 221 #define EHCI_QTD_XACTERR 0x08 222 #define EHCI_QTD_MISSEDMICRO 0x04 223 #define EHCI_QTD_SPLITXSTATE 0x02 224 #define EHCI_QTD_PINGSTATE 0x01 225 #define EHCI_QTD_STATERRS 0x3c 226 #define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3) 227 #define EHCI_QTD_SET_PID(x) ((x) << 8) 228 #define EHCI_QTD_PID_OUT 0x0 229 #define EHCI_QTD_PID_IN 0x1 230 #define EHCI_QTD_PID_SETUP 0x2 231 #define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3) 232 #define EHCI_QTD_SET_CERR(x) ((x) << 10) 233 #define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7) 234 #define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) 235 #define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1) 236 #define EHCI_QTD_IOC 0x00008000 237 #define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff) 238 #define EHCI_QTD_SET_BYTES(x) ((x) << 16) 239 #define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1) 240 #define EHCI_QTD_SET_TOGGLE(x) ((x) << 31) 241 #define EHCI_QTD_TOGGLE_MASK 0x80000000 242 ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 243 ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 244 } ehci_qtd_t; 245 #define EHCI_QTD_ALIGN 32 246 247 /* Queue Head */ 248 typedef struct { 249 ehci_link_t qh_link; 250 u_int32_t qh_endp; 251 #define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 252 #define EHCI_QH_SET_ADDR(x) (x) 253 #define EHCI_QH_ADDRMASK 0x0000007f 254 #define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */ 255 #define EHCI_QH_INACT 0x00000080 256 #define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */ 257 #define EHCI_QH_SET_ENDPT(x) ((x) << 8) 258 #define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */ 259 #define EHCI_QH_SET_EPS(x) ((x) << 12) 260 #define EHCI_QH_SPEED_FULL 0x0 261 #define EHCI_QH_SPEED_LOW 0x1 262 #define EHCI_QH_SPEED_HIGH 0x2 263 #define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */ 264 #define EHCI_QH_DTC 0x00004000 265 #define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */ 266 #define EHCI_QH_HRECL 0x00008000 267 #define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */ 268 #define EHCI_QH_SET_MPL(x) ((x) << 16) 269 #define EHCI_QH_MPLMASK 0x07ff0000 270 #define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */ 271 #define EHCI_QH_CTL 0x08000000 272 #define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */ 273 #define EHCI_QH_SET_NRL(x) ((x) << 28) 274 u_int32_t qh_endphub; 275 #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 276 #define EHCI_QH_SET_SMASK(x) ((x) << 0) 277 #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 278 #define EHCI_QH_SET_CMASK(x) ((x) << 8) 279 #define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 280 #define EHCI_QH_SET_HUBA(x) ((x) << 16) 281 #define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 282 #define EHCI_QH_SET_PORT(x) ((x) << 23) 283 #define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */ 284 #define EHCI_QH_SET_MULT(x) ((x) << 30) 285 ehci_link_t qh_curqtd; 286 ehci_qtd_t qh_qtd; 287 } ehci_qh_t; 288 #define EHCI_QH_ALIGN 32 289 290 /* Periodic Frame Span Traversal Node */ 291 typedef struct { 292 ehci_link_t fstn_link; 293 ehci_link_t fstn_back; 294 } ehci_fstn_t; 295 #define EHCI_FSTN_ALIGN 32 296 297 #endif /* _DEV_PCI_EHCIREG_H_ */ 298