1 /* $NetBSD: ehci.c,v 1.189 2012/03/17 11:45:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse@gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.189 2012/03/17 11:45:00 bouyer Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 #include "opt_usb.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/malloc.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 87 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 88 int ehcidebug = 0; 89 #else 90 #define DPRINTF(x) 91 #define DPRINTFN(n,x) 92 #endif 93 94 struct ehci_pipe { 95 struct usbd_pipe pipe; 96 int nexttoggle; 97 98 ehci_soft_qh_t *sqh; 99 union { 100 ehci_soft_qtd_t *qtd; 101 /* ehci_soft_itd_t *itd; */ 102 } tail; 103 union { 104 /* Control pipe */ 105 struct { 106 usb_dma_t reqdma; 107 u_int length; 108 } ctl; 109 /* Interrupt pipe */ 110 struct { 111 u_int length; 112 } intr; 113 /* Bulk pipe */ 114 struct { 115 u_int length; 116 } bulk; 117 /* Iso pipe */ 118 struct { 119 u_int next_frame; 120 u_int cur_xfers; 121 } isoc; 122 } u; 123 }; 124 125 Static usbd_status ehci_open(usbd_pipe_handle); 126 Static void ehci_poll(struct usbd_bus *); 127 Static void ehci_softintr(void *); 128 Static int ehci_intr1(ehci_softc_t *); 129 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 130 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_idone(struct ehci_xfer *); 134 Static void ehci_timeout(void *); 135 Static void ehci_timeout_task(void *); 136 Static void ehci_intrlist_timeout(void *); 137 138 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 139 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 140 141 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 142 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 143 144 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 145 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 146 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 147 Static void ehci_root_ctrl_close(usbd_pipe_handle); 148 Static void ehci_root_ctrl_done(usbd_xfer_handle); 149 150 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 151 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 152 Static void ehci_root_intr_abort(usbd_xfer_handle); 153 Static void ehci_root_intr_close(usbd_pipe_handle); 154 Static void ehci_root_intr_done(usbd_xfer_handle); 155 156 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 158 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_device_ctrl_close(usbd_pipe_handle); 160 Static void ehci_device_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 164 Static void ehci_device_bulk_abort(usbd_xfer_handle); 165 Static void ehci_device_bulk_close(usbd_pipe_handle); 166 Static void ehci_device_bulk_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 170 Static void ehci_device_intr_abort(usbd_xfer_handle); 171 Static void ehci_device_intr_close(usbd_pipe_handle); 172 Static void ehci_device_intr_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 176 Static void ehci_device_isoc_abort(usbd_xfer_handle); 177 Static void ehci_device_isoc_close(usbd_pipe_handle); 178 Static void ehci_device_isoc_done(usbd_xfer_handle); 179 180 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 181 Static void ehci_noop(usbd_pipe_handle pipe); 182 183 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 184 Static void ehci_disown(ehci_softc_t *, int, int); 185 186 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 187 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 188 189 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 190 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 191 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 192 ehci_softc_t *, int, int, usbd_xfer_handle, 193 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 194 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 195 ehci_soft_qtd_t *); 196 197 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 198 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 199 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 200 struct ehci_xfer *exfer); 201 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 202 usbd_status status); 203 204 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 205 206 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 207 int ival); 208 209 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 210 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 211 ehci_soft_qh_t *); 212 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 213 Static void ehci_sync_hc(ehci_softc_t *); 214 215 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 216 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 217 218 #ifdef EHCI_DEBUG 219 Static void ehci_dump_regs(ehci_softc_t *); 220 void ehci_dump(void); 221 Static ehci_softc_t *theehci; 222 Static void ehci_dump_link(ehci_link_t, int); 223 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 224 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 225 Static void ehci_dump_qtd(ehci_qtd_t *); 226 Static void ehci_dump_sqh(ehci_soft_qh_t *); 227 #if notyet 228 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 229 Static void ehci_dump_itd(struct ehci_soft_itd *); 230 #endif 231 #ifdef DIAGNOSTIC 232 Static void ehci_dump_exfer(struct ehci_xfer *); 233 #endif 234 #endif 235 236 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 237 238 #define EHCI_INTR_ENDPT 1 239 240 #define ehci_add_intr_list(sc, ex) \ 241 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 242 #define ehci_del_intr_list(sc, ex) \ 243 do { \ 244 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 245 (ex)->inext.tqe_prev = NULL; \ 246 } while (0) 247 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 248 249 Static const struct usbd_bus_methods ehci_bus_methods = { 250 .open_pipe = ehci_open, 251 .soft_intr = ehci_softintr, 252 .do_poll = ehci_poll, 253 .allocm = ehci_allocm, 254 .freem = ehci_freem, 255 .allocx = ehci_allocx, 256 .freex = ehci_freex, 257 }; 258 259 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 260 .transfer = ehci_root_ctrl_transfer, 261 .start = ehci_root_ctrl_start, 262 .abort = ehci_root_ctrl_abort, 263 .close = ehci_root_ctrl_close, 264 .cleartoggle = ehci_noop, 265 .done = ehci_root_ctrl_done, 266 }; 267 268 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 269 .transfer = ehci_root_intr_transfer, 270 .start = ehci_root_intr_start, 271 .abort = ehci_root_intr_abort, 272 .close = ehci_root_intr_close, 273 .cleartoggle = ehci_noop, 274 .done = ehci_root_intr_done, 275 }; 276 277 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 278 .transfer = ehci_device_ctrl_transfer, 279 .start = ehci_device_ctrl_start, 280 .abort = ehci_device_ctrl_abort, 281 .close = ehci_device_ctrl_close, 282 .cleartoggle = ehci_noop, 283 .done = ehci_device_ctrl_done, 284 }; 285 286 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 287 .transfer = ehci_device_intr_transfer, 288 .start = ehci_device_intr_start, 289 .abort = ehci_device_intr_abort, 290 .close = ehci_device_intr_close, 291 .cleartoggle = ehci_device_clear_toggle, 292 .done = ehci_device_intr_done, 293 }; 294 295 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 296 .transfer = ehci_device_bulk_transfer, 297 .start = ehci_device_bulk_start, 298 .abort = ehci_device_bulk_abort, 299 .close = ehci_device_bulk_close, 300 .cleartoggle = ehci_device_clear_toggle, 301 .done = ehci_device_bulk_done, 302 }; 303 304 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 305 .transfer = ehci_device_isoc_transfer, 306 .start = ehci_device_isoc_start, 307 .abort = ehci_device_isoc_abort, 308 .close = ehci_device_isoc_close, 309 .cleartoggle = ehci_noop, 310 .done = ehci_device_isoc_done, 311 }; 312 313 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 314 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 315 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 316 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 317 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 318 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 319 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 320 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 321 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 322 }; 323 324 usbd_status 325 ehci_init(ehci_softc_t *sc) 326 { 327 u_int32_t vers, sparams, cparams, hcr; 328 u_int i; 329 usbd_status err; 330 ehci_soft_qh_t *sqh; 331 u_int ncomp; 332 333 DPRINTF(("ehci_init: start\n")); 334 #ifdef EHCI_DEBUG 335 theehci = sc; 336 #endif 337 338 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 339 340 vers = EREAD2(sc, EHCI_HCIVERSION); 341 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 342 vers >> 8, vers & 0xff); 343 344 sparams = EREAD4(sc, EHCI_HCSPARAMS); 345 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 346 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 347 ncomp = EHCI_HCS_N_CC(sparams); 348 if (ncomp != sc->sc_ncomp) { 349 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 350 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 351 #if NOHCI == 0 || NUHCI == 0 352 aprint_error("%s: ohci or uhci probably not configured\n", 353 device_xname(sc->sc_dev)); 354 #endif 355 if (ncomp < sc->sc_ncomp) 356 sc->sc_ncomp = ncomp; 357 } 358 if (sc->sc_ncomp > 0) { 359 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 if (sc->sc_vendor_init) 399 sc->sc_vendor_init(sc); 400 401 /* 402 * If we are doing embedded transaction translation function, force 403 * the controller to host mode. 404 */ 405 if (sc->sc_flags & EHCIF_ETTF) { 406 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 407 usbmode &= ~EHCI_USBMODE_CM; 408 usbmode |= EHCI_USBMODE_CM_HOST; 409 EWRITE4(sc, EHCI_USBMODE, usbmode); 410 } 411 412 /* XXX need proper intr scheduling */ 413 sc->sc_rand = 96; 414 415 /* frame list size at default, read back what we got and use that */ 416 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 417 case 0: sc->sc_flsize = 1024; break; 418 case 1: sc->sc_flsize = 512; break; 419 case 2: sc->sc_flsize = 256; break; 420 case 3: return (USBD_IOERROR); 421 } 422 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 423 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 424 if (err) 425 return (err); 426 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 427 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 428 429 for (i = 0; i < sc->sc_flsize; i++) { 430 sc->sc_flist[i] = EHCI_NULL; 431 } 432 433 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 434 435 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 436 M_USB, M_NOWAIT | M_ZERO); 437 if (sc->sc_softitds == NULL) 438 return ENOMEM; 439 LIST_INIT(&sc->sc_freeitds); 440 TAILQ_INIT(&sc->sc_intrhead); 441 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 442 443 /* Set up the bus struct. */ 444 sc->sc_bus.methods = &ehci_bus_methods; 445 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 446 447 sc->sc_eintrs = EHCI_NORMAL_INTRS; 448 449 /* 450 * Allocate the interrupt dummy QHs. These are arranged to give poll 451 * intervals that are powers of 2 times 1ms. 452 */ 453 for (i = 0; i < EHCI_INTRQHS; i++) { 454 sqh = ehci_alloc_sqh(sc); 455 if (sqh == NULL) { 456 err = USBD_NOMEM; 457 goto bad1; 458 } 459 sc->sc_islots[i].sqh = sqh; 460 } 461 for (i = 0; i < EHCI_INTRQHS; i++) { 462 sqh = sc->sc_islots[i].sqh; 463 if (i == 0) { 464 /* The last (1ms) QH terminates. */ 465 sqh->qh.qh_link = EHCI_NULL; 466 sqh->next = NULL; 467 } else { 468 /* Otherwise the next QH has half the poll interval */ 469 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 470 sqh->qh.qh_link = htole32(sqh->next->physaddr | 471 EHCI_LINK_QH); 472 } 473 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 474 sqh->qh.qh_curqtd = EHCI_NULL; 475 sqh->next = NULL; 476 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 477 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 478 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 479 sqh->sqtd = NULL; 480 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 } 483 /* Point the frame list at the last level (128ms). */ 484 for (i = 0; i < sc->sc_flsize; i++) { 485 int j; 486 487 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 488 revbits[i & (EHCI_MAX_POLLRATE-1)]; 489 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 490 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 491 i)].sqh->physaddr); 492 } 493 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 494 BUS_DMASYNC_PREWRITE); 495 496 /* Allocate dummy QH that starts the async list. */ 497 sqh = ehci_alloc_sqh(sc); 498 if (sqh == NULL) { 499 err = USBD_NOMEM; 500 goto bad1; 501 } 502 /* Fill the QH */ 503 sqh->qh.qh_endp = 504 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 505 sqh->qh.qh_link = 506 htole32(sqh->physaddr | EHCI_LINK_QH); 507 sqh->qh.qh_curqtd = EHCI_NULL; 508 sqh->next = NULL; 509 /* Fill the overlay qTD */ 510 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 511 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 512 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 513 sqh->sqtd = NULL; 514 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 516 #ifdef EHCI_DEBUG 517 if (ehcidebug) { 518 ehci_dump_sqh(sqh); 519 } 520 #endif 521 522 /* Point to async list */ 523 sc->sc_async_head = sqh; 524 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 525 526 callout_init(&(sc->sc_tmo_intrlist), 0); 527 528 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 529 530 /* Turn on controller */ 531 EOWRITE4(sc, EHCI_USBCMD, 532 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 533 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 534 EHCI_CMD_ASE | 535 EHCI_CMD_PSE | 536 EHCI_CMD_RS); 537 538 /* Take over port ownership */ 539 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 540 541 for (i = 0; i < 100; i++) { 542 usb_delay_ms(&sc->sc_bus, 1); 543 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 544 if (!hcr) 545 break; 546 } 547 if (hcr) { 548 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 549 return (USBD_IOERROR); 550 } 551 552 /* Enable interrupts */ 553 DPRINTFN(1,("ehci_init: enabling\n")); 554 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 555 556 return (USBD_NORMAL_COMPLETION); 557 558 #if 0 559 bad2: 560 ehci_free_sqh(sc, sc->sc_async_head); 561 #endif 562 bad1: 563 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 564 return (err); 565 } 566 567 int 568 ehci_intr(void *v) 569 { 570 ehci_softc_t *sc = v; 571 572 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 573 return (0); 574 575 /* If we get an interrupt while polling, then just ignore it. */ 576 if (sc->sc_bus.use_polling) { 577 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 578 579 if (intrs) 580 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 581 #ifdef DIAGNOSTIC 582 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 583 #endif 584 return (0); 585 } 586 587 return (ehci_intr1(sc)); 588 } 589 590 Static int 591 ehci_intr1(ehci_softc_t *sc) 592 { 593 u_int32_t intrs, eintrs; 594 595 DPRINTFN(20,("ehci_intr1: enter\n")); 596 597 /* In case the interrupt occurs before initialization has completed. */ 598 if (sc == NULL) { 599 #ifdef DIAGNOSTIC 600 printf("ehci_intr1: sc == NULL\n"); 601 #endif 602 return (0); 603 } 604 605 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 606 if (!intrs) 607 return (0); 608 609 eintrs = intrs & sc->sc_eintrs; 610 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 611 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 612 (u_int)eintrs)); 613 if (!eintrs) 614 return (0); 615 616 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 617 sc->sc_bus.no_intrs++; 618 if (eintrs & EHCI_STS_IAA) { 619 DPRINTF(("ehci_intr1: door bell\n")); 620 wakeup(&sc->sc_async_head); 621 eintrs &= ~EHCI_STS_IAA; 622 } 623 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 624 DPRINTFN(5,("ehci_intr1: %s %s\n", 625 eintrs & EHCI_STS_INT ? "INT" : "", 626 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 627 usb_schedsoftintr(&sc->sc_bus); 628 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 629 } 630 if (eintrs & EHCI_STS_HSE) { 631 printf("%s: unrecoverable error, controller halted\n", 632 device_xname(sc->sc_dev)); 633 /* XXX what else */ 634 } 635 if (eintrs & EHCI_STS_PCD) { 636 ehci_pcd(sc, sc->sc_intrxfer); 637 eintrs &= ~EHCI_STS_PCD; 638 } 639 640 if (eintrs != 0) { 641 /* Block unprocessed interrupts. */ 642 sc->sc_eintrs &= ~eintrs; 643 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 644 printf("%s: blocking intrs 0x%x\n", 645 device_xname(sc->sc_dev), eintrs); 646 } 647 648 return (1); 649 } 650 651 652 Static void 653 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 654 { 655 usbd_pipe_handle pipe; 656 u_char *p; 657 int i, m; 658 659 if (xfer == NULL) { 660 /* Just ignore the change. */ 661 return; 662 } 663 664 pipe = xfer->pipe; 665 666 p = KERNADDR(&xfer->dmabuf, 0); 667 m = min(sc->sc_noport, xfer->length * 8 - 1); 668 memset(p, 0, xfer->length); 669 for (i = 1; i <= m; i++) { 670 /* Pick out CHANGE bits from the status reg. */ 671 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 672 p[i/8] |= 1 << (i%8); 673 } 674 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 675 xfer->actlen = xfer->length; 676 xfer->status = USBD_NORMAL_COMPLETION; 677 678 usb_transfer_complete(xfer); 679 } 680 681 Static void 682 ehci_softintr(void *v) 683 { 684 struct usbd_bus *bus = v; 685 ehci_softc_t *sc = bus->hci_private; 686 struct ehci_xfer *ex, *nextex; 687 688 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 689 690 /* 691 * The only explanation I can think of for why EHCI is as brain dead 692 * as UHCI interrupt-wise is that Intel was involved in both. 693 * An interrupt just tells us that something is done, we have no 694 * clue what, so we need to scan through all active transfers. :-( 695 */ 696 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 697 nextex = TAILQ_NEXT(ex, inext); 698 ehci_check_intr(sc, ex); 699 } 700 701 /* Schedule a callout to catch any dropped transactions. */ 702 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 703 !TAILQ_EMPTY(&sc->sc_intrhead)) 704 callout_reset(&(sc->sc_tmo_intrlist), 705 (hz), (ehci_intrlist_timeout), (sc)); 706 707 if (sc->sc_softwake) { 708 sc->sc_softwake = 0; 709 wakeup(&sc->sc_softwake); 710 } 711 } 712 713 /* Check for an interrupt. */ 714 Static void 715 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 716 { 717 int attr; 718 719 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 720 721 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 722 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 723 ehci_check_itd_intr(sc, ex); 724 else 725 ehci_check_qh_intr(sc, ex); 726 727 return; 728 } 729 730 Static void 731 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 732 { 733 ehci_soft_qtd_t *sqtd, *lsqtd; 734 __uint32_t status; 735 736 if (ex->sqtdstart == NULL) { 737 printf("ehci_check_qh_intr: not valid sqtd\n"); 738 return; 739 } 740 741 lsqtd = ex->sqtdend; 742 #ifdef DIAGNOSTIC 743 if (lsqtd == NULL) { 744 printf("ehci_check_qh_intr: lsqtd==0\n"); 745 return; 746 } 747 #endif 748 /* 749 * If the last TD is still active we need to check whether there 750 * is a an error somewhere in the middle, or whether there was a 751 * short packet (SPD and not ACTIVE). 752 */ 753 usb_syncmem(&lsqtd->dma, 754 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 755 sizeof(lsqtd->qtd.qtd_status), 756 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 757 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 758 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 759 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 760 usb_syncmem(&sqtd->dma, 761 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 762 sizeof(sqtd->qtd.qtd_status), 763 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 764 status = le32toh(sqtd->qtd.qtd_status); 765 usb_syncmem(&sqtd->dma, 766 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 767 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 768 /* If there's an active QTD the xfer isn't done. */ 769 if (status & EHCI_QTD_ACTIVE) 770 break; 771 /* Any kind of error makes the xfer done. */ 772 if (status & EHCI_QTD_HALTED) 773 goto done; 774 /* We want short packets, and it is short: it's done */ 775 if (EHCI_QTD_GET_BYTES(status) != 0) 776 goto done; 777 } 778 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 779 ex, ex->sqtdstart)); 780 usb_syncmem(&lsqtd->dma, 781 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 782 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 783 return; 784 } 785 done: 786 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 787 callout_stop(&ex->xfer.timeout_handle); 788 ehci_idone(ex); 789 } 790 791 Static void 792 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 793 ehci_soft_itd_t *itd; 794 int i; 795 796 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 797 return; 798 799 if (ex->itdstart == NULL) { 800 printf("ehci_check_itd_intr: not valid itd\n"); 801 return; 802 } 803 804 itd = ex->itdend; 805 #ifdef DIAGNOSTIC 806 if (itd == NULL) { 807 printf("ehci_check_itd_intr: itdend == 0\n"); 808 return; 809 } 810 #endif 811 812 /* 813 * check no active transfers in last itd, meaning we're finished 814 */ 815 816 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 817 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 818 BUS_DMASYNC_POSTREAD); 819 820 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 821 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 822 break; 823 } 824 825 if (i == EHCI_ITD_NUFRAMES) { 826 goto done; /* All 8 descriptors inactive, it's done */ 827 } 828 829 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 830 ex->itdstart)); 831 return; 832 done: 833 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 834 callout_stop(&ex->xfer.timeout_handle); 835 ehci_idone(ex); 836 } 837 838 Static void 839 ehci_idone(struct ehci_xfer *ex) 840 { 841 usbd_xfer_handle xfer = &ex->xfer; 842 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 843 ehci_soft_qtd_t *sqtd, *lsqtd; 844 u_int32_t status = 0, nstatus = 0; 845 int actlen; 846 847 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 848 #ifdef DIAGNOSTIC 849 { 850 int s = splhigh(); 851 if (ex->isdone) { 852 splx(s); 853 #ifdef EHCI_DEBUG 854 printf("ehci_idone: ex is done!\n "); 855 ehci_dump_exfer(ex); 856 #else 857 printf("ehci_idone: ex=%p is done!\n", ex); 858 #endif 859 return; 860 } 861 ex->isdone = 1; 862 splx(s); 863 } 864 #endif 865 if (xfer->status == USBD_CANCELLED || 866 xfer->status == USBD_TIMEOUT) { 867 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 868 return; 869 } 870 871 #ifdef EHCI_DEBUG 872 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 873 if (ehcidebug > 10) 874 ehci_dump_sqtds(ex->sqtdstart); 875 #endif 876 877 /* The transfer is done, compute actual length and status. */ 878 879 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 880 == UE_ISOCHRONOUS) { 881 /* Isoc transfer */ 882 struct ehci_soft_itd *itd; 883 int i, nframes, len, uframes; 884 885 nframes = 0; 886 actlen = 0; 887 888 i = xfer->pipe->endpoint->edesc->bInterval; 889 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 890 891 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 892 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 893 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 894 BUS_DMASYNC_POSTREAD); 895 896 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 897 /* XXX - driver didn't fill in the frame full 898 * of uframes. This leads to scheduling 899 * inefficiencies, but working around 900 * this doubles complexity of tracking 901 * an xfer. 902 */ 903 if (nframes >= xfer->nframes) 904 break; 905 906 status = le32toh(itd->itd.itd_ctl[i]); 907 len = EHCI_ITD_GET_LEN(status); 908 if (EHCI_ITD_GET_STATUS(status) != 0) 909 len = 0; /*No valid data on error*/ 910 911 xfer->frlengths[nframes++] = len; 912 actlen += len; 913 } 914 915 if (nframes >= xfer->nframes) 916 break; 917 } 918 919 xfer->actlen = actlen; 920 xfer->status = USBD_NORMAL_COMPLETION; 921 goto end; 922 } 923 924 /* Continue processing xfers using queue heads */ 925 926 lsqtd = ex->sqtdend; 927 actlen = 0; 928 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 929 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 931 nstatus = le32toh(sqtd->qtd.qtd_status); 932 if (nstatus & EHCI_QTD_ACTIVE) 933 break; 934 935 status = nstatus; 936 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 937 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 938 } 939 940 941 /* 942 * If there are left over TDs we need to update the toggle. 943 * The default pipe doesn't need it since control transfers 944 * start the toggle at 0 every time. 945 * For a short transfer we need to update the toggle for the missing 946 * packets within the qTD. 947 */ 948 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 949 xfer->pipe->device->default_pipe != xfer->pipe) { 950 DPRINTFN(2, ("ehci_idone: need toggle update " 951 "status=%08x nstatus=%08x\n", status, nstatus)); 952 #if 0 953 ehci_dump_sqh(epipe->sqh); 954 ehci_dump_sqtds(ex->sqtdstart); 955 #endif 956 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 957 } 958 959 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 960 xfer->length, actlen, status)); 961 xfer->actlen = actlen; 962 if (status & EHCI_QTD_HALTED) { 963 #ifdef EHCI_DEBUG 964 char sbuf[128]; 965 966 snprintb(sbuf, sizeof(sbuf), 967 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 968 (u_int32_t)status); 969 970 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 971 "status 0x%s\n", 972 xfer->pipe->device->address, 973 xfer->pipe->endpoint->edesc->bEndpointAddress, 974 sbuf)); 975 if (ehcidebug > 2) { 976 ehci_dump_sqh(epipe->sqh); 977 ehci_dump_sqtds(ex->sqtdstart); 978 } 979 #endif 980 /* low&full speed has an extra error flag */ 981 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 982 EHCI_QH_SPEED_HIGH) 983 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 984 else 985 status &= EHCI_QTD_STATERRS; 986 if (status == 0) /* no other errors means a stall */ { 987 xfer->status = USBD_STALLED; 988 } else { 989 xfer->status = USBD_IOERROR; /* more info XXX */ 990 } 991 /* XXX need to reset TT on missed microframe */ 992 if (status & EHCI_QTD_MISSEDMICRO) { 993 ehci_softc_t *sc = 994 xfer->pipe->device->bus->hci_private; 995 996 printf("%s: missed microframe, TT reset not " 997 "implemented, hub might be inoperational\n", 998 device_xname(sc->sc_dev)); 999 } 1000 } else { 1001 xfer->status = USBD_NORMAL_COMPLETION; 1002 } 1003 1004 end: 1005 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1006 * during this call, before methods->done is called: dma sync required 1007 * beforehand? */ 1008 usb_transfer_complete(xfer); 1009 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1010 } 1011 1012 /* 1013 * Wait here until controller claims to have an interrupt. 1014 * Then call ehci_intr and return. Use timeout to avoid waiting 1015 * too long. 1016 */ 1017 Static void 1018 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1019 { 1020 int timo; 1021 u_int32_t intrs; 1022 1023 xfer->status = USBD_IN_PROGRESS; 1024 for (timo = xfer->timeout; timo >= 0; timo--) { 1025 usb_delay_ms(&sc->sc_bus, 1); 1026 if (sc->sc_dying) 1027 break; 1028 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1029 sc->sc_eintrs; 1030 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1031 #ifdef EHCI_DEBUG 1032 if (ehcidebug > 15) 1033 ehci_dump_regs(sc); 1034 #endif 1035 if (intrs) { 1036 ehci_intr1(sc); 1037 if (xfer->status != USBD_IN_PROGRESS) 1038 return; 1039 } 1040 } 1041 1042 /* Timeout */ 1043 DPRINTF(("ehci_waitintr: timeout\n")); 1044 xfer->status = USBD_TIMEOUT; 1045 usb_transfer_complete(xfer); 1046 /* XXX should free TD */ 1047 } 1048 1049 Static void 1050 ehci_poll(struct usbd_bus *bus) 1051 { 1052 ehci_softc_t *sc = bus->hci_private; 1053 #ifdef EHCI_DEBUG 1054 static int last; 1055 int new; 1056 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1057 if (new != last) { 1058 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1059 last = new; 1060 } 1061 #endif 1062 1063 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1064 ehci_intr1(sc); 1065 } 1066 1067 void 1068 ehci_childdet(device_t self, device_t child) 1069 { 1070 struct ehci_softc *sc = device_private(self); 1071 1072 KASSERT(sc->sc_child == child); 1073 sc->sc_child = NULL; 1074 } 1075 1076 int 1077 ehci_detach(struct ehci_softc *sc, int flags) 1078 { 1079 int rv = 0; 1080 1081 if (sc->sc_child != NULL) 1082 rv = config_detach(sc->sc_child, flags); 1083 1084 if (rv != 0) 1085 return (rv); 1086 1087 callout_stop(&sc->sc_tmo_intrlist); 1088 1089 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1090 1091 /* XXX free other data structures XXX */ 1092 mutex_destroy(&sc->sc_doorbell_lock); 1093 mutex_destroy(&sc->sc_intrhead_lock); 1094 1095 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1096 1097 return (rv); 1098 } 1099 1100 1101 int 1102 ehci_activate(device_t self, enum devact act) 1103 { 1104 struct ehci_softc *sc = device_private(self); 1105 1106 switch (act) { 1107 case DVACT_DEACTIVATE: 1108 sc->sc_dying = 1; 1109 return 0; 1110 default: 1111 return EOPNOTSUPP; 1112 } 1113 } 1114 1115 /* 1116 * Handle suspend/resume. 1117 * 1118 * We need to switch to polling mode here, because this routine is 1119 * called from an interrupt context. This is all right since we 1120 * are almost suspended anyway. 1121 * 1122 * Note that this power handler isn't to be registered directly; the 1123 * bus glue needs to call out to it. 1124 */ 1125 bool 1126 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1127 { 1128 ehci_softc_t *sc = device_private(dv); 1129 int i, s; 1130 uint32_t cmd, hcr; 1131 1132 s = splhardusb(); 1133 1134 sc->sc_bus.use_polling++; 1135 1136 for (i = 1; i <= sc->sc_noport; i++) { 1137 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1138 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1139 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1140 } 1141 1142 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1143 1144 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1145 EOWRITE4(sc, EHCI_USBCMD, cmd); 1146 1147 for (i = 0; i < 100; i++) { 1148 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1149 if (hcr == 0) 1150 break; 1151 1152 usb_delay_ms(&sc->sc_bus, 1); 1153 } 1154 if (hcr != 0) 1155 printf("%s: reset timeout\n", device_xname(dv)); 1156 1157 cmd &= ~EHCI_CMD_RS; 1158 EOWRITE4(sc, EHCI_USBCMD, cmd); 1159 1160 for (i = 0; i < 100; i++) { 1161 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1162 if (hcr == EHCI_STS_HCH) 1163 break; 1164 1165 usb_delay_ms(&sc->sc_bus, 1); 1166 } 1167 if (hcr != EHCI_STS_HCH) 1168 printf("%s: config timeout\n", device_xname(dv)); 1169 1170 sc->sc_bus.use_polling--; 1171 splx(s); 1172 1173 return true; 1174 } 1175 1176 bool 1177 ehci_resume(device_t dv, const pmf_qual_t *qual) 1178 { 1179 ehci_softc_t *sc = device_private(dv); 1180 int i; 1181 uint32_t cmd, hcr; 1182 1183 /* restore things in case the bios sucks */ 1184 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1185 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1186 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1187 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1188 1189 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1190 1191 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1192 1193 hcr = 0; 1194 for (i = 1; i <= sc->sc_noport; i++) { 1195 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1196 if ((cmd & EHCI_PS_PO) == 0 && 1197 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1198 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1199 hcr = 1; 1200 } 1201 } 1202 1203 if (hcr) { 1204 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1205 1206 for (i = 1; i <= sc->sc_noport; i++) { 1207 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1208 if ((cmd & EHCI_PS_PO) == 0 && 1209 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1210 EOWRITE4(sc, EHCI_PORTSC(i), 1211 cmd & ~EHCI_PS_FPR); 1212 } 1213 } 1214 1215 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1216 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1217 1218 for (i = 0; i < 100; i++) { 1219 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1220 if (hcr != EHCI_STS_HCH) 1221 break; 1222 1223 usb_delay_ms(&sc->sc_bus, 1); 1224 } 1225 if (hcr == EHCI_STS_HCH) 1226 printf("%s: config timeout\n", device_xname(dv)); 1227 1228 return true; 1229 } 1230 1231 /* 1232 * Shut down the controller when the system is going down. 1233 */ 1234 bool 1235 ehci_shutdown(device_t self, int flags) 1236 { 1237 ehci_softc_t *sc = device_private(self); 1238 1239 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1240 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1241 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1242 return true; 1243 } 1244 1245 Static usbd_status 1246 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1247 { 1248 struct ehci_softc *sc = bus->hci_private; 1249 usbd_status err; 1250 1251 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1252 if (err == USBD_NOMEM) 1253 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1254 #ifdef EHCI_DEBUG 1255 if (err) 1256 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1257 #endif 1258 return (err); 1259 } 1260 1261 Static void 1262 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1263 { 1264 struct ehci_softc *sc = bus->hci_private; 1265 1266 if (dma->block->flags & USB_DMA_RESERVE) { 1267 usb_reserve_freem(&sc->sc_dma_reserve, 1268 dma); 1269 return; 1270 } 1271 usb_freemem(&sc->sc_bus, dma); 1272 } 1273 1274 Static usbd_xfer_handle 1275 ehci_allocx(struct usbd_bus *bus) 1276 { 1277 struct ehci_softc *sc = bus->hci_private; 1278 usbd_xfer_handle xfer; 1279 1280 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1281 if (xfer != NULL) { 1282 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1283 #ifdef DIAGNOSTIC 1284 if (xfer->busy_free != XFER_FREE) { 1285 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1286 xfer->busy_free); 1287 } 1288 #endif 1289 } else { 1290 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1291 } 1292 if (xfer != NULL) { 1293 memset(xfer, 0, sizeof(struct ehci_xfer)); 1294 #ifdef DIAGNOSTIC 1295 EXFER(xfer)->isdone = 1; 1296 xfer->busy_free = XFER_BUSY; 1297 #endif 1298 } 1299 return (xfer); 1300 } 1301 1302 Static void 1303 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1304 { 1305 struct ehci_softc *sc = bus->hci_private; 1306 1307 #ifdef DIAGNOSTIC 1308 if (xfer->busy_free != XFER_BUSY) { 1309 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1310 xfer->busy_free); 1311 } 1312 xfer->busy_free = XFER_FREE; 1313 if (!EXFER(xfer)->isdone) { 1314 printf("ehci_freex: !isdone\n"); 1315 } 1316 #endif 1317 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1318 } 1319 1320 Static void 1321 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1322 { 1323 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1324 1325 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1326 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1327 #ifdef EHCI_DEBUG 1328 if (ehcidebug) 1329 usbd_dump_pipe(pipe); 1330 #endif 1331 epipe->nexttoggle = 0; 1332 } 1333 1334 Static void 1335 ehci_noop(usbd_pipe_handle pipe) 1336 { 1337 } 1338 1339 #ifdef EHCI_DEBUG 1340 Static void 1341 ehci_dump_regs(ehci_softc_t *sc) 1342 { 1343 int i; 1344 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1345 EOREAD4(sc, EHCI_USBCMD), 1346 EOREAD4(sc, EHCI_USBSTS), 1347 EOREAD4(sc, EHCI_USBINTR)); 1348 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1349 EOREAD4(sc, EHCI_FRINDEX), 1350 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1351 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1352 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1353 for (i = 1; i <= sc->sc_noport; i++) 1354 printf("port %d status=0x%08x\n", i, 1355 EOREAD4(sc, EHCI_PORTSC(i))); 1356 } 1357 1358 /* 1359 * Unused function - this is meant to be called from a kernel 1360 * debugger. 1361 */ 1362 void 1363 ehci_dump(void) 1364 { 1365 ehci_dump_regs(theehci); 1366 } 1367 1368 Static void 1369 ehci_dump_link(ehci_link_t link, int type) 1370 { 1371 link = le32toh(link); 1372 printf("0x%08x", link); 1373 if (link & EHCI_LINK_TERMINATE) 1374 printf("<T>"); 1375 else { 1376 printf("<"); 1377 if (type) { 1378 switch (EHCI_LINK_TYPE(link)) { 1379 case EHCI_LINK_ITD: printf("ITD"); break; 1380 case EHCI_LINK_QH: printf("QH"); break; 1381 case EHCI_LINK_SITD: printf("SITD"); break; 1382 case EHCI_LINK_FSTN: printf("FSTN"); break; 1383 } 1384 } 1385 printf(">"); 1386 } 1387 } 1388 1389 Static void 1390 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1391 { 1392 int i; 1393 u_int32_t stop; 1394 1395 stop = 0; 1396 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1397 ehci_dump_sqtd(sqtd); 1398 usb_syncmem(&sqtd->dma, 1399 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1400 sizeof(sqtd->qtd), 1401 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1402 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1403 usb_syncmem(&sqtd->dma, 1404 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1405 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1406 } 1407 if (sqtd) 1408 printf("dump aborted, too many TDs\n"); 1409 } 1410 1411 Static void 1412 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1413 { 1414 usb_syncmem(&sqtd->dma, sqtd->offs, 1415 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1416 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1417 ehci_dump_qtd(&sqtd->qtd); 1418 usb_syncmem(&sqtd->dma, sqtd->offs, 1419 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1420 } 1421 1422 Static void 1423 ehci_dump_qtd(ehci_qtd_t *qtd) 1424 { 1425 u_int32_t s; 1426 char sbuf[128]; 1427 1428 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1429 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1430 printf("\n"); 1431 s = le32toh(qtd->qtd_status); 1432 snprintb(sbuf, sizeof(sbuf), 1433 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1434 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1435 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1436 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1437 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1438 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1439 EHCI_QTD_GET_PID(s), sbuf); 1440 for (s = 0; s < 5; s++) 1441 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1442 } 1443 1444 Static void 1445 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1446 { 1447 ehci_qh_t *qh = &sqh->qh; 1448 u_int32_t endp, endphub; 1449 1450 usb_syncmem(&sqh->dma, sqh->offs, 1451 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1452 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1453 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1454 endp = le32toh(qh->qh_endp); 1455 printf(" endp=0x%08x\n", endp); 1456 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1457 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1458 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1459 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1460 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1461 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1462 EHCI_QH_GET_NRL(endp)); 1463 endphub = le32toh(qh->qh_endphub); 1464 printf(" endphub=0x%08x\n", endphub); 1465 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1466 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1467 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1468 EHCI_QH_GET_MULT(endphub)); 1469 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1470 printf("Overlay qTD:\n"); 1471 ehci_dump_qtd(&qh->qh_qtd); 1472 usb_syncmem(&sqh->dma, sqh->offs, 1473 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1474 } 1475 1476 #if notyet 1477 Static void 1478 ehci_dump_itd(struct ehci_soft_itd *itd) 1479 { 1480 ehci_isoc_trans_t t; 1481 ehci_isoc_bufr_ptr_t b, b2, b3; 1482 int i; 1483 1484 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1485 1486 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1487 t = le32toh(itd->itd.itd_ctl[i]); 1488 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1489 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1490 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1491 EHCI_ITD_GET_OFFS(t)); 1492 } 1493 printf("ITDbufr: "); 1494 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1495 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1496 1497 b = le32toh(itd->itd.itd_bufr[0]); 1498 b2 = le32toh(itd->itd.itd_bufr[1]); 1499 b3 = le32toh(itd->itd.itd_bufr[2]); 1500 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1501 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1502 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1503 } 1504 1505 Static void 1506 ehci_dump_sitd(struct ehci_soft_itd *itd) 1507 { 1508 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1509 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1510 itd->xfer_next, itd->physaddr, itd->slot); 1511 } 1512 #endif 1513 1514 #ifdef DIAGNOSTIC 1515 Static void 1516 ehci_dump_exfer(struct ehci_xfer *ex) 1517 { 1518 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1519 } 1520 #endif 1521 #endif 1522 1523 Static usbd_status 1524 ehci_open(usbd_pipe_handle pipe) 1525 { 1526 usbd_device_handle dev = pipe->device; 1527 ehci_softc_t *sc = dev->bus->hci_private; 1528 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1529 u_int8_t addr = dev->address; 1530 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1531 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1532 ehci_soft_qh_t *sqh; 1533 usbd_status err; 1534 int s; 1535 int ival, speed, naks; 1536 int hshubaddr, hshubport; 1537 1538 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1539 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1540 1541 if (dev->myhsport) { 1542 /* 1543 * When directly attached FS/LS device while doing embedded 1544 * transaction translations and we are the hub, set the hub 1545 * adddress to 0 (us). 1546 */ 1547 if (!(sc->sc_flags & EHCIF_ETTF) 1548 || (dev->myhsport->parent->address != sc->sc_addr)) { 1549 hshubaddr = dev->myhsport->parent->address; 1550 } else { 1551 hshubaddr = 0; 1552 } 1553 hshubport = dev->myhsport->portno; 1554 } else { 1555 hshubaddr = 0; 1556 hshubport = 0; 1557 } 1558 1559 if (sc->sc_dying) 1560 return (USBD_IOERROR); 1561 1562 /* toggle state needed for bulk endpoints */ 1563 epipe->nexttoggle = pipe->endpoint->datatoggle; 1564 1565 if (addr == sc->sc_addr) { 1566 switch (ed->bEndpointAddress) { 1567 case USB_CONTROL_ENDPOINT: 1568 pipe->methods = &ehci_root_ctrl_methods; 1569 break; 1570 case UE_DIR_IN | EHCI_INTR_ENDPT: 1571 pipe->methods = &ehci_root_intr_methods; 1572 break; 1573 default: 1574 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1575 ed->bEndpointAddress)); 1576 return (USBD_INVAL); 1577 } 1578 return (USBD_NORMAL_COMPLETION); 1579 } 1580 1581 /* XXX All this stuff is only valid for async. */ 1582 switch (dev->speed) { 1583 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1584 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1585 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1586 default: panic("ehci_open: bad device speed %d", dev->speed); 1587 } 1588 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1589 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1590 "isoc endpoint.\n"); 1591 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1592 "attached to a USB2 hub, and transaction translations are " 1593 "not yet supported.\n"); 1594 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1595 "root hub instead.\n"); 1596 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1597 hshubaddr, hshubport)); 1598 return USBD_INVAL; 1599 } 1600 1601 /* 1602 * For interrupt transfer, nak throttling must be disabled, but for 1603 * the other transfer type, nak throttling should be enabled from the 1604 * veiwpoint that avoids the memory thrashing. 1605 */ 1606 naks = (xfertype == UE_INTERRUPT) ? 0 1607 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1608 1609 /* Allocate sqh for everything, save isoc xfers */ 1610 if (xfertype != UE_ISOCHRONOUS) { 1611 sqh = ehci_alloc_sqh(sc); 1612 if (sqh == NULL) 1613 return (USBD_NOMEM); 1614 /* qh_link filled when the QH is added */ 1615 sqh->qh.qh_endp = htole32( 1616 EHCI_QH_SET_ADDR(addr) | 1617 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1618 EHCI_QH_SET_EPS(speed) | 1619 EHCI_QH_DTC | 1620 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1621 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1622 EHCI_QH_CTL : 0) | 1623 EHCI_QH_SET_NRL(naks) 1624 ); 1625 sqh->qh.qh_endphub = htole32( 1626 EHCI_QH_SET_MULT(1) | 1627 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1628 ); 1629 if (speed != EHCI_QH_SPEED_HIGH) 1630 sqh->qh.qh_endphub |= htole32( 1631 EHCI_QH_SET_PORT(hshubport) | 1632 EHCI_QH_SET_HUBA(hshubaddr) | 1633 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1634 ); 1635 sqh->qh.qh_curqtd = EHCI_NULL; 1636 /* Fill the overlay qTD */ 1637 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1638 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1639 sqh->qh.qh_qtd.qtd_status = htole32(0); 1640 1641 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1643 epipe->sqh = sqh; 1644 } else { 1645 sqh = NULL; 1646 } /*xfertype == UE_ISOC*/ 1647 1648 switch (xfertype) { 1649 case UE_CONTROL: 1650 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1651 0, &epipe->u.ctl.reqdma); 1652 #ifdef EHCI_DEBUG 1653 if (err) 1654 printf("ehci_open: usb_allocmem()=%d\n", err); 1655 #endif 1656 if (err) 1657 goto bad; 1658 pipe->methods = &ehci_device_ctrl_methods; 1659 s = splusb(); 1660 ehci_add_qh(sqh, sc->sc_async_head); 1661 splx(s); 1662 break; 1663 case UE_BULK: 1664 pipe->methods = &ehci_device_bulk_methods; 1665 s = splusb(); 1666 ehci_add_qh(sqh, sc->sc_async_head); 1667 splx(s); 1668 break; 1669 case UE_INTERRUPT: 1670 pipe->methods = &ehci_device_intr_methods; 1671 ival = pipe->interval; 1672 if (ival == USBD_DEFAULT_INTERVAL) { 1673 if (speed == EHCI_QH_SPEED_HIGH) { 1674 if (ed->bInterval > 16) { 1675 /* 1676 * illegal with high-speed, but there 1677 * were documentation bugs in the spec, 1678 * so be generous 1679 */ 1680 ival = 256; 1681 } else 1682 ival = (1 << (ed->bInterval - 1)) / 8; 1683 } else 1684 ival = ed->bInterval; 1685 } 1686 err = ehci_device_setintr(sc, sqh, ival); 1687 if (err) 1688 goto bad; 1689 break; 1690 case UE_ISOCHRONOUS: 1691 pipe->methods = &ehci_device_isoc_methods; 1692 if (ed->bInterval == 0 || ed->bInterval > 16) { 1693 printf("ehci: opening pipe with invalid bInterval\n"); 1694 err = USBD_INVAL; 1695 goto bad; 1696 } 1697 if (UGETW(ed->wMaxPacketSize) == 0) { 1698 printf("ehci: zero length endpoint open request\n"); 1699 err = USBD_INVAL; 1700 goto bad; 1701 } 1702 epipe->u.isoc.next_frame = 0; 1703 epipe->u.isoc.cur_xfers = 0; 1704 break; 1705 default: 1706 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1707 err = USBD_INVAL; 1708 goto bad; 1709 } 1710 return (USBD_NORMAL_COMPLETION); 1711 1712 bad: 1713 if (sqh != NULL) 1714 ehci_free_sqh(sc, sqh); 1715 return (err); 1716 } 1717 1718 /* 1719 * Add an ED to the schedule. Called at splusb(). 1720 */ 1721 Static void 1722 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1723 { 1724 1725 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1726 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1727 sqh->next = head->next; 1728 sqh->qh.qh_link = head->qh.qh_link; 1729 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1730 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1731 head->next = sqh; 1732 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1733 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1734 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1735 1736 #ifdef EHCI_DEBUG 1737 if (ehcidebug > 5) { 1738 printf("ehci_add_qh:\n"); 1739 ehci_dump_sqh(sqh); 1740 } 1741 #endif 1742 } 1743 1744 /* 1745 * Remove an ED from the schedule. Called at splusb(). 1746 */ 1747 Static void 1748 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1749 { 1750 ehci_soft_qh_t *p; 1751 1752 /* XXX */ 1753 for (p = head; p != NULL && p->next != sqh; p = p->next) 1754 ; 1755 if (p == NULL) 1756 panic("ehci_rem_qh: ED not found"); 1757 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1758 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1759 p->next = sqh->next; 1760 p->qh.qh_link = sqh->qh.qh_link; 1761 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1762 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1763 1764 ehci_sync_hc(sc); 1765 } 1766 1767 Static void 1768 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1769 { 1770 int i; 1771 u_int32_t status; 1772 1773 /* Save toggle bit and ping status. */ 1774 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1775 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1776 status = sqh->qh.qh_qtd.qtd_status & 1777 htole32(EHCI_QTD_TOGGLE_MASK | 1778 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1779 /* Set HALTED to make hw leave it alone. */ 1780 sqh->qh.qh_qtd.qtd_status = 1781 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1782 usb_syncmem(&sqh->dma, 1783 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1784 sizeof(sqh->qh.qh_qtd.qtd_status), 1785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1786 sqh->qh.qh_curqtd = 0; 1787 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1788 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1789 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1790 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1791 sqh->sqtd = sqtd; 1792 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1794 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1795 sqh->qh.qh_qtd.qtd_status = status; 1796 usb_syncmem(&sqh->dma, 1797 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1798 sizeof(sqh->qh.qh_qtd.qtd_status), 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 } 1801 1802 /* 1803 * Ensure that the HC has released all references to the QH. We do this 1804 * by asking for a Async Advance Doorbell interrupt and then we wait for 1805 * the interrupt. 1806 * To make this easier we first obtain exclusive use of the doorbell. 1807 */ 1808 Static void 1809 ehci_sync_hc(ehci_softc_t *sc) 1810 { 1811 int s, error; 1812 1813 if (sc->sc_dying) { 1814 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1815 return; 1816 } 1817 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1818 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1819 s = splhardusb(); 1820 /* ask for doorbell */ 1821 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1822 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1823 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1824 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1825 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1826 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1827 splx(s); 1828 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1829 #ifdef DIAGNOSTIC 1830 if (error) 1831 printf("ehci_sync_hc: tsleep() = %d\n", error); 1832 #endif 1833 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1834 } 1835 1836 /*Call at splusb*/ 1837 Static void 1838 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1839 { 1840 struct ehci_soft_itd *itd, *prev; 1841 1842 prev = NULL; 1843 1844 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1845 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1846 1847 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1848 prev = itd->u.frame_list.prev; 1849 /* Unlink itd from hardware chain, or frame array */ 1850 if (prev == NULL) { /* We're at the table head */ 1851 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1852 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1853 usb_syncmem(&sc->sc_fldma, 1854 sizeof(ehci_link_t) * itd->slot, 1855 sizeof(ehci_link_t), 1856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1857 1858 if (itd->u.frame_list.next != NULL) 1859 itd->u.frame_list.next->u.frame_list.prev = NULL; 1860 } else { 1861 /* XXX this part is untested... */ 1862 prev->itd.itd_next = itd->itd.itd_next; 1863 usb_syncmem(&itd->dma, 1864 itd->offs + offsetof(ehci_itd_t, itd_next), 1865 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1866 1867 prev->u.frame_list.next = itd->u.frame_list.next; 1868 if (itd->u.frame_list.next != NULL) 1869 itd->u.frame_list.next->u.frame_list.prev = prev; 1870 } 1871 } 1872 1873 prev = NULL; 1874 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1875 if (prev != NULL) 1876 ehci_free_itd(sc, prev); 1877 prev = itd; 1878 } 1879 if (prev) 1880 ehci_free_itd(sc, prev); 1881 exfer->itdstart = NULL; 1882 exfer->itdend = NULL; 1883 } 1884 1885 /***********/ 1886 1887 /* 1888 * Data structures and routines to emulate the root hub. 1889 */ 1890 Static usb_device_descriptor_t ehci_devd = { 1891 USB_DEVICE_DESCRIPTOR_SIZE, 1892 UDESC_DEVICE, /* type */ 1893 {0x00, 0x02}, /* USB version */ 1894 UDCLASS_HUB, /* class */ 1895 UDSUBCLASS_HUB, /* subclass */ 1896 UDPROTO_HSHUBSTT, /* protocol */ 1897 64, /* max packet */ 1898 {0},{0},{0x00,0x01}, /* device id */ 1899 1,2,0, /* string indicies */ 1900 1 /* # of configurations */ 1901 }; 1902 1903 Static const usb_device_qualifier_t ehci_odevd = { 1904 USB_DEVICE_DESCRIPTOR_SIZE, 1905 UDESC_DEVICE_QUALIFIER, /* type */ 1906 {0x00, 0x02}, /* USB version */ 1907 UDCLASS_HUB, /* class */ 1908 UDSUBCLASS_HUB, /* subclass */ 1909 UDPROTO_FSHUB, /* protocol */ 1910 64, /* max packet */ 1911 1, /* # of configurations */ 1912 0 1913 }; 1914 1915 Static const usb_config_descriptor_t ehci_confd = { 1916 USB_CONFIG_DESCRIPTOR_SIZE, 1917 UDESC_CONFIG, 1918 {USB_CONFIG_DESCRIPTOR_SIZE + 1919 USB_INTERFACE_DESCRIPTOR_SIZE + 1920 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1921 1, 1922 1, 1923 0, 1924 UC_ATTR_MBO | UC_SELF_POWERED, 1925 0 /* max power */ 1926 }; 1927 1928 Static const usb_interface_descriptor_t ehci_ifcd = { 1929 USB_INTERFACE_DESCRIPTOR_SIZE, 1930 UDESC_INTERFACE, 1931 0, 1932 0, 1933 1, 1934 UICLASS_HUB, 1935 UISUBCLASS_HUB, 1936 UIPROTO_HSHUBSTT, 1937 0 1938 }; 1939 1940 Static const usb_endpoint_descriptor_t ehci_endpd = { 1941 USB_ENDPOINT_DESCRIPTOR_SIZE, 1942 UDESC_ENDPOINT, 1943 UE_DIR_IN | EHCI_INTR_ENDPT, 1944 UE_INTERRUPT, 1945 {8, 0}, /* max packet */ 1946 12 1947 }; 1948 1949 Static const usb_hub_descriptor_t ehci_hubd = { 1950 USB_HUB_DESCRIPTOR_SIZE, 1951 UDESC_HUB, 1952 0, 1953 {0,0}, 1954 0, 1955 0, 1956 {""}, 1957 {""}, 1958 }; 1959 1960 /* 1961 * Simulate a hardware hub by handling all the necessary requests. 1962 */ 1963 Static usbd_status 1964 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1965 { 1966 usbd_status err; 1967 1968 /* Insert last in queue. */ 1969 err = usb_insert_transfer(xfer); 1970 if (err) 1971 return (err); 1972 1973 /* Pipe isn't running, start first */ 1974 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1975 } 1976 1977 Static usbd_status 1978 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1979 { 1980 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1981 usb_device_request_t *req; 1982 void *buf = NULL; 1983 int port, i; 1984 int s, len, value, index, l, totlen = 0; 1985 usb_port_status_t ps; 1986 usb_hub_descriptor_t hubd; 1987 usbd_status err; 1988 u_int32_t v; 1989 1990 if (sc->sc_dying) 1991 return (USBD_IOERROR); 1992 1993 #ifdef DIAGNOSTIC 1994 if (!(xfer->rqflags & URQ_REQUEST)) 1995 /* XXX panic */ 1996 return (USBD_INVAL); 1997 #endif 1998 req = &xfer->request; 1999 2000 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2001 req->bmRequestType, req->bRequest)); 2002 2003 len = UGETW(req->wLength); 2004 value = UGETW(req->wValue); 2005 index = UGETW(req->wIndex); 2006 2007 if (len != 0) 2008 buf = KERNADDR(&xfer->dmabuf, 0); 2009 2010 #define C(x,y) ((x) | ((y) << 8)) 2011 switch(C(req->bRequest, req->bmRequestType)) { 2012 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2013 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2014 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2015 /* 2016 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2017 * for the integrated root hub. 2018 */ 2019 break; 2020 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2021 if (len > 0) { 2022 *(u_int8_t *)buf = sc->sc_conf; 2023 totlen = 1; 2024 } 2025 break; 2026 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2027 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2028 if (len == 0) 2029 break; 2030 switch(value >> 8) { 2031 case UDESC_DEVICE: 2032 if ((value & 0xff) != 0) { 2033 err = USBD_IOERROR; 2034 goto ret; 2035 } 2036 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2037 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2038 memcpy(buf, &ehci_devd, l); 2039 break; 2040 /* 2041 * We can't really operate at another speed, but the spec says 2042 * we need this descriptor. 2043 */ 2044 case UDESC_DEVICE_QUALIFIER: 2045 if ((value & 0xff) != 0) { 2046 err = USBD_IOERROR; 2047 goto ret; 2048 } 2049 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2050 memcpy(buf, &ehci_odevd, l); 2051 break; 2052 /* 2053 * We can't really operate at another speed, but the spec says 2054 * we need this descriptor. 2055 */ 2056 case UDESC_OTHER_SPEED_CONFIGURATION: 2057 case UDESC_CONFIG: 2058 if ((value & 0xff) != 0) { 2059 err = USBD_IOERROR; 2060 goto ret; 2061 } 2062 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2063 memcpy(buf, &ehci_confd, l); 2064 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2065 value >> 8; 2066 buf = (char *)buf + l; 2067 len -= l; 2068 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2069 totlen += l; 2070 memcpy(buf, &ehci_ifcd, l); 2071 buf = (char *)buf + l; 2072 len -= l; 2073 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2074 totlen += l; 2075 memcpy(buf, &ehci_endpd, l); 2076 break; 2077 case UDESC_STRING: 2078 #define sd ((usb_string_descriptor_t *)buf) 2079 switch (value & 0xff) { 2080 case 0: /* Language table */ 2081 totlen = usb_makelangtbl(sd, len); 2082 break; 2083 case 1: /* Vendor */ 2084 totlen = usb_makestrdesc(sd, len, 2085 sc->sc_vendor); 2086 break; 2087 case 2: /* Product */ 2088 totlen = usb_makestrdesc(sd, len, 2089 "EHCI root hub"); 2090 break; 2091 } 2092 #undef sd 2093 break; 2094 default: 2095 err = USBD_IOERROR; 2096 goto ret; 2097 } 2098 break; 2099 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2100 if (len > 0) { 2101 *(u_int8_t *)buf = 0; 2102 totlen = 1; 2103 } 2104 break; 2105 case C(UR_GET_STATUS, UT_READ_DEVICE): 2106 if (len > 1) { 2107 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2108 totlen = 2; 2109 } 2110 break; 2111 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2112 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2113 if (len > 1) { 2114 USETW(((usb_status_t *)buf)->wStatus, 0); 2115 totlen = 2; 2116 } 2117 break; 2118 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2119 if (value >= USB_MAX_DEVICES) { 2120 err = USBD_IOERROR; 2121 goto ret; 2122 } 2123 sc->sc_addr = value; 2124 break; 2125 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2126 if (value != 0 && value != 1) { 2127 err = USBD_IOERROR; 2128 goto ret; 2129 } 2130 sc->sc_conf = value; 2131 break; 2132 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2133 break; 2134 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2135 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2136 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2137 err = USBD_IOERROR; 2138 goto ret; 2139 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2140 break; 2141 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2142 break; 2143 /* Hub requests */ 2144 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2145 break; 2146 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2147 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2148 "port=%d feature=%d\n", 2149 index, value)); 2150 if (index < 1 || index > sc->sc_noport) { 2151 err = USBD_IOERROR; 2152 goto ret; 2153 } 2154 port = EHCI_PORTSC(index); 2155 v = EOREAD4(sc, port); 2156 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2157 v &= ~EHCI_PS_CLEAR; 2158 switch(value) { 2159 case UHF_PORT_ENABLE: 2160 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2161 break; 2162 case UHF_PORT_SUSPEND: 2163 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2164 break; 2165 v &= ~EHCI_PS_SUSP; 2166 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2167 /* see USB2 spec ch. 7.1.7.7 */ 2168 usb_delay_ms(&sc->sc_bus, 20); 2169 EOWRITE4(sc, port, v); 2170 usb_delay_ms(&sc->sc_bus, 2); 2171 #ifdef DEBUG 2172 v = EOREAD4(sc, port); 2173 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2174 printf("ehci: resume failed: %x\n", v); 2175 #endif 2176 break; 2177 case UHF_PORT_POWER: 2178 if (sc->sc_hasppc) 2179 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2180 break; 2181 case UHF_PORT_TEST: 2182 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2183 "%d\n", index)); 2184 break; 2185 case UHF_PORT_INDICATOR: 2186 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2187 "%d\n", index)); 2188 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2189 break; 2190 case UHF_C_PORT_CONNECTION: 2191 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2192 break; 2193 case UHF_C_PORT_ENABLE: 2194 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2195 break; 2196 case UHF_C_PORT_SUSPEND: 2197 /* how? */ 2198 break; 2199 case UHF_C_PORT_OVER_CURRENT: 2200 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2201 break; 2202 case UHF_C_PORT_RESET: 2203 sc->sc_isreset[index] = 0; 2204 break; 2205 default: 2206 err = USBD_IOERROR; 2207 goto ret; 2208 } 2209 #if 0 2210 switch(value) { 2211 case UHF_C_PORT_CONNECTION: 2212 case UHF_C_PORT_ENABLE: 2213 case UHF_C_PORT_SUSPEND: 2214 case UHF_C_PORT_OVER_CURRENT: 2215 case UHF_C_PORT_RESET: 2216 default: 2217 break; 2218 } 2219 #endif 2220 break; 2221 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2222 if (len == 0) 2223 break; 2224 if ((value & 0xff) != 0) { 2225 err = USBD_IOERROR; 2226 goto ret; 2227 } 2228 hubd = ehci_hubd; 2229 hubd.bNbrPorts = sc->sc_noport; 2230 v = EOREAD4(sc, EHCI_HCSPARAMS); 2231 USETW(hubd.wHubCharacteristics, 2232 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2233 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2234 ? UHD_PORT_IND : 0); 2235 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2236 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2237 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2238 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2239 l = min(len, hubd.bDescLength); 2240 totlen = l; 2241 memcpy(buf, &hubd, l); 2242 break; 2243 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2244 if (len != 4) { 2245 err = USBD_IOERROR; 2246 goto ret; 2247 } 2248 memset(buf, 0, len); /* ? XXX */ 2249 totlen = len; 2250 break; 2251 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2252 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2253 index)); 2254 if (index < 1 || index > sc->sc_noport) { 2255 err = USBD_IOERROR; 2256 goto ret; 2257 } 2258 if (len != 4) { 2259 err = USBD_IOERROR; 2260 goto ret; 2261 } 2262 v = EOREAD4(sc, EHCI_PORTSC(index)); 2263 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2264 2265 i = UPS_HIGH_SPEED; 2266 #if 0 2267 if (sc->sc_flags & EHCIF_ETTF) { 2268 /* 2269 * If we are doing embedded transaction translation, 2270 * then directly attached LS/FS devices are reset by 2271 * the EHCI controller itself. PSPD is encoded 2272 * the same way as in USBSTATUS. 2273 */ 2274 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2275 } 2276 #endif 2277 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2278 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2279 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2280 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2281 if (v & EHCI_PS_PR) i |= UPS_RESET; 2282 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2283 if (sc->sc_vendor_port_status) 2284 i = sc->sc_vendor_port_status(sc, v, i); 2285 USETW(ps.wPortStatus, i); 2286 i = 0; 2287 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2288 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2289 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2290 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2291 USETW(ps.wPortChange, i); 2292 l = min(len, sizeof ps); 2293 memcpy(buf, &ps, l); 2294 totlen = l; 2295 break; 2296 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2297 err = USBD_IOERROR; 2298 goto ret; 2299 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2300 break; 2301 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2302 if (index < 1 || index > sc->sc_noport) { 2303 err = USBD_IOERROR; 2304 goto ret; 2305 } 2306 port = EHCI_PORTSC(index); 2307 v = EOREAD4(sc, port); 2308 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2309 v &= ~EHCI_PS_CLEAR; 2310 switch(value) { 2311 case UHF_PORT_ENABLE: 2312 EOWRITE4(sc, port, v | EHCI_PS_PE); 2313 break; 2314 case UHF_PORT_SUSPEND: 2315 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2316 break; 2317 case UHF_PORT_RESET: 2318 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2319 index)); 2320 if (EHCI_PS_IS_LOWSPEED(v) 2321 && sc->sc_ncomp > 0 2322 && !(sc->sc_flags & EHCIF_ETTF)) { 2323 /* 2324 * Low speed device on non-ETTF controller or 2325 * unaccompanied controller, give up ownership. 2326 */ 2327 ehci_disown(sc, index, 1); 2328 break; 2329 } 2330 /* Start reset sequence. */ 2331 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2332 EOWRITE4(sc, port, v | EHCI_PS_PR); 2333 /* Wait for reset to complete. */ 2334 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2335 if (sc->sc_dying) { 2336 err = USBD_IOERROR; 2337 goto ret; 2338 } 2339 /* 2340 * An embedded transaction translater will automatically 2341 * terminate the reset sequence so there's no need to 2342 * it. 2343 */ 2344 v = EOREAD4(sc, port); 2345 if (v & EHCI_PS_PR) { 2346 /* Terminate reset sequence. */ 2347 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2348 /* Wait for HC to complete reset. */ 2349 usb_delay_ms(&sc->sc_bus, 2350 EHCI_PORT_RESET_COMPLETE); 2351 if (sc->sc_dying) { 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 } 2356 2357 v = EOREAD4(sc, port); 2358 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2359 if (v & EHCI_PS_PR) { 2360 printf("%s: port reset timeout\n", 2361 device_xname(sc->sc_dev)); 2362 return (USBD_TIMEOUT); 2363 } 2364 if (!(v & EHCI_PS_PE)) { 2365 /* Not a high speed device, give up ownership.*/ 2366 ehci_disown(sc, index, 0); 2367 break; 2368 } 2369 sc->sc_isreset[index] = 1; 2370 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2371 index, v)); 2372 break; 2373 case UHF_PORT_POWER: 2374 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2375 "%d (has PPC = %d)\n", index, 2376 sc->sc_hasppc)); 2377 if (sc->sc_hasppc) 2378 EOWRITE4(sc, port, v | EHCI_PS_PP); 2379 break; 2380 case UHF_PORT_TEST: 2381 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2382 "%d\n", index)); 2383 break; 2384 case UHF_PORT_INDICATOR: 2385 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2386 "%d\n", index)); 2387 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2388 break; 2389 default: 2390 err = USBD_IOERROR; 2391 goto ret; 2392 } 2393 break; 2394 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2395 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2396 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2397 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2398 break; 2399 default: 2400 err = USBD_IOERROR; 2401 goto ret; 2402 } 2403 xfer->actlen = totlen; 2404 err = USBD_NORMAL_COMPLETION; 2405 ret: 2406 xfer->status = err; 2407 s = splusb(); 2408 usb_transfer_complete(xfer); 2409 splx(s); 2410 return (USBD_IN_PROGRESS); 2411 } 2412 2413 Static void 2414 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2415 { 2416 int port; 2417 u_int32_t v; 2418 2419 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2420 #ifdef DIAGNOSTIC 2421 if (sc->sc_npcomp != 0) { 2422 int i = (index-1) / sc->sc_npcomp; 2423 if (i >= sc->sc_ncomp) 2424 printf("%s: strange port\n", 2425 device_xname(sc->sc_dev)); 2426 else 2427 printf("%s: handing over %s speed device on " 2428 "port %d to %s\n", 2429 device_xname(sc->sc_dev), 2430 lowspeed ? "low" : "full", 2431 index, device_xname(sc->sc_comps[i])); 2432 } else { 2433 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2434 } 2435 #endif 2436 port = EHCI_PORTSC(index); 2437 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2438 EOWRITE4(sc, port, v | EHCI_PS_PO); 2439 } 2440 2441 /* Abort a root control request. */ 2442 Static void 2443 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2444 { 2445 /* Nothing to do, all transfers are synchronous. */ 2446 } 2447 2448 /* Close the root pipe. */ 2449 Static void 2450 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2451 { 2452 DPRINTF(("ehci_root_ctrl_close\n")); 2453 /* Nothing to do. */ 2454 } 2455 2456 Static void 2457 ehci_root_intr_done(usbd_xfer_handle xfer) 2458 { 2459 xfer->hcpriv = NULL; 2460 } 2461 2462 Static usbd_status 2463 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2464 { 2465 usbd_status err; 2466 2467 /* Insert last in queue. */ 2468 err = usb_insert_transfer(xfer); 2469 if (err) 2470 return (err); 2471 2472 /* Pipe isn't running, start first */ 2473 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2474 } 2475 2476 Static usbd_status 2477 ehci_root_intr_start(usbd_xfer_handle xfer) 2478 { 2479 usbd_pipe_handle pipe = xfer->pipe; 2480 ehci_softc_t *sc = pipe->device->bus->hci_private; 2481 2482 if (sc->sc_dying) 2483 return (USBD_IOERROR); 2484 2485 sc->sc_intrxfer = xfer; 2486 2487 return (USBD_IN_PROGRESS); 2488 } 2489 2490 /* Abort a root interrupt request. */ 2491 Static void 2492 ehci_root_intr_abort(usbd_xfer_handle xfer) 2493 { 2494 int s; 2495 2496 if (xfer->pipe->intrxfer == xfer) { 2497 DPRINTF(("ehci_root_intr_abort: remove\n")); 2498 xfer->pipe->intrxfer = NULL; 2499 } 2500 xfer->status = USBD_CANCELLED; 2501 s = splusb(); 2502 usb_transfer_complete(xfer); 2503 splx(s); 2504 } 2505 2506 /* Close the root pipe. */ 2507 Static void 2508 ehci_root_intr_close(usbd_pipe_handle pipe) 2509 { 2510 ehci_softc_t *sc = pipe->device->bus->hci_private; 2511 2512 DPRINTF(("ehci_root_intr_close\n")); 2513 2514 sc->sc_intrxfer = NULL; 2515 } 2516 2517 Static void 2518 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2519 { 2520 xfer->hcpriv = NULL; 2521 } 2522 2523 /************************/ 2524 2525 Static ehci_soft_qh_t * 2526 ehci_alloc_sqh(ehci_softc_t *sc) 2527 { 2528 ehci_soft_qh_t *sqh; 2529 usbd_status err; 2530 int i, offs; 2531 usb_dma_t dma; 2532 2533 if (sc->sc_freeqhs == NULL) { 2534 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2535 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2536 EHCI_PAGE_SIZE, &dma); 2537 #ifdef EHCI_DEBUG 2538 if (err) 2539 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2540 #endif 2541 if (err) 2542 return (NULL); 2543 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2544 offs = i * EHCI_SQH_SIZE; 2545 sqh = KERNADDR(&dma, offs); 2546 sqh->physaddr = DMAADDR(&dma, offs); 2547 sqh->dma = dma; 2548 sqh->offs = offs; 2549 sqh->next = sc->sc_freeqhs; 2550 sc->sc_freeqhs = sqh; 2551 } 2552 } 2553 sqh = sc->sc_freeqhs; 2554 sc->sc_freeqhs = sqh->next; 2555 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2556 sqh->next = NULL; 2557 return (sqh); 2558 } 2559 2560 Static void 2561 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2562 { 2563 sqh->next = sc->sc_freeqhs; 2564 sc->sc_freeqhs = sqh; 2565 } 2566 2567 Static ehci_soft_qtd_t * 2568 ehci_alloc_sqtd(ehci_softc_t *sc) 2569 { 2570 ehci_soft_qtd_t *sqtd; 2571 usbd_status err; 2572 int i, offs; 2573 usb_dma_t dma; 2574 int s; 2575 2576 if (sc->sc_freeqtds == NULL) { 2577 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2578 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2579 EHCI_PAGE_SIZE, &dma); 2580 #ifdef EHCI_DEBUG 2581 if (err) 2582 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2583 #endif 2584 if (err) 2585 return (NULL); 2586 s = splusb(); 2587 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2588 offs = i * EHCI_SQTD_SIZE; 2589 sqtd = KERNADDR(&dma, offs); 2590 sqtd->physaddr = DMAADDR(&dma, offs); 2591 sqtd->dma = dma; 2592 sqtd->offs = offs; 2593 sqtd->nextqtd = sc->sc_freeqtds; 2594 sc->sc_freeqtds = sqtd; 2595 } 2596 splx(s); 2597 } 2598 2599 s = splusb(); 2600 sqtd = sc->sc_freeqtds; 2601 sc->sc_freeqtds = sqtd->nextqtd; 2602 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2603 sqtd->nextqtd = NULL; 2604 sqtd->xfer = NULL; 2605 splx(s); 2606 2607 return (sqtd); 2608 } 2609 2610 Static void 2611 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2612 { 2613 int s; 2614 2615 s = splusb(); 2616 sqtd->nextqtd = sc->sc_freeqtds; 2617 sc->sc_freeqtds = sqtd; 2618 splx(s); 2619 } 2620 2621 Static usbd_status 2622 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2623 int alen, int rd, usbd_xfer_handle xfer, 2624 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2625 { 2626 ehci_soft_qtd_t *next, *cur; 2627 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2628 u_int32_t qtdstatus; 2629 int len, curlen, mps; 2630 int i, tog; 2631 usb_dma_t *dma = &xfer->dmabuf; 2632 u_int16_t flags = xfer->flags; 2633 2634 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2635 2636 len = alen; 2637 dataphys = DMAADDR(dma, 0); 2638 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2639 qtdstatus = EHCI_QTD_ACTIVE | 2640 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2641 EHCI_QTD_SET_CERR(3) 2642 /* IOC set below */ 2643 /* BYTES set below */ 2644 ; 2645 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2646 tog = epipe->nexttoggle; 2647 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2648 2649 cur = ehci_alloc_sqtd(sc); 2650 *sp = cur; 2651 if (cur == NULL) 2652 goto nomem; 2653 2654 usb_syncmem(dma, 0, alen, 2655 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2656 for (;;) { 2657 dataphyspage = EHCI_PAGE(dataphys); 2658 /* The EHCI hardware can handle at most 5 pages. */ 2659 if (dataphyslastpage - dataphyspage < 2660 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2661 /* we can handle it in this QTD */ 2662 curlen = len; 2663 } else { 2664 /* must use multiple TDs, fill as much as possible. */ 2665 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2666 EHCI_PAGE_OFFSET(dataphys); 2667 #ifdef DIAGNOSTIC 2668 if (curlen > len) { 2669 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2670 "len=0x%x offs=0x%x\n", curlen, len, 2671 EHCI_PAGE_OFFSET(dataphys)); 2672 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2673 dataphyslastpage, dataphyspage, 2674 dataphys); 2675 curlen = len; 2676 } 2677 #endif 2678 /* the length must be a multiple of the max size */ 2679 curlen -= curlen % mps; 2680 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2681 "curlen=%d\n", curlen)); 2682 #ifdef DIAGNOSTIC 2683 if (curlen == 0) 2684 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2685 #endif 2686 } 2687 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2688 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2689 dataphys, dataphyslastpage, 2690 len, curlen)); 2691 len -= curlen; 2692 2693 /* 2694 * Allocate another transfer if there's more data left, 2695 * or if force last short transfer flag is set and we're 2696 * allocating a multiple of the max packet size. 2697 */ 2698 if (len != 0 || 2699 ((curlen % mps) == 0 && !rd && curlen != 0 && 2700 (flags & USBD_FORCE_SHORT_XFER))) { 2701 next = ehci_alloc_sqtd(sc); 2702 if (next == NULL) 2703 goto nomem; 2704 nextphys = htole32(next->physaddr); 2705 } else { 2706 next = NULL; 2707 nextphys = EHCI_NULL; 2708 } 2709 2710 for (i = 0; i * EHCI_PAGE_SIZE < 2711 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2712 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2713 if (i != 0) /* use offset only in first buffer */ 2714 a = EHCI_PAGE(a); 2715 if (i >= EHCI_QTD_NBUFFERS) { 2716 #ifdef DIAGNOSTIC 2717 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2718 #endif 2719 goto nomem; 2720 } 2721 cur->qtd.qtd_buffer[i] = htole32(a); 2722 cur->qtd.qtd_buffer_hi[i] = 0; 2723 } 2724 cur->nextqtd = next; 2725 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2726 cur->qtd.qtd_status = 2727 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2728 cur->xfer = xfer; 2729 cur->len = curlen; 2730 2731 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2732 dataphys, dataphys + curlen)); 2733 /* adjust the toggle based on the number of packets in this 2734 qtd */ 2735 if (((curlen + mps - 1) / mps) & 1) { 2736 tog ^= 1; 2737 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2738 } 2739 if (next == NULL) 2740 break; 2741 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2743 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2744 if (len) 2745 dataphys += curlen; 2746 cur = next; 2747 } 2748 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2749 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2751 *ep = cur; 2752 epipe->nexttoggle = tog; 2753 2754 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2755 *sp, *ep)); 2756 2757 return (USBD_NORMAL_COMPLETION); 2758 2759 nomem: 2760 /* XXX free chain */ 2761 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2762 return (USBD_NOMEM); 2763 } 2764 2765 Static void 2766 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2767 ehci_soft_qtd_t *sqtdend) 2768 { 2769 ehci_soft_qtd_t *p; 2770 int i; 2771 2772 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2773 sqtd, sqtdend)); 2774 2775 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2776 p = sqtd->nextqtd; 2777 ehci_free_sqtd(sc, sqtd); 2778 } 2779 } 2780 2781 Static ehci_soft_itd_t * 2782 ehci_alloc_itd(ehci_softc_t *sc) 2783 { 2784 struct ehci_soft_itd *itd, *freeitd; 2785 usbd_status err; 2786 int i, s, offs, frindex, previndex; 2787 usb_dma_t dma; 2788 2789 s = splusb(); 2790 2791 /* Find an itd that wasn't freed this frame or last frame. This can 2792 * discard itds that were freed before frindex wrapped around 2793 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2794 * interrupt and fiddling with list when that happens */ 2795 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2796 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2797 2798 freeitd = NULL; 2799 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2800 if (itd == NULL) 2801 break; 2802 if (itd->slot != frindex && itd->slot != previndex) { 2803 freeitd = itd; 2804 break; 2805 } 2806 } 2807 2808 if (freeitd == NULL) { 2809 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2810 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2811 EHCI_PAGE_SIZE, &dma); 2812 2813 if (err) { 2814 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2815 return NULL; 2816 } 2817 2818 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2819 offs = i * EHCI_ITD_SIZE; 2820 itd = KERNADDR(&dma, offs); 2821 itd->physaddr = DMAADDR(&dma, offs); 2822 itd->dma = dma; 2823 itd->offs = offs; 2824 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2825 } 2826 freeitd = LIST_FIRST(&sc->sc_freeitds); 2827 } 2828 2829 itd = freeitd; 2830 LIST_REMOVE(itd, u.free_list); 2831 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2832 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2833 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2834 BUS_DMASYNC_PREREAD); 2835 2836 itd->u.frame_list.next = NULL; 2837 itd->u.frame_list.prev = NULL; 2838 itd->xfer_next = NULL; 2839 itd->slot = 0; 2840 splx(s); 2841 2842 return itd; 2843 } 2844 2845 Static void 2846 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2847 { 2848 int s; 2849 2850 s = splusb(); 2851 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2852 splx(s); 2853 } 2854 2855 /****************/ 2856 2857 /* 2858 * Close a reqular pipe. 2859 * Assumes that there are no pending transactions. 2860 */ 2861 Static void 2862 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2863 { 2864 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2865 ehci_softc_t *sc = pipe->device->bus->hci_private; 2866 ehci_soft_qh_t *sqh = epipe->sqh; 2867 int s; 2868 2869 s = splusb(); 2870 ehci_rem_qh(sc, sqh, head); 2871 splx(s); 2872 ehci_free_sqh(sc, epipe->sqh); 2873 } 2874 2875 /* 2876 * Abort a device request. 2877 * If this routine is called at splusb() it guarantees that the request 2878 * will be removed from the hardware scheduling and that the callback 2879 * for it will be called with USBD_CANCELLED status. 2880 * It's impossible to guarantee that the requested transfer will not 2881 * have happened since the hardware runs concurrently. 2882 * If the transaction has already happened we rely on the ordinary 2883 * interrupt processing to process it. 2884 * XXX This is most probably wrong. 2885 */ 2886 Static void 2887 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2888 { 2889 #define exfer EXFER(xfer) 2890 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2891 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2892 ehci_soft_qh_t *sqh = epipe->sqh; 2893 ehci_soft_qtd_t *sqtd; 2894 ehci_physaddr_t cur; 2895 u_int32_t qhstatus; 2896 int s; 2897 int hit; 2898 int wake; 2899 2900 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2901 2902 if (sc->sc_dying) { 2903 /* If we're dying, just do the software part. */ 2904 s = splusb(); 2905 xfer->status = status; /* make software ignore it */ 2906 callout_stop(&xfer->timeout_handle); 2907 usb_transfer_complete(xfer); 2908 splx(s); 2909 return; 2910 } 2911 2912 if (cpu_intr_p() || cpu_softintr_p()) 2913 panic("ehci_abort_xfer: not in process context"); 2914 2915 /* 2916 * If an abort is already in progress then just wait for it to 2917 * complete and return. 2918 */ 2919 if (xfer->hcflags & UXFER_ABORTING) { 2920 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2921 #ifdef DIAGNOSTIC 2922 if (status == USBD_TIMEOUT) 2923 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2924 #endif 2925 /* Override the status which might be USBD_TIMEOUT. */ 2926 xfer->status = status; 2927 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2928 xfer->hcflags |= UXFER_ABORTWAIT; 2929 while (xfer->hcflags & UXFER_ABORTING) 2930 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2931 return; 2932 } 2933 xfer->hcflags |= UXFER_ABORTING; 2934 2935 /* 2936 * Step 1: Make interrupt routine and hardware ignore xfer. 2937 */ 2938 s = splusb(); 2939 xfer->status = status; /* make software ignore it */ 2940 callout_stop(&xfer->timeout_handle); 2941 2942 usb_syncmem(&sqh->dma, 2943 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2944 sizeof(sqh->qh.qh_qtd.qtd_status), 2945 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2946 qhstatus = sqh->qh.qh_qtd.qtd_status; 2947 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2948 usb_syncmem(&sqh->dma, 2949 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2950 sizeof(sqh->qh.qh_qtd.qtd_status), 2951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2952 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2953 usb_syncmem(&sqtd->dma, 2954 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2955 sizeof(sqtd->qtd.qtd_status), 2956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2957 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2958 usb_syncmem(&sqtd->dma, 2959 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2960 sizeof(sqtd->qtd.qtd_status), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 if (sqtd == exfer->sqtdend) 2963 break; 2964 } 2965 splx(s); 2966 2967 /* 2968 * Step 2: Wait until we know hardware has finished any possible 2969 * use of the xfer. Also make sure the soft interrupt routine 2970 * has run. 2971 */ 2972 ehci_sync_hc(sc); 2973 s = splusb(); 2974 sc->sc_softwake = 1; 2975 usb_schedsoftintr(&sc->sc_bus); 2976 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2977 splx(s); 2978 2979 /* 2980 * Step 3: Remove any vestiges of the xfer from the hardware. 2981 * The complication here is that the hardware may have executed 2982 * beyond the xfer we're trying to abort. So as we're scanning 2983 * the TDs of this xfer we check if the hardware points to 2984 * any of them. 2985 */ 2986 s = splusb(); /* XXX why? */ 2987 2988 usb_syncmem(&sqh->dma, 2989 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2990 sizeof(sqh->qh.qh_curqtd), 2991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2992 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2993 hit = 0; 2994 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2995 hit |= cur == sqtd->physaddr; 2996 if (sqtd == exfer->sqtdend) 2997 break; 2998 } 2999 sqtd = sqtd->nextqtd; 3000 /* Zap curqtd register if hardware pointed inside the xfer. */ 3001 if (hit && sqtd != NULL) { 3002 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3003 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3004 usb_syncmem(&sqh->dma, 3005 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3006 sizeof(sqh->qh.qh_curqtd), 3007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3008 sqh->qh.qh_qtd.qtd_status = qhstatus; 3009 usb_syncmem(&sqh->dma, 3010 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3011 sizeof(sqh->qh.qh_qtd.qtd_status), 3012 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3013 } else { 3014 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3015 } 3016 3017 /* 3018 * Step 4: Execute callback. 3019 */ 3020 #ifdef DIAGNOSTIC 3021 exfer->isdone = 1; 3022 #endif 3023 wake = xfer->hcflags & UXFER_ABORTWAIT; 3024 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3025 usb_transfer_complete(xfer); 3026 if (wake) 3027 wakeup(&xfer->hcflags); 3028 3029 splx(s); 3030 #undef exfer 3031 } 3032 3033 Static void 3034 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3035 { 3036 ehci_isoc_trans_t trans_status; 3037 struct ehci_pipe *epipe; 3038 struct ehci_xfer *exfer; 3039 ehci_softc_t *sc; 3040 struct ehci_soft_itd *itd; 3041 int s, i, wake; 3042 3043 epipe = (struct ehci_pipe *) xfer->pipe; 3044 exfer = EXFER(xfer); 3045 sc = epipe->pipe.device->bus->hci_private; 3046 3047 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3048 3049 if (sc->sc_dying) { 3050 s = splusb(); 3051 xfer->status = status; 3052 callout_stop(&xfer->timeout_handle); 3053 usb_transfer_complete(xfer); 3054 splx(s); 3055 return; 3056 } 3057 3058 if (xfer->hcflags & UXFER_ABORTING) { 3059 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3060 3061 #ifdef DIAGNOSTIC 3062 if (status == USBD_TIMEOUT) 3063 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3064 #endif 3065 3066 xfer->status = status; 3067 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3068 xfer->hcflags |= UXFER_ABORTWAIT; 3069 while (xfer->hcflags & UXFER_ABORTING) 3070 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3071 return; 3072 } 3073 xfer->hcflags |= UXFER_ABORTING; 3074 3075 xfer->status = status; 3076 callout_stop(&xfer->timeout_handle); 3077 3078 s = splusb(); 3079 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3080 usb_syncmem(&itd->dma, 3081 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3082 sizeof(itd->itd.itd_ctl), 3083 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3084 3085 for (i = 0; i < 8; i++) { 3086 trans_status = le32toh(itd->itd.itd_ctl[i]); 3087 trans_status &= ~EHCI_ITD_ACTIVE; 3088 itd->itd.itd_ctl[i] = htole32(trans_status); 3089 } 3090 3091 usb_syncmem(&itd->dma, 3092 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3093 sizeof(itd->itd.itd_ctl), 3094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3095 } 3096 splx(s); 3097 3098 s = splusb(); 3099 sc->sc_softwake = 1; 3100 usb_schedsoftintr(&sc->sc_bus); 3101 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3102 splx(s); 3103 3104 #ifdef DIAGNOSTIC 3105 exfer->isdone = 1; 3106 #endif 3107 wake = xfer->hcflags & UXFER_ABORTWAIT; 3108 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3109 usb_transfer_complete(xfer); 3110 if (wake) 3111 wakeup(&xfer->hcflags); 3112 3113 return; 3114 } 3115 3116 Static void 3117 ehci_timeout(void *addr) 3118 { 3119 struct ehci_xfer *exfer = addr; 3120 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3121 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3122 3123 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3124 #ifdef EHCI_DEBUG 3125 if (ehcidebug > 1) 3126 usbd_dump_pipe(exfer->xfer.pipe); 3127 #endif 3128 3129 if (sc->sc_dying) { 3130 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3131 return; 3132 } 3133 3134 /* Execute the abort in a process context. */ 3135 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3136 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3137 USB_TASKQ_HC); 3138 } 3139 3140 Static void 3141 ehci_timeout_task(void *addr) 3142 { 3143 usbd_xfer_handle xfer = addr; 3144 int s; 3145 3146 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3147 3148 s = splusb(); 3149 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3150 splx(s); 3151 } 3152 3153 /************************/ 3154 3155 Static usbd_status 3156 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3157 { 3158 usbd_status err; 3159 3160 /* Insert last in queue. */ 3161 err = usb_insert_transfer(xfer); 3162 if (err) 3163 return (err); 3164 3165 /* Pipe isn't running, start first */ 3166 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3167 } 3168 3169 Static usbd_status 3170 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3171 { 3172 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3173 usbd_status err; 3174 3175 if (sc->sc_dying) 3176 return (USBD_IOERROR); 3177 3178 #ifdef DIAGNOSTIC 3179 if (!(xfer->rqflags & URQ_REQUEST)) { 3180 /* XXX panic */ 3181 printf("ehci_device_ctrl_transfer: not a request\n"); 3182 return (USBD_INVAL); 3183 } 3184 #endif 3185 3186 err = ehci_device_request(xfer); 3187 if (err) 3188 return (err); 3189 3190 if (sc->sc_bus.use_polling) 3191 ehci_waitintr(sc, xfer); 3192 return (USBD_IN_PROGRESS); 3193 } 3194 3195 Static void 3196 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3197 { 3198 struct ehci_xfer *ex = EXFER(xfer); 3199 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3200 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3201 usb_device_request_t *req = &xfer->request; 3202 int len = UGETW(req->wLength); 3203 int rd = req->bmRequestType & UT_READ; 3204 3205 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3206 3207 #ifdef DIAGNOSTIC 3208 if (!(xfer->rqflags & URQ_REQUEST)) { 3209 panic("ehci_ctrl_done: not a request"); 3210 } 3211 #endif 3212 3213 mutex_enter(&sc->sc_intrhead_lock); 3214 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3215 ehci_del_intr_list(sc, ex); /* remove from active list */ 3216 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3217 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3218 BUS_DMASYNC_POSTWRITE); 3219 if (len) 3220 usb_syncmem(&xfer->dmabuf, 0, len, 3221 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3222 } 3223 mutex_exit(&sc->sc_intrhead_lock); 3224 3225 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3226 } 3227 3228 /* Abort a device control request. */ 3229 Static void 3230 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3231 { 3232 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3233 ehci_abort_xfer(xfer, USBD_CANCELLED); 3234 } 3235 3236 /* Close a device control pipe. */ 3237 Static void 3238 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3239 { 3240 ehci_softc_t *sc = pipe->device->bus->hci_private; 3241 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3242 3243 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3244 ehci_close_pipe(pipe, sc->sc_async_head); 3245 } 3246 3247 Static usbd_status 3248 ehci_device_request(usbd_xfer_handle xfer) 3249 { 3250 #define exfer EXFER(xfer) 3251 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3252 usb_device_request_t *req = &xfer->request; 3253 usbd_device_handle dev = epipe->pipe.device; 3254 ehci_softc_t *sc = dev->bus->hci_private; 3255 int addr = dev->address; 3256 ehci_soft_qtd_t *setup, *stat, *next; 3257 ehci_soft_qh_t *sqh; 3258 int isread; 3259 int len; 3260 usbd_status err; 3261 int s; 3262 3263 isread = req->bmRequestType & UT_READ; 3264 len = UGETW(req->wLength); 3265 3266 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3267 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3268 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3269 UGETW(req->wIndex), len, addr, 3270 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3271 3272 setup = ehci_alloc_sqtd(sc); 3273 if (setup == NULL) { 3274 err = USBD_NOMEM; 3275 goto bad1; 3276 } 3277 stat = ehci_alloc_sqtd(sc); 3278 if (stat == NULL) { 3279 err = USBD_NOMEM; 3280 goto bad2; 3281 } 3282 3283 sqh = epipe->sqh; 3284 epipe->u.ctl.length = len; 3285 3286 /* Update device address and length since they may have changed 3287 during the setup of the control pipe in usbd_new_device(). */ 3288 /* XXX This only needs to be done once, but it's too early in open. */ 3289 /* XXXX Should not touch ED here! */ 3290 sqh->qh.qh_endp = 3291 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3292 htole32( 3293 EHCI_QH_SET_ADDR(addr) | 3294 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3295 ); 3296 3297 /* Set up data transaction */ 3298 if (len != 0) { 3299 ehci_soft_qtd_t *end; 3300 3301 /* Start toggle at 1. */ 3302 epipe->nexttoggle = 1; 3303 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3304 &next, &end); 3305 if (err) 3306 goto bad3; 3307 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3308 end->nextqtd = stat; 3309 end->qtd.qtd_next = 3310 end->qtd.qtd_altnext = htole32(stat->physaddr); 3311 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3313 } else { 3314 next = stat; 3315 } 3316 3317 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3318 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3319 3320 /* Clear toggle */ 3321 setup->qtd.qtd_status = htole32( 3322 EHCI_QTD_ACTIVE | 3323 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3324 EHCI_QTD_SET_CERR(3) | 3325 EHCI_QTD_SET_TOGGLE(0) | 3326 EHCI_QTD_SET_BYTES(sizeof *req) 3327 ); 3328 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3329 setup->qtd.qtd_buffer_hi[0] = 0; 3330 setup->nextqtd = next; 3331 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3332 setup->xfer = xfer; 3333 setup->len = sizeof *req; 3334 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3335 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3336 3337 stat->qtd.qtd_status = htole32( 3338 EHCI_QTD_ACTIVE | 3339 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3340 EHCI_QTD_SET_CERR(3) | 3341 EHCI_QTD_SET_TOGGLE(1) | 3342 EHCI_QTD_IOC 3343 ); 3344 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3345 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3346 stat->nextqtd = NULL; 3347 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3348 stat->xfer = xfer; 3349 stat->len = 0; 3350 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3351 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3352 3353 #ifdef EHCI_DEBUG 3354 if (ehcidebug > 5) { 3355 DPRINTF(("ehci_device_request:\n")); 3356 ehci_dump_sqh(sqh); 3357 ehci_dump_sqtds(setup); 3358 } 3359 #endif 3360 3361 exfer->sqtdstart = setup; 3362 exfer->sqtdend = stat; 3363 #ifdef DIAGNOSTIC 3364 if (!exfer->isdone) { 3365 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3366 } 3367 exfer->isdone = 0; 3368 #endif 3369 3370 /* Insert qTD in QH list. */ 3371 s = splusb(); 3372 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3373 if (xfer->timeout && !sc->sc_bus.use_polling) { 3374 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3375 (ehci_timeout), (xfer)); 3376 } 3377 mutex_enter(&sc->sc_intrhead_lock); 3378 ehci_add_intr_list(sc, exfer); 3379 mutex_exit(&sc->sc_intrhead_lock); 3380 xfer->status = USBD_IN_PROGRESS; 3381 splx(s); 3382 3383 #ifdef EHCI_DEBUG 3384 if (ehcidebug > 10) { 3385 DPRINTF(("ehci_device_request: status=%x\n", 3386 EOREAD4(sc, EHCI_USBSTS))); 3387 delay(10000); 3388 ehci_dump_regs(sc); 3389 ehci_dump_sqh(sc->sc_async_head); 3390 ehci_dump_sqh(sqh); 3391 ehci_dump_sqtds(setup); 3392 } 3393 #endif 3394 3395 return (USBD_NORMAL_COMPLETION); 3396 3397 bad3: 3398 ehci_free_sqtd(sc, stat); 3399 bad2: 3400 ehci_free_sqtd(sc, setup); 3401 bad1: 3402 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3403 xfer->status = err; 3404 usb_transfer_complete(xfer); 3405 return (err); 3406 #undef exfer 3407 } 3408 3409 /* 3410 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3411 * qTD status, or miss signalling occasionally under heavy load. If the host 3412 * machine is too fast, we we can miss transaction completion - when we scan 3413 * the active list the transaction still seems to be active. This generally 3414 * exhibits itself as a umass stall that never recovers. 3415 * 3416 * We work around this behaviour by setting up this callback after any softintr 3417 * that completes with transactions still pending, giving us another chance to 3418 * check for completion after the writeback has taken place. 3419 */ 3420 Static void 3421 ehci_intrlist_timeout(void *arg) 3422 { 3423 ehci_softc_t *sc = arg; 3424 int s = splusb(); 3425 3426 DPRINTF(("ehci_intrlist_timeout\n")); 3427 usb_schedsoftintr(&sc->sc_bus); 3428 3429 splx(s); 3430 } 3431 3432 /************************/ 3433 3434 Static usbd_status 3435 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3436 { 3437 usbd_status err; 3438 3439 /* Insert last in queue. */ 3440 err = usb_insert_transfer(xfer); 3441 if (err) 3442 return (err); 3443 3444 /* Pipe isn't running, start first */ 3445 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3446 } 3447 3448 Static usbd_status 3449 ehci_device_bulk_start(usbd_xfer_handle xfer) 3450 { 3451 #define exfer EXFER(xfer) 3452 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3453 usbd_device_handle dev = epipe->pipe.device; 3454 ehci_softc_t *sc = dev->bus->hci_private; 3455 ehci_soft_qtd_t *data, *dataend; 3456 ehci_soft_qh_t *sqh; 3457 usbd_status err; 3458 int len, isread, endpt; 3459 int s; 3460 3461 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3462 xfer, xfer->length, xfer->flags)); 3463 3464 if (sc->sc_dying) 3465 return (USBD_IOERROR); 3466 3467 #ifdef DIAGNOSTIC 3468 if (xfer->rqflags & URQ_REQUEST) 3469 panic("ehci_device_bulk_start: a request"); 3470 #endif 3471 3472 len = xfer->length; 3473 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3474 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3475 sqh = epipe->sqh; 3476 3477 epipe->u.bulk.length = len; 3478 3479 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3480 &dataend); 3481 if (err) { 3482 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3483 xfer->status = err; 3484 usb_transfer_complete(xfer); 3485 return (err); 3486 } 3487 3488 #ifdef EHCI_DEBUG 3489 if (ehcidebug > 5) { 3490 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3491 ehci_dump_sqh(sqh); 3492 ehci_dump_sqtds(data); 3493 } 3494 #endif 3495 3496 /* Set up interrupt info. */ 3497 exfer->sqtdstart = data; 3498 exfer->sqtdend = dataend; 3499 #ifdef DIAGNOSTIC 3500 if (!exfer->isdone) { 3501 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3502 } 3503 exfer->isdone = 0; 3504 #endif 3505 3506 s = splusb(); 3507 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3508 if (xfer->timeout && !sc->sc_bus.use_polling) { 3509 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3510 (ehci_timeout), (xfer)); 3511 } 3512 mutex_enter(&sc->sc_intrhead_lock); 3513 ehci_add_intr_list(sc, exfer); 3514 mutex_exit(&sc->sc_intrhead_lock); 3515 xfer->status = USBD_IN_PROGRESS; 3516 splx(s); 3517 3518 #ifdef EHCI_DEBUG 3519 if (ehcidebug > 10) { 3520 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3521 delay(10000); 3522 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3523 ehci_dump_regs(sc); 3524 #if 0 3525 printf("async_head:\n"); 3526 ehci_dump_sqh(sc->sc_async_head); 3527 #endif 3528 printf("sqh:\n"); 3529 ehci_dump_sqh(sqh); 3530 ehci_dump_sqtds(data); 3531 } 3532 #endif 3533 3534 if (sc->sc_bus.use_polling) 3535 ehci_waitintr(sc, xfer); 3536 3537 return (USBD_IN_PROGRESS); 3538 #undef exfer 3539 } 3540 3541 Static void 3542 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3543 { 3544 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3545 ehci_abort_xfer(xfer, USBD_CANCELLED); 3546 } 3547 3548 /* 3549 * Close a device bulk pipe. 3550 */ 3551 Static void 3552 ehci_device_bulk_close(usbd_pipe_handle pipe) 3553 { 3554 ehci_softc_t *sc = pipe->device->bus->hci_private; 3555 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3556 3557 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3558 pipe->endpoint->datatoggle = epipe->nexttoggle; 3559 ehci_close_pipe(pipe, sc->sc_async_head); 3560 } 3561 3562 Static void 3563 ehci_device_bulk_done(usbd_xfer_handle xfer) 3564 { 3565 struct ehci_xfer *ex = EXFER(xfer); 3566 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3567 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3568 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3569 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3570 3571 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3572 xfer, xfer->actlen)); 3573 3574 mutex_enter(&sc->sc_intrhead_lock); 3575 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3576 ehci_del_intr_list(sc, ex); /* remove from active list */ 3577 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3578 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3579 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3580 } 3581 mutex_exit(&sc->sc_intrhead_lock); 3582 3583 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3584 } 3585 3586 /************************/ 3587 3588 Static usbd_status 3589 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3590 { 3591 struct ehci_soft_islot *isp; 3592 int islot, lev; 3593 3594 /* Find a poll rate that is large enough. */ 3595 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3596 if (EHCI_ILEV_IVAL(lev) <= ival) 3597 break; 3598 3599 /* Pick an interrupt slot at the right level. */ 3600 /* XXX could do better than picking at random */ 3601 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3602 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3603 3604 sqh->islot = islot; 3605 isp = &sc->sc_islots[islot]; 3606 ehci_add_qh(sqh, isp->sqh); 3607 3608 return (USBD_NORMAL_COMPLETION); 3609 } 3610 3611 Static usbd_status 3612 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3613 { 3614 usbd_status err; 3615 3616 /* Insert last in queue. */ 3617 err = usb_insert_transfer(xfer); 3618 if (err) 3619 return (err); 3620 3621 /* 3622 * Pipe isn't running (otherwise err would be USBD_INPROG), 3623 * so start it first. 3624 */ 3625 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3626 } 3627 3628 Static usbd_status 3629 ehci_device_intr_start(usbd_xfer_handle xfer) 3630 { 3631 #define exfer EXFER(xfer) 3632 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3633 usbd_device_handle dev = xfer->pipe->device; 3634 ehci_softc_t *sc = dev->bus->hci_private; 3635 ehci_soft_qtd_t *data, *dataend; 3636 ehci_soft_qh_t *sqh; 3637 usbd_status err; 3638 int len, isread, endpt; 3639 int s; 3640 3641 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3642 xfer, xfer->length, xfer->flags)); 3643 3644 if (sc->sc_dying) 3645 return (USBD_IOERROR); 3646 3647 #ifdef DIAGNOSTIC 3648 if (xfer->rqflags & URQ_REQUEST) 3649 panic("ehci_device_intr_start: a request"); 3650 #endif 3651 3652 len = xfer->length; 3653 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3654 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3655 sqh = epipe->sqh; 3656 3657 epipe->u.intr.length = len; 3658 3659 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3660 &dataend); 3661 if (err) { 3662 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3663 xfer->status = err; 3664 usb_transfer_complete(xfer); 3665 return (err); 3666 } 3667 3668 #ifdef EHCI_DEBUG 3669 if (ehcidebug > 5) { 3670 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3671 ehci_dump_sqh(sqh); 3672 ehci_dump_sqtds(data); 3673 } 3674 #endif 3675 3676 /* Set up interrupt info. */ 3677 exfer->sqtdstart = data; 3678 exfer->sqtdend = dataend; 3679 #ifdef DIAGNOSTIC 3680 if (!exfer->isdone) { 3681 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3682 } 3683 exfer->isdone = 0; 3684 #endif 3685 3686 s = splusb(); 3687 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3688 if (xfer->timeout && !sc->sc_bus.use_polling) { 3689 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3690 (ehci_timeout), (xfer)); 3691 } 3692 mutex_enter(&sc->sc_intrhead_lock); 3693 ehci_add_intr_list(sc, exfer); 3694 mutex_exit(&sc->sc_intrhead_lock); 3695 xfer->status = USBD_IN_PROGRESS; 3696 splx(s); 3697 3698 #ifdef EHCI_DEBUG 3699 if (ehcidebug > 10) { 3700 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3701 delay(10000); 3702 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3703 ehci_dump_regs(sc); 3704 printf("sqh:\n"); 3705 ehci_dump_sqh(sqh); 3706 ehci_dump_sqtds(data); 3707 } 3708 #endif 3709 3710 if (sc->sc_bus.use_polling) 3711 ehci_waitintr(sc, xfer); 3712 3713 return (USBD_IN_PROGRESS); 3714 #undef exfer 3715 } 3716 3717 Static void 3718 ehci_device_intr_abort(usbd_xfer_handle xfer) 3719 { 3720 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3721 if (xfer->pipe->intrxfer == xfer) { 3722 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3723 xfer->pipe->intrxfer = NULL; 3724 } 3725 /* 3726 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3727 * async doorbell. That's dependent on the async list, wheras 3728 * intr xfers are periodic, should not use this? 3729 */ 3730 ehci_abort_xfer(xfer, USBD_CANCELLED); 3731 } 3732 3733 Static void 3734 ehci_device_intr_close(usbd_pipe_handle pipe) 3735 { 3736 ehci_softc_t *sc = pipe->device->bus->hci_private; 3737 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3738 struct ehci_soft_islot *isp; 3739 3740 isp = &sc->sc_islots[epipe->sqh->islot]; 3741 ehci_close_pipe(pipe, isp->sqh); 3742 } 3743 3744 Static void 3745 ehci_device_intr_done(usbd_xfer_handle xfer) 3746 { 3747 #define exfer EXFER(xfer) 3748 struct ehci_xfer *ex = EXFER(xfer); 3749 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3750 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3751 ehci_soft_qtd_t *data, *dataend; 3752 ehci_soft_qh_t *sqh; 3753 usbd_status err; 3754 int len, isread, endpt, s; 3755 3756 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3757 xfer, xfer->actlen)); 3758 3759 mutex_enter(&sc->sc_intrhead_lock); 3760 if (xfer->pipe->repeat) { 3761 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3762 3763 len = epipe->u.intr.length; 3764 xfer->length = len; 3765 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3766 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3767 usb_syncmem(&xfer->dmabuf, 0, len, 3768 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3769 sqh = epipe->sqh; 3770 3771 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3772 &data, &dataend); 3773 if (err) { 3774 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3775 xfer->status = err; 3776 mutex_exit(&sc->sc_intrhead_lock); 3777 return; 3778 } 3779 3780 /* Set up interrupt info. */ 3781 exfer->sqtdstart = data; 3782 exfer->sqtdend = dataend; 3783 #ifdef DIAGNOSTIC 3784 if (!exfer->isdone) { 3785 printf("ehci_device_intr_done: not done, ex=%p\n", 3786 exfer); 3787 } 3788 exfer->isdone = 0; 3789 #endif 3790 3791 s = splusb(); 3792 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3793 if (xfer->timeout && !sc->sc_bus.use_polling) { 3794 callout_reset(&(xfer->timeout_handle), 3795 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3796 } 3797 splx(s); 3798 3799 xfer->status = USBD_IN_PROGRESS; 3800 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3801 ehci_del_intr_list(sc, ex); /* remove from active list */ 3802 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3803 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3804 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3805 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3806 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3807 } 3808 mutex_exit(&sc->sc_intrhead_lock); 3809 #undef exfer 3810 } 3811 3812 /************************/ 3813 3814 Static usbd_status 3815 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3816 { 3817 usbd_status err; 3818 3819 err = usb_insert_transfer(xfer); 3820 if (err && err != USBD_IN_PROGRESS) 3821 return err; 3822 3823 return ehci_device_isoc_start(xfer); 3824 } 3825 3826 Static usbd_status 3827 ehci_device_isoc_start(usbd_xfer_handle xfer) 3828 { 3829 struct ehci_pipe *epipe; 3830 usbd_device_handle dev; 3831 ehci_softc_t *sc; 3832 struct ehci_xfer *exfer; 3833 ehci_soft_itd_t *itd, *prev, *start, *stop; 3834 usb_dma_t *dma_buf; 3835 int i, j, k, frames, uframes, ufrperframe; 3836 int s, trans_count, offs, total_length; 3837 int frindex; 3838 3839 start = NULL; 3840 prev = NULL; 3841 itd = NULL; 3842 trans_count = 0; 3843 total_length = 0; 3844 exfer = (struct ehci_xfer *) xfer; 3845 sc = xfer->pipe->device->bus->hci_private; 3846 dev = xfer->pipe->device; 3847 epipe = (struct ehci_pipe *)xfer->pipe; 3848 3849 /* 3850 * To allow continuous transfers, above we start all transfers 3851 * immediately. However, we're still going to get usbd_start_next call 3852 * this when another xfer completes. So, check if this is already 3853 * in progress or not 3854 */ 3855 3856 if (exfer->itdstart != NULL) 3857 return USBD_IN_PROGRESS; 3858 3859 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3860 xfer, xfer->length, xfer->flags)); 3861 3862 if (sc->sc_dying) 3863 return USBD_IOERROR; 3864 3865 /* 3866 * To avoid complication, don't allow a request right now that'll span 3867 * the entire frame table. To within 4 frames, to allow some leeway 3868 * on either side of where the hc currently is. 3869 */ 3870 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3871 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3872 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3873 return USBD_INVAL; 3874 } 3875 3876 #ifdef DIAGNOSTIC 3877 if (xfer->rqflags & URQ_REQUEST) 3878 panic("ehci_device_isoc_start: request\n"); 3879 3880 if (!exfer->isdone) 3881 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3882 exfer->isdone = 0; 3883 #endif 3884 3885 /* 3886 * Step 1: Allocate and initialize itds, how many do we need? 3887 * One per transfer if interval >= 8 microframes, fewer if we use 3888 * multiple microframes per frame. 3889 */ 3890 3891 i = epipe->pipe.endpoint->edesc->bInterval; 3892 if (i > 16 || i == 0) { 3893 /* Spec page 271 says intervals > 16 are invalid */ 3894 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3895 return USBD_INVAL; 3896 } 3897 3898 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3899 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3900 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3901 3902 if (frames == 0) { 3903 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3904 return USBD_INVAL; 3905 } 3906 3907 dma_buf = &xfer->dmabuf; 3908 offs = 0; 3909 3910 for (i = 0; i < frames; i++) { 3911 int froffs = offs; 3912 itd = ehci_alloc_itd(sc); 3913 3914 if (prev != NULL) { 3915 prev->itd.itd_next = 3916 htole32(itd->physaddr | EHCI_LINK_ITD); 3917 usb_syncmem(&itd->dma, 3918 itd->offs + offsetof(ehci_itd_t, itd_next), 3919 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3920 3921 prev->xfer_next = itd; 3922 } else { 3923 start = itd; 3924 } 3925 3926 /* 3927 * Step 1.5, initialize uframes 3928 */ 3929 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3930 /* Calculate which page in the list this starts in */ 3931 int addr = DMAADDR(dma_buf, froffs); 3932 addr = EHCI_PAGE_OFFSET(addr); 3933 addr += (offs - froffs); 3934 addr = EHCI_PAGE(addr); 3935 addr /= EHCI_PAGE_SIZE; 3936 3937 /* This gets the initial offset into the first page, 3938 * looks how far further along the current uframe 3939 * offset is. Works out how many pages that is. 3940 */ 3941 3942 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3943 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3944 EHCI_ITD_SET_PG(addr) | 3945 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3946 3947 total_length += xfer->frlengths[trans_count]; 3948 offs += xfer->frlengths[trans_count]; 3949 trans_count++; 3950 3951 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3952 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3953 break; 3954 } 3955 } 3956 3957 /* Step 1.75, set buffer pointers. To simplify matters, all 3958 * pointers are filled out for the next 7 hardware pages in 3959 * the dma block, so no need to worry what pages to cover 3960 * and what to not. 3961 */ 3962 3963 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 3964 /* 3965 * Don't try to lookup a page that's past the end 3966 * of buffer 3967 */ 3968 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3969 if (page_offs >= dma_buf->block->size) 3970 break; 3971 3972 unsigned long long page = DMAADDR(dma_buf, page_offs); 3973 page = EHCI_PAGE(page); 3974 itd->itd.itd_bufr[j] = 3975 htole32(EHCI_ITD_SET_BPTR(page)); 3976 itd->itd.itd_bufr_hi[j] = 3977 htole32(page >> 32); 3978 } 3979 3980 /* 3981 * Other special values 3982 */ 3983 3984 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3985 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3986 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3987 3988 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3989 ? 1 : 0; 3990 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3991 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3992 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3993 3994 /* FIXME: handle invalid trans */ 3995 itd->itd.itd_bufr[2] |= 3996 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3997 3998 usb_syncmem(&itd->dma, 3999 itd->offs + offsetof(ehci_itd_t, itd_next), 4000 sizeof(ehci_itd_t), 4001 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4002 4003 prev = itd; 4004 } /* End of frame */ 4005 4006 stop = itd; 4007 stop->xfer_next = NULL; 4008 exfer->isoc_len = total_length; 4009 4010 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4012 4013 /* 4014 * Part 2: Transfer descriptors have now been set up, now they must 4015 * be scheduled into the period frame list. Erk. Not wanting to 4016 * complicate matters, transfer is denied if the transfer spans 4017 * more than the period frame list. 4018 */ 4019 4020 s = splusb(); 4021 4022 /* Start inserting frames */ 4023 if (epipe->u.isoc.cur_xfers > 0) { 4024 frindex = epipe->u.isoc.next_frame; 4025 } else { 4026 frindex = EOREAD4(sc, EHCI_FRINDEX); 4027 frindex = frindex >> 3; /* Erase microframe index */ 4028 frindex += 2; 4029 } 4030 4031 if (frindex >= sc->sc_flsize) 4032 frindex &= (sc->sc_flsize - 1); 4033 4034 /* What's the frame interval? */ 4035 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4036 if (i / USB_UFRAMES_PER_FRAME == 0) 4037 i = 1; 4038 else 4039 i /= USB_UFRAMES_PER_FRAME; 4040 4041 itd = start; 4042 for (j = 0; j < frames; j++) { 4043 if (itd == NULL) 4044 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4045 4046 itd->itd.itd_next = sc->sc_flist[frindex]; 4047 if (itd->itd.itd_next == 0) 4048 /* FIXME: frindex table gets initialized to NULL 4049 * or EHCI_NULL? */ 4050 itd->itd.itd_next = EHCI_NULL; 4051 4052 usb_syncmem(&itd->dma, 4053 itd->offs + offsetof(ehci_itd_t, itd_next), 4054 sizeof(itd->itd.itd_next), 4055 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4056 4057 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4058 4059 usb_syncmem(&sc->sc_fldma, 4060 sizeof(ehci_link_t) * frindex, 4061 sizeof(ehci_link_t), 4062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4063 4064 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4065 sc->sc_softitds[frindex] = itd; 4066 if (itd->u.frame_list.next != NULL) 4067 itd->u.frame_list.next->u.frame_list.prev = itd; 4068 itd->slot = frindex; 4069 itd->u.frame_list.prev = NULL; 4070 4071 frindex += i; 4072 if (frindex >= sc->sc_flsize) 4073 frindex -= sc->sc_flsize; 4074 4075 itd = itd->xfer_next; 4076 } 4077 4078 epipe->u.isoc.cur_xfers++; 4079 epipe->u.isoc.next_frame = frindex; 4080 4081 exfer->itdstart = start; 4082 exfer->itdend = stop; 4083 exfer->sqtdstart = NULL; 4084 exfer->sqtdstart = NULL; 4085 4086 mutex_enter(&sc->sc_intrhead_lock); 4087 ehci_add_intr_list(sc, exfer); 4088 mutex_exit(&sc->sc_intrhead_lock); 4089 xfer->status = USBD_IN_PROGRESS; 4090 xfer->done = 0; 4091 splx(s); 4092 4093 if (sc->sc_bus.use_polling) { 4094 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4095 ehci_waitintr(sc, xfer); 4096 } 4097 4098 return USBD_IN_PROGRESS; 4099 } 4100 4101 Static void 4102 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4103 { 4104 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4105 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4106 } 4107 4108 Static void 4109 ehci_device_isoc_close(usbd_pipe_handle pipe) 4110 { 4111 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4112 } 4113 4114 Static void 4115 ehci_device_isoc_done(usbd_xfer_handle xfer) 4116 { 4117 struct ehci_xfer *exfer; 4118 ehci_softc_t *sc; 4119 struct ehci_pipe *epipe; 4120 int s; 4121 4122 exfer = EXFER(xfer); 4123 sc = xfer->pipe->device->bus->hci_private; 4124 epipe = (struct ehci_pipe *) xfer->pipe; 4125 4126 s = splusb(); 4127 epipe->u.isoc.cur_xfers--; 4128 mutex_enter(&sc->sc_intrhead_lock); 4129 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4130 ehci_del_intr_list(sc, exfer); 4131 ehci_rem_free_itd_chain(sc, exfer); 4132 } 4133 mutex_exit(&sc->sc_intrhead_lock); 4134 splx(s); 4135 4136 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4137 BUS_DMASYNC_POSTREAD); 4138 4139 } 4140