1 2 #define AR3K_FIRMWARE_HEADER_SIZE 20 3 4 #define AR3K_SEND_FIRMWARE 1 5 #define AR3K_GET_STATE 5 6 #define AR3K_SET_NORMAL_MODE 7 7 #define AR3K_GET_VERSION 9 8 #define AR3K_SWITCH_VID_PID 10 9 10 #define AR3K_STATE_MODE_MASK 0x3f 11 #define AR3K_STATE_MODE_NORMAL 14 12 #define AR3K_STATE_IS_SYSCFGED 0x40 13 #define AR3K_STATE_IS_PATCHED 0x80 14 15 struct ar3k_version { 16 uint32_t rom; 17 uint32_t build; 18 uint32_t ram; 19 uint8_t clock; 20 #define AR3K_CLOCK_26M 0 21 #define AR3K_CLOCK_40M 1 22 #define AR3K_CLOCK_19M 2 23 uint8_t pad[7]; 24 }; 25