1 /* $NetBSD: pxg.c,v 1.29 2008/04/28 20:23:58 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEC PixelStamp graphics accelerators with onboard SRAM and 34 * Intel i860 co-processor (PMAG-D, E and F). 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.29 2008/04/28 20:23:58 martin Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/proc.h> 46 #include <sys/kauth.h> 47 48 #if defined(pmax) 49 #include <mips/cpuregs.h> 50 #elif defined(alpha) 51 #include <alpha/alpha_cpu.h> 52 #endif 53 54 #include <machine/autoconf.h> 55 #include <sys/cpu.h> 56 #include <sys/bus.h> 57 58 #include <dev/cons.h> 59 60 #include <dev/wscons/wsconsio.h> 61 #include <dev/wscons/wsdisplayvar.h> 62 63 #include <dev/ic/bt459reg.h> 64 65 #include <dev/tc/tcvar.h> 66 #include <dev/tc/sticreg.h> 67 #include <dev/tc/sticio.h> 68 #include <dev/tc/sticvar.h> 69 #include <dev/tc/pxgvar.h> 70 71 #define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */ 72 #define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */ 73 #define PXG_STIC_OFFSET 0x180000 /* STIC registers */ 74 #define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */ 75 #define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */ 76 #define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */ 77 #define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */ 78 #define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */ 79 #define PXG_ROM_OFFSET 0x380000 /* ROM code */ 80 #define PXG_I860_START_OFFSET 0x380000 /* i860 start register */ 81 #define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */ 82 83 static void pxg_attach(struct device *, struct device *, void *); 84 static int pxg_intr(void *); 85 static int pxg_match(struct device *, struct cfdata *, void *); 86 87 static void pxg_init(struct stic_info *); 88 static int pxg_ioctl(struct stic_info *, u_long, void *, int, struct lwp *); 89 static uint32_t *pxg_pbuf_get(struct stic_info *); 90 static int pxg_pbuf_post(struct stic_info *, u_int32_t *); 91 static int pxg_probe_planes(struct stic_info *); 92 static int pxg_probe_sram(struct stic_info *); 93 94 void pxg_cnattach(tc_addr_t); 95 96 struct pxg_softc { 97 struct device pxg_dv; 98 struct stic_info *pxg_si; 99 }; 100 101 CFATTACH_DECL(pxg, sizeof(struct pxg_softc), 102 pxg_match, pxg_attach, NULL, NULL); 103 104 static const char *pxg_types[] = { 105 "PMAG-DA ", 106 "PMAG-FA ", 107 "PMAG-FB ", 108 "PMAGB-FA", 109 "PMAGB-FB", 110 }; 111 112 static int 113 pxg_match(struct device *parent, struct cfdata *match, void *aux) 114 { 115 struct tc_attach_args *ta; 116 int i; 117 118 ta = aux; 119 120 for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++) 121 if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0) 122 return (1); 123 124 return (0); 125 } 126 127 static void 128 pxg_attach(struct device *parent, struct device *self, void *aux) 129 { 130 struct stic_info *si; 131 struct tc_attach_args *ta; 132 struct pxg_softc *pxg; 133 int console; 134 135 pxg = device_private(self); 136 ta = (struct tc_attach_args *)aux; 137 138 if (ta->ta_addr == stic_consinfo.si_slotbase) { 139 si = &stic_consinfo; 140 console = 1; 141 } else { 142 if (stic_consinfo.si_slotbase == 0) 143 si = &stic_consinfo; 144 else { 145 si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT|M_ZERO); 146 } 147 si->si_slotbase = ta->ta_addr; 148 pxg_init(si); 149 console = 0; 150 } 151 152 pxg->pxg_si = si; 153 si->si_dv = self; 154 tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si); 155 156 printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth, 157 si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10); 158 159 stic_attach(self, si, console); 160 161 #ifdef notyet 162 /* Load the co-processor "firmware". */ 163 for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++) 164 pxg_load_fwseg(si, &pxg_fwsegs[i]); 165 166 /* Start the i860. */ 167 si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1; 168 tc_wmb(); 169 tc_syncbus(); 170 DELAY(40000); 171 #endif 172 } 173 174 void 175 pxg_cnattach(tc_addr_t addr) 176 { 177 struct stic_info *si; 178 179 si = &stic_consinfo; 180 si->si_slotbase = addr; 181 pxg_init(si); 182 stic_cnattach(si); 183 } 184 185 static void 186 pxg_init(struct stic_info *si) 187 { 188 volatile u_int32_t *slot; 189 char *kva; 190 191 kva = (void *)si->si_slotbase; 192 193 si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET); 194 si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET); 195 si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET); 196 si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET); 197 si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET); 198 si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf); 199 si->si_buf_size = pxg_probe_sram(si); 200 si->si_disptype = WSDISPLAY_TYPE_PXG; 201 si->si_sxc = (volatile struct stic_xcomm *)si->si_buf; 202 203 si->si_pbuf_get = pxg_pbuf_get; 204 si->si_pbuf_post = pxg_pbuf_post; 205 si->si_ioctl = pxg_ioctl; 206 207 /* Disable the co-processor. */ 208 slot = (volatile u_int32_t *)kva; 209 slot[PXG_I860_RESET_OFFSET >> 2] = 0; 210 tc_wmb(); 211 slot[PXG_HOST_INTR_OFFSET >> 2] = 0; 212 tc_wmb(); 213 tc_syncbus(); 214 DELAY(40000); 215 216 /* XXX Check for a second PixelStamp. */ 217 if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1) 218 si->si_depth = 24; 219 else 220 si->si_depth = pxg_probe_planes(si); 221 222 stic_init(si); 223 } 224 225 static int 226 pxg_probe_sram(struct stic_info *si) 227 { 228 volatile u_int32_t *a, *b; 229 230 a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2); 231 b = a + (0x20000 >> 2); 232 *a = 4321; 233 *b = 1234; 234 tc_mb(); 235 return ((*a == *b) ? 0x20000 : 0x40000); 236 } 237 238 static int 239 pxg_probe_planes(struct stic_info *si) 240 { 241 volatile u_int32_t *vdac; 242 int id; 243 244 /* 245 * For the visible framebuffer (# 0), we can cheat and use the VDAC 246 * ID. 247 */ 248 vdac = si->si_vdac; 249 vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) | 250 ((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16); 251 vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) | 252 (BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8); 253 tc_mb(); 254 id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff; 255 256 /* 3 VDACs */ 257 if (id == 0x004a4a4a) 258 return (24); 259 260 /* 1 VDAC */ 261 if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 || 262 (id & 0x0000ff) == 0x00004a) 263 return (8); 264 265 /* XXX Assume 8 planes. */ 266 printf("pxg_probe_planes: invalid VDAC ID %x\n", id); 267 return (8); 268 } 269 270 static int 271 pxg_intr(void *cookie) 272 { 273 #ifdef notyet 274 struct stic_info *si; 275 volatile struct stic_regs *sr; 276 volatile u_int32_t *hi; 277 u_int32_t state; 278 int it; 279 280 si = cookie; 281 sr = si->si_stic; 282 state = sr->sr_ipdvint; 283 hi = (volatile u_int32_t *)si->si_slotbase + 284 (PXG_HOST_INTR_OFFSET / sizeof(u_int32_t)); 285 286 /* Clear the interrupt condition */ 287 it = hi[0] & 15; 288 hi[0] = 0; 289 tc_wmb(); 290 hi[2] = 0; 291 tc_wmb(); 292 293 switch (it) { 294 case 3: 295 sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN; 296 tc_wmb(); 297 stic_flush(si); 298 break; 299 } 300 #else 301 printf("pxg_intr: how did this happen?\n"); 302 #endif 303 return (1); 304 } 305 306 static uint32_t * 307 pxg_pbuf_get(struct stic_info *si) 308 { 309 u_long off; 310 311 si->si_pbuf_select ^= STIC_PACKET_SIZE; 312 off = si->si_pbuf_select + STIC_XCOMM_SIZE; 313 return ((u_int32_t *)((char *)si->si_buf + off)); 314 } 315 316 static int 317 pxg_pbuf_post(struct stic_info *si, u_int32_t *buf) 318 { 319 volatile u_int32_t *poll, junk; 320 volatile struct stic_regs *sr; 321 u_long v; 322 int c; 323 324 sr = si->si_stic; 325 326 /* Get address of poll register for this buffer. */ 327 v = ((u_long)buf - (u_long)si->si_buf) >> 9; 328 poll = (volatile u_int32_t *)((char *)si->si_slotbase + v); 329 330 /* 331 * Read the poll register and make sure the stamp wants to accept 332 * our packet. This read will initiate the DMA. Don't wait for 333 * ever, just in case something's wrong. 334 */ 335 tc_mb(); 336 337 for (c = STAMP_RETRIES; c != 0; c--) { 338 if ((sr->sr_ipdvint & STIC_INT_P) != 0) { 339 sr->sr_ipdvint = STIC_INT_P_WE; 340 tc_wmb(); 341 junk = *poll; 342 return (0); 343 } 344 DELAY(STAMP_DELAY); 345 } 346 347 /* STIC has lost the plot, punish it. */ 348 stic_reset(si); 349 return (-1); 350 } 351 352 static int 353 pxg_ioctl(struct stic_info *si, u_long cmd, void *data, int flag, 354 struct lwp *l) 355 { 356 struct stic_xinfo *sxi; 357 volatile u_int32_t *ptr = NULL; 358 int rv, s; 359 360 switch (cmd) { 361 case STICIO_START860: 362 case STICIO_RESET860: 363 if ((rv = kauth_authorize_generic(l->l_cred, 364 KAUTH_GENERIC_ISSUSER, NULL)) != 0) 365 return (rv); 366 if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED) 367 return (EBUSY); 368 ptr = (volatile u_int32_t *)si->si_slotbase; 369 break; 370 } 371 372 switch (cmd) { 373 case STICIO_START860: 374 s = spltty(); 375 ptr[PXG_I860_START_OFFSET >> 2] = 1; 376 tc_wmb(); 377 splx(s); 378 rv = 0; 379 break; 380 381 case STICIO_RESET860: 382 s = spltty(); 383 ptr[PXG_I860_RESET_OFFSET >> 2] = 0; 384 tc_wmb(); 385 splx(s); 386 rv = 0; 387 break; 388 389 case STICIO_GXINFO: 390 sxi = (struct stic_xinfo *)data; 391 sxi->sxi_unit = si->si_unit; 392 sxi->sxi_stampw = si->si_stampw; 393 sxi->sxi_stamph = si->si_stamph; 394 sxi->sxi_buf_size = si->si_buf_size; 395 sxi->sxi_buf_phys = 0; 396 sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE; 397 sxi->sxi_buf_pktcnt = 2; 398 sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2; 399 rv = 0; 400 break; 401 402 default: 403 rv = EPASSTHROUGH; 404 break; 405 } 406 407 return (rv); 408 } 409 410 #ifdef notyet 411 void 412 pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs) 413 { 414 const u_int32_t *src; 415 u_int32_t *dst; 416 u_int left, i; 417 418 dst = (u_int32_t *)((void *)si->si_buf + pfs->pfs_addr); 419 src = pfs->pfs_data; 420 421 for (left = pfs->pfs_compsize; left != 0; left -= 4) { 422 if (src[0] == PXGFW_RLE_MAGIC) { 423 for (i = src[2]; i != 0; i--) 424 *dst++ = src[1]; 425 src += 3; 426 } else { 427 *dst++ = src[0]; 428 src++; 429 } 430 } 431 432 if (src == NULL) 433 memset(dst, 0, pfs->pfs_realsize); 434 } 435 #endif 436