1 /* $NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $"); 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/device.h> 75 #include <sys/buf.h> 76 77 #include <dev/scsipi/scsi_all.h> 78 #include <dev/scsipi/scsipi_all.h> 79 #include <dev/scsipi/scsiconf.h> 80 81 #include <dev/ic/ncr53c9xreg.h> 82 #include <dev/ic/ncr53c9xvar.h> 83 84 #include <machine/bus.h> 85 86 #include <dev/tc/tcvar.h> 87 #include <dev/tc/tcdsreg.h> 88 #include <dev/tc/tcdsvar.h> 89 90 struct asc_softc { 91 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 92 bus_space_tag_t sc_bst; /* bus space tag */ 93 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 94 bus_dma_tag_t sc_dmat; /* bus dma tag */ 95 bus_dmamap_t sc_dmamap; /* bus dmamap */ 96 caddr_t *sc_dmaaddr; 97 size_t *sc_dmalen; 98 size_t sc_dmasize; 99 unsigned sc_flags; 100 #define ASC_ISPULLUP 0x01 101 #define ASC_DMAACTIVE 0x02 102 #define ASC_MAPLOADED 0x04 103 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 104 }; 105 106 static int asc_tcds_match __P((struct device *, struct cfdata *, void *)); 107 static void asc_tcds_attach __P((struct device *, struct device *, void *)); 108 109 /* Linkup to the rest of the kernel */ 110 struct cfattach asc_tcds_ca = { 111 sizeof(struct asc_softc), asc_tcds_match, asc_tcds_attach 112 }; 113 114 /* 115 * Functions and the switch for the MI code. 116 */ 117 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 118 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 119 static int tcds_dma_isintr __P((struct ncr53c9x_softc *)); 120 static void tcds_dma_reset __P((struct ncr53c9x_softc *)); 121 static int tcds_dma_intr __P((struct ncr53c9x_softc *)); 122 static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 123 size_t *, int, size_t *)); 124 static void tcds_dma_go __P((struct ncr53c9x_softc *)); 125 static void tcds_dma_stop __P((struct ncr53c9x_softc *)); 126 static int tcds_dma_isactive __P((struct ncr53c9x_softc *)); 127 static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *)); 128 129 static struct ncr53c9x_glue asc_tcds_glue = { 130 asc_read_reg, 131 asc_write_reg, 132 tcds_dma_isintr, 133 tcds_dma_reset, 134 tcds_dma_intr, 135 tcds_dma_setup, 136 tcds_dma_go, 137 tcds_dma_stop, 138 tcds_dma_isactive, 139 tcds_clear_latched_intr, 140 }; 141 142 static int 143 asc_tcds_match(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 149 /* We always exist. */ 150 return 1; 151 } 152 153 #define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) 154 155 /* 156 * Attach this instance, and then all the sub-devices 157 */ 158 static void 159 asc_tcds_attach(parent, self, aux) 160 struct device *parent, *self; 161 void *aux; 162 { 163 struct tcdsdev_attach_args *tcdsdev = aux; 164 struct asc_softc *asc = (struct asc_softc *)self; 165 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 166 int error; 167 168 /* 169 * Set up glue for MI code early; we use some of it here. 170 */ 171 sc->sc_glue = &asc_tcds_glue; 172 173 asc->sc_bst = tcdsdev->tcdsda_bst; 174 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 175 asc->sc_tcds = tcdsdev->tcdsda_sc; 176 177 /* 178 * The TCDS ASIC cannot DMA across 8k boundaries, and this 179 * driver is written such that each DMA segment gets a new 180 * call to tcds_dma_setup(). Thus, the DMA map only needs 181 * to support 8k transfers. 182 */ 183 asc->sc_dmat = tcdsdev->tcdsda_dmat; 184 if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG, 185 NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 186 printf("failed to create dma map, error = %d\n", error); 187 } 188 189 sc->sc_id = tcdsdev->tcdsda_id; 190 sc->sc_freq = tcdsdev->tcdsda_freq; 191 192 /* gimme Mhz */ 193 sc->sc_freq /= 1000000; 194 195 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 196 197 /* 198 * XXX More of this should be in ncr53c9x_attach(), but 199 * XXX should we really poke around the chip that much in 200 * XXX the MI code? Think about this more... 201 */ 202 203 /* 204 * Set up static configuration info. 205 */ 206 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 207 sc->sc_cfg2 = NCRCFG2_SCSI2; 208 sc->sc_cfg3 = NCRCFG3_CDB; 209 if (sc->sc_freq > 25) 210 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 211 sc->sc_rev = tcdsdev->tcdsda_variant; 212 if (tcdsdev->tcdsda_fast) { 213 sc->sc_features |= NCR_F_FASTSCSI; 214 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 215 } 216 217 /* 218 * XXX minsync and maxxfer _should_ be set up in MI code, 219 * XXX but it appears to have some dependency on what sort 220 * XXX of DMA we're hooked up to, etc. 221 */ 222 223 /* 224 * This is the value used to start sync negotiations 225 * Note that the NCR register "SYNCTP" is programmed 226 * in "clocks per byte", and has a minimum value of 4. 227 * The SCSI period used in negotiation is one-fourth 228 * of the time (in nanoseconds) needed to transfer one byte. 229 * Since the chip's clock is given in MHz, we have the following 230 * formula: 4 * period = (1000 / freq) * 4 231 */ 232 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 233 234 sc->sc_maxxfer = 64 * 1024; 235 236 /* Do the common parts of attachment. */ 237 sc->sc_adapter.adapt_minphys = minphys; 238 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 239 ncr53c9x_attach(sc); 240 } 241 242 static void 243 tcds_dma_reset(sc) 244 struct ncr53c9x_softc *sc; 245 { 246 struct asc_softc *asc = (struct asc_softc *)sc; 247 248 /* TCDS SCSI disable/reset/enable. */ 249 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 250 251 if (asc->sc_flags & ASC_MAPLOADED) 252 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 253 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 254 } 255 256 /* 257 * start a dma transfer or keep it going 258 */ 259 int 260 tcds_dma_setup(sc, addr, len, ispullup, dmasize) 261 struct ncr53c9x_softc *sc; 262 caddr_t *addr; 263 size_t *len, *dmasize; 264 int ispullup; /* DMA into main memory */ 265 { 266 struct asc_softc *asc = (struct asc_softc *)sc; 267 struct tcds_slotconfig *tcds = asc->sc_tcds; 268 size_t size; 269 u_int32_t dic; 270 271 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 272 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 273 (ispullup) ? "IN" : "OUT")); 274 275 /* 276 * the rules say we cannot transfer more than the limit 277 * of this DMA chip (64k) and we cannot cross a 8k boundary. 278 */ 279 size = min(*dmasize, DMAMAX((size_t)*addr)); 280 asc->sc_dmaaddr = addr; 281 asc->sc_dmalen = len; 282 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 283 *dmasize = asc->sc_dmasize = size; 284 285 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 286 287 if (size == 0) 288 return 0; 289 290 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 291 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 292 /* 293 * XXX Should return an error, here, but the upper-layer 294 * XXX doesn't check the return value! 295 */ 296 panic("tcds_dma_setup: dmamap load failed"); 297 } 298 299 /* synchronize dmamap contents with memory image */ 300 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 301 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 302 303 /* load address, set/clear unaligned transfer and read/write bits. */ 304 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 305 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 306 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 307 dic &= ~TCDS_DIC_ADDRMASK; 308 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 309 if (ispullup) 310 dic |= TCDS_DIC_WRITE; 311 else 312 dic &= ~TCDS_DIC_WRITE; 313 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 314 315 asc->sc_flags |= ASC_MAPLOADED; 316 return 0; 317 } 318 319 static void 320 tcds_dma_go(sc) 321 struct ncr53c9x_softc *sc; 322 { 323 struct asc_softc *asc = (struct asc_softc *)sc; 324 325 /* mark unit as DMA-active */ 326 asc->sc_flags |= ASC_DMAACTIVE; 327 328 /* start DMA */ 329 tcds_dma_enable(asc->sc_tcds, 1); 330 } 331 332 static void 333 tcds_dma_stop(sc) 334 struct ncr53c9x_softc *sc; 335 { 336 #if 0 337 struct asc_softc *asc = (struct asc_softc *)sc; 338 #endif 339 340 /* 341 * XXX STOP DMA HERE! 342 */ 343 } 344 345 /* 346 * Pseudo (chained) interrupt from the asc driver to kick the 347 * current running DMA transfer. Called from ncr53c9x_intr() 348 * for now. 349 * 350 * return 1 if it was a DMA continue. 351 */ 352 static int 353 tcds_dma_intr(sc) 354 struct ncr53c9x_softc *sc; 355 { 356 struct asc_softc *asc = (struct asc_softc *)sc; 357 struct tcds_slotconfig *tcds = asc->sc_tcds; 358 int trans, resid; 359 u_int32_t tcl, tcm; 360 u_int32_t dud, dudmask, *addr; 361 bus_addr_t pa; 362 363 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 364 365 if (tcds_scsi_iserr(tcds)) 366 return 0; 367 368 /* This is an "assertion" :) */ 369 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 370 panic("tcds_dma_intr: DMA wasn't active"); 371 372 /* DMA has stopped */ 373 tcds_dma_enable(tcds, 0); 374 asc->sc_flags &= ~ASC_DMAACTIVE; 375 376 if (asc->sc_dmasize == 0) { 377 /* A "Transfer Pad" operation completed */ 378 tcl = NCR_READ_REG(sc, NCR_TCL); 379 tcm = NCR_READ_REG(sc, NCR_TCM); 380 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 381 tcl | (tcm << 8), tcl, tcm)); 382 return 0; 383 } 384 385 resid = 0; 386 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 387 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 388 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 389 DELAY(1); 390 } 391 392 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 393 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 394 395 trans = asc->sc_dmasize - resid; 396 if (trans < 0) { /* transferred < 0 ? */ 397 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 398 tcds->sc_slot, trans, (int)asc->sc_dmasize); 399 trans = asc->sc_dmasize; 400 } 401 402 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 403 tcl, tcm, trans, resid)); 404 405 *asc->sc_dmalen -= trans; 406 *asc->sc_dmaaddr += trans; 407 408 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 409 0, asc->sc_dmamap->dm_mapsize, 410 (sc->sc_flags & ASC_ISPULLUP) 411 ? BUS_DMASYNC_POSTREAD 412 : BUS_DMASYNC_POSTWRITE); 413 414 /* 415 * Clean up unaligned DMAs into main memory. 416 */ 417 if (asc->sc_flags & ASC_ISPULLUP) { 418 /* Handle unaligned starting address, length. */ 419 dud = bus_space_read_4(tcds->sc_bst, 420 tcds->sc_bsh, tcds->sc_dud0); 421 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 422 addr = (u_int32_t *) 423 ((paddr_t)*asc->sc_dmaaddr & ~0x3); 424 dudmask = 0; 425 if (dud & TCDS_DUD0_VALID00) 426 panic("tcds_dma: dud0 byte 0 valid"); 427 if (dud & TCDS_DUD0_VALID01) 428 dudmask |= TCDS_DUD_BYTE01; 429 if (dud & TCDS_DUD0_VALID10) 430 dudmask |= TCDS_DUD_BYTE10; 431 #ifdef DIAGNOSTIC 432 if (dud & TCDS_DUD0_VALID11) 433 dudmask |= TCDS_DUD_BYTE11; 434 #endif 435 NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", 436 addr, dudmask)); 437 *addr = (*addr & ~dudmask) | (dud & dudmask); 438 } 439 dud = bus_space_read_4(tcds->sc_bst, 440 tcds->sc_bsh, tcds->sc_dud1); 441 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 442 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 443 tcds->sc_sda) << 2; 444 dudmask = 0; 445 if (dud & TCDS_DUD1_VALID00) 446 dudmask |= TCDS_DUD_BYTE00; 447 if (dud & TCDS_DUD1_VALID01) 448 dudmask |= TCDS_DUD_BYTE01; 449 if (dud & TCDS_DUD1_VALID10) 450 dudmask |= TCDS_DUD_BYTE10; 451 #ifdef DIAGNOSTIC 452 if (dud & TCDS_DUD1_VALID11) 453 panic("tcds_dma: dud1 byte 3 valid"); 454 #endif 455 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 456 pa, dudmask)); 457 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 458 #if defined(__alpha__) 459 addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); 460 #elif defined(__mips__) 461 addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); 462 #else 463 #error TURBOchannel only exists on DECs, folks... 464 #endif 465 *addr = (*addr & ~dudmask) | (dud & dudmask); 466 } 467 /* XXX deal with saved residual byte? */ 468 } 469 470 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 471 asc->sc_flags &= ~ASC_MAPLOADED; 472 473 return 0; 474 } 475 476 /* 477 * Glue functions. 478 */ 479 static u_char 480 asc_read_reg(sc, reg) 481 struct ncr53c9x_softc *sc; 482 int reg; 483 { 484 struct asc_softc *asc = (struct asc_softc *)sc; 485 u_int32_t v; 486 487 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 488 reg * sizeof(u_int32_t)); 489 490 return v & 0xff; 491 } 492 493 static void 494 asc_write_reg(sc, reg, val) 495 struct ncr53c9x_softc *sc; 496 int reg; 497 u_char val; 498 { 499 struct asc_softc *asc = (struct asc_softc *)sc; 500 501 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 502 reg * sizeof(u_int32_t), val); 503 } 504 505 static int 506 tcds_dma_isintr(sc) 507 struct ncr53c9x_softc *sc; 508 { 509 struct asc_softc *asc = (struct asc_softc *)sc; 510 int x; 511 512 x = tcds_scsi_isintr(asc->sc_tcds, 1); 513 514 /* XXX */ 515 return x; 516 } 517 518 static int 519 tcds_dma_isactive(sc) 520 struct ncr53c9x_softc *sc; 521 { 522 struct asc_softc *asc = (struct asc_softc *)sc; 523 524 return !!(asc->sc_flags & ASC_DMAACTIVE); 525 } 526 527 static void 528 tcds_clear_latched_intr(sc) 529 struct ncr53c9x_softc *sc; 530 { 531 struct asc_softc *asc = (struct asc_softc *)sc; 532 533 /* Clear the TCDS interrupt bit. */ 534 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 535 } 536