1 /* $NetBSD: sdmmc_mem.c,v 1.34 2015/02/27 16:08:17 nonaka Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka@netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.34 2015/02/27 16:08:17 nonaka Exp $"); 49 50 #ifdef _KERNEL_OPT 51 #include "opt_sdmmc.h" 52 #endif 53 54 #include <sys/param.h> 55 #include <sys/kernel.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 60 #include <dev/sdmmc/sdmmcchip.h> 61 #include <dev/sdmmc/sdmmcreg.h> 62 #include <dev/sdmmc/sdmmcvar.h> 63 64 #ifdef SDMMC_DEBUG 65 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 66 #else 67 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 68 #endif 69 70 typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t; 71 72 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 73 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 75 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 76 sdmmc_response *); 77 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 78 uint32_t *scr); 79 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 80 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 81 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 82 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, sdmmc_bitfield512_t *); 83 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 84 uint8_t); 85 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 86 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 89 u_char *, size_t); 90 static int sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *, 91 uint32_t, u_char *, size_t); 92 static int sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *, 93 uint32_t, u_char *, size_t); 94 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, bus_dmamap_t, 95 uint32_t, u_char *, size_t); 96 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 97 uint32_t, u_char *, size_t); 98 99 /* 100 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 101 */ 102 int 103 sdmmc_mem_enable(struct sdmmc_softc *sc) 104 { 105 uint32_t host_ocr; 106 uint32_t card_ocr; 107 uint32_t ocr = 0; 108 int error; 109 110 SDMMC_LOCK(sc); 111 112 /* Set host mode to SD "combo" card or SD memory-only. */ 113 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 114 115 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 116 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 117 118 /* Reset memory (*must* do that before CMD55 or CMD1). */ 119 sdmmc_go_idle_state(sc); 120 121 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 122 /* Check SD Ver.2 */ 123 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 124 if (error == 0 && card_ocr == 0x1aa) 125 SET(ocr, MMC_OCR_HCS); 126 } 127 128 /* 129 * Read the SD/MMC memory OCR value by issuing CMD55 followed 130 * by ACMD41 to read the OCR value from memory-only SD cards. 131 * MMC cards will not respond to CMD55 or ACMD41 and this is 132 * how we distinguish them from SD cards. 133 */ 134 mmc_mode: 135 error = sdmmc_mem_send_op_cond(sc, 136 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 137 if (error) { 138 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 139 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 140 /* Not a SD card, switch to MMC mode. */ 141 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 142 CLR(sc->sc_flags, SMF_SD_MODE); 143 goto mmc_mode; 144 } 145 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 146 DPRINTF(("%s: couldn't read memory OCR\n", 147 SDMMCDEVNAME(sc))); 148 goto out; 149 } else { 150 /* Not a "combo" card. */ 151 CLR(sc->sc_flags, SMF_MEM_MODE); 152 error = 0; 153 goto out; 154 } 155 } 156 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 157 /* get card OCR */ 158 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 159 if (error) { 160 DPRINTF(("%s: couldn't read SPI memory OCR\n", 161 SDMMCDEVNAME(sc))); 162 goto out; 163 } 164 } 165 166 /* Set the lowest voltage supported by the card and host. */ 167 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 168 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 169 if (error) { 170 DPRINTF(("%s: couldn't supply voltage requested by card\n", 171 SDMMCDEVNAME(sc))); 172 goto out; 173 } 174 175 /* Tell the card(s) to enter the idle state (again). */ 176 sdmmc_go_idle_state(sc); 177 178 DPRINTF(("%s: host_ocr 0x%08x\n", SDMMCDEVNAME(sc), host_ocr)); 179 DPRINTF(("%s: card_ocr 0x%08x\n", SDMMCDEVNAME(sc), card_ocr)); 180 181 host_ocr &= card_ocr; /* only allow the common voltages */ 182 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 183 /* Check SD Ver.2 */ 184 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 185 if (error == 0 && card_ocr == 0x1aa) 186 SET(ocr, MMC_OCR_HCS); 187 } 188 host_ocr |= ocr; 189 190 /* Send the new OCR value until all cards are ready. */ 191 error = sdmmc_mem_send_op_cond(sc, host_ocr, NULL); 192 if (error) { 193 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 194 goto out; 195 } 196 197 out: 198 SDMMC_UNLOCK(sc); 199 200 return error; 201 } 202 203 /* 204 * Read the CSD and CID from all cards and assign each card a unique 205 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 206 */ 207 void 208 sdmmc_mem_scan(struct sdmmc_softc *sc) 209 { 210 sdmmc_response resp; 211 struct sdmmc_function *sf; 212 uint16_t next_rca; 213 int error; 214 int retry; 215 216 SDMMC_LOCK(sc); 217 218 /* 219 * CMD2 is a broadcast command understood by SD cards and MMC 220 * cards. All cards begin to respond to the command, but back 221 * off if another card drives the CMD line to a different level. 222 * Only one card will get its entire response through. That 223 * card remains silent once it has been assigned a RCA. 224 */ 225 for (retry = 0; retry < 100; retry++) { 226 error = sdmmc_mem_send_cid(sc, &resp); 227 if (error) { 228 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 229 error == ETIMEDOUT) { 230 /* No more cards there. */ 231 break; 232 } 233 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 234 break; 235 } 236 237 /* In MMC mode, find the next available RCA. */ 238 next_rca = 1; 239 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 240 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 241 next_rca++; 242 } 243 244 /* Allocate a sdmmc_function structure. */ 245 sf = sdmmc_function_alloc(sc); 246 sf->rca = next_rca; 247 248 /* 249 * Remember the CID returned in the CMD2 response for 250 * later decoding. 251 */ 252 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 253 254 /* 255 * Silence the card by assigning it a unique RCA, or 256 * querying it for its RCA in the case of SD. 257 */ 258 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 259 if (sdmmc_set_relative_addr(sc, sf) != 0) { 260 aprint_error_dev(sc->sc_dev, 261 "couldn't set mem RCA\n"); 262 sdmmc_function_free(sf); 263 break; 264 } 265 } 266 267 /* 268 * If this is a memory-only card, the card responding 269 * first becomes an alias for SDIO function 0. 270 */ 271 if (sc->sc_fn0 == NULL) 272 sc->sc_fn0 = sf; 273 274 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 275 276 /* only one function in SPI mode */ 277 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 278 break; 279 } 280 281 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 282 /* Go to Data Transfer Mode, if possible. */ 283 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 284 285 /* 286 * All cards are either inactive or awaiting further commands. 287 * Read the CSDs and decode the raw CID for each card. 288 */ 289 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 290 error = sdmmc_mem_send_csd(sc, sf, &resp); 291 if (error) { 292 SET(sf->flags, SFF_ERROR); 293 continue; 294 } 295 296 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 297 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 298 SET(sf->flags, SFF_ERROR); 299 continue; 300 } 301 302 #ifdef SDMMC_DEBUG 303 printf("%s: CID: ", SDMMCDEVNAME(sc)); 304 sdmmc_print_cid(&sf->cid); 305 #endif 306 } 307 308 SDMMC_UNLOCK(sc); 309 } 310 311 int 312 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 313 struct sdmmc_function *sf) 314 { 315 /* TRAN_SPEED(2:0): transfer rate exponent */ 316 static const int speed_exponent[8] = { 317 100 * 1, /* 100 Kbits/s */ 318 1 * 1000, /* 1 Mbits/s */ 319 10 * 1000, /* 10 Mbits/s */ 320 100 * 1000, /* 100 Mbits/s */ 321 0, 322 0, 323 0, 324 0, 325 }; 326 /* TRAN_SPEED(6:3): time mantissa */ 327 static const int speed_mantissa[16] = { 328 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 329 }; 330 struct sdmmc_csd *csd = &sf->csd; 331 int e, m; 332 333 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 334 /* 335 * CSD version 1.0 corresponds to SD system 336 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 337 */ 338 csd->csdver = SD_CSD_CSDVER(resp); 339 switch (csd->csdver) { 340 case SD_CSD_CSDVER_2_0: 341 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 342 SET(sf->flags, SFF_SDHC); 343 csd->capacity = SD_CSD_V2_CAPACITY(resp); 344 csd->read_bl_len = SD_CSD_V2_BL_LEN; 345 break; 346 347 case SD_CSD_CSDVER_1_0: 348 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 349 csd->capacity = SD_CSD_CAPACITY(resp); 350 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 351 break; 352 353 default: 354 aprint_error_dev(sc->sc_dev, 355 "unknown SD CSD structure version 0x%x\n", 356 csd->csdver); 357 return 1; 358 } 359 360 csd->mmcver = SD_CSD_MMCVER(resp); 361 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 362 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 363 e = SD_CSD_SPEED_EXP(resp); 364 m = SD_CSD_SPEED_MANT(resp); 365 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 366 csd->ccc = SD_CSD_CCC(resp); 367 } else { 368 csd->csdver = MMC_CSD_CSDVER(resp); 369 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 370 aprint_error_dev(sc->sc_dev, 371 "unknown MMC CSD structure version 0x%x\n", 372 csd->csdver); 373 return 1; 374 } 375 376 csd->mmcver = MMC_CSD_MMCVER(resp); 377 csd->capacity = MMC_CSD_CAPACITY(resp); 378 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 379 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 380 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 381 e = MMC_CSD_TRAN_SPEED_EXP(resp); 382 m = MMC_CSD_TRAN_SPEED_MANT(resp); 383 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 384 } 385 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 386 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 387 388 #ifdef SDMMC_DUMP_CSD 389 sdmmc_print_csd(resp, csd); 390 #endif 391 392 return 0; 393 } 394 395 int 396 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 397 struct sdmmc_function *sf) 398 { 399 struct sdmmc_cid *cid = &sf->cid; 400 401 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 402 cid->mid = SD_CID_MID(resp); 403 cid->oid = SD_CID_OID(resp); 404 SD_CID_PNM_CPY(resp, cid->pnm); 405 cid->rev = SD_CID_REV(resp); 406 cid->psn = SD_CID_PSN(resp); 407 cid->mdt = SD_CID_MDT(resp); 408 } else { 409 switch(sf->csd.mmcver) { 410 case MMC_CSD_MMCVER_1_0: 411 case MMC_CSD_MMCVER_1_4: 412 cid->mid = MMC_CID_MID_V1(resp); 413 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 414 cid->rev = MMC_CID_REV_V1(resp); 415 cid->psn = MMC_CID_PSN_V1(resp); 416 cid->mdt = MMC_CID_MDT_V1(resp); 417 break; 418 case MMC_CSD_MMCVER_2_0: 419 case MMC_CSD_MMCVER_3_1: 420 case MMC_CSD_MMCVER_4_0: 421 cid->mid = MMC_CID_MID_V2(resp); 422 cid->oid = MMC_CID_OID_V2(resp); 423 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 424 cid->psn = MMC_CID_PSN_V2(resp); 425 break; 426 default: 427 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 428 sf->csd.mmcver); 429 return 1; 430 } 431 } 432 return 0; 433 } 434 435 void 436 sdmmc_print_cid(struct sdmmc_cid *cid) 437 { 438 439 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 440 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 441 cid->mdt); 442 } 443 444 #ifdef SDMMC_DUMP_CSD 445 void 446 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 447 { 448 449 printf("csdver = %d\n", csd->csdver); 450 printf("mmcver = %d\n", csd->mmcver); 451 printf("capacity = 0x%08x\n", csd->capacity); 452 printf("read_bl_len = %d\n", csd->read_bl_len); 453 printf("write_bl_len = %d\n", csd->write_bl_len); 454 printf("r2w_factor = %d\n", csd->r2w_factor); 455 printf("tran_speed = %d\n", csd->tran_speed); 456 printf("ccc = 0x%x\n", csd->ccc); 457 } 458 #endif 459 460 /* 461 * Initialize a SD/MMC memory card. 462 */ 463 int 464 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 465 { 466 int error = 0; 467 468 SDMMC_LOCK(sc); 469 470 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 471 error = sdmmc_select_card(sc, sf); 472 if (error) 473 goto out; 474 } 475 476 error = sdmmc_mem_set_blocklen(sc, sf, SDMMC_SECTOR_SIZE); 477 if (error) 478 goto out; 479 480 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 481 error = sdmmc_mem_sd_init(sc, sf); 482 else 483 error = sdmmc_mem_mmc_init(sc, sf); 484 485 out: 486 SDMMC_UNLOCK(sc); 487 488 return error; 489 } 490 491 /* 492 * Get or set the card's memory OCR value (SD or MMC). 493 */ 494 int 495 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 496 { 497 struct sdmmc_command cmd; 498 int error; 499 int retry; 500 501 /* Don't lock */ 502 503 DPRINTF(("%s: sdmmc_mem_send_op_cond: ocr=%#x\n", 504 SDMMCDEVNAME(sc), ocr)); 505 506 /* 507 * If we change the OCR value, retry the command until the OCR 508 * we receive in response has the "CARD BUSY" bit set, meaning 509 * that all cards are ready for identification. 510 */ 511 for (retry = 0; retry < 100; retry++) { 512 memset(&cmd, 0, sizeof(cmd)); 513 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 514 ocr : (ocr & MMC_OCR_HCS); 515 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 516 517 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 518 cmd.c_opcode = SD_APP_OP_COND; 519 error = sdmmc_app_command(sc, NULL, &cmd); 520 } else { 521 cmd.c_opcode = MMC_SEND_OP_COND; 522 error = sdmmc_mmc_command(sc, &cmd); 523 } 524 if (error) 525 break; 526 527 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 528 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 529 break; 530 } else { 531 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 532 ocr == 0) 533 break; 534 } 535 536 error = ETIMEDOUT; 537 sdmmc_delay(10000); 538 } 539 if (error == 0 && 540 ocrp != NULL && 541 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 542 *ocrp = MMC_R3(cmd.c_resp); 543 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 544 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 545 return error; 546 } 547 548 int 549 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 550 { 551 struct sdmmc_command cmd; 552 int error; 553 554 /* Don't lock */ 555 556 memset(&cmd, 0, sizeof(cmd)); 557 cmd.c_arg = ocr; 558 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 559 cmd.c_opcode = SD_SEND_IF_COND; 560 561 error = sdmmc_mmc_command(sc, &cmd); 562 if (error == 0 && ocrp != NULL) { 563 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 564 *ocrp = MMC_SPI_R7(cmd.c_resp); 565 } else { 566 *ocrp = MMC_R7(cmd.c_resp); 567 } 568 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 569 SDMMCDEVNAME(sc), error, *ocrp)); 570 } 571 return error; 572 } 573 574 /* 575 * Set the read block length appropriately for this card, according to 576 * the card CSD register value. 577 */ 578 int 579 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf, 580 int block_len) 581 { 582 struct sdmmc_command cmd; 583 int error; 584 585 /* Don't lock */ 586 587 memset(&cmd, 0, sizeof(cmd)); 588 cmd.c_opcode = MMC_SET_BLOCKLEN; 589 cmd.c_arg = block_len; 590 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 591 592 error = sdmmc_mmc_command(sc, &cmd); 593 594 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 595 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, block_len)); 596 597 return error; 598 } 599 600 /* make 512-bit BE quantity __bitfield()-compatible */ 601 static void 602 sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 603 size_t i; 604 uint32_t tmp0, tmp1; 605 const size_t bitswords = __arraycount(buf->_bits); 606 for (i = 0; i < bitswords/2; i++) { 607 tmp0 = buf->_bits[i]; 608 tmp1 = buf->_bits[bitswords - 1 - i]; 609 buf->_bits[i] = be32toh(tmp1); 610 buf->_bits[bitswords - 1 - i] = be32toh(tmp0); 611 } 612 } 613 614 static int 615 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 616 { 617 static const struct { 618 int v; 619 int freq; 620 } switch_group0_functions[] = { 621 /* Default/SDR12 */ 622 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 623 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000 }, 624 625 /* High-Speed/SDR25 */ 626 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 627 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000 }, 628 629 /* SDR50 */ 630 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000 }, 631 632 /* SDR104 */ 633 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000 }, 634 635 /* DDR50 */ 636 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000 }, 637 }; 638 int host_ocr, support_func, best_func, bus_clock, error, g, i; 639 sdmmc_bitfield512_t status; /* Switch Function Status */ 640 641 /* change bus clock */ 642 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 643 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 644 if (error) { 645 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 646 return error; 647 } 648 649 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 650 if (error) { 651 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 652 return error; 653 } 654 error = sdmmc_mem_decode_scr(sc, sf); 655 if (error) 656 return error; 657 658 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 659 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 660 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 661 error = sdmmc_set_bus_width(sf, 4); 662 if (error) { 663 aprint_error_dev(sc->sc_dev, 664 "can't change bus width (%d bit)\n", 4); 665 return error; 666 } 667 sf->width = 4; 668 } 669 670 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 671 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 672 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 673 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 674 if (error) { 675 aprint_error_dev(sc->sc_dev, 676 "switch func mode 0 failed\n"); 677 return error; 678 } 679 680 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 681 support_func = SFUNC_STATUS_GROUP(&status, 1); 682 best_func = 0; 683 for (i = 0, g = 1; 684 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 685 if (!(switch_group0_functions[i].v & host_ocr)) 686 continue; 687 if (g & support_func) 688 best_func = i; 689 } 690 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 691 best_func != 0) { 692 DPRINTF(("%s: switch func mode 1(func=%d)\n", 693 SDMMCDEVNAME(sc), best_func)); 694 error = 695 sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 696 if (error) { 697 aprint_error_dev(sc->sc_dev, 698 "switch func mode 1 failed:" 699 " group 1 function %d(0x%2x)\n", 700 best_func, support_func); 701 return error; 702 } 703 sf->csd.tran_speed = 704 switch_group0_functions[best_func].freq; 705 706 /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 707 delay(25); 708 } 709 } 710 711 /* update bus clock */ 712 if (sc->sc_busclk > sf->csd.tran_speed) 713 sc->sc_busclk = sf->csd.tran_speed; 714 if (sc->sc_busclk == bus_clock) 715 return 0; 716 717 /* change bus clock */ 718 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 719 if (error) { 720 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 721 return error; 722 } 723 724 return 0; 725 } 726 727 static int 728 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 729 { 730 int width, value, hs_timing, bus_clock, error; 731 char ext_csd[512]; 732 uint32_t sectors = 0; 733 734 /* change bus clock */ 735 bus_clock = min(sc->sc_busclk, sf->csd.tran_speed); 736 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, bus_clock); 737 if (error) { 738 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 739 return error; 740 } 741 742 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 743 error = sdmmc_mem_send_cxd_data(sc, 744 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 745 if (error) { 746 aprint_error_dev(sc->sc_dev, 747 "can't read EXT_CSD (error=%d)\n", error); 748 return error; 749 } 750 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 751 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 752 aprint_error_dev(sc->sc_dev, 753 "unrecognised future version (%d)\n", 754 ext_csd[EXT_CSD_STRUCTURE]); 755 return ENOTSUP; 756 } 757 758 if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_52M) { 759 sf->csd.tran_speed = 52000; /* 52MHz */ 760 hs_timing = 1; 761 } else if (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_F_26M) { 762 sf->csd.tran_speed = 26000; /* 26MHz */ 763 hs_timing = 0; 764 } else { 765 aprint_error_dev(sc->sc_dev, 766 "unknown CARD_TYPE: 0x%x\n", 767 ext_csd[EXT_CSD_CARD_TYPE]); 768 return ENOTSUP; 769 } 770 771 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 772 hs_timing = 0; 773 } 774 if (hs_timing) { 775 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 776 EXT_CSD_HS_TIMING, hs_timing); 777 if (error) { 778 aprint_error_dev(sc->sc_dev, 779 "can't change high speed\n"); 780 return error; 781 } 782 } 783 784 if (sc->sc_busclk > sf->csd.tran_speed) 785 sc->sc_busclk = sf->csd.tran_speed; 786 if (sc->sc_busclk != bus_clock) { 787 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 788 sc->sc_busclk); 789 if (error) { 790 aprint_error_dev(sc->sc_dev, 791 "can't change bus clock\n"); 792 return error; 793 } 794 } 795 796 if (hs_timing) { 797 error = sdmmc_mem_send_cxd_data(sc, 798 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 799 if (error) { 800 aprint_error_dev(sc->sc_dev, 801 "can't re-read EXT_CSD\n"); 802 return error; 803 } 804 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 805 aprint_error_dev(sc->sc_dev, 806 "HS_TIMING set failed\n"); 807 return EINVAL; 808 } 809 } 810 811 sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 812 ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 813 ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 814 ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 815 if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 816 SET(sf->flags, SFF_SDHC); 817 sf->csd.capacity = sectors; 818 } 819 820 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 821 width = 8; 822 value = EXT_CSD_BUS_WIDTH_8; 823 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 824 width = 4; 825 value = EXT_CSD_BUS_WIDTH_4; 826 } else { 827 width = 1; 828 value = EXT_CSD_BUS_WIDTH_1; 829 } 830 831 if (width != 1) { 832 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 833 EXT_CSD_BUS_WIDTH, value); 834 if (error == 0) 835 error = sdmmc_chip_bus_width(sc->sc_sct, 836 sc->sc_sch, width); 837 else { 838 DPRINTF(("%s: can't change bus width" 839 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 840 return error; 841 } 842 843 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 844 } 845 sf->width = width; 846 } else { 847 if (sc->sc_busclk > sf->csd.tran_speed) 848 sc->sc_busclk = sf->csd.tran_speed; 849 if (sc->sc_busclk != bus_clock) { 850 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, 851 sc->sc_busclk); 852 if (error) { 853 aprint_error_dev(sc->sc_dev, 854 "can't change bus clock\n"); 855 return error; 856 } 857 } 858 } 859 860 return 0; 861 } 862 863 static int 864 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 865 { 866 struct sdmmc_command cmd; 867 int error; 868 869 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 870 memset(&cmd, 0, sizeof cmd); 871 cmd.c_opcode = MMC_ALL_SEND_CID; 872 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 873 874 error = sdmmc_mmc_command(sc, &cmd); 875 } else { 876 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 877 sizeof(cmd.c_resp)); 878 } 879 880 #ifdef SDMMC_DEBUG 881 if (error == 0) 882 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 883 #endif 884 if (error == 0 && resp != NULL) 885 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 886 return error; 887 } 888 889 static int 890 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 891 sdmmc_response *resp) 892 { 893 struct sdmmc_command cmd; 894 int error; 895 896 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 897 memset(&cmd, 0, sizeof cmd); 898 cmd.c_opcode = MMC_SEND_CSD; 899 cmd.c_arg = MMC_ARG_RCA(sf->rca); 900 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 901 902 error = sdmmc_mmc_command(sc, &cmd); 903 } else { 904 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 905 sizeof(cmd.c_resp)); 906 } 907 908 #ifdef SDMMC_DEBUG 909 if (error == 0) 910 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 911 #endif 912 if (error == 0 && resp != NULL) 913 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 914 return error; 915 } 916 917 static int 918 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 919 uint32_t *scr) 920 { 921 struct sdmmc_command cmd; 922 bus_dma_segment_t ds[1]; 923 void *ptr = NULL; 924 int datalen = 8; 925 int rseg; 926 int error = 0; 927 928 /* Don't lock */ 929 930 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 931 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 932 ds, 1, &rseg, BUS_DMA_NOWAIT); 933 if (error) 934 goto out; 935 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 936 BUS_DMA_NOWAIT); 937 if (error) 938 goto dmamem_free; 939 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 940 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 941 if (error) 942 goto dmamem_unmap; 943 944 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 945 BUS_DMASYNC_PREREAD); 946 } else { 947 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 948 if (ptr == NULL) 949 goto out; 950 } 951 952 memset(&cmd, 0, sizeof(cmd)); 953 cmd.c_data = ptr; 954 cmd.c_datalen = datalen; 955 cmd.c_blklen = datalen; 956 cmd.c_arg = 0; 957 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 958 cmd.c_opcode = SD_APP_SEND_SCR; 959 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 960 cmd.c_dmamap = sc->sc_dmap; 961 962 error = sdmmc_app_command(sc, sf, &cmd); 963 if (error == 0) { 964 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 965 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 966 BUS_DMASYNC_POSTREAD); 967 } 968 memcpy(scr, ptr, datalen); 969 } 970 971 out: 972 if (ptr != NULL) { 973 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 974 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 975 dmamem_unmap: 976 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 977 dmamem_free: 978 bus_dmamem_free(sc->sc_dmat, ds, rseg); 979 } else { 980 free(ptr, M_DEVBUF); 981 } 982 } 983 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 984 error)); 985 986 #ifdef SDMMC_DEBUG 987 if (error == 0) 988 sdmmc_dump_data("SCR", scr, datalen); 989 #endif 990 return error; 991 } 992 993 static int 994 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 995 { 996 sdmmc_response resp; 997 int ver; 998 999 memset(resp, 0, sizeof(resp)); 1000 /* 1001 * Change the raw-scr received from the DMA stream to resp. 1002 */ 1003 resp[0] = be32toh(sf->raw_scr[1]) >> 8; // LSW 1004 resp[1] = be32toh(sf->raw_scr[0]); // MSW 1005 resp[0] |= (resp[1] & 0xff) << 24; 1006 resp[1] >>= 8; 1007 1008 ver = SCR_STRUCTURE(resp); 1009 sf->scr.sd_spec = SCR_SD_SPEC(resp); 1010 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 1011 1012 DPRINTF(("%s: sdmmc_mem_decode_scr: %08x%08x spec=%d, bus width=%d\n", 1013 SDMMCDEVNAME(sc), resp[1], resp[0], 1014 sf->scr.sd_spec, sf->scr.bus_width)); 1015 1016 if (ver != 0) { 1017 DPRINTF(("%s: unknown structure version: %d\n", 1018 SDMMCDEVNAME(sc), ver)); 1019 return EINVAL; 1020 } 1021 return 0; 1022 } 1023 1024 static int 1025 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 1026 size_t datalen) 1027 { 1028 struct sdmmc_command cmd; 1029 bus_dma_segment_t ds[1]; 1030 void *ptr = NULL; 1031 int rseg; 1032 int error = 0; 1033 1034 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1035 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 1036 1, &rseg, BUS_DMA_NOWAIT); 1037 if (error) 1038 goto out; 1039 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 1040 BUS_DMA_NOWAIT); 1041 if (error) 1042 goto dmamem_free; 1043 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 1044 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1045 if (error) 1046 goto dmamem_unmap; 1047 1048 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1049 BUS_DMASYNC_PREREAD); 1050 } else { 1051 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 1052 if (ptr == NULL) 1053 goto out; 1054 } 1055 1056 memset(&cmd, 0, sizeof(cmd)); 1057 cmd.c_data = ptr; 1058 cmd.c_datalen = datalen; 1059 cmd.c_blklen = datalen; 1060 cmd.c_opcode = opcode; 1061 cmd.c_arg = 0; 1062 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 1063 if (opcode == MMC_SEND_EXT_CSD) 1064 SET(cmd.c_flags, SCF_RSP_R1); 1065 else 1066 SET(cmd.c_flags, SCF_RSP_R2); 1067 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1068 cmd.c_dmamap = sc->sc_dmap; 1069 1070 error = sdmmc_mmc_command(sc, &cmd); 1071 if (error == 0) { 1072 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1073 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1074 BUS_DMASYNC_POSTREAD); 1075 } 1076 memcpy(data, ptr, datalen); 1077 #ifdef SDMMC_DEBUG 1078 sdmmc_dump_data("CXD", data, datalen); 1079 #endif 1080 } 1081 1082 out: 1083 if (ptr != NULL) { 1084 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1085 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1086 dmamem_unmap: 1087 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1088 dmamem_free: 1089 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1090 } else { 1091 free(ptr, M_DEVBUF); 1092 } 1093 } 1094 return error; 1095 } 1096 1097 static int 1098 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1099 { 1100 struct sdmmc_softc *sc = sf->sc; 1101 struct sdmmc_command cmd; 1102 int error; 1103 1104 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1105 return ENODEV; 1106 1107 memset(&cmd, 0, sizeof(cmd)); 1108 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1109 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1110 1111 switch (width) { 1112 case 1: 1113 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1114 break; 1115 1116 case 4: 1117 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1118 break; 1119 1120 default: 1121 return EINVAL; 1122 } 1123 1124 error = sdmmc_app_command(sc, sf, &cmd); 1125 if (error == 0) 1126 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1127 return error; 1128 } 1129 1130 static int 1131 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1132 int function, sdmmc_bitfield512_t *status) 1133 { 1134 struct sdmmc_softc *sc = sf->sc; 1135 struct sdmmc_command cmd; 1136 bus_dma_segment_t ds[1]; 1137 void *ptr = NULL; 1138 int gsft, rseg, error = 0; 1139 const int statlen = 64; 1140 1141 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1142 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1143 return EINVAL; 1144 1145 if (group <= 0 || group > 6 || 1146 function < 0 || function > 15) 1147 return EINVAL; 1148 1149 gsft = (group - 1) << 2; 1150 1151 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1152 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1153 1, &rseg, BUS_DMA_NOWAIT); 1154 if (error) 1155 goto out; 1156 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1157 BUS_DMA_NOWAIT); 1158 if (error) 1159 goto dmamem_free; 1160 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1161 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1162 if (error) 1163 goto dmamem_unmap; 1164 1165 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1166 BUS_DMASYNC_PREREAD); 1167 } else { 1168 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1169 if (ptr == NULL) 1170 goto out; 1171 } 1172 1173 memset(&cmd, 0, sizeof(cmd)); 1174 cmd.c_data = ptr; 1175 cmd.c_datalen = statlen; 1176 cmd.c_blklen = statlen; 1177 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1178 cmd.c_arg = 1179 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1180 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1181 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1182 cmd.c_dmamap = sc->sc_dmap; 1183 1184 error = sdmmc_mmc_command(sc, &cmd); 1185 if (error == 0) { 1186 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1187 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1188 BUS_DMASYNC_POSTREAD); 1189 } 1190 memcpy(status, ptr, statlen); 1191 } 1192 1193 out: 1194 if (ptr != NULL) { 1195 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1196 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1197 dmamem_unmap: 1198 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1199 dmamem_free: 1200 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1201 } else { 1202 free(ptr, M_DEVBUF); 1203 } 1204 } 1205 1206 if (error == 0) 1207 sdmmc_be512_to_bitfield512(status); 1208 1209 return error; 1210 } 1211 1212 static int 1213 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1214 uint8_t value) 1215 { 1216 struct sdmmc_softc *sc = sf->sc; 1217 struct sdmmc_command cmd; 1218 1219 memset(&cmd, 0, sizeof(cmd)); 1220 cmd.c_opcode = MMC_SWITCH; 1221 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1222 (index << 16) | (value << 8) | set; 1223 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1224 1225 return sdmmc_mmc_command(sc, &cmd); 1226 } 1227 1228 /* 1229 * SPI mode function 1230 */ 1231 static int 1232 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1233 { 1234 struct sdmmc_command cmd; 1235 int error; 1236 1237 memset(&cmd, 0, sizeof(cmd)); 1238 cmd.c_opcode = MMC_READ_OCR; 1239 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1240 cmd.c_flags = SCF_RSP_SPI_R3; 1241 1242 error = sdmmc_mmc_command(sc, &cmd); 1243 if (error == 0 && card_ocr != NULL) 1244 *card_ocr = cmd.c_resp[1]; 1245 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1246 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1247 return error; 1248 } 1249 1250 /* 1251 * read/write function 1252 */ 1253 /* read */ 1254 static int 1255 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1256 u_char *data, size_t datalen) 1257 { 1258 struct sdmmc_softc *sc = sf->sc; 1259 int error = 0; 1260 int i; 1261 1262 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1263 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1264 1265 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1266 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno + i, 1267 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1268 if (error) 1269 break; 1270 } 1271 return error; 1272 } 1273 1274 /* 1275 * Simulate multi-segment dma transfer. 1276 */ 1277 static int 1278 sdmmc_mem_single_segment_dma_read_block(struct sdmmc_function *sf, 1279 uint32_t blkno, u_char *data, size_t datalen) 1280 { 1281 struct sdmmc_softc *sc = sf->sc; 1282 bool use_bbuf = false; 1283 int error = 0; 1284 int i; 1285 1286 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1287 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1288 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1289 use_bbuf = true; 1290 break; 1291 } 1292 } 1293 if (use_bbuf) { 1294 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1295 BUS_DMASYNC_PREREAD); 1296 1297 error = sdmmc_mem_read_block_subr(sf, sf->bbuf_dmap, 1298 blkno, data, datalen); 1299 if (error) { 1300 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1301 return error; 1302 } 1303 1304 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1305 BUS_DMASYNC_POSTREAD); 1306 1307 /* Copy from bounce buffer */ 1308 memcpy(data, sf->bbuf, datalen); 1309 1310 return 0; 1311 } 1312 1313 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1314 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1315 1316 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1317 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_READ); 1318 if (error) 1319 return error; 1320 1321 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1322 BUS_DMASYNC_PREREAD); 1323 1324 error = sdmmc_mem_read_block_subr(sf, sf->sseg_dmap, 1325 blkno, data, len); 1326 if (error) { 1327 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1328 return error; 1329 } 1330 1331 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1332 BUS_DMASYNC_POSTREAD); 1333 1334 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1335 1336 blkno += len / SDMMC_SECTOR_SIZE; 1337 data += len; 1338 } 1339 return 0; 1340 } 1341 1342 static int 1343 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1344 uint32_t blkno, u_char *data, size_t datalen) 1345 { 1346 struct sdmmc_softc *sc = sf->sc; 1347 struct sdmmc_command cmd; 1348 int error; 1349 1350 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1351 error = sdmmc_select_card(sc, sf); 1352 if (error) 1353 goto out; 1354 } 1355 1356 memset(&cmd, 0, sizeof(cmd)); 1357 cmd.c_data = data; 1358 cmd.c_datalen = datalen; 1359 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1360 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1361 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1362 cmd.c_arg = blkno; 1363 if (!ISSET(sf->flags, SFF_SDHC)) 1364 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1365 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1366 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1367 cmd.c_dmamap = dmap; 1368 1369 error = sdmmc_mmc_command(sc, &cmd); 1370 if (error) 1371 goto out; 1372 1373 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1374 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1375 memset(&cmd, 0, sizeof cmd); 1376 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1377 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1378 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1379 error = sdmmc_mmc_command(sc, &cmd); 1380 if (error) 1381 goto out; 1382 } 1383 } 1384 1385 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1386 do { 1387 memset(&cmd, 0, sizeof(cmd)); 1388 cmd.c_opcode = MMC_SEND_STATUS; 1389 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1390 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1391 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1392 error = sdmmc_mmc_command(sc, &cmd); 1393 if (error) 1394 break; 1395 /* XXX time out */ 1396 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1397 } 1398 1399 out: 1400 return error; 1401 } 1402 1403 int 1404 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1405 size_t datalen) 1406 { 1407 struct sdmmc_softc *sc = sf->sc; 1408 int error; 1409 1410 SDMMC_LOCK(sc); 1411 1412 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1413 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1414 goto out; 1415 } 1416 1417 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1418 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1419 datalen); 1420 goto out; 1421 } 1422 1423 /* DMA transfer */ 1424 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1425 BUS_DMA_NOWAIT|BUS_DMA_READ); 1426 if (error) 1427 goto out; 1428 1429 #ifdef SDMMC_DEBUG 1430 printf("data=%p, datalen=%zu\n", data, datalen); 1431 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1432 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1433 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1434 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1435 } 1436 #endif 1437 1438 if (sc->sc_dmap->dm_nsegs > 1 1439 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1440 error = sdmmc_mem_single_segment_dma_read_block(sf, blkno, 1441 data, datalen); 1442 goto unload; 1443 } 1444 1445 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1446 BUS_DMASYNC_PREREAD); 1447 1448 error = sdmmc_mem_read_block_subr(sf, sc->sc_dmap, blkno, data, 1449 datalen); 1450 if (error) 1451 goto unload; 1452 1453 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1454 BUS_DMASYNC_POSTREAD); 1455 unload: 1456 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1457 1458 out: 1459 SDMMC_UNLOCK(sc); 1460 1461 return error; 1462 } 1463 1464 /* write */ 1465 static int 1466 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1467 u_char *data, size_t datalen) 1468 { 1469 struct sdmmc_softc *sc = sf->sc; 1470 int error = 0; 1471 int i; 1472 1473 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1474 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1475 1476 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1477 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno + i, 1478 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1479 if (error) 1480 break; 1481 } 1482 return error; 1483 } 1484 1485 /* 1486 * Simulate multi-segment dma transfer. 1487 */ 1488 static int 1489 sdmmc_mem_single_segment_dma_write_block(struct sdmmc_function *sf, 1490 uint32_t blkno, u_char *data, size_t datalen) 1491 { 1492 struct sdmmc_softc *sc = sf->sc; 1493 bool use_bbuf = false; 1494 int error = 0; 1495 int i; 1496 1497 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1498 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1499 if ((len % SDMMC_SECTOR_SIZE) != 0) { 1500 use_bbuf = true; 1501 break; 1502 } 1503 } 1504 if (use_bbuf) { 1505 /* Copy to bounce buffer */ 1506 memcpy(sf->bbuf, data, datalen); 1507 1508 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1509 BUS_DMASYNC_PREWRITE); 1510 1511 error = sdmmc_mem_write_block_subr(sf, sf->bbuf_dmap, 1512 blkno, data, datalen); 1513 if (error) { 1514 bus_dmamap_unload(sc->sc_dmat, sf->bbuf_dmap); 1515 return error; 1516 } 1517 1518 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, datalen, 1519 BUS_DMASYNC_POSTWRITE); 1520 1521 return 0; 1522 } 1523 1524 for (i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1525 size_t len = sc->sc_dmap->dm_segs[i].ds_len; 1526 1527 error = bus_dmamap_load(sc->sc_dmat, sf->sseg_dmap, 1528 data, len, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1529 if (error) 1530 return error; 1531 1532 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1533 BUS_DMASYNC_PREWRITE); 1534 1535 error = sdmmc_mem_write_block_subr(sf, sf->sseg_dmap, 1536 blkno, data, len); 1537 if (error) { 1538 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1539 return error; 1540 } 1541 1542 bus_dmamap_sync(sc->sc_dmat, sf->sseg_dmap, 0, len, 1543 BUS_DMASYNC_POSTWRITE); 1544 1545 bus_dmamap_unload(sc->sc_dmat, sf->sseg_dmap); 1546 1547 blkno += len / SDMMC_SECTOR_SIZE; 1548 data += len; 1549 } 1550 1551 return error; 1552 } 1553 1554 static int 1555 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, bus_dmamap_t dmap, 1556 uint32_t blkno, u_char *data, size_t datalen) 1557 { 1558 struct sdmmc_softc *sc = sf->sc; 1559 struct sdmmc_command cmd; 1560 int error; 1561 1562 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1563 error = sdmmc_select_card(sc, sf); 1564 if (error) 1565 goto out; 1566 } 1567 1568 memset(&cmd, 0, sizeof(cmd)); 1569 cmd.c_data = data; 1570 cmd.c_datalen = datalen; 1571 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1572 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1573 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1574 cmd.c_arg = blkno; 1575 if (!ISSET(sf->flags, SFF_SDHC)) 1576 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1577 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1578 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1579 cmd.c_dmamap = dmap; 1580 1581 error = sdmmc_mmc_command(sc, &cmd); 1582 if (error) 1583 goto out; 1584 1585 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1586 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1587 memset(&cmd, 0, sizeof(cmd)); 1588 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1589 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1590 error = sdmmc_mmc_command(sc, &cmd); 1591 if (error) 1592 goto out; 1593 } 1594 } 1595 1596 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1597 do { 1598 memset(&cmd, 0, sizeof(cmd)); 1599 cmd.c_opcode = MMC_SEND_STATUS; 1600 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1601 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1602 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1603 error = sdmmc_mmc_command(sc, &cmd); 1604 if (error) 1605 break; 1606 /* XXX time out */ 1607 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1608 } 1609 1610 out: 1611 return error; 1612 } 1613 1614 int 1615 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1616 size_t datalen) 1617 { 1618 struct sdmmc_softc *sc = sf->sc; 1619 int error; 1620 1621 SDMMC_LOCK(sc); 1622 1623 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1624 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1625 error = EIO; 1626 goto out; 1627 } 1628 1629 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1630 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1631 goto out; 1632 } 1633 1634 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1635 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1636 datalen); 1637 goto out; 1638 } 1639 1640 /* DMA transfer */ 1641 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1642 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1643 if (error) 1644 goto out; 1645 1646 #ifdef SDMMC_DEBUG 1647 aprint_normal_dev(sc->sc_dev, "%s: data=%p, datalen=%zu\n", 1648 __func__, data, datalen); 1649 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1650 aprint_normal_dev(sc->sc_dev, 1651 "%s: seg#%d: addr=%#lx, size=%#lx\n", __func__, i, 1652 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1653 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1654 } 1655 #endif 1656 1657 if (sc->sc_dmap->dm_nsegs > 1 1658 && !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1659 error = sdmmc_mem_single_segment_dma_write_block(sf, blkno, 1660 data, datalen); 1661 goto unload; 1662 } 1663 1664 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1665 BUS_DMASYNC_PREWRITE); 1666 1667 error = sdmmc_mem_write_block_subr(sf, sc->sc_dmap, blkno, data, 1668 datalen); 1669 if (error) 1670 goto unload; 1671 1672 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1673 BUS_DMASYNC_POSTWRITE); 1674 unload: 1675 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1676 1677 out: 1678 SDMMC_UNLOCK(sc); 1679 1680 return error; 1681 } 1682