1 /* $NetBSD: sdmmc_mem.c,v 1.18 2012/01/21 19:44:31 nonaka Exp $ */ 2 /* $OpenBSD: sdmmc_mem.c,v 1.10 2009/01/09 10:55:22 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2007, 2008, 2009, 2010 NONAKA Kimihiro <nonaka@netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 /* Routines for SD/MMC memory cards. */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: sdmmc_mem.c,v 1.18 2012/01/21 19:44:31 nonaka Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 56 #include <dev/sdmmc/sdmmcchip.h> 57 #include <dev/sdmmc/sdmmcreg.h> 58 #include <dev/sdmmc/sdmmcvar.h> 59 60 #ifdef SDMMC_DEBUG 61 #define DPRINTF(s) do { printf s; } while (/*CONSTCOND*/0) 62 #else 63 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 64 #endif 65 66 static int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 67 static int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 68 static int sdmmc_mem_send_cid(struct sdmmc_softc *, sdmmc_response *); 69 static int sdmmc_mem_send_csd(struct sdmmc_softc *, struct sdmmc_function *, 70 sdmmc_response *); 71 static int sdmmc_mem_send_scr(struct sdmmc_softc *, struct sdmmc_function *, 72 uint32_t scr[2]); 73 static int sdmmc_mem_decode_scr(struct sdmmc_softc *, struct sdmmc_function *); 74 static int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 75 static int sdmmc_set_bus_width(struct sdmmc_function *, int); 76 static int sdmmc_mem_sd_switch(struct sdmmc_function *, int, int, int, void *); 77 static int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, 78 uint8_t); 79 static int sdmmc_mem_spi_read_ocr(struct sdmmc_softc *, uint32_t, uint32_t *); 80 static int sdmmc_mem_single_read_block(struct sdmmc_function *, uint32_t, 81 u_char *, size_t); 82 static int sdmmc_mem_single_write_block(struct sdmmc_function *, uint32_t, 83 u_char *, size_t); 84 static int sdmmc_mem_read_block_subr(struct sdmmc_function *, uint32_t, 85 u_char *, size_t); 86 static int sdmmc_mem_write_block_subr(struct sdmmc_function *, uint32_t, 87 u_char *, size_t); 88 89 /* 90 * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 91 */ 92 int 93 sdmmc_mem_enable(struct sdmmc_softc *sc) 94 { 95 uint32_t host_ocr; 96 uint32_t card_ocr; 97 uint32_t ocr = 0; 98 int error; 99 100 SDMMC_LOCK(sc); 101 102 /* Set host mode to SD "combo" card or SD memory-only. */ 103 SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 104 105 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 106 sdmmc_spi_chip_initialize(sc->sc_spi_sct, sc->sc_sch); 107 108 /* Reset memory (*must* do that before CMD55 or CMD1). */ 109 sdmmc_go_idle_state(sc); 110 111 /* Check SD Ver.2 */ 112 error = sdmmc_mem_send_if_cond(sc, 0x1aa, &card_ocr); 113 if (error == 0 && card_ocr == 0x1aa) 114 SET(ocr, MMC_OCR_HCS); 115 116 /* 117 * Read the SD/MMC memory OCR value by issuing CMD55 followed 118 * by ACMD41 to read the OCR value from memory-only SD cards. 119 * MMC cards will not respond to CMD55 or ACMD41 and this is 120 * how we distinguish them from SD cards. 121 */ 122 mmc_mode: 123 error = sdmmc_mem_send_op_cond(sc, 124 ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? ocr : 0, &card_ocr); 125 if (error) { 126 if (ISSET(sc->sc_flags, SMF_SD_MODE) && 127 !ISSET(sc->sc_flags, SMF_IO_MODE)) { 128 /* Not a SD card, switch to MMC mode. */ 129 DPRINTF(("%s: switch to MMC mode\n", SDMMCDEVNAME(sc))); 130 CLR(sc->sc_flags, SMF_SD_MODE); 131 goto mmc_mode; 132 } 133 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 134 DPRINTF(("%s: couldn't read memory OCR\n", 135 SDMMCDEVNAME(sc))); 136 goto out; 137 } else { 138 /* Not a "combo" card. */ 139 CLR(sc->sc_flags, SMF_MEM_MODE); 140 error = 0; 141 goto out; 142 } 143 } 144 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 145 /* get card OCR */ 146 error = sdmmc_mem_spi_read_ocr(sc, ocr, &card_ocr); 147 if (error) { 148 DPRINTF(("%s: couldn't read SPI memory OCR\n", 149 SDMMCDEVNAME(sc))); 150 goto out; 151 } 152 } 153 154 /* Set the lowest voltage supported by the card and host. */ 155 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 156 error = sdmmc_set_bus_power(sc, host_ocr, card_ocr); 157 if (error) { 158 DPRINTF(("%s: couldn't supply voltage requested by card\n", 159 SDMMCDEVNAME(sc))); 160 goto out; 161 } 162 host_ocr &= card_ocr; 163 host_ocr |= ocr; 164 165 /* Send the new OCR value until all cards are ready. */ 166 error = sdmmc_mem_send_op_cond(sc, host_ocr, NULL); 167 if (error) { 168 DPRINTF(("%s: couldn't send memory OCR\n", SDMMCDEVNAME(sc))); 169 goto out; 170 } 171 172 out: 173 SDMMC_UNLOCK(sc); 174 175 return error; 176 } 177 178 /* 179 * Read the CSD and CID from all cards and assign each card a unique 180 * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 181 */ 182 void 183 sdmmc_mem_scan(struct sdmmc_softc *sc) 184 { 185 sdmmc_response resp; 186 struct sdmmc_function *sf; 187 uint16_t next_rca; 188 int error; 189 int retry; 190 191 SDMMC_LOCK(sc); 192 193 /* 194 * CMD2 is a broadcast command understood by SD cards and MMC 195 * cards. All cards begin to respond to the command, but back 196 * off if another card drives the CMD line to a different level. 197 * Only one card will get its entire response through. That 198 * card remains silent once it has been assigned a RCA. 199 */ 200 for (retry = 0; retry < 100; retry++) { 201 error = sdmmc_mem_send_cid(sc, &resp); 202 if (error) { 203 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) && 204 error == ETIMEDOUT) { 205 /* No more cards there. */ 206 break; 207 } 208 DPRINTF(("%s: couldn't read CID\n", SDMMCDEVNAME(sc))); 209 break; 210 } 211 212 /* In MMC mode, find the next available RCA. */ 213 next_rca = 1; 214 if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 215 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) 216 next_rca++; 217 } 218 219 /* Allocate a sdmmc_function structure. */ 220 sf = sdmmc_function_alloc(sc); 221 sf->rca = next_rca; 222 223 /* 224 * Remember the CID returned in the CMD2 response for 225 * later decoding. 226 */ 227 memcpy(sf->raw_cid, resp, sizeof(sf->raw_cid)); 228 229 /* 230 * Silence the card by assigning it a unique RCA, or 231 * querying it for its RCA in the case of SD. 232 */ 233 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 234 if (sdmmc_set_relative_addr(sc, sf) != 0) { 235 aprint_error_dev(sc->sc_dev, 236 "couldn't set mem RCA\n"); 237 sdmmc_function_free(sf); 238 break; 239 } 240 } 241 242 /* 243 * If this is a memory-only card, the card responding 244 * first becomes an alias for SDIO function 0. 245 */ 246 if (sc->sc_fn0 == NULL) 247 sc->sc_fn0 = sf; 248 249 SIMPLEQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 250 251 /* only one function in SPI mode */ 252 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 253 break; 254 } 255 256 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 257 /* Go to Data Transfer Mode, if possible. */ 258 sdmmc_chip_bus_rod(sc->sc_sct, sc->sc_sch, 0); 259 260 /* 261 * All cards are either inactive or awaiting further commands. 262 * Read the CSDs and decode the raw CID for each card. 263 */ 264 SIMPLEQ_FOREACH(sf, &sc->sf_head, sf_list) { 265 error = sdmmc_mem_send_csd(sc, sf, &resp); 266 if (error) { 267 SET(sf->flags, SFF_ERROR); 268 continue; 269 } 270 271 if (sdmmc_decode_csd(sc, resp, sf) != 0 || 272 sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 273 SET(sf->flags, SFF_ERROR); 274 continue; 275 } 276 277 #ifdef SDMMC_DEBUG 278 printf("%s: CID: ", SDMMCDEVNAME(sc)); 279 sdmmc_print_cid(&sf->cid); 280 #endif 281 } 282 283 SDMMC_UNLOCK(sc); 284 } 285 286 int 287 sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 288 struct sdmmc_function *sf) 289 { 290 /* TRAN_SPEED(2:0): transfer rate exponent */ 291 static const int speed_exponent[8] = { 292 100 * 1, /* 100 Kbits/s */ 293 1 * 1000, /* 1 Mbits/s */ 294 10 * 1000, /* 10 Mbits/s */ 295 100 * 1000, /* 100 Mbits/s */ 296 0, 297 0, 298 0, 299 0, 300 }; 301 /* TRAN_SPEED(6:3): time mantissa */ 302 static const int speed_mantissa[16] = { 303 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 304 }; 305 struct sdmmc_csd *csd = &sf->csd; 306 int e, m; 307 308 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 309 /* 310 * CSD version 1.0 corresponds to SD system 311 * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 312 */ 313 csd->csdver = SD_CSD_CSDVER(resp); 314 switch (csd->csdver) { 315 case SD_CSD_CSDVER_2_0: 316 DPRINTF(("%s: SD Ver.2.0\n", SDMMCDEVNAME(sc))); 317 SET(sf->flags, SFF_SDHC); 318 csd->capacity = SD_CSD_V2_CAPACITY(resp); 319 csd->read_bl_len = SD_CSD_V2_BL_LEN; 320 csd->ccc = SD_CSD_CCC(resp); 321 break; 322 323 case SD_CSD_CSDVER_1_0: 324 DPRINTF(("%s: SD Ver.1.0\n", SDMMCDEVNAME(sc))); 325 csd->capacity = SD_CSD_CAPACITY(resp); 326 csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 327 break; 328 329 default: 330 aprint_error_dev(sc->sc_dev, 331 "unknown SD CSD structure version 0x%x\n", 332 csd->csdver); 333 return 1; 334 } 335 336 csd->mmcver = SD_CSD_MMCVER(resp); 337 csd->write_bl_len = SD_CSD_WRITE_BL_LEN(resp); 338 csd->r2w_factor = SD_CSD_R2W_FACTOR(resp); 339 e = SD_CSD_SPEED_EXP(resp); 340 m = SD_CSD_SPEED_MANT(resp); 341 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 342 } else { 343 csd->csdver = MMC_CSD_CSDVER(resp); 344 if (csd->csdver == MMC_CSD_CSDVER_1_0) { 345 aprint_error_dev(sc->sc_dev, 346 "unknown MMC CSD structure version 0x%x\n", 347 csd->csdver); 348 return 1; 349 } 350 351 csd->mmcver = MMC_CSD_MMCVER(resp); 352 csd->capacity = MMC_CSD_CAPACITY(resp); 353 csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 354 csd->write_bl_len = MMC_CSD_WRITE_BL_LEN(resp); 355 csd->r2w_factor = MMC_CSD_R2W_FACTOR(resp); 356 e = MMC_CSD_TRAN_SPEED_EXP(resp); 357 m = MMC_CSD_TRAN_SPEED_MANT(resp); 358 csd->tran_speed = speed_exponent[e] * speed_mantissa[m] / 10; 359 } 360 if ((1 << csd->read_bl_len) > SDMMC_SECTOR_SIZE) 361 csd->capacity *= (1 << csd->read_bl_len) / SDMMC_SECTOR_SIZE; 362 363 #ifdef SDMMC_DUMP_CSD 364 sdmmc_print_csd(resp, csd); 365 #endif 366 367 return 0; 368 } 369 370 int 371 sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 372 struct sdmmc_function *sf) 373 { 374 struct sdmmc_cid *cid = &sf->cid; 375 376 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 377 cid->mid = SD_CID_MID(resp); 378 cid->oid = SD_CID_OID(resp); 379 SD_CID_PNM_CPY(resp, cid->pnm); 380 cid->rev = SD_CID_REV(resp); 381 cid->psn = SD_CID_PSN(resp); 382 cid->mdt = SD_CID_MDT(resp); 383 } else { 384 switch(sf->csd.mmcver) { 385 case MMC_CSD_MMCVER_1_0: 386 case MMC_CSD_MMCVER_1_4: 387 cid->mid = MMC_CID_MID_V1(resp); 388 MMC_CID_PNM_V1_CPY(resp, cid->pnm); 389 cid->rev = MMC_CID_REV_V1(resp); 390 cid->psn = MMC_CID_PSN_V1(resp); 391 cid->mdt = MMC_CID_MDT_V1(resp); 392 break; 393 case MMC_CSD_MMCVER_2_0: 394 case MMC_CSD_MMCVER_3_1: 395 case MMC_CSD_MMCVER_4_0: 396 cid->mid = MMC_CID_MID_V2(resp); 397 cid->oid = MMC_CID_OID_V2(resp); 398 MMC_CID_PNM_V2_CPY(resp, cid->pnm); 399 cid->psn = MMC_CID_PSN_V2(resp); 400 break; 401 default: 402 aprint_error_dev(sc->sc_dev, "unknown MMC version %d\n", 403 sf->csd.mmcver); 404 return 1; 405 } 406 } 407 return 0; 408 } 409 410 void 411 sdmmc_print_cid(struct sdmmc_cid *cid) 412 { 413 414 printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 415 " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 416 cid->mdt); 417 } 418 419 #ifdef SDMMC_DUMP_CSD 420 void 421 sdmmc_print_csd(sdmmc_response resp, struct sdmmc_csd *csd) 422 { 423 424 printf("csdver = %d\n", csd->csdver); 425 printf("mmcver = %d\n", csd->mmcver); 426 printf("capacity = 0x%08x\n", csd->capacity); 427 printf("read_bl_len = %d\n", csd->read_bl_len); 428 printf("write_cl_len = %d\n", csd->write_bl_len); 429 printf("r2w_factor = %d\n", csd->r2w_factor); 430 printf("tran_speed = %d\n", csd->tran_speed); 431 printf("ccc = 0x%x\n", csd->ccc); 432 } 433 #endif 434 435 /* 436 * Initialize a SD/MMC memory card. 437 */ 438 int 439 sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 440 { 441 int error = 0; 442 443 SDMMC_LOCK(sc); 444 445 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 446 error = sdmmc_select_card(sc, sf); 447 if (error) 448 goto out; 449 } 450 451 if (!ISSET(sf->flags, SFF_SDHC)) { 452 error = sdmmc_mem_set_blocklen(sc, sf); 453 if (error) 454 goto out; 455 } 456 457 if (ISSET(sc->sc_flags, SMF_SD_MODE)) 458 error = sdmmc_mem_sd_init(sc, sf); 459 else 460 error = sdmmc_mem_mmc_init(sc, sf); 461 462 out: 463 SDMMC_UNLOCK(sc); 464 465 return error; 466 } 467 468 /* 469 * Get or set the card's memory OCR value (SD or MMC). 470 */ 471 int 472 sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 473 { 474 struct sdmmc_command cmd; 475 int error; 476 int retry; 477 478 /* Don't lock */ 479 480 /* 481 * If we change the OCR value, retry the command until the OCR 482 * we receive in response has the "CARD BUSY" bit set, meaning 483 * that all cards are ready for identification. 484 */ 485 for (retry = 0; retry < 100; retry++) { 486 memset(&cmd, 0, sizeof(cmd)); 487 cmd.c_arg = !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE) ? 488 ocr : (ocr & MMC_OCR_HCS); 489 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3 | SCF_RSP_SPI_R1; 490 491 if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 492 cmd.c_opcode = SD_APP_OP_COND; 493 error = sdmmc_app_command(sc, NULL, &cmd); 494 } else { 495 cmd.c_opcode = MMC_SEND_OP_COND; 496 error = sdmmc_mmc_command(sc, &cmd); 497 } 498 if (error) 499 break; 500 501 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 502 if (!ISSET(MMC_SPI_R1(cmd.c_resp), R1_SPI_IDLE)) 503 break; 504 } else { 505 if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 506 ocr == 0) 507 break; 508 } 509 510 error = ETIMEDOUT; 511 sdmmc_delay(10000); 512 } 513 if (error == 0 && 514 ocrp != NULL && 515 !ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 516 *ocrp = MMC_R3(cmd.c_resp); 517 DPRINTF(("%s: sdmmc_mem_send_op_cond: error=%d, ocr=%#x\n", 518 SDMMCDEVNAME(sc), error, MMC_R3(cmd.c_resp))); 519 return error; 520 } 521 522 int 523 sdmmc_mem_send_if_cond(struct sdmmc_softc *sc, uint32_t ocr, uint32_t *ocrp) 524 { 525 struct sdmmc_command cmd; 526 int error; 527 528 /* Don't lock */ 529 530 memset(&cmd, 0, sizeof(cmd)); 531 cmd.c_arg = ocr; 532 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7 | SCF_RSP_SPI_R7; 533 cmd.c_opcode = SD_SEND_IF_COND; 534 535 error = sdmmc_mmc_command(sc, &cmd); 536 if (error == 0 && ocrp != NULL) { 537 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 538 *ocrp = MMC_SPI_R7(cmd.c_resp); 539 } else { 540 *ocrp = MMC_R7(cmd.c_resp); 541 } 542 DPRINTF(("%s: sdmmc_mem_send_if_cond: error=%d, ocr=%#x\n", 543 SDMMCDEVNAME(sc), error, *ocrp)); 544 } 545 return error; 546 } 547 548 /* 549 * Set the read block length appropriately for this card, according to 550 * the card CSD register value. 551 */ 552 int 553 sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf) 554 { 555 struct sdmmc_command cmd; 556 int error; 557 558 /* Don't lock */ 559 560 memset(&cmd, 0, sizeof(cmd)); 561 cmd.c_opcode = MMC_SET_BLOCKLEN; 562 cmd.c_arg = SDMMC_SECTOR_SIZE; 563 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R1; 564 565 error = sdmmc_mmc_command(sc, &cmd); 566 567 DPRINTF(("%s: sdmmc_mem_set_blocklen: read_bl_len=%d sector_size=%d\n", 568 SDMMCDEVNAME(sc), 1 << sf->csd.read_bl_len, SDMMC_SECTOR_SIZE)); 569 570 return error; 571 } 572 573 static int 574 sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 575 { 576 static const struct { 577 int v; 578 int freq; 579 } switch_group0_functions[] = { 580 /* Default/SDR12 */ 581 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 582 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 25000 }, 583 584 /* High-Speed/SDR25 */ 585 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V | 586 MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V, 50000 }, 587 588 /* SDR50 */ 589 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 100000 }, 590 591 /* SDR104 */ 592 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 208000 }, 593 594 /* DDR50 */ 595 { MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V, 50000 }, 596 }; 597 int host_ocr, support_func, best_func, error, g, i; 598 char status[64]; 599 600 error = sdmmc_mem_send_scr(sc, sf, sf->raw_scr); 601 if (error) { 602 aprint_error_dev(sc->sc_dev, "SD_SEND_SCR send failed.\n"); 603 return error; 604 } 605 error = sdmmc_mem_decode_scr(sc, sf); 606 if (error) 607 return error; 608 609 if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 610 ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 611 DPRINTF(("%s: change bus width\n", SDMMCDEVNAME(sc))); 612 error = sdmmc_set_bus_width(sf, 4); 613 if (error) { 614 aprint_error_dev(sc->sc_dev, 615 "can't change bus width (%d bit)\n", 4); 616 return error; 617 } 618 sf->width = 4; 619 } 620 621 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 622 ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 623 DPRINTF(("%s: switch func mode 0\n", SDMMCDEVNAME(sc))); 624 error = sdmmc_mem_sd_switch(sf, 0, 1, 0, status); 625 if (error) { 626 aprint_error_dev(sc->sc_dev, 627 "switch func mode 0 failed\n"); 628 return error; 629 } 630 631 host_ocr = sdmmc_chip_host_ocr(sc->sc_sct, sc->sc_sch); 632 support_func = SFUNC_STATUS_GROUP(status, 1); 633 best_func = 0; 634 for (i = 0, g = 1; 635 i < __arraycount(switch_group0_functions); i++, g <<= 1) { 636 if (!(switch_group0_functions[i].v & host_ocr)) 637 continue; 638 if (g & support_func) 639 best_func = i; 640 } 641 if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED) && 642 best_func != 0) { 643 DPRINTF(("%s: switch func mode 1(func=%d)\n", 644 SDMMCDEVNAME(sc), best_func)); 645 error = 646 sdmmc_mem_sd_switch(sf, 1, 1, best_func, status); 647 if (error) { 648 aprint_error_dev(sc->sc_dev, 649 "switch func mode 1 failed:" 650 " group 1 function %d(0x%2x)\n", 651 best_func, support_func); 652 return error; 653 } 654 sf->csd.tran_speed = 655 switch_group0_functions[best_func].freq; 656 657 /* Wait 400KHz x 8 clock */ 658 delay(1); 659 } 660 } 661 662 /* change bus clock */ 663 if (sc->sc_busclk > sf->csd.tran_speed) 664 sc->sc_busclk = sf->csd.tran_speed; 665 error = sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 666 if (error) { 667 aprint_error_dev(sc->sc_dev, "can't change bus clock\n"); 668 return error; 669 } 670 671 return 0; 672 } 673 674 static int 675 sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 676 { 677 int width, value, hs_timing, error; 678 char ext_csd[512]; 679 680 if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 681 error = sdmmc_mem_send_cxd_data(sc, 682 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 683 if (error) { 684 aprint_error_dev(sc->sc_dev, "can't read EXT_CSD\n"); 685 return error; 686 } 687 if ((sf->csd.csdver == MMC_CSD_CSDVER_EXT_CSD) && 688 (ext_csd[EXT_CSD_STRUCTURE] > EXT_CSD_STRUCTURE_VER_1_2)) { 689 aprint_error_dev(sc->sc_dev, 690 "unrecognised future version (%d)\n", 691 ext_csd[EXT_CSD_STRUCTURE]); 692 return error; 693 } 694 hs_timing = 0; 695 switch (ext_csd[EXT_CSD_CARD_TYPE]) { 696 case EXT_CSD_CARD_TYPE_26M: 697 sf->csd.tran_speed = 26000; /* 26MHz */ 698 break; 699 700 case EXT_CSD_CARD_TYPE_52M | EXT_CSD_CARD_TYPE_26M: 701 sf->csd.tran_speed = 52000; /* 52MHz */ 702 hs_timing = 1; 703 break; 704 705 default: 706 aprint_error_dev(sc->sc_dev, 707 "unknwon CARD_TYPE: 0x%x\n", 708 ext_csd[EXT_CSD_CARD_TYPE]); 709 return error; 710 } 711 712 if (!ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 713 hs_timing = 0; 714 } 715 if (hs_timing) { 716 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 717 EXT_CSD_HS_TIMING, hs_timing); 718 if (error) { 719 aprint_error_dev(sc->sc_dev, 720 "can't change high speed\n"); 721 return error; 722 } 723 } 724 725 if (sc->sc_busclk > sf->csd.tran_speed) 726 sc->sc_busclk = sf->csd.tran_speed; 727 error = 728 sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 729 if (error) { 730 aprint_error_dev(sc->sc_dev, 731 "can't change bus clock\n"); 732 return error; 733 } 734 735 if (hs_timing) { 736 error = sdmmc_mem_send_cxd_data(sc, 737 MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 738 if (error) { 739 aprint_error_dev(sc->sc_dev, 740 "can't re-read EXT_CSD\n"); 741 return error; 742 } 743 if (ext_csd[EXT_CSD_HS_TIMING] != hs_timing) { 744 aprint_error_dev(sc->sc_dev, 745 "HS_TIMING set failed\n"); 746 return EINVAL; 747 } 748 } 749 750 if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 751 width = 8; 752 value = EXT_CSD_BUS_WIDTH_8; 753 } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 754 width = 4; 755 value = EXT_CSD_BUS_WIDTH_4; 756 } else { 757 width = 1; 758 value = EXT_CSD_BUS_WIDTH_1; 759 } 760 761 if (width != 1) { 762 error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 763 EXT_CSD_BUS_WIDTH, value); 764 if (error == 0) 765 error = sdmmc_chip_bus_width(sc->sc_sct, 766 sc->sc_sch, width); 767 else { 768 DPRINTF(("%s: can't change bus width" 769 " (%d bit)\n", SDMMCDEVNAME(sc), width)); 770 return error; 771 } 772 773 /* XXXX: need bus test? (using by CMD14 & CMD19) */ 774 } 775 sf->width = width; 776 } else { 777 if (sc->sc_busclk > sf->csd.tran_speed) 778 sc->sc_busclk = sf->csd.tran_speed; 779 error = 780 sdmmc_chip_bus_clock(sc->sc_sct, sc->sc_sch, sc->sc_busclk); 781 if (error) { 782 aprint_error_dev(sc->sc_dev, 783 "can't change bus clock\n"); 784 return error; 785 } 786 } 787 788 return 0; 789 } 790 791 static int 792 sdmmc_mem_send_cid(struct sdmmc_softc *sc, sdmmc_response *resp) 793 { 794 struct sdmmc_command cmd; 795 int error; 796 797 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 798 memset(&cmd, 0, sizeof cmd); 799 cmd.c_opcode = MMC_ALL_SEND_CID; 800 cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 801 802 error = sdmmc_mmc_command(sc, &cmd); 803 } else { 804 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CID, &cmd.c_resp, 805 sizeof(cmd.c_resp)); 806 } 807 808 #ifdef SDMMC_DEBUG 809 sdmmc_dump_data("CID", cmd.c_resp, sizeof(cmd.c_resp)); 810 #endif 811 if (error == 0 && resp != NULL) 812 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 813 return error; 814 } 815 816 static int 817 sdmmc_mem_send_csd(struct sdmmc_softc *sc, struct sdmmc_function *sf, 818 sdmmc_response *resp) 819 { 820 struct sdmmc_command cmd; 821 int error; 822 823 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 824 memset(&cmd, 0, sizeof cmd); 825 cmd.c_opcode = MMC_SEND_CSD; 826 cmd.c_arg = MMC_ARG_RCA(sf->rca); 827 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 828 829 error = sdmmc_mmc_command(sc, &cmd); 830 } else { 831 error = sdmmc_mem_send_cxd_data(sc, MMC_SEND_CSD, &cmd.c_resp, 832 sizeof(cmd.c_resp)); 833 } 834 835 #ifdef SDMMC_DEBUG 836 sdmmc_dump_data("CSD", cmd.c_resp, sizeof(cmd.c_resp)); 837 #endif 838 if (error == 0 && resp != NULL) 839 memcpy(resp, &cmd.c_resp, sizeof(*resp)); 840 return error; 841 } 842 843 static int 844 sdmmc_mem_send_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf, 845 uint32_t scr[2]) 846 { 847 struct sdmmc_command cmd; 848 bus_dma_segment_t ds[1]; 849 void *ptr = NULL; 850 int datalen = 8; 851 int rseg; 852 int error = 0; 853 854 /* Don't lock */ 855 856 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 857 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, 858 ds, 1, &rseg, BUS_DMA_NOWAIT); 859 if (error) 860 goto out; 861 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 862 BUS_DMA_NOWAIT); 863 if (error) 864 goto dmamem_free; 865 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 866 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 867 if (error) 868 goto dmamem_unmap; 869 870 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 871 BUS_DMASYNC_PREREAD); 872 } else { 873 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 874 if (ptr == NULL) 875 goto out; 876 } 877 878 memset(&cmd, 0, sizeof(cmd)); 879 cmd.c_data = ptr; 880 cmd.c_datalen = datalen; 881 cmd.c_blklen = datalen; 882 cmd.c_arg = 0; 883 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 884 cmd.c_opcode = SD_APP_SEND_SCR; 885 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 886 cmd.c_dmamap = sc->sc_dmap; 887 888 error = sdmmc_app_command(sc, sf, &cmd); 889 if (error == 0) { 890 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 891 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 892 BUS_DMASYNC_POSTREAD); 893 } 894 memcpy(scr, ptr, datalen); 895 } 896 897 out: 898 if (ptr != NULL) { 899 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 900 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 901 dmamem_unmap: 902 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 903 dmamem_free: 904 bus_dmamem_free(sc->sc_dmat, ds, rseg); 905 } else { 906 free(ptr, M_DEVBUF); 907 } 908 } 909 DPRINTF(("%s: sdmem_mem_send_scr: error = %d\n", SDMMCDEVNAME(sc), 910 error)); 911 912 #ifdef SDMMC_DEBUG 913 if (error == 0) 914 sdmmc_dump_data("SCR", scr, 8); 915 #endif 916 return error; 917 } 918 919 static int 920 sdmmc_mem_decode_scr(struct sdmmc_softc *sc, struct sdmmc_function *sf) 921 { 922 sdmmc_response resp; 923 int ver; 924 925 memset(resp, 0, sizeof(resp)); 926 /* 927 * Change the raw-scr received from the DMA stream to resp. 928 */ 929 resp[0] = be32toh(sf->raw_scr[1]); 930 resp[1] = be32toh(sf->raw_scr[0]) >> 8; 931 932 ver = SCR_STRUCTURE(resp); 933 sf->scr.sd_spec = SCR_SD_SPEC(resp); 934 sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 935 936 DPRINTF(("%s: sdmmc_mem_decode_scr: spec=%d, bus width=%d\n", 937 SDMMCDEVNAME(sc), sf->scr.sd_spec, sf->scr.bus_width)); 938 939 if (ver != 0) { 940 DPRINTF(("%s: unknown structure version: %d\n", 941 SDMMCDEVNAME(sc), ver)); 942 return EINVAL; 943 } 944 return 0; 945 } 946 947 static int 948 sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 949 size_t datalen) 950 { 951 struct sdmmc_command cmd; 952 bus_dma_segment_t ds[1]; 953 void *ptr = NULL; 954 int rseg; 955 int error = 0; 956 957 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 958 error = bus_dmamem_alloc(sc->sc_dmat, datalen, PAGE_SIZE, 0, ds, 959 1, &rseg, BUS_DMA_NOWAIT); 960 if (error) 961 goto out; 962 error = bus_dmamem_map(sc->sc_dmat, ds, 1, datalen, &ptr, 963 BUS_DMA_NOWAIT); 964 if (error) 965 goto dmamem_free; 966 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, datalen, 967 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 968 if (error) 969 goto dmamem_unmap; 970 971 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 972 BUS_DMASYNC_PREREAD); 973 } else { 974 ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 975 if (ptr == NULL) 976 goto out; 977 } 978 979 memset(&cmd, 0, sizeof(cmd)); 980 cmd.c_data = ptr; 981 cmd.c_datalen = datalen; 982 cmd.c_blklen = datalen; 983 cmd.c_opcode = opcode; 984 cmd.c_arg = 0; 985 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_SPI_R1; 986 if (opcode == MMC_SEND_EXT_CSD) 987 SET(cmd.c_flags, SCF_RSP_R1); 988 else 989 SET(cmd.c_flags, SCF_RSP_R2); 990 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 991 cmd.c_dmamap = sc->sc_dmap; 992 993 error = sdmmc_mmc_command(sc, &cmd); 994 if (error == 0) { 995 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 996 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 997 BUS_DMASYNC_POSTREAD); 998 } 999 memcpy(data, ptr, datalen); 1000 #ifdef SDMMC_DEBUG 1001 sdmmc_dump_data("CXD", data, datalen); 1002 #endif 1003 } 1004 1005 out: 1006 if (ptr != NULL) { 1007 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1008 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1009 dmamem_unmap: 1010 bus_dmamem_unmap(sc->sc_dmat, ptr, datalen); 1011 dmamem_free: 1012 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1013 } else { 1014 free(ptr, M_DEVBUF); 1015 } 1016 } 1017 return error; 1018 } 1019 1020 static int 1021 sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 1022 { 1023 struct sdmmc_softc *sc = sf->sc; 1024 struct sdmmc_command cmd; 1025 int error; 1026 1027 if (ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1028 return ENODEV; 1029 1030 memset(&cmd, 0, sizeof(cmd)); 1031 cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 1032 cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 1033 1034 switch (width) { 1035 case 1: 1036 cmd.c_arg = SD_ARG_BUS_WIDTH_1; 1037 break; 1038 1039 case 4: 1040 cmd.c_arg = SD_ARG_BUS_WIDTH_4; 1041 break; 1042 1043 default: 1044 return EINVAL; 1045 } 1046 1047 error = sdmmc_app_command(sc, sf, &cmd); 1048 if (error == 0) 1049 error = sdmmc_chip_bus_width(sc->sc_sct, sc->sc_sch, width); 1050 return error; 1051 } 1052 1053 static int 1054 sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 1055 int function, void *status) 1056 { 1057 struct sdmmc_softc *sc = sf->sc; 1058 struct sdmmc_command cmd; 1059 bus_dma_segment_t ds[1]; 1060 void *ptr = NULL; 1061 int gsft, rseg, error = 0; 1062 const int statlen = 64; 1063 1064 if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 1065 !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 1066 return EINVAL; 1067 1068 if (group <= 0 || group > 6 || 1069 function < 0 || function > 16) 1070 return EINVAL; 1071 1072 gsft = (group - 1) << 2; 1073 1074 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1075 error = bus_dmamem_alloc(sc->sc_dmat, statlen, PAGE_SIZE, 0, ds, 1076 1, &rseg, BUS_DMA_NOWAIT); 1077 if (error) 1078 goto out; 1079 error = bus_dmamem_map(sc->sc_dmat, ds, 1, statlen, &ptr, 1080 BUS_DMA_NOWAIT); 1081 if (error) 1082 goto dmamem_free; 1083 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, ptr, statlen, 1084 NULL, BUS_DMA_NOWAIT|BUS_DMA_STREAMING|BUS_DMA_READ); 1085 if (error) 1086 goto dmamem_unmap; 1087 1088 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1089 BUS_DMASYNC_PREREAD); 1090 } else { 1091 ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 1092 if (ptr == NULL) 1093 goto out; 1094 } 1095 1096 memset(&cmd, 0, sizeof(cmd)); 1097 cmd.c_data = ptr; 1098 cmd.c_datalen = statlen; 1099 cmd.c_blklen = statlen; 1100 cmd.c_opcode = SD_SEND_SWITCH_FUNC; 1101 cmd.c_arg = 1102 (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 1103 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1104 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 1105 cmd.c_dmamap = sc->sc_dmap; 1106 1107 error = sdmmc_mmc_command(sc, &cmd); 1108 if (error == 0) { 1109 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1110 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, statlen, 1111 BUS_DMASYNC_POSTREAD); 1112 } 1113 memcpy(status, ptr, statlen); 1114 } 1115 1116 out: 1117 if (ptr != NULL) { 1118 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1119 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1120 dmamem_unmap: 1121 bus_dmamem_unmap(sc->sc_dmat, ptr, statlen); 1122 dmamem_free: 1123 bus_dmamem_free(sc->sc_dmat, ds, rseg); 1124 } else { 1125 free(ptr, M_DEVBUF); 1126 } 1127 } 1128 return error; 1129 } 1130 1131 static int 1132 sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 1133 uint8_t value) 1134 { 1135 struct sdmmc_softc *sc = sf->sc; 1136 struct sdmmc_command cmd; 1137 1138 memset(&cmd, 0, sizeof(cmd)); 1139 cmd.c_opcode = MMC_SWITCH; 1140 cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 1141 (index << 16) | (value << 8) | set; 1142 cmd.c_flags = SCF_RSP_SPI_R1B | SCF_RSP_R1B | SCF_CMD_AC; 1143 1144 return sdmmc_mmc_command(sc, &cmd); 1145 } 1146 1147 /* 1148 * SPI mode function 1149 */ 1150 static int 1151 sdmmc_mem_spi_read_ocr(struct sdmmc_softc *sc, uint32_t hcs, uint32_t *card_ocr) 1152 { 1153 struct sdmmc_command cmd; 1154 int error; 1155 1156 memset(&cmd, 0, sizeof(cmd)); 1157 cmd.c_opcode = MMC_READ_OCR; 1158 cmd.c_arg = hcs ? MMC_OCR_HCS : 0; 1159 cmd.c_flags = SCF_RSP_SPI_R3; 1160 1161 error = sdmmc_mmc_command(sc, &cmd); 1162 if (error == 0 && card_ocr != NULL) 1163 *card_ocr = cmd.c_resp[1]; 1164 DPRINTF(("%s: sdmmc_mem_spi_read_ocr: error=%d, ocr=%#x\n", 1165 SDMMCDEVNAME(sc), error, cmd.c_resp[1])); 1166 return error; 1167 } 1168 1169 /* 1170 * read/write function 1171 */ 1172 /* read */ 1173 static int 1174 sdmmc_mem_single_read_block(struct sdmmc_function *sf, uint32_t blkno, 1175 u_char *data, size_t datalen) 1176 { 1177 struct sdmmc_softc *sc __unused = sf->sc; 1178 int error = 0; 1179 int i; 1180 1181 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1182 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1183 1184 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1185 error = sdmmc_mem_read_block_subr(sf, blkno + i, 1186 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1187 if (error) 1188 break; 1189 } 1190 return error; 1191 } 1192 1193 static int 1194 sdmmc_mem_read_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1195 u_char *data, size_t datalen) 1196 { 1197 struct sdmmc_softc *sc = sf->sc; 1198 struct sdmmc_command cmd; 1199 int error, bbuf, seg, off, len, num; 1200 1201 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1202 error = sdmmc_select_card(sc, sf); 1203 if (error) 1204 goto out; 1205 } 1206 1207 bbuf = 0; 1208 num = 0; 1209 seg = off = len = 0; 1210 retry: 1211 memset(&cmd, 0, sizeof(cmd)); 1212 cmd.c_data = data; 1213 cmd.c_datalen = datalen; 1214 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1215 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1216 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1217 cmd.c_arg = blkno; 1218 if (!ISSET(sf->flags, SFF_SDHC)) 1219 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1220 cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1 | SCF_RSP_SPI_R1; 1221 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1222 cmd.c_dmamap = sc->sc_dmap; 1223 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1224 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1225 len &= ~(SDMMC_SECTOR_SIZE - 1); 1226 cmd.c_datalen = len; 1227 cmd.c_dmaseg = seg; 1228 cmd.c_dmaoff = off; 1229 bbuf = 0; 1230 if (len == 0) { 1231 /* Use bounce buffer */ 1232 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1233 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1234 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1235 cmd.c_dmamap = sf->bbuf_dmap; 1236 cmd.c_dmaseg = 0; 1237 cmd.c_dmaoff = 0; 1238 bbuf = 1; 1239 len = SDMMC_SECTOR_SIZE; 1240 } 1241 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1242 MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 1243 } 1244 } 1245 1246 error = sdmmc_mmc_command(sc, &cmd); 1247 if (error) 1248 goto out; 1249 1250 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1251 if (cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 1252 memset(&cmd, 0, sizeof cmd); 1253 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1254 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1255 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1256 error = sdmmc_mmc_command(sc, &cmd); 1257 if (error) 1258 goto out; 1259 } 1260 } 1261 1262 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1263 do { 1264 memset(&cmd, 0, sizeof(cmd)); 1265 cmd.c_opcode = MMC_SEND_STATUS; 1266 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1267 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1268 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1269 error = sdmmc_mmc_command(sc, &cmd); 1270 if (error) 1271 break; 1272 /* XXX time out */ 1273 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1274 } 1275 1276 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1277 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1278 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1279 1280 if (bbuf) { 1281 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1282 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1283 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1284 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTREAD); 1285 memcpy(data, sf->bbuf, SDMMC_SECTOR_SIZE); 1286 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1287 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREREAD); 1288 } 1289 num += len; 1290 data += len; 1291 datalen -= len; 1292 blkno += (len / SDMMC_SECTOR_SIZE); 1293 1294 while (off + len >= dm_segs[seg].ds_len) { 1295 len -= dm_segs[seg++].ds_len; 1296 off = 0; 1297 } 1298 off += len; 1299 1300 if (seg < sc->sc_dmap->dm_nsegs) 1301 goto retry; 1302 } 1303 1304 out: 1305 return error; 1306 } 1307 1308 int 1309 sdmmc_mem_read_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1310 size_t datalen) 1311 { 1312 struct sdmmc_softc *sc = sf->sc; 1313 int error; 1314 1315 SDMMC_LOCK(sc); 1316 1317 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1318 error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 1319 goto out; 1320 } 1321 1322 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1323 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1324 goto out; 1325 } 1326 1327 /* DMA transfer */ 1328 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1329 BUS_DMA_NOWAIT|BUS_DMA_READ); 1330 if (error) 1331 goto out; 1332 1333 #ifdef SDMMC_DEBUG 1334 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1335 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1336 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1337 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1338 } 1339 #endif 1340 1341 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1342 BUS_DMASYNC_PREREAD); 1343 1344 error = sdmmc_mem_read_block_subr(sf, blkno, data, datalen); 1345 if (error) 1346 goto unload; 1347 1348 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1349 BUS_DMASYNC_POSTREAD); 1350 unload: 1351 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1352 1353 out: 1354 SDMMC_UNLOCK(sc); 1355 1356 return error; 1357 } 1358 1359 /* write */ 1360 static int 1361 sdmmc_mem_single_write_block(struct sdmmc_function *sf, uint32_t blkno, 1362 u_char *data, size_t datalen) 1363 { 1364 struct sdmmc_softc *sc __unused = sf->sc; 1365 int error = 0; 1366 int i; 1367 1368 KASSERT((datalen % SDMMC_SECTOR_SIZE) == 0); 1369 KASSERT(!ISSET(sc->sc_caps, SMC_CAPS_DMA)); 1370 1371 for (i = 0; i < datalen / SDMMC_SECTOR_SIZE; i++) { 1372 error = sdmmc_mem_write_block_subr(sf, blkno + i, 1373 data + i * SDMMC_SECTOR_SIZE, SDMMC_SECTOR_SIZE); 1374 if (error) 1375 break; 1376 } 1377 return error; 1378 } 1379 1380 static int 1381 sdmmc_mem_write_block_subr(struct sdmmc_function *sf, uint32_t blkno, 1382 u_char *data, size_t datalen) 1383 { 1384 struct sdmmc_softc *sc = sf->sc; 1385 struct sdmmc_command cmd; 1386 int error, bbuf, seg, off, len, num; 1387 1388 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1389 error = sdmmc_select_card(sc, sf); 1390 if (error) 1391 goto out; 1392 } 1393 1394 bbuf = 0; 1395 num = 0; 1396 seg = off = len = 0; 1397 retry: 1398 memset(&cmd, 0, sizeof(cmd)); 1399 cmd.c_data = data; 1400 cmd.c_datalen = datalen; 1401 cmd.c_blklen = SDMMC_SECTOR_SIZE; 1402 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1403 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1404 cmd.c_arg = blkno; 1405 if (!ISSET(sf->flags, SFF_SDHC)) 1406 cmd.c_arg <<= SDMMC_SECTOR_SIZE_SB; 1407 cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 1408 if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1409 cmd.c_dmamap = sc->sc_dmap; 1410 if (!ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1411 len = sc->sc_dmap->dm_segs[seg].ds_len - off; 1412 len &= ~(SDMMC_SECTOR_SIZE - 1); 1413 cmd.c_datalen = len; 1414 cmd.c_dmaseg = seg; 1415 cmd.c_dmaoff = off; 1416 bbuf = 0; 1417 if (len == 0) { 1418 /* Use bounce buffer */ 1419 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1420 SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1421 memcpy(sf->bbuf, data, SDMMC_SECTOR_SIZE); 1422 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, num, 1423 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1424 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 0, 1425 SDMMC_SECTOR_SIZE, BUS_DMASYNC_PREWRITE); 1426 cmd.c_datalen = SDMMC_SECTOR_SIZE; 1427 cmd.c_dmamap = sf->bbuf_dmap; 1428 cmd.c_dmaseg = 0; 1429 cmd.c_dmaoff = 0; 1430 bbuf = 1; 1431 len = SDMMC_SECTOR_SIZE; 1432 } 1433 cmd.c_opcode = (cmd.c_datalen / cmd.c_blklen) > 1 ? 1434 MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 1435 } 1436 } 1437 1438 error = sdmmc_mmc_command(sc, &cmd); 1439 if (error) 1440 goto out; 1441 1442 if (!ISSET(sc->sc_caps, SMC_CAPS_AUTO_STOP)) { 1443 if (cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1444 memset(&cmd, 0, sizeof(cmd)); 1445 cmd.c_opcode = MMC_STOP_TRANSMISSION; 1446 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B | SCF_RSP_SPI_R1B; 1447 error = sdmmc_mmc_command(sc, &cmd); 1448 if (error) 1449 goto out; 1450 } 1451 } 1452 1453 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) { 1454 do { 1455 memset(&cmd, 0, sizeof(cmd)); 1456 cmd.c_opcode = MMC_SEND_STATUS; 1457 if (!ISSET(sc->sc_caps, SMC_CAPS_SPI_MODE)) 1458 cmd.c_arg = MMC_ARG_RCA(sf->rca); 1459 cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1 | SCF_RSP_SPI_R2; 1460 error = sdmmc_mmc_command(sc, &cmd); 1461 if (error) 1462 break; 1463 /* XXX time out */ 1464 } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1465 } 1466 1467 if (ISSET(sc->sc_caps, SMC_CAPS_DMA) && 1468 !ISSET(sc->sc_caps, SMC_CAPS_MULTI_SEG_DMA)) { 1469 bus_dma_segment_t *dm_segs = sc->sc_dmap->dm_segs; 1470 1471 if (bbuf) 1472 bus_dmamap_sync(sc->sc_dmat, sf->bbuf_dmap, 1473 0, SDMMC_SECTOR_SIZE, BUS_DMASYNC_POSTWRITE); 1474 num += len; 1475 data += len; 1476 datalen -= len; 1477 blkno += (len / SDMMC_SECTOR_SIZE); 1478 1479 while (off + len >= dm_segs[seg].ds_len) { 1480 len -= dm_segs[seg++].ds_len; 1481 off = 0; 1482 } 1483 off += len; 1484 1485 if (seg < sc->sc_dmap->dm_nsegs) 1486 goto retry; 1487 } 1488 1489 out: 1490 return error; 1491 } 1492 1493 int 1494 sdmmc_mem_write_block(struct sdmmc_function *sf, uint32_t blkno, u_char *data, 1495 size_t datalen) 1496 { 1497 struct sdmmc_softc *sc = sf->sc; 1498 int error; 1499 1500 SDMMC_LOCK(sc); 1501 1502 if (sdmmc_chip_write_protect(sc->sc_sct, sc->sc_sch)) { 1503 aprint_normal_dev(sc->sc_dev, "write-protected\n"); 1504 error = EIO; 1505 goto out; 1506 } 1507 1508 if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1509 error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1510 goto out; 1511 } 1512 1513 if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1514 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1515 goto out; 1516 } 1517 1518 /* DMA transfer */ 1519 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, data, datalen, NULL, 1520 BUS_DMA_NOWAIT|BUS_DMA_WRITE); 1521 if (error) 1522 goto out; 1523 1524 #ifdef SDMMC_DEBUG 1525 for (int i = 0; i < sc->sc_dmap->dm_nsegs; i++) { 1526 printf("seg#%d: addr=%#lx, size=%#lx\n", i, 1527 (u_long)sc->sc_dmap->dm_segs[i].ds_addr, 1528 (u_long)sc->sc_dmap->dm_segs[i].ds_len); 1529 } 1530 #endif 1531 1532 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1533 BUS_DMASYNC_PREWRITE); 1534 1535 error = sdmmc_mem_write_block_subr(sf, blkno, data, datalen); 1536 if (error) 1537 goto unload; 1538 1539 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, datalen, 1540 BUS_DMASYNC_POSTWRITE); 1541 unload: 1542 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap); 1543 1544 out: 1545 SDMMC_UNLOCK(sc); 1546 1547 return error; 1548 } 1549