xref: /netbsd-src/sys/dev/sdmmc/sdmmc_ioreg.h (revision abb0f93cd77b67f080613360c65701f85e5f5cfe)
1 /*	$NetBSD: sdmmc_ioreg.h,v 1.1 2009/04/21 03:00:30 nonaka Exp $	*/
2 /*	$OpenBSD: sdmmc_ioreg.h,v 1.4 2007/06/02 01:48:37 uwe Exp $	*/
3 
4 /*
5  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef	_SDMMC_IOREG_H_
21 #define	_SDMMC_IOREG_H_
22 
23 /* SDIO commands */				/* response type */
24 #define SD_IO_SEND_OP_COND		5	/* R4 */
25 #define SD_IO_RW_DIRECT			52	/* R5 */
26 #define SD_IO_RW_EXTENDED		53	/* R5? */
27 
28 /* CMD52 arguments */
29 #define SD_ARG_CMD52_READ		(0<<31)
30 #define SD_ARG_CMD52_WRITE		(1<<31)
31 #define SD_ARG_CMD52_FUNC_SHIFT		28
32 #define SD_ARG_CMD52_FUNC_MASK		0x7
33 #define SD_ARG_CMD52_EXCHANGE		(1<<27)
34 #define SD_ARG_CMD52_REG_SHIFT		9
35 #define SD_ARG_CMD52_REG_MASK		0x1ffff
36 #define SD_ARG_CMD52_DATA_SHIFT		0
37 #define SD_ARG_CMD52_DATA_MASK		0xff
38 #define SD_R5_DATA(resp)		((resp)[0] & 0xff)
39 
40 /* CMD53 arguments */
41 #define SD_ARG_CMD53_READ		(0<<31)
42 #define SD_ARG_CMD53_WRITE		(1<<31)
43 #define SD_ARG_CMD53_FUNC_SHIFT		28
44 #define SD_ARG_CMD53_FUNC_MASK		0x7
45 #define SD_ARG_CMD53_BLOCK_MODE		(1<<27)
46 #define SD_ARG_CMD53_INCREMENT		(1<<26)
47 #define SD_ARG_CMD53_REG_SHIFT		9
48 #define SD_ARG_CMD53_REG_MASK		0x1ffff
49 #define SD_ARG_CMD53_LENGTH_SHIFT	0
50 #define SD_ARG_CMD53_LENGTH_MASK	0x1ff
51 #define SD_ARG_CMD53_LENGTH_MAX		64 /* XXX should be 511? */
52 
53 /* 48-bit response decoding (32 bits w/o CRC) */
54 #define MMC_R4(resp)			((resp)[0])
55 #define MMC_R5(resp)			((resp)[0])
56 
57 /* SD R4 response (IO OCR) */
58 #define SD_IO_OCR_MEM_READY		(1<<31)
59 #define SD_IO_OCR_NUM_FUNCTIONS(ocr)	(((ocr) >> 28) & 0x3)
60 /* XXX big fat memory present "flag" because we don't know better */
61 #define SD_IO_OCR_MEM_PRESENT		(0xf<<24)
62 #define SD_IO_OCR_MASK			0x00fffff0
63 
64 /* Card Common Control Registers (CCCR) */
65 #define SD_IO_CCCR_START		0x00000
66 #define SD_IO_CCCR_SIZE			0x100
67 #define SD_IO_CCCR_CCCR_SDIO_REV	0x00
68 #define SD_IO_CCCR_CCCR_REV(r)		((r) & 0xf)
69 #define  CCCR_CCCR_REV_1_00		0
70 #define  CCCR_CCCR_REV_1_10		1
71 #define SD_IO_CCCR_SDIO_REV(r)		(((r) >> 4) & 0xf)
72 #define  CCCR_SDIO_REV_1_00		0
73 #define  CCCR_SDIO_REV_1_10		1
74 #define SD_IO_CCCR_SPEC_REV		0x01
75 #define SD_IO_CCCR_SD_PHYS_SPEC_VER(r)	((r) & 0xf)
76 #define  CCCR_SD_PHYS_SPEC_VER_1_01	0
77 #define  CCCR_SD_PHYS_SPEC_VER_1_10	1
78 #define SD_IO_CCCR_FN_ENABLE		0x02
79 #define SD_IO_CCCR_FN_IOREADY		0x03
80 #define SD_IO_CCCR_FN_INTEN		0x04
81 #define  CCCR_INTEN_INTM		(1<<0)
82 #define SD_IO_CCCR_FN_INTPENDING	0x05
83 #define SD_IO_CCCR_CTL			0x06
84 #define  CCCR_CTL_RES			(1<<3)
85 #define SD_IO_CCCR_BUS_WIDTH		0x07
86 #define  CCCR_BUS_WIDTH_4		(1<<1)
87 #define  CCCR_BUS_WIDTH_1		(1<<0)
88 #define SD_IO_CCCR_CAPABILITY		0x08
89 #define  CCCR_CAPS_SDC			(1<<0)
90 #define  CCCR_CAPS_SMB			(1<<1) /* Multi-Block support */
91 #define  CCCR_CAPS_SRB			(1<<2) /* Read Wait support */
92 #define  CCCR_CAPS_SBS			(1<<3) /* Suspend/Resume support */
93 #define  CCCR_CAPS_S4MI			(1<<4) /* intr support in 4-bit mode */
94 #define  CCCR_CAPS_E4MI			(1<<5) /* enable intr in 4-bit mode */
95 #define  CCCR_CAPS_LSC			(1<<6) /* Low speed card */
96 #define  CCCR_CAPS_4BLS			(1<<7) /* 4-bit support for low speed */
97 #define SD_IO_CCCR_CISPTR		0x09 /* XXX 9-10, 10-11, or 9-12 */
98 #define SD_IO_CCCR_BUS_SUSPEND		0x0c
99 #define SD_IO_CCCR_FUNC_SELECT		0x0d
100 #define  CCCR_FUNC_FS(r)		((r) & 0xf)
101 #define  CCCR_FUNC_FS_FN(fn)		((fn) & 0x7)
102 #define  CCCR_FUNC_FS_MEM		8
103 #define SD_IO_CCCR_FN_EXEC_FLG		0x0e
104 #define SD_IO_CCCR_FN_READY_FLG		0x0f
105 #define SD_IO_CCCR_FN0_BLKSIZ		0x10 /* 0x10-0x11 */
106 #define SD_IO_CCCR_POWER_CTL		0x12
107 
108 /* Function Basic Registers (FBR) */
109 #define SD_IO_FBR_START			0x00100
110 #define SD_IO_FBR_SIZE			0x00700
111 
112 /* Card Information Structure (CIS) */
113 #define SD_IO_CIS_START			0x01000
114 #define SD_IO_CIS_SIZE			0x17000
115 
116 /* CIS tuple codes (based on PC Card 16) */
117 #define SD_IO_CISTPL_VERS_1		0x15
118 #define SD_IO_CISTPL_MANFID		0x20
119 #define SD_IO_CISTPL_FUNCID		0x21
120 #define SD_IO_CISTPL_FUNCE		0x22
121 
122 /* CISTPL_FUNCID codes */
123 #define SDMMC_FUNCTION_WLAN		0x0c
124 
125 #endif	/* _SDMMC_IOREG_H_ */
126