1 /* $NetBSD: sdhc.c,v 1.8 2010/10/07 12:06:10 kiyohara Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.8 2010/10/07 12:06:10 kiyohara Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/kthread.h> 32 #include <sys/malloc.h> 33 #include <sys/systm.h> 34 #include <sys/mutex.h> 35 #include <sys/condvar.h> 36 37 #include <dev/sdmmc/sdhcreg.h> 38 #include <dev/sdmmc/sdhcvar.h> 39 #include <dev/sdmmc/sdmmcchip.h> 40 #include <dev/sdmmc/sdmmcreg.h> 41 #include <dev/sdmmc/sdmmcvar.h> 42 43 #ifdef SDHC_DEBUG 44 int sdhcdebug = 1; 45 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 46 void sdhc_dump_regs(struct sdhc_host *); 47 #else 48 #define DPRINTF(n,s) do {} while (0) 49 #endif 50 51 #define SDHC_COMMAND_TIMEOUT hz 52 #define SDHC_BUFFER_TIMEOUT hz 53 #define SDHC_TRANSFER_TIMEOUT hz 54 #define SDHC_DMA_TIMEOUT hz 55 56 struct sdhc_host { 57 struct sdhc_softc *sc; /* host controller device */ 58 59 bus_space_tag_t iot; /* host register set tag */ 60 bus_space_handle_t ioh; /* host register set handle */ 61 bus_dma_tag_t dmat; /* host DMA tag */ 62 63 device_t sdmmc; /* generic SD/MMC device */ 64 65 struct kmutex host_mtx; 66 67 u_int clkbase; /* base clock frequency in KHz */ 68 int maxblklen; /* maximum block length */ 69 uint32_t ocr; /* OCR value from capabilities */ 70 71 uint8_t regs[14]; /* host controller state */ 72 73 uint16_t intr_status; /* soft interrupt status */ 74 uint16_t intr_error_status; /* soft error status */ 75 struct kmutex intr_mtx; 76 struct kcondvar intr_cv; 77 78 uint32_t flags; /* flags for this host */ 79 #define SHF_USE_DMA 0x0001 80 #define SHF_USE_4BIT_MODE 0x0002 81 }; 82 83 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 84 85 #define HREAD1(hp, reg) \ 86 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 87 #define HREAD2(hp, reg) \ 88 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 89 #define HREAD4(hp, reg) \ 90 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 91 #define HWRITE1(hp, reg, val) \ 92 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 93 #define HWRITE2(hp, reg, val) \ 94 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 95 #define HWRITE4(hp, reg, val) \ 96 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 97 #define HCLR1(hp, reg, bits) \ 98 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 99 #define HCLR2(hp, reg, bits) \ 100 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 101 #define HSET1(hp, reg, bits) \ 102 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 103 #define HSET2(hp, reg, bits) \ 104 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 105 106 static int sdhc_host_reset(sdmmc_chipset_handle_t); 107 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 108 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 109 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 110 static int sdhc_card_detect(sdmmc_chipset_handle_t); 111 static int sdhc_write_protect(sdmmc_chipset_handle_t); 112 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 113 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 114 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 115 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 116 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 117 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 118 static void sdhc_exec_command(sdmmc_chipset_handle_t, 119 struct sdmmc_command *); 120 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 121 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 122 static int sdhc_soft_reset(struct sdhc_host *, int); 123 static int sdhc_wait_intr(struct sdhc_host *, int, int); 124 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 125 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 126 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 127 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int); 128 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int); 129 130 static struct sdmmc_chip_functions sdhc_functions = { 131 /* host controller reset */ 132 sdhc_host_reset, 133 134 /* host controller capabilities */ 135 sdhc_host_ocr, 136 sdhc_host_maxblklen, 137 138 /* card detection */ 139 sdhc_card_detect, 140 141 /* write protect */ 142 sdhc_write_protect, 143 144 /* bus power, clock frequency and width */ 145 sdhc_bus_power, 146 sdhc_bus_clock, 147 sdhc_bus_width, 148 sdhc_bus_rod, 149 150 /* command execution */ 151 sdhc_exec_command, 152 153 /* card interrupt */ 154 sdhc_card_enable_intr, 155 sdhc_card_intr_ack 156 }; 157 158 /* 159 * Called by attachment driver. For each SD card slot there is one SD 160 * host controller standard register set. (1.3) 161 */ 162 int 163 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 164 bus_space_handle_t ioh, bus_size_t iosize) 165 { 166 struct sdmmcbus_attach_args saa; 167 struct sdhc_host *hp; 168 uint32_t caps; 169 #ifdef SDHC_DEBUG 170 uint16_t sdhcver; 171 172 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 173 aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version "); 174 switch (SDHC_SPEC_VERSION(sdhcver)) { 175 case 0x00: 176 aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 177 break; 178 179 default: 180 aprint_normal(">1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 181 break; 182 } 183 #endif 184 185 /* Allocate one more host structure. */ 186 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 187 if (hp == NULL) { 188 aprint_error_dev(sc->sc_dev, 189 "couldn't alloc memory (sdhc host)\n"); 190 goto err1; 191 } 192 sc->sc_host[sc->sc_nhosts++] = hp; 193 194 /* Fill in the new host structure. */ 195 hp->sc = sc; 196 hp->iot = iot; 197 hp->ioh = ioh; 198 hp->dmat = sc->sc_dmat; 199 200 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 201 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 202 cv_init(&hp->intr_cv, "sdhcintr"); 203 204 /* 205 * Reset the host controller and enable interrupts. 206 */ 207 (void)sdhc_host_reset(hp); 208 209 /* Determine host capabilities. */ 210 mutex_enter(&hp->host_mtx); 211 caps = HREAD4(hp, SDHC_CAPABILITIES); 212 mutex_exit(&hp->host_mtx); 213 214 #if notyet 215 /* Use DMA if the host system and the controller support it. */ 216 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 217 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 218 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 219 SET(hp->flags, SHF_USE_DMA); 220 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 221 } 222 #endif 223 224 /* 225 * Determine the base clock frequency. (2.2.24) 226 */ 227 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 228 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 229 if (hp->clkbase == 0) { 230 /* The attachment driver must tell us. */ 231 aprint_error_dev(sc->sc_dev, "unknown base clock frequency\n"); 232 goto err; 233 } else if (hp->clkbase < 10000 || hp->clkbase > 63000) { 234 /* SDHC 1.0 supports only 10-63 MHz. */ 235 aprint_error_dev(sc->sc_dev, 236 "base clock frequency out of range: %u MHz\n", 237 hp->clkbase / 1000); 238 goto err; 239 } 240 DPRINTF(1,("%s: base clock frequency %u MHz\n", 241 device_xname(sc->sc_dev), hp->clkbase / 1000)); 242 243 /* 244 * XXX Set the data timeout counter value according to 245 * capabilities. (2.2.15) 246 */ 247 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 248 249 /* 250 * Determine SD bus voltage levels supported by the controller. 251 */ 252 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 253 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 254 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 255 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 256 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 257 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 258 259 /* 260 * Determine the maximum block length supported by the host 261 * controller. (2.2.24) 262 */ 263 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 264 case SDHC_MAX_BLK_LEN_512: 265 hp->maxblklen = 512; 266 break; 267 268 case SDHC_MAX_BLK_LEN_1024: 269 hp->maxblklen = 1024; 270 break; 271 272 case SDHC_MAX_BLK_LEN_2048: 273 hp->maxblklen = 2048; 274 break; 275 276 default: 277 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 278 goto err; 279 } 280 DPRINTF(1, ("%s: max block length %u byte%s\n", 281 device_xname(sc->sc_dev), hp->maxblklen, 282 hp->maxblklen > 1 ? "s" : "")); 283 284 /* 285 * Attach the generic SD/MMC bus driver. (The bus driver must 286 * not invoke any chipset functions before it is attached.) 287 */ 288 memset(&saa, 0, sizeof(saa)); 289 saa.saa_busname = "sdmmc"; 290 saa.saa_sct = &sdhc_functions; 291 saa.saa_sch = hp; 292 saa.saa_dmat = hp->dmat; 293 saa.saa_clkmin = hp->clkbase / 256; 294 saa.saa_clkmax = hp->clkbase; 295 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 296 #if notyet 297 if (ISSET(hp->flags, SHF_USE_DMA)) 298 saa.saa_caps |= SMC_CAPS_DMA; 299 #endif 300 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 301 302 return 0; 303 304 err: 305 cv_destroy(&hp->intr_cv); 306 mutex_destroy(&hp->intr_mtx); 307 mutex_destroy(&hp->host_mtx); 308 free(hp, M_DEVBUF); 309 sc->sc_host[--sc->sc_nhosts] = NULL; 310 err1: 311 return 1; 312 } 313 314 int 315 sdhc_detach(device_t dev, int flags) 316 { 317 struct sdhc_host *hp = (struct sdhc_host *)dev; 318 struct sdhc_softc *sc = hp->sc; 319 int rv = 0; 320 321 if (hp->sdmmc) 322 rv = config_detach(hp->sdmmc, flags); 323 324 cv_destroy(&hp->intr_cv); 325 mutex_destroy(&hp->intr_mtx); 326 mutex_destroy(&hp->host_mtx); 327 free(hp, M_DEVBUF); 328 sc->sc_host[--sc->sc_nhosts] = NULL; 329 330 return rv; 331 } 332 333 bool 334 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 335 { 336 struct sdhc_softc *sc = device_private(dev); 337 struct sdhc_host *hp; 338 int n, i; 339 340 /* XXX poll for command completion or suspend command 341 * in progress */ 342 343 /* Save the host controller state. */ 344 for (n = 0; n < sc->sc_nhosts; n++) { 345 hp = sc->sc_host[n]; 346 for (i = 0; i < sizeof hp->regs; i++) 347 hp->regs[i] = HREAD1(hp, i); 348 } 349 return true; 350 } 351 352 bool 353 sdhc_resume(device_t dev, const pmf_qual_t *qual) 354 { 355 struct sdhc_softc *sc = device_private(dev); 356 struct sdhc_host *hp; 357 int n, i; 358 359 /* Restore the host controller state. */ 360 for (n = 0; n < sc->sc_nhosts; n++) { 361 hp = sc->sc_host[n]; 362 (void)sdhc_host_reset(hp); 363 for (i = 0; i < sizeof hp->regs; i++) 364 HWRITE1(hp, i, hp->regs[i]); 365 } 366 return true; 367 } 368 369 bool 370 sdhc_shutdown(device_t dev, int flags) 371 { 372 struct sdhc_softc *sc = device_private(dev); 373 struct sdhc_host *hp; 374 int i; 375 376 /* XXX chip locks up if we don't disable it before reboot. */ 377 for (i = 0; i < sc->sc_nhosts; i++) { 378 hp = sc->sc_host[i]; 379 (void)sdhc_host_reset(hp); 380 } 381 return true; 382 } 383 384 /* 385 * Reset the host controller. Called during initialization, when 386 * cards are removed, upon resume, and during error recovery. 387 */ 388 static int 389 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 390 { 391 struct sdhc_host *hp = (struct sdhc_host *)sch; 392 uint16_t sdhcimask; 393 int error; 394 395 /* Don't lock. */ 396 397 /* Disable all interrupts. */ 398 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 399 400 /* 401 * Reset the entire host controller and wait up to 100ms for 402 * the controller to clear the reset bit. 403 */ 404 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 405 if (error) 406 goto out; 407 408 /* Set data timeout counter value to max for now. */ 409 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 410 411 /* Enable interrupts. */ 412 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 413 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 414 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 415 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 416 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 417 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 418 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 419 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 420 421 out: 422 return error; 423 } 424 425 static int 426 sdhc_host_reset(sdmmc_chipset_handle_t sch) 427 { 428 struct sdhc_host *hp = (struct sdhc_host *)sch; 429 int error; 430 431 mutex_enter(&hp->host_mtx); 432 error = sdhc_host_reset1(sch); 433 mutex_exit(&hp->host_mtx); 434 435 return error; 436 } 437 438 static uint32_t 439 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 440 { 441 struct sdhc_host *hp = (struct sdhc_host *)sch; 442 443 return hp->ocr; 444 } 445 446 static int 447 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 448 { 449 struct sdhc_host *hp = (struct sdhc_host *)sch; 450 451 return hp->maxblklen; 452 } 453 454 /* 455 * Return non-zero if the card is currently inserted. 456 */ 457 static int 458 sdhc_card_detect(sdmmc_chipset_handle_t sch) 459 { 460 struct sdhc_host *hp = (struct sdhc_host *)sch; 461 int r; 462 463 mutex_enter(&hp->host_mtx); 464 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 465 mutex_exit(&hp->host_mtx); 466 467 if (r) 468 return 1; 469 return 0; 470 } 471 472 /* 473 * Return non-zero if the card is currently write-protected. 474 */ 475 static int 476 sdhc_write_protect(sdmmc_chipset_handle_t sch) 477 { 478 struct sdhc_host *hp = (struct sdhc_host *)sch; 479 int r; 480 481 mutex_enter(&hp->host_mtx); 482 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 483 mutex_exit(&hp->host_mtx); 484 485 if (!r) 486 return 1; 487 return 0; 488 } 489 490 /* 491 * Set or change SD bus voltage and enable or disable SD bus power. 492 * Return zero on success. 493 */ 494 static int 495 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 496 { 497 struct sdhc_host *hp = (struct sdhc_host *)sch; 498 uint8_t vdd; 499 int error = 0; 500 501 mutex_enter(&hp->host_mtx); 502 503 /* 504 * Disable bus power before voltage change. 505 */ 506 if (!(hp->sc->sc_flags & SDHC_FLAG_NO_PWR0)) 507 HWRITE1(hp, SDHC_POWER_CTL, 0); 508 509 /* If power is disabled, reset the host and return now. */ 510 if (ocr == 0) { 511 (void)sdhc_host_reset1(hp); 512 goto out; 513 } 514 515 /* 516 * Select the lowest voltage according to capabilities. 517 */ 518 ocr &= hp->ocr; 519 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) 520 vdd = SDHC_VOLTAGE_1_8V; 521 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 522 vdd = SDHC_VOLTAGE_3_0V; 523 else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 524 vdd = SDHC_VOLTAGE_3_3V; 525 else { 526 /* Unsupported voltage level requested. */ 527 error = EINVAL; 528 goto out; 529 } 530 531 /* 532 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 533 * voltage ramp until power rises. 534 */ 535 HWRITE1(hp, SDHC_POWER_CTL, 536 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 537 sdmmc_delay(10000); 538 539 /* 540 * The host system may not power the bus due to battery low, 541 * etc. In that case, the host controller should clear the 542 * bus power bit. 543 */ 544 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 545 error = ENXIO; 546 goto out; 547 } 548 549 out: 550 mutex_exit(&hp->host_mtx); 551 552 return error; 553 } 554 555 /* 556 * Return the smallest possible base clock frequency divisor value 557 * for the CLOCK_CTL register to produce `freq' (KHz). 558 */ 559 static int 560 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 561 { 562 int div; 563 564 for (div = 1; div <= 256; div *= 2) 565 if ((hp->clkbase / div) <= freq) 566 return (div / 2); 567 /* No divisor found. */ 568 return -1; 569 } 570 571 /* 572 * Set or change SDCLK frequency or disable the SD clock. 573 * Return zero on success. 574 */ 575 static int 576 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 577 { 578 struct sdhc_host *hp = (struct sdhc_host *)sch; 579 int div; 580 int timo; 581 int error = 0; 582 #ifdef DIAGNOSTIC 583 int ispresent; 584 #endif 585 586 #ifdef DIAGNOSTIC 587 mutex_enter(&hp->host_mtx); 588 ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 589 mutex_exit(&hp->host_mtx); 590 591 /* Must not stop the clock if commands are in progress. */ 592 if (ispresent && sdhc_card_detect(hp)) 593 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 594 device_xname(hp->sc->sc_dev)); 595 #endif 596 597 mutex_enter(&hp->host_mtx); 598 599 /* 600 * Stop SD clock before changing the frequency. 601 */ 602 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 603 if (freq == SDMMC_SDCLK_OFF) 604 goto out; 605 606 /* 607 * Set the minimum base clock frequency divisor. 608 */ 609 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 610 /* Invalid base clock frequency or `freq' value. */ 611 error = EINVAL; 612 goto out; 613 } 614 HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT); 615 616 /* 617 * Start internal clock. Wait 10ms for stabilization. 618 */ 619 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 620 for (timo = 1000; timo > 0; timo--) { 621 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 622 break; 623 sdmmc_delay(10); 624 } 625 if (timo == 0) { 626 error = ETIMEDOUT; 627 goto out; 628 } 629 630 /* 631 * Enable SD clock. 632 */ 633 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 634 635 if (freq > 25000) 636 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 637 else 638 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 639 640 out: 641 mutex_exit(&hp->host_mtx); 642 643 return error; 644 } 645 646 static int 647 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 648 { 649 struct sdhc_host *hp = (struct sdhc_host *)sch; 650 int reg; 651 652 switch (width) { 653 case 1: 654 case 4: 655 break; 656 657 default: 658 DPRINTF(0,("%s: unsupported bus width (%d)\n", 659 HDEVNAME(hp), width)); 660 return 1; 661 } 662 663 mutex_enter(&hp->host_mtx); 664 reg = HREAD1(hp, SDHC_HOST_CTL); 665 reg &= ~SDHC_4BIT_MODE; 666 if (width == 4) 667 reg |= SDHC_4BIT_MODE; 668 HWRITE1(hp, SDHC_HOST_CTL, reg); 669 mutex_exit(&hp->host_mtx); 670 671 return 0; 672 } 673 674 static int 675 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 676 { 677 678 /* Nothing ?? */ 679 return 0; 680 } 681 682 static void 683 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 684 { 685 struct sdhc_host *hp = (struct sdhc_host *)sch; 686 687 mutex_enter(&hp->host_mtx); 688 if (enable) { 689 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 690 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 691 } else { 692 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 693 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 694 } 695 mutex_exit(&hp->host_mtx); 696 } 697 698 static void 699 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 700 { 701 struct sdhc_host *hp = (struct sdhc_host *)sch; 702 703 mutex_enter(&hp->host_mtx); 704 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 705 mutex_exit(&hp->host_mtx); 706 } 707 708 static int 709 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 710 { 711 uint32_t state; 712 int timeout; 713 714 for (timeout = 10; timeout > 0; timeout--) { 715 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 716 return 0; 717 sdmmc_delay(10000); 718 } 719 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 720 value, state)); 721 return ETIMEDOUT; 722 } 723 724 static void 725 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 726 { 727 struct sdhc_host *hp = (struct sdhc_host *)sch; 728 int error; 729 730 /* 731 * Start the MMC command, or mark `cmd' as failed and return. 732 */ 733 error = sdhc_start_command(hp, cmd); 734 if (error) { 735 cmd->c_error = error; 736 goto out; 737 } 738 739 /* 740 * Wait until the command phase is done, or until the command 741 * is marked done for any other reason. 742 */ 743 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 744 cmd->c_error = ETIMEDOUT; 745 goto out; 746 } 747 748 /* 749 * The host controller removes bits [0:7] from the response 750 * data (CRC) and we pass the data up unchanged to the bus 751 * driver (without padding). 752 */ 753 mutex_enter(&hp->host_mtx); 754 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 755 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 756 uint8_t *p = (uint8_t *)cmd->c_resp; 757 int i; 758 759 for (i = 0; i < 15; i++) 760 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 761 } else { 762 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 763 } 764 } 765 mutex_exit(&hp->host_mtx); 766 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 767 768 /* 769 * If the command has data to transfer in any direction, 770 * execute the transfer now. 771 */ 772 if (cmd->c_error == 0 && cmd->c_data != NULL) 773 sdhc_transfer_data(hp, cmd); 774 775 out: 776 mutex_enter(&hp->host_mtx); 777 /* Turn off the LED. */ 778 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 779 mutex_exit(&hp->host_mtx); 780 SET(cmd->c_flags, SCF_ITSDONE); 781 782 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 783 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 784 cmd->c_flags, cmd->c_error)); 785 } 786 787 static int 788 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 789 { 790 uint16_t blksize = 0; 791 uint16_t blkcount = 0; 792 uint16_t mode; 793 uint16_t command; 794 int error; 795 796 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x\n", 797 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 798 cmd->c_datalen, cmd->c_flags)); 799 800 /* 801 * The maximum block length for commands should be the minimum 802 * of the host buffer size and the card buffer size. (1.7.2) 803 */ 804 805 /* Fragment the data into proper blocks. */ 806 if (cmd->c_datalen > 0) { 807 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 808 blkcount = cmd->c_datalen / blksize; 809 if (cmd->c_datalen % blksize > 0) { 810 /* XXX: Split this command. (1.7.4) */ 811 aprint_error_dev(hp->sc->sc_dev, 812 "data not a multiple of %u bytes\n", blksize); 813 return EINVAL; 814 } 815 } 816 817 /* Check limit imposed by 9-bit block count. (1.7.2) */ 818 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 819 aprint_error_dev(hp->sc->sc_dev, "too much data\n"); 820 return EINVAL; 821 } 822 823 /* Prepare transfer mode register value. (2.2.5) */ 824 mode = 0; 825 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 826 mode |= SDHC_READ_MODE; 827 if (blkcount > 0) { 828 mode |= SDHC_BLOCK_COUNT_ENABLE; 829 if (blkcount > 1) { 830 mode |= SDHC_MULTI_BLOCK_MODE; 831 /* XXX only for memory commands? */ 832 mode |= SDHC_AUTO_CMD12_ENABLE; 833 } 834 } 835 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 836 if (cmd->c_dmamap->dm_nsegs == 1) { 837 mode |= SDHC_DMA_ENABLE; 838 } else { 839 cmd->c_dmamap = NULL; 840 } 841 } 842 843 /* 844 * Prepare command register value. (2.2.6) 845 */ 846 command = 847 (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 848 849 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 850 command |= SDHC_CRC_CHECK_ENABLE; 851 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 852 command |= SDHC_INDEX_CHECK_ENABLE; 853 if (cmd->c_data != NULL) 854 command |= SDHC_DATA_PRESENT_SELECT; 855 856 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 857 command |= SDHC_NO_RESPONSE; 858 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 859 command |= SDHC_RESP_LEN_136; 860 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 861 command |= SDHC_RESP_LEN_48_CHK_BUSY; 862 else 863 command |= SDHC_RESP_LEN_48; 864 865 /* Wait until command and data inhibit bits are clear. (1.5) */ 866 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 867 if (error) 868 return error; 869 870 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 871 HDEVNAME(hp), blksize, blkcount, mode, command)); 872 873 mutex_enter(&hp->host_mtx); 874 875 /* Alert the user not to remove the card. */ 876 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 877 878 /* Set DMA start address. */ 879 if (ISSET(mode, SDHC_DMA_ENABLE)) 880 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 881 882 /* 883 * Start a CPU data transfer. Writing to the high order byte 884 * of the SDHC_COMMAND register triggers the SD command. (1.5) 885 */ 886 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 887 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 888 if (blkcount > 1) 889 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 890 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 891 HWRITE2(hp, SDHC_COMMAND, command); 892 893 mutex_exit(&hp->host_mtx); 894 895 return 0; 896 } 897 898 static void 899 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 900 { 901 int error; 902 903 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 904 MMC_R1(cmd->c_resp), cmd->c_datalen)); 905 906 #ifdef SDHC_DEBUG 907 /* XXX I forgot why I wanted to know when this happens :-( */ 908 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 909 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 910 aprint_error_dev(hp->sc->sc_dev, 911 "CMD52/53 error response flags %#x\n", 912 MMC_R1(cmd->c_resp) & 0xff00); 913 } 914 #endif 915 916 if (cmd->c_dmamap != NULL) 917 error = sdhc_transfer_data_dma(hp, cmd); 918 else 919 error = sdhc_transfer_data_pio(hp, cmd); 920 if (error) 921 cmd->c_error = error; 922 SET(cmd->c_flags, SCF_ITSDONE); 923 924 DPRINTF(1,("%s: data transfer done (error=%d)\n", 925 HDEVNAME(hp), cmd->c_error)); 926 } 927 928 static int 929 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 930 { 931 bus_dmamap_t dmap = cmd->c_dmamap; 932 uint16_t blklen = cmd->c_blklen; 933 uint16_t blkcnt = cmd->c_datalen / blklen; 934 uint16_t remain; 935 int error = 0; 936 937 for (;;) { 938 if (!sdhc_wait_intr(hp, 939 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 940 SDHC_DMA_TIMEOUT)) { 941 error = ETIMEDOUT; 942 break; 943 } 944 945 /* single block mode */ 946 if (blkcnt == 1) 947 break; 948 949 /* multi block mode */ 950 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 951 if (remain == 0) 952 break; 953 954 HWRITE4(hp, SDHC_DMA_ADDR, 955 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 956 } 957 958 #if 0 959 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 960 SDHC_TRANSFER_TIMEOUT)) 961 error = ETIMEDOUT; 962 #endif 963 964 return error; 965 } 966 967 static int 968 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 969 { 970 uint8_t *data = cmd->c_data; 971 int len, datalen; 972 int mask; 973 int error = 0; 974 975 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 976 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 977 datalen = cmd->c_datalen; 978 979 while (datalen > 0) { 980 if (!sdhc_wait_intr(hp, 981 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY, 982 SDHC_BUFFER_TIMEOUT)) { 983 error = ETIMEDOUT; 984 break; 985 } 986 987 error = sdhc_wait_state(hp, mask, mask); 988 if (error) 989 break; 990 991 len = MIN(datalen, cmd->c_blklen); 992 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 993 sdhc_read_data_pio(hp, data, len); 994 else 995 sdhc_write_data_pio(hp, data, len); 996 997 data += len; 998 datalen -= len; 999 } 1000 1001 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1002 SDHC_TRANSFER_TIMEOUT)) 1003 error = ETIMEDOUT; 1004 1005 return error; 1006 } 1007 1008 static void 1009 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 1010 { 1011 1012 if (((__uintptr_t)data & 3) == 0) { 1013 while (datalen > 3) { 1014 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1015 data += 4; 1016 datalen -= 4; 1017 } 1018 if (datalen > 1) { 1019 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1020 data += 2; 1021 datalen -= 2; 1022 } 1023 if (datalen > 0) { 1024 *data = HREAD1(hp, SDHC_DATA); 1025 data += 1; 1026 datalen -= 1; 1027 } 1028 } else if (((__uintptr_t)data & 1) == 0) { 1029 while (datalen > 1) { 1030 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1031 data += 2; 1032 datalen -= 2; 1033 } 1034 if (datalen > 0) { 1035 *data = HREAD1(hp, SDHC_DATA); 1036 data += 1; 1037 datalen -= 1; 1038 } 1039 } else { 1040 while (datalen > 0) { 1041 *data = HREAD1(hp, SDHC_DATA); 1042 data += 1; 1043 datalen -= 1; 1044 } 1045 } 1046 } 1047 1048 static void 1049 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 1050 { 1051 1052 if (((__uintptr_t)data & 3) == 0) { 1053 while (datalen > 3) { 1054 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1055 data += 4; 1056 datalen -= 4; 1057 } 1058 if (datalen > 1) { 1059 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1060 data += 2; 1061 datalen -= 2; 1062 } 1063 if (datalen > 0) { 1064 HWRITE1(hp, SDHC_DATA, *data); 1065 data += 1; 1066 datalen -= 1; 1067 } 1068 } else if (((__uintptr_t)data & 1) == 0) { 1069 while (datalen > 1) { 1070 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1071 data += 2; 1072 datalen -= 2; 1073 } 1074 if (datalen > 0) { 1075 HWRITE1(hp, SDHC_DATA, *data); 1076 data += 1; 1077 datalen -= 1; 1078 } 1079 } else { 1080 while (datalen > 0) { 1081 HWRITE1(hp, SDHC_DATA, *data); 1082 data += 1; 1083 datalen -= 1; 1084 } 1085 } 1086 } 1087 1088 /* Prepare for another command. */ 1089 static int 1090 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1091 { 1092 int timo; 1093 1094 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1095 1096 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1097 for (timo = 10; timo > 0; timo--) { 1098 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1099 break; 1100 sdmmc_delay(10000); 1101 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1102 } 1103 if (timo == 0) { 1104 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1105 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1106 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1107 return ETIMEDOUT; 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int 1114 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1115 { 1116 int status; 1117 1118 mask |= SDHC_ERROR_INTERRUPT; 1119 1120 mutex_enter(&hp->intr_mtx); 1121 status = hp->intr_status & mask; 1122 while (status == 0) { 1123 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1124 == EWOULDBLOCK) { 1125 status |= SDHC_ERROR_INTERRUPT; 1126 break; 1127 } 1128 status = hp->intr_status & mask; 1129 } 1130 hp->intr_status &= ~status; 1131 1132 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1133 hp->intr_error_status)); 1134 1135 /* Command timeout has higher priority than command complete. */ 1136 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1137 hp->intr_error_status = 0; 1138 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1139 status = 0; 1140 } 1141 mutex_exit(&hp->intr_mtx); 1142 1143 return status; 1144 } 1145 1146 /* 1147 * Established by attachment driver at interrupt priority IPL_SDMMC. 1148 */ 1149 int 1150 sdhc_intr(void *arg) 1151 { 1152 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1153 struct sdhc_host *hp; 1154 int host; 1155 int done = 0; 1156 uint16_t status; 1157 uint16_t error; 1158 1159 /* We got an interrupt, but we don't know from which slot. */ 1160 for (host = 0; host < sc->sc_nhosts; host++) { 1161 hp = sc->sc_host[host]; 1162 if (hp == NULL) 1163 continue; 1164 1165 /* Find out which interrupts are pending. */ 1166 status = HREAD2(hp, SDHC_NINTR_STATUS); 1167 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1168 continue; /* no interrupt for us */ 1169 1170 /* Acknowledge the interrupts we are about to handle. */ 1171 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1172 DPRINTF(2,("%s: interrupt status=%x\n", HDEVNAME(hp), 1173 status)); 1174 1175 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1176 continue; 1177 1178 /* Claim this interrupt. */ 1179 done = 1; 1180 1181 /* 1182 * Service error interrupts. 1183 */ 1184 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1185 /* Acknowledge error interrupts. */ 1186 error = HREAD2(hp, SDHC_EINTR_STATUS); 1187 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1188 DPRINTF(2,("%s: error interrupt, status=%x\n", 1189 HDEVNAME(hp), error)); 1190 1191 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1192 SDHC_DATA_TIMEOUT_ERROR)) { 1193 hp->intr_error_status |= error; 1194 hp->intr_status |= status; 1195 cv_broadcast(&hp->intr_cv); 1196 } 1197 } 1198 1199 /* 1200 * Wake up the sdmmc event thread to scan for cards. 1201 */ 1202 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1203 sdmmc_needs_discover(hp->sdmmc); 1204 1205 /* 1206 * Wake up the blocking process to service command 1207 * related interrupt(s). 1208 */ 1209 if (ISSET(status, SDHC_BUFFER_READ_READY| 1210 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1211 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1212 hp->intr_status |= status; 1213 cv_broadcast(&hp->intr_cv); 1214 } 1215 1216 /* 1217 * Service SD card interrupts. 1218 */ 1219 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1220 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1221 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1222 sdmmc_card_intr(hp->sdmmc); 1223 } 1224 } 1225 1226 return done; 1227 } 1228 1229 #ifdef SDHC_DEBUG 1230 void 1231 sdhc_dump_regs(struct sdhc_host *hp) 1232 { 1233 1234 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1235 HREAD4(hp, SDHC_PRESENT_STATE)); 1236 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1237 HREAD1(hp, SDHC_POWER_CTL)); 1238 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1239 HREAD2(hp, SDHC_NINTR_STATUS)); 1240 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1241 HREAD2(hp, SDHC_EINTR_STATUS)); 1242 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1243 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1244 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1245 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1246 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1247 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1248 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1249 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1250 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1251 HREAD4(hp, SDHC_CAPABILITIES)); 1252 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1253 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1254 } 1255 #endif 1256