1 /* $NetBSD: sdhc.c,v 1.13 2012/03/15 18:37:43 bouyer Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.13 2012/03/15 18:37:43 bouyer Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85 #define SHF_USE_DMA 0x0001 86 #define SHF_USE_4BIT_MODE 0x0002 87 #define SHF_USE_8BIT_MODE 0x0004 88 }; 89 90 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 92 static uint8_t 93 hread1(struct sdhc_host *hp, bus_size_t reg) 94 { 95 96 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 97 return bus_space_read_1(hp->iot, hp->ioh, reg); 98 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 99 } 100 101 static uint16_t 102 hread2(struct sdhc_host *hp, bus_size_t reg) 103 { 104 105 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 106 return bus_space_read_2(hp->iot, hp->ioh, reg); 107 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 108 } 109 110 #define HREAD1(hp, reg) hread1(hp, reg) 111 #define HREAD2(hp, reg) hread2(hp, reg) 112 #define HREAD4(hp, reg) \ 113 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 114 115 116 static void 117 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 118 { 119 120 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 121 bus_space_write_1(hp->iot, hp->ioh, o, val); 122 } else { 123 const size_t shift = 8 * (o & 3); 124 o &= -4; 125 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 126 tmp = (val << shift) | (tmp & ~(0xff << shift)); 127 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 128 } 129 } 130 131 static void 132 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 133 { 134 135 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 136 bus_space_write_2(hp->iot, hp->ioh, o, val); 137 } else { 138 const size_t shift = 8 * (o & 2); 139 o &= -4; 140 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 141 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 142 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 143 } 144 } 145 146 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 147 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 148 #define HWRITE4(hp, reg, val) \ 149 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 150 151 #define HCLR1(hp, reg, bits) \ 152 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 153 #define HCLR2(hp, reg, bits) \ 154 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 155 #define HCLR4(hp, reg, bits) \ 156 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 157 #define HSET1(hp, reg, bits) \ 158 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 159 #define HSET2(hp, reg, bits) \ 160 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 161 #define HSET4(hp, reg, bits) \ 162 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 163 164 static int sdhc_host_reset(sdmmc_chipset_handle_t); 165 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 166 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 167 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 168 static int sdhc_card_detect(sdmmc_chipset_handle_t); 169 static int sdhc_write_protect(sdmmc_chipset_handle_t); 170 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 171 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 172 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 174 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 176 static void sdhc_exec_command(sdmmc_chipset_handle_t, 177 struct sdmmc_command *); 178 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 179 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 180 static int sdhc_soft_reset(struct sdhc_host *, int); 181 static int sdhc_wait_intr(struct sdhc_host *, int, int); 182 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 183 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 185 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 186 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 190 191 static struct sdmmc_chip_functions sdhc_functions = { 192 /* host controller reset */ 193 sdhc_host_reset, 194 195 /* host controller capabilities */ 196 sdhc_host_ocr, 197 sdhc_host_maxblklen, 198 199 /* card detection */ 200 sdhc_card_detect, 201 202 /* write protect */ 203 sdhc_write_protect, 204 205 /* bus power, clock frequency and width */ 206 sdhc_bus_power, 207 sdhc_bus_clock, 208 sdhc_bus_width, 209 sdhc_bus_rod, 210 211 /* command execution */ 212 sdhc_exec_command, 213 214 /* card interrupt */ 215 sdhc_card_enable_intr, 216 sdhc_card_intr_ack 217 }; 218 219 /* 220 * Called by attachment driver. For each SD card slot there is one SD 221 * host controller standard register set. (1.3) 222 */ 223 int 224 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 225 bus_space_handle_t ioh, bus_size_t iosize) 226 { 227 struct sdmmcbus_attach_args saa; 228 struct sdhc_host *hp; 229 uint32_t caps; 230 uint16_t sdhcver; 231 232 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 233 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 234 switch (SDHC_SPEC_VERSION(sdhcver)) { 235 case SDHC_SPEC_VERS_100: 236 aprint_normal("1.0"); 237 break; 238 239 case SDHC_SPEC_VERS_200: 240 aprint_normal("2.0"); 241 break; 242 243 case SDHC_SPEC_VERS_300: 244 aprint_normal("3.0"); 245 break; 246 247 default: 248 aprint_normal("unknown version(0x%x)", 249 SDHC_SPEC_VERSION(sdhcver)); 250 break; 251 } 252 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 253 254 /* Allocate one more host structure. */ 255 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 256 if (hp == NULL) { 257 aprint_error_dev(sc->sc_dev, 258 "couldn't alloc memory (sdhc host)\n"); 259 goto err1; 260 } 261 sc->sc_host[sc->sc_nhosts++] = hp; 262 263 /* Fill in the new host structure. */ 264 hp->sc = sc; 265 hp->iot = iot; 266 hp->ioh = ioh; 267 hp->dmat = sc->sc_dmat; 268 hp->specver = SDHC_SPEC_VERSION(sdhcver); 269 270 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 271 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 272 cv_init(&hp->intr_cv, "sdhcintr"); 273 274 /* 275 * Reset the host controller and enable interrupts. 276 */ 277 (void)sdhc_host_reset(hp); 278 279 /* Determine host capabilities. */ 280 mutex_enter(&hp->host_mtx); 281 caps = HREAD4(hp, SDHC_CAPABILITIES); 282 mutex_exit(&hp->host_mtx); 283 284 #if notyet 285 /* Use DMA if the host system and the controller support it. */ 286 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 287 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 288 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 289 SET(hp->flags, SHF_USE_DMA); 290 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 291 } 292 #endif 293 294 /* 295 * Determine the base clock frequency. (2.2.24) 296 */ 297 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 298 if (hp->clkbase == 0) { 299 if (sc->sc_clkbase == 0) { 300 /* The attachment driver must tell us. */ 301 aprint_error_dev(sc->sc_dev, 302 "unknown base clock frequency\n"); 303 goto err; 304 } 305 hp->clkbase = sc->sc_clkbase; 306 } 307 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 308 /* SDHC 1.0 supports only 10-63 MHz. */ 309 aprint_error_dev(sc->sc_dev, 310 "base clock frequency out of range: %u MHz\n", 311 hp->clkbase / 1000); 312 goto err; 313 } 314 DPRINTF(1,("%s: base clock frequency %u MHz\n", 315 device_xname(sc->sc_dev), hp->clkbase / 1000)); 316 317 /* 318 * XXX Set the data timeout counter value according to 319 * capabilities. (2.2.15) 320 */ 321 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 322 #if 0 323 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 324 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 325 #endif 326 327 /* 328 * Determine SD bus voltage levels supported by the controller. 329 */ 330 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 331 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 332 } 333 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 334 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 335 } 336 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 337 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 338 } 339 340 /* 341 * Determine the maximum block length supported by the host 342 * controller. (2.2.24) 343 */ 344 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 345 case SDHC_MAX_BLK_LEN_512: 346 hp->maxblklen = 512; 347 break; 348 349 case SDHC_MAX_BLK_LEN_1024: 350 hp->maxblklen = 1024; 351 break; 352 353 case SDHC_MAX_BLK_LEN_2048: 354 hp->maxblklen = 2048; 355 break; 356 357 case SDHC_MAX_BLK_LEN_4096: 358 hp->maxblklen = 4096; 359 break; 360 361 default: 362 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 363 goto err; 364 } 365 DPRINTF(1, ("%s: max block length %u byte%s\n", 366 device_xname(sc->sc_dev), hp->maxblklen, 367 hp->maxblklen > 1 ? "s" : "")); 368 369 /* 370 * Attach the generic SD/MMC bus driver. (The bus driver must 371 * not invoke any chipset functions before it is attached.) 372 */ 373 memset(&saa, 0, sizeof(saa)); 374 saa.saa_busname = "sdmmc"; 375 saa.saa_sct = &sdhc_functions; 376 saa.saa_sch = hp; 377 saa.saa_dmat = hp->dmat; 378 saa.saa_clkmin = hp->clkbase / 256; 379 saa.saa_clkmax = hp->clkbase; 380 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 381 saa.saa_clkmin /= 2046; 382 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 383 saa.saa_clkmin /= 16; 384 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 385 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 386 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 387 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 388 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 389 #if notyet 390 if (ISSET(hp->flags, SHF_USE_DMA)) 391 saa.saa_caps |= SMC_CAPS_DMA; 392 #endif 393 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 394 395 return 0; 396 397 err: 398 cv_destroy(&hp->intr_cv); 399 mutex_destroy(&hp->intr_mtx); 400 mutex_destroy(&hp->host_mtx); 401 free(hp, M_DEVBUF); 402 sc->sc_host[--sc->sc_nhosts] = NULL; 403 err1: 404 return 1; 405 } 406 407 int 408 sdhc_detach(device_t dev, int flags) 409 { 410 struct sdhc_host *hp = (struct sdhc_host *)dev; 411 struct sdhc_softc *sc = hp->sc; 412 int rv = 0; 413 414 if (hp->sdmmc) 415 rv = config_detach(hp->sdmmc, flags); 416 417 cv_destroy(&hp->intr_cv); 418 mutex_destroy(&hp->intr_mtx); 419 mutex_destroy(&hp->host_mtx); 420 free(hp, M_DEVBUF); 421 sc->sc_host[--sc->sc_nhosts] = NULL; 422 423 return rv; 424 } 425 426 bool 427 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 428 { 429 struct sdhc_softc *sc = device_private(dev); 430 struct sdhc_host *hp; 431 size_t i; 432 433 /* XXX poll for command completion or suspend command 434 * in progress */ 435 436 /* Save the host controller state. */ 437 for (size_t n = 0; n < sc->sc_nhosts; n++) { 438 hp = sc->sc_host[n]; 439 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 440 for (i = 0; i < sizeof hp->regs; i += 4) { 441 uint32_t v = HREAD4(hp, i); 442 hp->regs[i + 0] = (v >> 0); 443 hp->regs[i + 1] = (v >> 8); 444 if (i + 3 < sizeof hp->regs) { 445 hp->regs[i + 2] = (v >> 16); 446 hp->regs[i + 3] = (v >> 24); 447 } 448 } 449 } else { 450 for (i = 0; i < sizeof hp->regs; i++) { 451 hp->regs[i] = HREAD1(hp, i); 452 } 453 } 454 } 455 return true; 456 } 457 458 bool 459 sdhc_resume(device_t dev, const pmf_qual_t *qual) 460 { 461 struct sdhc_softc *sc = device_private(dev); 462 struct sdhc_host *hp; 463 size_t i; 464 465 /* Restore the host controller state. */ 466 for (size_t n = 0; n < sc->sc_nhosts; n++) { 467 hp = sc->sc_host[n]; 468 (void)sdhc_host_reset(hp); 469 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 470 for (i = 0; i < sizeof hp->regs; i += 4) { 471 if (i + 3 < sizeof hp->regs) { 472 HWRITE4(hp, i, 473 (hp->regs[i + 0] << 0) 474 | (hp->regs[i + 1] << 8) 475 | (hp->regs[i + 2] << 16) 476 | (hp->regs[i + 3] << 24)); 477 } else { 478 HWRITE4(hp, i, 479 (hp->regs[i + 0] << 0) 480 | (hp->regs[i + 1] << 8)); 481 } 482 } 483 } else { 484 for (i = 0; i < sizeof hp->regs; i++) { 485 HWRITE1(hp, i, hp->regs[i]); 486 } 487 } 488 } 489 return true; 490 } 491 492 bool 493 sdhc_shutdown(device_t dev, int flags) 494 { 495 struct sdhc_softc *sc = device_private(dev); 496 struct sdhc_host *hp; 497 498 /* XXX chip locks up if we don't disable it before reboot. */ 499 for (size_t i = 0; i < sc->sc_nhosts; i++) { 500 hp = sc->sc_host[i]; 501 (void)sdhc_host_reset(hp); 502 } 503 return true; 504 } 505 506 /* 507 * Reset the host controller. Called during initialization, when 508 * cards are removed, upon resume, and during error recovery. 509 */ 510 static int 511 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 512 { 513 struct sdhc_host *hp = (struct sdhc_host *)sch; 514 uint32_t sdhcimask; 515 int error; 516 517 /* Don't lock. */ 518 519 /* Disable all interrupts. */ 520 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 521 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 522 } else { 523 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 524 } 525 526 /* 527 * Reset the entire host controller and wait up to 100ms for 528 * the controller to clear the reset bit. 529 */ 530 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 531 if (error) 532 goto out; 533 534 /* Set data timeout counter value to max for now. */ 535 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 536 #if 0 537 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 538 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 539 #endif 540 541 /* Enable interrupts. */ 542 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 543 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 544 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 545 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 546 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 547 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 548 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 549 sdhcimask ^= 550 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 551 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 552 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 553 } else { 554 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 555 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 556 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 557 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 558 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 559 } 560 561 out: 562 return error; 563 } 564 565 static int 566 sdhc_host_reset(sdmmc_chipset_handle_t sch) 567 { 568 struct sdhc_host *hp = (struct sdhc_host *)sch; 569 int error; 570 571 mutex_enter(&hp->host_mtx); 572 error = sdhc_host_reset1(sch); 573 mutex_exit(&hp->host_mtx); 574 575 return error; 576 } 577 578 static uint32_t 579 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 580 { 581 struct sdhc_host *hp = (struct sdhc_host *)sch; 582 583 return hp->ocr; 584 } 585 586 static int 587 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 588 { 589 struct sdhc_host *hp = (struct sdhc_host *)sch; 590 591 return hp->maxblklen; 592 } 593 594 /* 595 * Return non-zero if the card is currently inserted. 596 */ 597 static int 598 sdhc_card_detect(sdmmc_chipset_handle_t sch) 599 { 600 struct sdhc_host *hp = (struct sdhc_host *)sch; 601 int r; 602 603 mutex_enter(&hp->host_mtx); 604 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 605 mutex_exit(&hp->host_mtx); 606 607 return r ? 1 : 0; 608 } 609 610 /* 611 * Return non-zero if the card is currently write-protected. 612 */ 613 static int 614 sdhc_write_protect(sdmmc_chipset_handle_t sch) 615 { 616 struct sdhc_host *hp = (struct sdhc_host *)sch; 617 int r; 618 619 mutex_enter(&hp->host_mtx); 620 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 621 mutex_exit(&hp->host_mtx); 622 623 return r ? 0 : 1; 624 } 625 626 /* 627 * Set or change SD bus voltage and enable or disable SD bus power. 628 * Return zero on success. 629 */ 630 static int 631 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 632 { 633 struct sdhc_host *hp = (struct sdhc_host *)sch; 634 uint8_t vdd; 635 int error = 0; 636 637 mutex_enter(&hp->host_mtx); 638 639 /* 640 * Disable bus power before voltage change. 641 */ 642 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 643 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 644 HWRITE1(hp, SDHC_POWER_CTL, 0); 645 646 /* If power is disabled, reset the host and return now. */ 647 if (ocr == 0) { 648 (void)sdhc_host_reset1(hp); 649 goto out; 650 } 651 652 /* 653 * Select the lowest voltage according to capabilities. 654 */ 655 ocr &= hp->ocr; 656 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 657 vdd = SDHC_VOLTAGE_1_8V; 658 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 659 vdd = SDHC_VOLTAGE_3_0V; 660 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 661 vdd = SDHC_VOLTAGE_3_3V; 662 } else { 663 /* Unsupported voltage level requested. */ 664 error = EINVAL; 665 goto out; 666 } 667 668 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 669 /* 670 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 671 * voltage ramp until power rises. 672 */ 673 HWRITE1(hp, SDHC_POWER_CTL, 674 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 675 sdmmc_delay(10000); 676 677 /* 678 * The host system may not power the bus due to battery low, 679 * etc. In that case, the host controller should clear the 680 * bus power bit. 681 */ 682 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 683 error = ENXIO; 684 goto out; 685 } 686 } 687 688 out: 689 mutex_exit(&hp->host_mtx); 690 691 return error; 692 } 693 694 /* 695 * Return the smallest possible base clock frequency divisor value 696 * for the CLOCK_CTL register to produce `freq' (KHz). 697 */ 698 static bool 699 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 700 { 701 u_int div; 702 703 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 704 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 705 if ((hp->clkbase / div) <= freq) { 706 *divp = SDHC_SDCLK_CGM 707 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 708 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 709 return true; 710 } 711 } 712 /* No divisor found. */ 713 return false; 714 } 715 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 716 u_int dvs = (hp->clkbase + freq - 1) / freq; 717 u_int roundup = dvs & 1; 718 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 719 if (dvs + roundup <= 16) { 720 dvs += roundup - 1; 721 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 722 | (dvs << SDHC_SDCLK_DVS_SHIFT); 723 DPRINTF(2, 724 ("%s: divisor for freq %u is %u * %u\n", 725 HDEVNAME(hp), freq, div * 2, dvs + 1)); 726 return true; 727 } 728 /* 729 * If we drop bits, we need to round up the divisor. 730 */ 731 roundup |= dvs & 1; 732 } 733 panic("%s: can't find divisor for freq %u", HDEVNAME(hp), freq); 734 } else { 735 for (div = 1; div <= 256; div *= 2) { 736 if ((hp->clkbase / div) <= freq) { 737 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 738 return true; 739 } 740 } 741 } 742 /* No divisor found. */ 743 return false; 744 } 745 746 /* 747 * Set or change SDCLK frequency or disable the SD clock. 748 * Return zero on success. 749 */ 750 static int 751 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 752 { 753 struct sdhc_host *hp = (struct sdhc_host *)sch; 754 u_int div; 755 u_int timo; 756 int error = 0; 757 #ifdef DIAGNOSTIC 758 bool present; 759 760 mutex_enter(&hp->host_mtx); 761 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 762 mutex_exit(&hp->host_mtx); 763 764 /* Must not stop the clock if commands are in progress. */ 765 if (present && sdhc_card_detect(hp)) { 766 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 767 device_xname(hp->sc->sc_dev)); 768 } 769 #endif 770 771 mutex_enter(&hp->host_mtx); 772 773 /* 774 * Stop SD clock before changing the frequency. 775 */ 776 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 777 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 778 if (freq == SDMMC_SDCLK_OFF) { 779 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 780 goto out; 781 } 782 } else { 783 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 784 if (freq == SDMMC_SDCLK_OFF) 785 goto out; 786 } 787 788 /* 789 * Set the minimum base clock frequency divisor. 790 */ 791 if (!sdhc_clock_divisor(hp, freq, &div)) { 792 /* Invalid base clock frequency or `freq' value. */ 793 error = EINVAL; 794 goto out; 795 } 796 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 797 HWRITE4(hp, SDHC_CLOCK_CTL, 798 div | (SDHC_TIMEOUT_MAX << 16)); 799 } else { 800 HWRITE2(hp, SDHC_CLOCK_CTL, div); 801 } 802 803 /* 804 * Start internal clock. Wait 10ms for stabilization. 805 */ 806 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 807 sdmmc_delay(10000); 808 HSET4(hp, SDHC_CLOCK_CTL, 809 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 810 } else { 811 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 812 for (timo = 1000; timo > 0; timo--) { 813 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 814 SDHC_INTCLK_STABLE)) 815 break; 816 sdmmc_delay(10); 817 } 818 if (timo == 0) { 819 error = ETIMEDOUT; 820 goto out; 821 } 822 } 823 824 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 825 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 826 /* 827 * Sending 80 clocks at 400kHz takes 200us. 828 * So delay for that time + slop and then 829 * check a few times for completion. 830 */ 831 sdmmc_delay(210); 832 for (timo = 10; timo > 0; timo--) { 833 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 834 SDHC_INIT_ACTIVE)) 835 break; 836 sdmmc_delay(10); 837 } 838 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 839 840 /* 841 * Enable SD clock. 842 */ 843 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 844 } else { 845 /* 846 * Enable SD clock. 847 */ 848 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 849 850 if (freq > 25000) 851 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 852 else 853 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 854 } 855 856 out: 857 mutex_exit(&hp->host_mtx); 858 859 return error; 860 } 861 862 static int 863 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 864 { 865 struct sdhc_host *hp = (struct sdhc_host *)sch; 866 int reg; 867 868 switch (width) { 869 case 1: 870 case 4: 871 break; 872 873 case 8: 874 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 875 break; 876 /* FALLTHROUGH */ 877 default: 878 DPRINTF(0,("%s: unsupported bus width (%d)\n", 879 HDEVNAME(hp), width)); 880 return 1; 881 } 882 883 mutex_enter(&hp->host_mtx); 884 reg = HREAD1(hp, SDHC_HOST_CTL); 885 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 886 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 887 if (width == 4) 888 reg |= SDHC_4BIT_MODE; 889 else if (width == 8) 890 reg |= SDHC_ESDHC_8BIT_MODE; 891 } else { 892 reg &= ~SDHC_4BIT_MODE; 893 if (width == 4) 894 reg |= SDHC_4BIT_MODE; 895 } 896 HWRITE1(hp, SDHC_HOST_CTL, reg); 897 mutex_exit(&hp->host_mtx); 898 899 return 0; 900 } 901 902 static int 903 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 904 { 905 906 /* Nothing ?? */ 907 return 0; 908 } 909 910 static void 911 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 912 { 913 struct sdhc_host *hp = (struct sdhc_host *)sch; 914 915 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 916 mutex_enter(&hp->host_mtx); 917 if (enable) { 918 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 919 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 920 } else { 921 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 922 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 923 } 924 mutex_exit(&hp->host_mtx); 925 } 926 } 927 928 static void 929 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 930 { 931 struct sdhc_host *hp = (struct sdhc_host *)sch; 932 933 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 934 mutex_enter(&hp->host_mtx); 935 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 936 mutex_exit(&hp->host_mtx); 937 } 938 } 939 940 static int 941 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 942 { 943 uint32_t state; 944 int timeout; 945 946 for (timeout = 10; timeout > 0; timeout--) { 947 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 948 return 0; 949 sdmmc_delay(10000); 950 } 951 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 952 value, state)); 953 return ETIMEDOUT; 954 } 955 956 static void 957 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 958 { 959 struct sdhc_host *hp = (struct sdhc_host *)sch; 960 int error; 961 962 #if 0 963 if (cmd->c_data) { 964 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 965 if (ISSET(hp->flags, SHF_USE_DMA)) { 966 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 967 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 968 } else { 969 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 970 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 971 } 972 } 973 #endif 974 975 /* 976 * Start the MMC command, or mark `cmd' as failed and return. 977 */ 978 error = sdhc_start_command(hp, cmd); 979 if (error) { 980 cmd->c_error = error; 981 goto out; 982 } 983 984 /* 985 * Wait until the command phase is done, or until the command 986 * is marked done for any other reason. 987 */ 988 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 989 cmd->c_error = ETIMEDOUT; 990 goto out; 991 } 992 993 /* 994 * The host controller removes bits [0:7] from the response 995 * data (CRC) and we pass the data up unchanged to the bus 996 * driver (without padding). 997 */ 998 mutex_enter(&hp->host_mtx); 999 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1000 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1001 uint8_t *p = (uint8_t *)cmd->c_resp; 1002 int i; 1003 1004 for (i = 0; i < 15; i++) 1005 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 1006 } else { 1007 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 1008 } 1009 } 1010 mutex_exit(&hp->host_mtx); 1011 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1012 1013 /* 1014 * If the command has data to transfer in any direction, 1015 * execute the transfer now. 1016 */ 1017 if (cmd->c_error == 0 && cmd->c_data != NULL) 1018 sdhc_transfer_data(hp, cmd); 1019 1020 out: 1021 #if 0 1022 if (cmd->c_dmamap != NULL && cmd->c_error == 0 1023 && ISSET(hp->flags, SHF_USE_DMA) 1024 && ISSET(cmd->c_flags, SCF_CMD_READ) { 1025 if (((uintptr_t)cmd->c_data & PAGE_MASK) + cmd->c_datalen > PAGE_SIZE) { 1026 memcpy(cmd->c_data, 1027 (void *)hp->sc->dma_map->dm_segs[0].ds_addr, 1028 cmd->c_datalen); 1029 } 1030 bus_dmamap_unload(hp->sc->dt, hp->sc->dma_map); 1031 } 1032 #endif 1033 1034 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1035 mutex_enter(&hp->host_mtx); 1036 /* Turn off the LED. */ 1037 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1038 mutex_exit(&hp->host_mtx); 1039 } 1040 SET(cmd->c_flags, SCF_ITSDONE); 1041 1042 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1043 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1044 cmd->c_flags, cmd->c_error)); 1045 } 1046 1047 static int 1048 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1049 { 1050 struct sdhc_softc * const sc = hp->sc; 1051 uint16_t blksize = 0; 1052 uint16_t blkcount = 0; 1053 uint16_t mode; 1054 uint16_t command; 1055 int error; 1056 1057 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1058 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1059 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1060 1061 /* 1062 * The maximum block length for commands should be the minimum 1063 * of the host buffer size and the card buffer size. (1.7.2) 1064 */ 1065 1066 /* Fragment the data into proper blocks. */ 1067 if (cmd->c_datalen > 0) { 1068 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1069 blkcount = cmd->c_datalen / blksize; 1070 if (cmd->c_datalen % blksize > 0) { 1071 /* XXX: Split this command. (1.7.4) */ 1072 aprint_error_dev(sc->sc_dev, 1073 "data not a multiple of %u bytes\n", blksize); 1074 return EINVAL; 1075 } 1076 } 1077 1078 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1079 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1080 aprint_error_dev(sc->sc_dev, "too much data\n"); 1081 return EINVAL; 1082 } 1083 1084 /* Prepare transfer mode register value. (2.2.5) */ 1085 mode = 0; 1086 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1087 mode |= SDHC_READ_MODE; 1088 if (blkcount > 0) { 1089 mode |= SDHC_BLOCK_COUNT_ENABLE; 1090 if (blkcount > 1) { 1091 mode |= SDHC_MULTI_BLOCK_MODE; 1092 /* XXX only for memory commands? */ 1093 mode |= SDHC_AUTO_CMD12_ENABLE; 1094 } 1095 } 1096 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1097 if (cmd->c_dmamap->dm_nsegs == 1) { 1098 mode |= SDHC_DMA_ENABLE; 1099 } else { 1100 cmd->c_dmamap = NULL; 1101 } 1102 } 1103 1104 /* 1105 * Prepare command register value. (2.2.6) 1106 */ 1107 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1108 1109 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1110 command |= SDHC_CRC_CHECK_ENABLE; 1111 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1112 command |= SDHC_INDEX_CHECK_ENABLE; 1113 if (cmd->c_data != NULL) 1114 command |= SDHC_DATA_PRESENT_SELECT; 1115 1116 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1117 command |= SDHC_NO_RESPONSE; 1118 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1119 command |= SDHC_RESP_LEN_136; 1120 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1121 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1122 else 1123 command |= SDHC_RESP_LEN_48; 1124 1125 /* Wait until command and data inhibit bits are clear. (1.5) */ 1126 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1127 if (error) 1128 return error; 1129 1130 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1131 HDEVNAME(hp), blksize, blkcount, mode, command)); 1132 1133 mutex_enter(&hp->host_mtx); 1134 1135 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1136 /* Alert the user not to remove the card. */ 1137 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1138 } 1139 1140 /* Set DMA start address. */ 1141 if (ISSET(mode, SDHC_DMA_ENABLE)) 1142 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1143 1144 /* 1145 * Start a CPU data transfer. Writing to the high order byte 1146 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1147 */ 1148 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1149 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1150 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1151 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1152 } else { 1153 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1154 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1155 if (blkcount > 1) 1156 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1157 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1158 HWRITE2(hp, SDHC_COMMAND, command); 1159 } 1160 1161 mutex_exit(&hp->host_mtx); 1162 1163 return 0; 1164 } 1165 1166 static void 1167 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1168 { 1169 int error; 1170 1171 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1172 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1173 1174 #ifdef SDHC_DEBUG 1175 /* XXX I forgot why I wanted to know when this happens :-( */ 1176 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1177 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1178 aprint_error_dev(hp->sc->sc_dev, 1179 "CMD52/53 error response flags %#x\n", 1180 MMC_R1(cmd->c_resp) & 0xff00); 1181 } 1182 #endif 1183 1184 if (cmd->c_dmamap != NULL) 1185 error = sdhc_transfer_data_dma(hp, cmd); 1186 else 1187 error = sdhc_transfer_data_pio(hp, cmd); 1188 if (error) 1189 cmd->c_error = error; 1190 SET(cmd->c_flags, SCF_ITSDONE); 1191 1192 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1193 HDEVNAME(hp), cmd->c_error)); 1194 } 1195 1196 static int 1197 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1198 { 1199 bus_dmamap_t dmap = cmd->c_dmamap; 1200 uint16_t blklen = cmd->c_blklen; 1201 uint16_t blkcnt = cmd->c_datalen / blklen; 1202 uint16_t remain; 1203 int error = 0; 1204 1205 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1206 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1207 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1208 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1209 1210 for (;;) { 1211 if (!sdhc_wait_intr(hp, 1212 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1213 SDHC_DMA_TIMEOUT)) { 1214 error = ETIMEDOUT; 1215 break; 1216 } 1217 1218 /* single block mode */ 1219 if (blkcnt == 1) 1220 break; 1221 1222 /* multi block mode */ 1223 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 1224 if (remain == 0) 1225 break; 1226 1227 HWRITE4(hp, SDHC_DMA_ADDR, 1228 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 1229 } 1230 1231 #if 0 1232 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1233 SDHC_TRANSFER_TIMEOUT)) 1234 error = ETIMEDOUT; 1235 #endif 1236 1237 return error; 1238 } 1239 1240 static int 1241 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1242 { 1243 uint8_t *data = cmd->c_data; 1244 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1245 u_int len, datalen; 1246 u_int imask; 1247 u_int pmask; 1248 int error = 0; 1249 1250 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1251 imask = SDHC_BUFFER_READ_READY; 1252 pmask = SDHC_BUFFER_READ_ENABLE; 1253 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1254 pio_func = esdhc_read_data_pio; 1255 } else { 1256 pio_func = sdhc_read_data_pio; 1257 } 1258 } else { 1259 imask = SDHC_BUFFER_WRITE_READY; 1260 pmask = SDHC_BUFFER_WRITE_ENABLE; 1261 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1262 pio_func = esdhc_write_data_pio; 1263 } else { 1264 pio_func = sdhc_write_data_pio; 1265 } 1266 } 1267 datalen = cmd->c_datalen; 1268 1269 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1270 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1271 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1272 1273 while (datalen > 0) { 1274 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1275 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1276 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1277 } else { 1278 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1279 } 1280 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1281 error = ETIMEDOUT; 1282 break; 1283 } 1284 1285 error = sdhc_wait_state(hp, pmask, pmask); 1286 if (error) 1287 break; 1288 } 1289 1290 len = MIN(datalen, cmd->c_blklen); 1291 (*pio_func)(hp, data, len); 1292 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1293 HDEVNAME(hp), len, data)); 1294 1295 data += len; 1296 datalen -= len; 1297 } 1298 1299 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1300 SDHC_TRANSFER_TIMEOUT)) 1301 error = ETIMEDOUT; 1302 1303 return error; 1304 } 1305 1306 static void 1307 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1308 { 1309 1310 if (((__uintptr_t)data & 3) == 0) { 1311 while (datalen > 3) { 1312 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1313 data += 4; 1314 datalen -= 4; 1315 } 1316 if (datalen > 1) { 1317 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1318 data += 2; 1319 datalen -= 2; 1320 } 1321 if (datalen > 0) { 1322 *data = HREAD1(hp, SDHC_DATA); 1323 data += 1; 1324 datalen -= 1; 1325 } 1326 } else if (((__uintptr_t)data & 1) == 0) { 1327 while (datalen > 1) { 1328 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1329 data += 2; 1330 datalen -= 2; 1331 } 1332 if (datalen > 0) { 1333 *data = HREAD1(hp, SDHC_DATA); 1334 data += 1; 1335 datalen -= 1; 1336 } 1337 } else { 1338 while (datalen > 0) { 1339 *data = HREAD1(hp, SDHC_DATA); 1340 data += 1; 1341 datalen -= 1; 1342 } 1343 } 1344 } 1345 1346 static void 1347 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1348 { 1349 1350 if (((__uintptr_t)data & 3) == 0) { 1351 while (datalen > 3) { 1352 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1353 data += 4; 1354 datalen -= 4; 1355 } 1356 if (datalen > 1) { 1357 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1358 data += 2; 1359 datalen -= 2; 1360 } 1361 if (datalen > 0) { 1362 HWRITE1(hp, SDHC_DATA, *data); 1363 data += 1; 1364 datalen -= 1; 1365 } 1366 } else if (((__uintptr_t)data & 1) == 0) { 1367 while (datalen > 1) { 1368 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1369 data += 2; 1370 datalen -= 2; 1371 } 1372 if (datalen > 0) { 1373 HWRITE1(hp, SDHC_DATA, *data); 1374 data += 1; 1375 datalen -= 1; 1376 } 1377 } else { 1378 while (datalen > 0) { 1379 HWRITE1(hp, SDHC_DATA, *data); 1380 data += 1; 1381 datalen -= 1; 1382 } 1383 } 1384 } 1385 1386 static void 1387 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1388 { 1389 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1390 uint32_t v; 1391 1392 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1393 v = HREAD4(hp, SDHC_DATA); 1394 v = le32toh(v); 1395 *(uint32_t *)data = v; 1396 data += 4; 1397 datalen -= 4; 1398 status = HREAD2(hp, SDHC_NINTR_STATUS); 1399 } 1400 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1401 v = HREAD4(hp, SDHC_DATA); 1402 v = le32toh(v); 1403 do { 1404 *data++ = v; 1405 v >>= 8; 1406 } while (--datalen > 0); 1407 } 1408 } 1409 1410 static void 1411 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1412 { 1413 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1414 uint32_t v; 1415 1416 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1417 v = *(uint32_t *)data; 1418 v = htole32(v); 1419 HWRITE4(hp, SDHC_DATA, v); 1420 data += 4; 1421 datalen -= 4; 1422 status = HREAD2(hp, SDHC_NINTR_STATUS); 1423 } 1424 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1425 v = *(uint32_t *)data; 1426 v = htole32(v); 1427 HWRITE4(hp, SDHC_DATA, v); 1428 } 1429 } 1430 1431 /* Prepare for another command. */ 1432 static int 1433 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1434 { 1435 int timo; 1436 1437 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1438 1439 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1440 for (timo = 10; timo > 0; timo--) { 1441 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1442 break; 1443 sdmmc_delay(10000); 1444 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1445 } 1446 if (timo == 0) { 1447 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1448 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1449 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1450 return ETIMEDOUT; 1451 } 1452 1453 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1454 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int 1461 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1462 { 1463 int status; 1464 1465 mask |= SDHC_ERROR_INTERRUPT; 1466 1467 mutex_enter(&hp->intr_mtx); 1468 status = hp->intr_status & mask; 1469 while (status == 0) { 1470 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1471 == EWOULDBLOCK) { 1472 status |= SDHC_ERROR_INTERRUPT; 1473 break; 1474 } 1475 status = hp->intr_status & mask; 1476 } 1477 hp->intr_status &= ~status; 1478 1479 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1480 hp->intr_error_status)); 1481 1482 /* Command timeout has higher priority than command complete. */ 1483 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1484 hp->intr_error_status = 0; 1485 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1486 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1487 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1488 } 1489 status = 0; 1490 } 1491 mutex_exit(&hp->intr_mtx); 1492 1493 return status; 1494 } 1495 1496 /* 1497 * Established by attachment driver at interrupt priority IPL_SDMMC. 1498 */ 1499 int 1500 sdhc_intr(void *arg) 1501 { 1502 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1503 struct sdhc_host *hp; 1504 int done = 0; 1505 uint16_t status; 1506 uint16_t error; 1507 1508 /* We got an interrupt, but we don't know from which slot. */ 1509 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1510 hp = sc->sc_host[host]; 1511 if (hp == NULL) 1512 continue; 1513 1514 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1515 /* Find out which interrupts are pending. */ 1516 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1517 status = xstatus; 1518 error = xstatus >> 16; 1519 status |= (error ? SDHC_ERROR_INTERRUPT : 0); 1520 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1521 continue; /* no interrupt for us */ 1522 /* Acknowledge the interrupts we are about to handle. */ 1523 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1524 } else { 1525 /* Find out which interrupts are pending. */ 1526 error = 0; 1527 status = HREAD2(hp, SDHC_NINTR_STATUS); 1528 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1529 continue; /* no interrupt for us */ 1530 /* Acknowledge the interrupts we are about to handle. */ 1531 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1532 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1533 /* Acknowledge error interrupts. */ 1534 error = HREAD2(hp, SDHC_EINTR_STATUS); 1535 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1536 } 1537 } 1538 1539 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1540 status, error)); 1541 1542 /* Claim this interrupt. */ 1543 done = 1; 1544 1545 /* 1546 * Service error interrupts. 1547 */ 1548 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1549 SDHC_DATA_TIMEOUT_ERROR)) { 1550 hp->intr_error_status |= error; 1551 hp->intr_status |= status; 1552 cv_broadcast(&hp->intr_cv); 1553 } 1554 1555 /* 1556 * Wake up the sdmmc event thread to scan for cards. 1557 */ 1558 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1559 sdmmc_needs_discover(hp->sdmmc); 1560 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1561 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1562 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1563 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1564 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1565 } 1566 } 1567 1568 /* 1569 * Wake up the blocking process to service command 1570 * related interrupt(s). 1571 */ 1572 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1573 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1574 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1575 hp->intr_status |= status; 1576 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1577 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1578 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1579 } 1580 cv_broadcast(&hp->intr_cv); 1581 } 1582 1583 /* 1584 * Service SD card interrupts. 1585 */ 1586 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1587 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1588 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1589 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1590 sdmmc_card_intr(hp->sdmmc); 1591 } 1592 } 1593 1594 return done; 1595 } 1596 1597 #ifdef SDHC_DEBUG 1598 void 1599 sdhc_dump_regs(struct sdhc_host *hp) 1600 { 1601 1602 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1603 HREAD4(hp, SDHC_PRESENT_STATE)); 1604 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1605 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1606 HREAD1(hp, SDHC_POWER_CTL)); 1607 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1608 HREAD2(hp, SDHC_NINTR_STATUS)); 1609 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1610 HREAD2(hp, SDHC_EINTR_STATUS)); 1611 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1612 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1613 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1614 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1615 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1616 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1617 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1618 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1619 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1620 HREAD4(hp, SDHC_CAPABILITIES)); 1621 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1622 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1623 } 1624 #endif 1625