1 /* $NetBSD: sdhc.c,v 1.7 2010/03/27 03:04:52 nonaka Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.7 2010/03/27 03:04:52 nonaka Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/kthread.h> 32 #include <sys/malloc.h> 33 #include <sys/systm.h> 34 #include <sys/mutex.h> 35 #include <sys/condvar.h> 36 37 #include <dev/sdmmc/sdhcreg.h> 38 #include <dev/sdmmc/sdhcvar.h> 39 #include <dev/sdmmc/sdmmcchip.h> 40 #include <dev/sdmmc/sdmmcreg.h> 41 #include <dev/sdmmc/sdmmcvar.h> 42 43 #ifdef SDHC_DEBUG 44 int sdhcdebug = 1; 45 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 46 void sdhc_dump_regs(struct sdhc_host *); 47 #else 48 #define DPRINTF(n,s) do {} while (0) 49 #endif 50 51 #define SDHC_COMMAND_TIMEOUT hz 52 #define SDHC_BUFFER_TIMEOUT hz 53 #define SDHC_TRANSFER_TIMEOUT hz 54 #define SDHC_DMA_TIMEOUT hz 55 56 struct sdhc_host { 57 struct sdhc_softc *sc; /* host controller device */ 58 59 bus_space_tag_t iot; /* host register set tag */ 60 bus_space_handle_t ioh; /* host register set handle */ 61 bus_dma_tag_t dmat; /* host DMA tag */ 62 63 device_t sdmmc; /* generic SD/MMC device */ 64 65 struct kmutex host_mtx; 66 67 u_int clkbase; /* base clock frequency in KHz */ 68 int maxblklen; /* maximum block length */ 69 uint32_t ocr; /* OCR value from capabilities */ 70 71 uint8_t regs[14]; /* host controller state */ 72 73 uint16_t intr_status; /* soft interrupt status */ 74 uint16_t intr_error_status; /* soft error status */ 75 struct kmutex intr_mtx; 76 struct kcondvar intr_cv; 77 78 uint32_t flags; /* flags for this host */ 79 #define SHF_USE_DMA 0x0001 80 #define SHF_USE_4BIT_MODE 0x0002 81 }; 82 83 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 84 85 #define HREAD1(hp, reg) \ 86 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 87 #define HREAD2(hp, reg) \ 88 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 89 #define HREAD4(hp, reg) \ 90 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 91 #define HWRITE1(hp, reg, val) \ 92 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 93 #define HWRITE2(hp, reg, val) \ 94 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 95 #define HWRITE4(hp, reg, val) \ 96 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 97 #define HCLR1(hp, reg, bits) \ 98 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 99 #define HCLR2(hp, reg, bits) \ 100 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 101 #define HSET1(hp, reg, bits) \ 102 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 103 #define HSET2(hp, reg, bits) \ 104 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 105 106 static int sdhc_host_reset(sdmmc_chipset_handle_t); 107 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 108 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 109 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 110 static int sdhc_card_detect(sdmmc_chipset_handle_t); 111 static int sdhc_write_protect(sdmmc_chipset_handle_t); 112 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 113 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 114 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 115 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 116 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 117 static void sdhc_exec_command(sdmmc_chipset_handle_t, 118 struct sdmmc_command *); 119 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 120 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 121 static int sdhc_soft_reset(struct sdhc_host *, int); 122 static int sdhc_wait_intr(struct sdhc_host *, int, int); 123 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 124 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 125 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 126 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int); 127 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int); 128 129 static struct sdmmc_chip_functions sdhc_functions = { 130 /* host controller reset */ 131 sdhc_host_reset, 132 133 /* host controller capabilities */ 134 sdhc_host_ocr, 135 sdhc_host_maxblklen, 136 137 /* card detection */ 138 sdhc_card_detect, 139 140 /* write protect */ 141 sdhc_write_protect, 142 143 /* bus power, clock frequency and width */ 144 sdhc_bus_power, 145 sdhc_bus_clock, 146 sdhc_bus_width, 147 148 /* command execution */ 149 sdhc_exec_command, 150 151 /* card interrupt */ 152 sdhc_card_enable_intr, 153 sdhc_card_intr_ack 154 }; 155 156 /* 157 * Called by attachment driver. For each SD card slot there is one SD 158 * host controller standard register set. (1.3) 159 */ 160 int 161 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 162 bus_space_handle_t ioh, bus_size_t iosize) 163 { 164 struct sdmmcbus_attach_args saa; 165 struct sdhc_host *hp; 166 uint32_t caps; 167 #ifdef SDHC_DEBUG 168 uint16_t sdhcver; 169 170 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 171 aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version "); 172 switch (SDHC_SPEC_VERSION(sdhcver)) { 173 case 0x00: 174 aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 175 break; 176 177 default: 178 aprint_normal(">1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 179 break; 180 } 181 #endif 182 183 /* Allocate one more host structure. */ 184 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 185 if (hp == NULL) { 186 aprint_error_dev(sc->sc_dev, 187 "couldn't alloc memory (sdhc host)\n"); 188 goto err1; 189 } 190 sc->sc_host[sc->sc_nhosts++] = hp; 191 192 /* Fill in the new host structure. */ 193 hp->sc = sc; 194 hp->iot = iot; 195 hp->ioh = ioh; 196 hp->dmat = sc->sc_dmat; 197 198 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 199 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 200 cv_init(&hp->intr_cv, "sdhcintr"); 201 202 /* 203 * Reset the host controller and enable interrupts. 204 */ 205 (void)sdhc_host_reset(hp); 206 207 /* Determine host capabilities. */ 208 mutex_enter(&hp->host_mtx); 209 caps = HREAD4(hp, SDHC_CAPABILITIES); 210 mutex_exit(&hp->host_mtx); 211 212 #if notyet 213 /* Use DMA if the host system and the controller support it. */ 214 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 215 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 216 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 217 SET(hp->flags, SHF_USE_DMA); 218 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 219 } 220 #endif 221 222 /* 223 * Determine the base clock frequency. (2.2.24) 224 */ 225 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 226 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 227 if (hp->clkbase == 0) { 228 /* The attachment driver must tell us. */ 229 aprint_error_dev(sc->sc_dev, "unknown base clock frequency\n"); 230 goto err; 231 } else if (hp->clkbase < 10000 || hp->clkbase > 63000) { 232 /* SDHC 1.0 supports only 10-63 MHz. */ 233 aprint_error_dev(sc->sc_dev, 234 "base clock frequency out of range: %u MHz\n", 235 hp->clkbase / 1000); 236 goto err; 237 } 238 DPRINTF(1,("%s: base clock frequency %u MHz\n", 239 device_xname(sc->sc_dev), hp->clkbase / 1000)); 240 241 /* 242 * XXX Set the data timeout counter value according to 243 * capabilities. (2.2.15) 244 */ 245 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 246 247 /* 248 * Determine SD bus voltage levels supported by the controller. 249 */ 250 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 251 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 252 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 253 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 254 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 255 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 256 257 /* 258 * Determine the maximum block length supported by the host 259 * controller. (2.2.24) 260 */ 261 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 262 case SDHC_MAX_BLK_LEN_512: 263 hp->maxblklen = 512; 264 break; 265 266 case SDHC_MAX_BLK_LEN_1024: 267 hp->maxblklen = 1024; 268 break; 269 270 case SDHC_MAX_BLK_LEN_2048: 271 hp->maxblklen = 2048; 272 break; 273 274 default: 275 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 276 goto err; 277 } 278 DPRINTF(1, ("%s: max block length %u byte%s\n", 279 device_xname(sc->sc_dev), hp->maxblklen, 280 hp->maxblklen > 1 ? "s" : "")); 281 282 /* 283 * Attach the generic SD/MMC bus driver. (The bus driver must 284 * not invoke any chipset functions before it is attached.) 285 */ 286 memset(&saa, 0, sizeof(saa)); 287 saa.saa_busname = "sdmmc"; 288 saa.saa_sct = &sdhc_functions; 289 saa.saa_sch = hp; 290 saa.saa_dmat = hp->dmat; 291 saa.saa_clkmin = hp->clkbase / 256; 292 saa.saa_clkmax = hp->clkbase; 293 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 294 #if notyet 295 if (ISSET(hp->flags, SHF_USE_DMA)) 296 saa.saa_caps |= SMC_CAPS_DMA; 297 #endif 298 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 299 300 return 0; 301 302 err: 303 cv_destroy(&hp->intr_cv); 304 mutex_destroy(&hp->intr_mtx); 305 mutex_destroy(&hp->host_mtx); 306 free(hp, M_DEVBUF); 307 sc->sc_host[--sc->sc_nhosts] = NULL; 308 err1: 309 return 1; 310 } 311 312 int 313 sdhc_detach(device_t dev, int flags) 314 { 315 struct sdhc_host *hp = (struct sdhc_host *)dev; 316 struct sdhc_softc *sc = hp->sc; 317 int rv = 0; 318 319 if (hp->sdmmc) 320 rv = config_detach(hp->sdmmc, flags); 321 322 cv_destroy(&hp->intr_cv); 323 mutex_destroy(&hp->intr_mtx); 324 mutex_destroy(&hp->host_mtx); 325 free(hp, M_DEVBUF); 326 sc->sc_host[--sc->sc_nhosts] = NULL; 327 328 return rv; 329 } 330 331 bool 332 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 333 { 334 struct sdhc_softc *sc = device_private(dev); 335 struct sdhc_host *hp; 336 int n, i; 337 338 /* XXX poll for command completion or suspend command 339 * in progress */ 340 341 /* Save the host controller state. */ 342 for (n = 0; n < sc->sc_nhosts; n++) { 343 hp = sc->sc_host[n]; 344 for (i = 0; i < sizeof hp->regs; i++) 345 hp->regs[i] = HREAD1(hp, i); 346 } 347 return true; 348 } 349 350 bool 351 sdhc_resume(device_t dev, const pmf_qual_t *qual) 352 { 353 struct sdhc_softc *sc = device_private(dev); 354 struct sdhc_host *hp; 355 int n, i; 356 357 /* Restore the host controller state. */ 358 for (n = 0; n < sc->sc_nhosts; n++) { 359 hp = sc->sc_host[n]; 360 (void)sdhc_host_reset(hp); 361 for (i = 0; i < sizeof hp->regs; i++) 362 HWRITE1(hp, i, hp->regs[i]); 363 } 364 return true; 365 } 366 367 bool 368 sdhc_shutdown(device_t dev, int flags) 369 { 370 struct sdhc_softc *sc = device_private(dev); 371 struct sdhc_host *hp; 372 int i; 373 374 /* XXX chip locks up if we don't disable it before reboot. */ 375 for (i = 0; i < sc->sc_nhosts; i++) { 376 hp = sc->sc_host[i]; 377 (void)sdhc_host_reset(hp); 378 } 379 return true; 380 } 381 382 /* 383 * Reset the host controller. Called during initialization, when 384 * cards are removed, upon resume, and during error recovery. 385 */ 386 static int 387 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 388 { 389 struct sdhc_host *hp = (struct sdhc_host *)sch; 390 uint16_t sdhcimask; 391 int error; 392 393 /* Don't lock. */ 394 395 /* Disable all interrupts. */ 396 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 397 398 /* 399 * Reset the entire host controller and wait up to 100ms for 400 * the controller to clear the reset bit. 401 */ 402 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 403 if (error) 404 goto out; 405 406 /* Set data timeout counter value to max for now. */ 407 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 408 409 /* Enable interrupts. */ 410 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 411 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 412 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 413 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 414 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 415 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 416 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 417 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 418 419 out: 420 return error; 421 } 422 423 static int 424 sdhc_host_reset(sdmmc_chipset_handle_t sch) 425 { 426 struct sdhc_host *hp = (struct sdhc_host *)sch; 427 int error; 428 429 mutex_enter(&hp->host_mtx); 430 error = sdhc_host_reset1(sch); 431 mutex_exit(&hp->host_mtx); 432 433 return error; 434 } 435 436 static uint32_t 437 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 438 { 439 struct sdhc_host *hp = (struct sdhc_host *)sch; 440 441 return hp->ocr; 442 } 443 444 static int 445 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 446 { 447 struct sdhc_host *hp = (struct sdhc_host *)sch; 448 449 return hp->maxblklen; 450 } 451 452 /* 453 * Return non-zero if the card is currently inserted. 454 */ 455 static int 456 sdhc_card_detect(sdmmc_chipset_handle_t sch) 457 { 458 struct sdhc_host *hp = (struct sdhc_host *)sch; 459 int r; 460 461 mutex_enter(&hp->host_mtx); 462 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 463 mutex_exit(&hp->host_mtx); 464 465 if (r) 466 return 1; 467 return 0; 468 } 469 470 /* 471 * Return non-zero if the card is currently write-protected. 472 */ 473 static int 474 sdhc_write_protect(sdmmc_chipset_handle_t sch) 475 { 476 struct sdhc_host *hp = (struct sdhc_host *)sch; 477 int r; 478 479 mutex_enter(&hp->host_mtx); 480 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 481 mutex_exit(&hp->host_mtx); 482 483 if (!r) 484 return 1; 485 return 0; 486 } 487 488 /* 489 * Set or change SD bus voltage and enable or disable SD bus power. 490 * Return zero on success. 491 */ 492 static int 493 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 494 { 495 struct sdhc_host *hp = (struct sdhc_host *)sch; 496 uint8_t vdd; 497 int error = 0; 498 499 mutex_enter(&hp->host_mtx); 500 501 /* 502 * Disable bus power before voltage change. 503 */ 504 if (!(hp->sc->sc_flags & SDHC_FLAG_NO_PWR0)) 505 HWRITE1(hp, SDHC_POWER_CTL, 0); 506 507 /* If power is disabled, reset the host and return now. */ 508 if (ocr == 0) { 509 (void)sdhc_host_reset1(hp); 510 goto out; 511 } 512 513 /* 514 * Select the lowest voltage according to capabilities. 515 */ 516 ocr &= hp->ocr; 517 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) 518 vdd = SDHC_VOLTAGE_1_8V; 519 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 520 vdd = SDHC_VOLTAGE_3_0V; 521 else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 522 vdd = SDHC_VOLTAGE_3_3V; 523 else { 524 /* Unsupported voltage level requested. */ 525 error = EINVAL; 526 goto out; 527 } 528 529 /* 530 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 531 * voltage ramp until power rises. 532 */ 533 HWRITE1(hp, SDHC_POWER_CTL, 534 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 535 sdmmc_delay(10000); 536 537 /* 538 * The host system may not power the bus due to battery low, 539 * etc. In that case, the host controller should clear the 540 * bus power bit. 541 */ 542 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 543 error = ENXIO; 544 goto out; 545 } 546 547 out: 548 mutex_exit(&hp->host_mtx); 549 550 return error; 551 } 552 553 /* 554 * Return the smallest possible base clock frequency divisor value 555 * for the CLOCK_CTL register to produce `freq' (KHz). 556 */ 557 static int 558 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 559 { 560 int div; 561 562 for (div = 1; div <= 256; div *= 2) 563 if ((hp->clkbase / div) <= freq) 564 return (div / 2); 565 /* No divisor found. */ 566 return -1; 567 } 568 569 /* 570 * Set or change SDCLK frequency or disable the SD clock. 571 * Return zero on success. 572 */ 573 static int 574 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 575 { 576 struct sdhc_host *hp = (struct sdhc_host *)sch; 577 int div; 578 int timo; 579 int error = 0; 580 #ifdef DIAGNOSTIC 581 int ispresent; 582 #endif 583 584 #ifdef DIAGNOSTIC 585 mutex_enter(&hp->host_mtx); 586 ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 587 mutex_exit(&hp->host_mtx); 588 589 /* Must not stop the clock if commands are in progress. */ 590 if (ispresent && sdhc_card_detect(hp)) 591 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 592 device_xname(hp->sc->sc_dev)); 593 #endif 594 595 mutex_enter(&hp->host_mtx); 596 597 /* 598 * Stop SD clock before changing the frequency. 599 */ 600 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 601 if (freq == SDMMC_SDCLK_OFF) 602 goto out; 603 604 /* 605 * Set the minimum base clock frequency divisor. 606 */ 607 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 608 /* Invalid base clock frequency or `freq' value. */ 609 error = EINVAL; 610 goto out; 611 } 612 HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT); 613 614 /* 615 * Start internal clock. Wait 10ms for stabilization. 616 */ 617 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 618 for (timo = 1000; timo > 0; timo--) { 619 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 620 break; 621 sdmmc_delay(10); 622 } 623 if (timo == 0) { 624 error = ETIMEDOUT; 625 goto out; 626 } 627 628 /* 629 * Enable SD clock. 630 */ 631 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 632 633 out: 634 mutex_exit(&hp->host_mtx); 635 636 return error; 637 } 638 639 static int 640 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 641 { 642 struct sdhc_host *hp = (struct sdhc_host *)sch; 643 int reg; 644 645 switch (width) { 646 case 1: 647 case 4: 648 break; 649 650 default: 651 DPRINTF(0,("%s: unsupported bus width (%d)\n", 652 HDEVNAME(hp), width)); 653 return 1; 654 } 655 656 mutex_enter(&hp->host_mtx); 657 reg = HREAD1(hp, SDHC_HOST_CTL); 658 reg &= ~SDHC_4BIT_MODE; 659 if (width == 4) 660 reg |= SDHC_4BIT_MODE; 661 HWRITE1(hp, SDHC_HOST_CTL, reg); 662 mutex_exit(&hp->host_mtx); 663 664 return 0; 665 } 666 667 static void 668 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 669 { 670 struct sdhc_host *hp = (struct sdhc_host *)sch; 671 672 mutex_enter(&hp->host_mtx); 673 if (enable) { 674 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 675 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 676 } else { 677 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 678 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 679 } 680 mutex_exit(&hp->host_mtx); 681 } 682 683 static void 684 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 685 { 686 struct sdhc_host *hp = (struct sdhc_host *)sch; 687 688 mutex_enter(&hp->host_mtx); 689 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 690 mutex_exit(&hp->host_mtx); 691 } 692 693 static int 694 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 695 { 696 uint32_t state; 697 int timeout; 698 699 for (timeout = 10; timeout > 0; timeout--) { 700 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 701 return 0; 702 sdmmc_delay(10000); 703 } 704 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 705 value, state)); 706 return ETIMEDOUT; 707 } 708 709 static void 710 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 711 { 712 struct sdhc_host *hp = (struct sdhc_host *)sch; 713 int error; 714 715 /* 716 * Start the MMC command, or mark `cmd' as failed and return. 717 */ 718 error = sdhc_start_command(hp, cmd); 719 if (error) { 720 cmd->c_error = error; 721 goto out; 722 } 723 724 /* 725 * Wait until the command phase is done, or until the command 726 * is marked done for any other reason. 727 */ 728 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 729 cmd->c_error = ETIMEDOUT; 730 goto out; 731 } 732 733 /* 734 * The host controller removes bits [0:7] from the response 735 * data (CRC) and we pass the data up unchanged to the bus 736 * driver (without padding). 737 */ 738 mutex_enter(&hp->host_mtx); 739 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 740 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 741 uint8_t *p = (uint8_t *)cmd->c_resp; 742 int i; 743 744 for (i = 0; i < 15; i++) 745 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 746 } else { 747 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 748 } 749 } 750 mutex_exit(&hp->host_mtx); 751 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 752 753 /* 754 * If the command has data to transfer in any direction, 755 * execute the transfer now. 756 */ 757 if (cmd->c_error == 0 && cmd->c_data != NULL) 758 sdhc_transfer_data(hp, cmd); 759 760 out: 761 mutex_enter(&hp->host_mtx); 762 /* Turn off the LED. */ 763 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 764 mutex_exit(&hp->host_mtx); 765 SET(cmd->c_flags, SCF_ITSDONE); 766 767 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 768 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 769 cmd->c_flags, cmd->c_error)); 770 } 771 772 static int 773 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 774 { 775 uint16_t blksize = 0; 776 uint16_t blkcount = 0; 777 uint16_t mode; 778 uint16_t command; 779 int error; 780 781 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x\n", 782 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 783 cmd->c_datalen, cmd->c_flags)); 784 785 /* 786 * The maximum block length for commands should be the minimum 787 * of the host buffer size and the card buffer size. (1.7.2) 788 */ 789 790 /* Fragment the data into proper blocks. */ 791 if (cmd->c_datalen > 0) { 792 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 793 blkcount = cmd->c_datalen / blksize; 794 if (cmd->c_datalen % blksize > 0) { 795 /* XXX: Split this command. (1.7.4) */ 796 aprint_error_dev(hp->sc->sc_dev, 797 "data not a multiple of %u bytes\n", blksize); 798 return EINVAL; 799 } 800 } 801 802 /* Check limit imposed by 9-bit block count. (1.7.2) */ 803 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 804 aprint_error_dev(hp->sc->sc_dev, "too much data\n"); 805 return EINVAL; 806 } 807 808 /* Prepare transfer mode register value. (2.2.5) */ 809 mode = 0; 810 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 811 mode |= SDHC_READ_MODE; 812 if (blkcount > 0) { 813 mode |= SDHC_BLOCK_COUNT_ENABLE; 814 if (blkcount > 1) { 815 mode |= SDHC_MULTI_BLOCK_MODE; 816 /* XXX only for memory commands? */ 817 mode |= SDHC_AUTO_CMD12_ENABLE; 818 } 819 } 820 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 821 if (cmd->c_dmamap->dm_nsegs == 1) { 822 mode |= SDHC_DMA_ENABLE; 823 } else { 824 cmd->c_dmamap = NULL; 825 } 826 } 827 828 /* 829 * Prepare command register value. (2.2.6) 830 */ 831 command = 832 (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 833 834 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 835 command |= SDHC_CRC_CHECK_ENABLE; 836 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 837 command |= SDHC_INDEX_CHECK_ENABLE; 838 if (cmd->c_data != NULL) 839 command |= SDHC_DATA_PRESENT_SELECT; 840 841 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 842 command |= SDHC_NO_RESPONSE; 843 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 844 command |= SDHC_RESP_LEN_136; 845 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 846 command |= SDHC_RESP_LEN_48_CHK_BUSY; 847 else 848 command |= SDHC_RESP_LEN_48; 849 850 /* Wait until command and data inhibit bits are clear. (1.5) */ 851 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 852 if (error) 853 return error; 854 855 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 856 HDEVNAME(hp), blksize, blkcount, mode, command)); 857 858 mutex_enter(&hp->host_mtx); 859 860 /* Alert the user not to remove the card. */ 861 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 862 863 /* Set DMA start address. */ 864 if (ISSET(mode, SDHC_DMA_ENABLE)) 865 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 866 867 /* 868 * Start a CPU data transfer. Writing to the high order byte 869 * of the SDHC_COMMAND register triggers the SD command. (1.5) 870 */ 871 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 872 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 873 if (blkcount > 1) 874 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 875 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 876 HWRITE2(hp, SDHC_COMMAND, command); 877 878 mutex_exit(&hp->host_mtx); 879 880 return 0; 881 } 882 883 static void 884 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 885 { 886 int error; 887 888 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 889 MMC_R1(cmd->c_resp), cmd->c_datalen)); 890 891 #ifdef SDHC_DEBUG 892 /* XXX I forgot why I wanted to know when this happens :-( */ 893 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 894 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 895 aprint_error_dev(hp->sc->sc_dev, 896 "CMD52/53 error response flags %#x\n", 897 MMC_R1(cmd->c_resp) & 0xff00); 898 } 899 #endif 900 901 if (cmd->c_dmamap != NULL) 902 error = sdhc_transfer_data_dma(hp, cmd); 903 else 904 error = sdhc_transfer_data_pio(hp, cmd); 905 if (error) 906 cmd->c_error = error; 907 SET(cmd->c_flags, SCF_ITSDONE); 908 909 DPRINTF(1,("%s: data transfer done (error=%d)\n", 910 HDEVNAME(hp), cmd->c_error)); 911 } 912 913 static int 914 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 915 { 916 bus_dmamap_t dmap = cmd->c_dmamap; 917 uint16_t blklen = cmd->c_blklen; 918 uint16_t blkcnt = cmd->c_datalen / blklen; 919 uint16_t remain; 920 int error = 0; 921 922 for (;;) { 923 if (!sdhc_wait_intr(hp, 924 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 925 SDHC_DMA_TIMEOUT)) { 926 error = ETIMEDOUT; 927 break; 928 } 929 930 /* single block mode */ 931 if (blkcnt == 1) 932 break; 933 934 /* multi block mode */ 935 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 936 if (remain == 0) 937 break; 938 939 HWRITE4(hp, SDHC_DMA_ADDR, 940 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 941 } 942 943 #if 0 944 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 945 SDHC_TRANSFER_TIMEOUT)) 946 error = ETIMEDOUT; 947 #endif 948 949 return error; 950 } 951 952 static int 953 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 954 { 955 uint8_t *data = cmd->c_data; 956 int len, datalen; 957 int mask; 958 int error = 0; 959 960 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 961 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 962 datalen = cmd->c_datalen; 963 964 while (datalen > 0) { 965 if (!sdhc_wait_intr(hp, 966 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY, 967 SDHC_BUFFER_TIMEOUT)) { 968 error = ETIMEDOUT; 969 break; 970 } 971 972 error = sdhc_wait_state(hp, mask, mask); 973 if (error) 974 break; 975 976 len = MIN(datalen, cmd->c_blklen); 977 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 978 sdhc_read_data_pio(hp, data, len); 979 else 980 sdhc_write_data_pio(hp, data, len); 981 982 data += len; 983 datalen -= len; 984 } 985 986 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 987 SDHC_TRANSFER_TIMEOUT)) 988 error = ETIMEDOUT; 989 990 return error; 991 } 992 993 static void 994 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 995 { 996 997 if (((__uintptr_t)data & 3) == 0) { 998 while (datalen > 3) { 999 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1000 data += 4; 1001 datalen -= 4; 1002 } 1003 if (datalen > 1) { 1004 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1005 data += 2; 1006 datalen -= 2; 1007 } 1008 if (datalen > 0) { 1009 *data = HREAD1(hp, SDHC_DATA); 1010 data += 1; 1011 datalen -= 1; 1012 } 1013 } else if (((__uintptr_t)data & 1) == 0) { 1014 while (datalen > 1) { 1015 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1016 data += 2; 1017 datalen -= 2; 1018 } 1019 if (datalen > 0) { 1020 *data = HREAD1(hp, SDHC_DATA); 1021 data += 1; 1022 datalen -= 1; 1023 } 1024 } else { 1025 while (datalen > 0) { 1026 *data = HREAD1(hp, SDHC_DATA); 1027 data += 1; 1028 datalen -= 1; 1029 } 1030 } 1031 } 1032 1033 static void 1034 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 1035 { 1036 1037 if (((__uintptr_t)data & 3) == 0) { 1038 while (datalen > 3) { 1039 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1040 data += 4; 1041 datalen -= 4; 1042 } 1043 if (datalen > 1) { 1044 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1045 data += 2; 1046 datalen -= 2; 1047 } 1048 if (datalen > 0) { 1049 HWRITE1(hp, SDHC_DATA, *data); 1050 data += 1; 1051 datalen -= 1; 1052 } 1053 } else if (((__uintptr_t)data & 1) == 0) { 1054 while (datalen > 1) { 1055 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1056 data += 2; 1057 datalen -= 2; 1058 } 1059 if (datalen > 0) { 1060 HWRITE1(hp, SDHC_DATA, *data); 1061 data += 1; 1062 datalen -= 1; 1063 } 1064 } else { 1065 while (datalen > 0) { 1066 HWRITE1(hp, SDHC_DATA, *data); 1067 data += 1; 1068 datalen -= 1; 1069 } 1070 } 1071 } 1072 1073 /* Prepare for another command. */ 1074 static int 1075 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1076 { 1077 int timo; 1078 1079 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1080 1081 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1082 for (timo = 10; timo > 0; timo--) { 1083 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1084 break; 1085 sdmmc_delay(10000); 1086 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1087 } 1088 if (timo == 0) { 1089 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1090 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1091 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1092 return ETIMEDOUT; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int 1099 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1100 { 1101 int status; 1102 1103 mask |= SDHC_ERROR_INTERRUPT; 1104 1105 mutex_enter(&hp->intr_mtx); 1106 status = hp->intr_status & mask; 1107 while (status == 0) { 1108 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1109 == EWOULDBLOCK) { 1110 status |= SDHC_ERROR_INTERRUPT; 1111 break; 1112 } 1113 status = hp->intr_status & mask; 1114 } 1115 hp->intr_status &= ~status; 1116 1117 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1118 hp->intr_error_status)); 1119 1120 /* Command timeout has higher priority than command complete. */ 1121 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1122 hp->intr_error_status = 0; 1123 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1124 status = 0; 1125 } 1126 mutex_exit(&hp->intr_mtx); 1127 1128 return status; 1129 } 1130 1131 /* 1132 * Established by attachment driver at interrupt priority IPL_SDMMC. 1133 */ 1134 int 1135 sdhc_intr(void *arg) 1136 { 1137 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1138 struct sdhc_host *hp; 1139 int host; 1140 int done = 0; 1141 uint16_t status; 1142 uint16_t error; 1143 1144 /* We got an interrupt, but we don't know from which slot. */ 1145 for (host = 0; host < sc->sc_nhosts; host++) { 1146 hp = sc->sc_host[host]; 1147 if (hp == NULL) 1148 continue; 1149 1150 /* Find out which interrupts are pending. */ 1151 status = HREAD2(hp, SDHC_NINTR_STATUS); 1152 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1153 continue; /* no interrupt for us */ 1154 1155 /* Acknowledge the interrupts we are about to handle. */ 1156 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1157 DPRINTF(2,("%s: interrupt status=%x\n", HDEVNAME(hp), 1158 status)); 1159 1160 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1161 continue; 1162 1163 /* Claim this interrupt. */ 1164 done = 1; 1165 1166 /* 1167 * Service error interrupts. 1168 */ 1169 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1170 /* Acknowledge error interrupts. */ 1171 error = HREAD2(hp, SDHC_EINTR_STATUS); 1172 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1173 DPRINTF(2,("%s: error interrupt, status=%x\n", 1174 HDEVNAME(hp), error)); 1175 1176 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1177 SDHC_DATA_TIMEOUT_ERROR)) { 1178 hp->intr_error_status |= error; 1179 hp->intr_status |= status; 1180 cv_broadcast(&hp->intr_cv); 1181 } 1182 } 1183 1184 /* 1185 * Wake up the sdmmc event thread to scan for cards. 1186 */ 1187 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1188 sdmmc_needs_discover(hp->sdmmc); 1189 1190 /* 1191 * Wake up the blocking process to service command 1192 * related interrupt(s). 1193 */ 1194 if (ISSET(status, SDHC_BUFFER_READ_READY| 1195 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1196 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1197 hp->intr_status |= status; 1198 cv_broadcast(&hp->intr_cv); 1199 } 1200 1201 /* 1202 * Service SD card interrupts. 1203 */ 1204 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1205 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1206 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1207 sdmmc_card_intr(hp->sdmmc); 1208 } 1209 } 1210 1211 return done; 1212 } 1213 1214 #ifdef SDHC_DEBUG 1215 void 1216 sdhc_dump_regs(struct sdhc_host *hp) 1217 { 1218 1219 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1220 HREAD4(hp, SDHC_PRESENT_STATE)); 1221 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1222 HREAD1(hp, SDHC_POWER_CTL)); 1223 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1224 HREAD2(hp, SDHC_NINTR_STATUS)); 1225 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1226 HREAD2(hp, SDHC_EINTR_STATUS)); 1227 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1228 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1229 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1230 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1231 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1232 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1233 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1234 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1235 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1236 HREAD4(hp, SDHC_CAPABILITIES)); 1237 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1238 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1239 } 1240 #endif 1241