1 /* $NetBSD: sdhc.c,v 1.47 2014/09/14 08:47:08 skrll Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.47 2014/09/14 08:47:08 skrll Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_sdmmc.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/sdmmc/sdhcreg.h> 42 #include <dev/sdmmc/sdhcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #ifdef SDHC_DEBUG 48 int sdhcdebug = 1; 49 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50 void sdhc_dump_regs(struct sdhc_host *); 51 #else 52 #define DPRINTF(n,s) do {} while (0) 53 #endif 54 55 #define SDHC_COMMAND_TIMEOUT hz 56 #define SDHC_BUFFER_TIMEOUT hz 57 #define SDHC_TRANSFER_TIMEOUT hz 58 #define SDHC_DMA_TIMEOUT hz 59 60 struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_size_t ios; /* host register space size */ 66 bus_dma_tag_t dmat; /* host DMA tag */ 67 68 device_t sdmmc; /* generic SD/MMC device */ 69 70 struct kmutex host_mtx; 71 72 u_int clkbase; /* base clock frequency in KHz */ 73 int maxblklen; /* maximum block length */ 74 uint32_t ocr; /* OCR value from capabilities */ 75 76 uint8_t regs[14]; /* host controller state */ 77 78 uint16_t intr_status; /* soft interrupt status */ 79 uint16_t intr_error_status; /* soft error status */ 80 struct kmutex intr_mtx; 81 struct kcondvar intr_cv; 82 83 int specver; /* spec. version */ 84 85 uint32_t flags; /* flags for this host */ 86 #define SHF_USE_DMA 0x0001 87 #define SHF_USE_4BIT_MODE 0x0002 88 #define SHF_USE_8BIT_MODE 0x0004 89 }; 90 91 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 92 93 static uint8_t 94 hread1(struct sdhc_host *hp, bus_size_t reg) 95 { 96 97 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 98 return bus_space_read_1(hp->iot, hp->ioh, reg); 99 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 100 } 101 102 static uint16_t 103 hread2(struct sdhc_host *hp, bus_size_t reg) 104 { 105 106 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 107 return bus_space_read_2(hp->iot, hp->ioh, reg); 108 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 109 } 110 111 #define HREAD1(hp, reg) hread1(hp, reg) 112 #define HREAD2(hp, reg) hread2(hp, reg) 113 #define HREAD4(hp, reg) \ 114 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 115 116 117 static void 118 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 119 { 120 121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 122 bus_space_write_1(hp->iot, hp->ioh, o, val); 123 } else { 124 const size_t shift = 8 * (o & 3); 125 o &= -4; 126 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 127 tmp = (val << shift) | (tmp & ~(0xff << shift)); 128 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 129 } 130 } 131 132 static void 133 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 134 { 135 136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 137 bus_space_write_2(hp->iot, hp->ioh, o, val); 138 } else { 139 const size_t shift = 8 * (o & 2); 140 o &= -4; 141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 142 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 143 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 144 } 145 } 146 147 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 148 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 149 #define HWRITE4(hp, reg, val) \ 150 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 151 152 #define HCLR1(hp, reg, bits) \ 153 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 154 #define HCLR2(hp, reg, bits) \ 155 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 156 #define HCLR4(hp, reg, bits) \ 157 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 158 #define HSET1(hp, reg, bits) \ 159 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 160 #define HSET2(hp, reg, bits) \ 161 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 162 #define HSET4(hp, reg, bits) \ 163 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 164 165 static int sdhc_host_reset(sdmmc_chipset_handle_t); 166 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 167 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 168 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 169 static int sdhc_card_detect(sdmmc_chipset_handle_t); 170 static int sdhc_write_protect(sdmmc_chipset_handle_t); 171 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 172 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 173 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 174 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 175 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 176 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 177 static void sdhc_exec_command(sdmmc_chipset_handle_t, 178 struct sdmmc_command *); 179 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 180 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 181 static int sdhc_soft_reset(struct sdhc_host *, int); 182 static int sdhc_wait_intr(struct sdhc_host *, int, int); 183 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 184 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 185 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 186 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 188 static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 189 static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 190 191 192 static struct sdmmc_chip_functions sdhc_functions = { 193 /* host controller reset */ 194 sdhc_host_reset, 195 196 /* host controller capabilities */ 197 sdhc_host_ocr, 198 sdhc_host_maxblklen, 199 200 /* card detection */ 201 sdhc_card_detect, 202 203 /* write protect */ 204 sdhc_write_protect, 205 206 /* bus power, clock frequency and width */ 207 sdhc_bus_power, 208 sdhc_bus_clock, 209 sdhc_bus_width, 210 sdhc_bus_rod, 211 212 /* command execution */ 213 sdhc_exec_command, 214 215 /* card interrupt */ 216 sdhc_card_enable_intr, 217 sdhc_card_intr_ack 218 }; 219 220 static int 221 sdhc_cfprint(void *aux, const char *pnp) 222 { 223 const struct sdmmcbus_attach_args * const saa = aux; 224 const struct sdhc_host * const hp = saa->saa_sch; 225 226 if (pnp) { 227 aprint_normal("sdmmc at %s", pnp); 228 } 229 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) { 230 if (hp->sc->sc_host[host] == hp) { 231 aprint_normal(" slot %zu", host); 232 } 233 } 234 235 return UNCONF; 236 } 237 238 /* 239 * Called by attachment driver. For each SD card slot there is one SD 240 * host controller standard register set. (1.3) 241 */ 242 int 243 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 244 bus_space_handle_t ioh, bus_size_t iosize) 245 { 246 struct sdmmcbus_attach_args saa; 247 struct sdhc_host *hp; 248 uint32_t caps; 249 uint16_t sdhcver; 250 251 /* Allocate one more host structure. */ 252 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 253 if (hp == NULL) { 254 aprint_error_dev(sc->sc_dev, 255 "couldn't alloc memory (sdhc host)\n"); 256 goto err1; 257 } 258 sc->sc_host[sc->sc_nhosts++] = hp; 259 260 /* Fill in the new host structure. */ 261 hp->sc = sc; 262 hp->iot = iot; 263 hp->ioh = ioh; 264 hp->ios = iosize; 265 hp->dmat = sc->sc_dmat; 266 267 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 268 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 269 cv_init(&hp->intr_cv, "sdhcintr"); 270 271 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 272 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 273 hp->specver = SDHC_SPEC_VERSION(sdhcver); 274 switch (SDHC_SPEC_VERSION(sdhcver)) { 275 case SDHC_SPEC_VERS_100: 276 aprint_normal("1.0"); 277 break; 278 279 case SDHC_SPEC_VERS_200: 280 aprint_normal("2.0"); 281 break; 282 283 case SDHC_SPEC_VERS_300: 284 aprint_normal("3.0"); 285 break; 286 287 default: 288 aprint_normal("unknown version(0x%x)", 289 SDHC_SPEC_VERSION(sdhcver)); 290 break; 291 } 292 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 293 294 /* 295 * Reset the host controller and enable interrupts. 296 */ 297 (void)sdhc_host_reset(hp); 298 299 /* Determine host capabilities. */ 300 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 301 caps = sc->sc_caps; 302 } else { 303 mutex_enter(&hp->host_mtx); 304 caps = HREAD4(hp, SDHC_CAPABILITIES); 305 mutex_exit(&hp->host_mtx); 306 } 307 308 /* Use DMA if the host system and the controller support it. */ 309 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) || 310 (ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA && 311 ISSET(caps, SDHC_DMA_SUPPORT)))) { 312 SET(hp->flags, SHF_USE_DMA); 313 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 314 } 315 316 /* 317 * Determine the base clock frequency. (2.2.24) 318 */ 319 if (hp->specver == SDHC_SPEC_VERS_300) { 320 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 321 } else { 322 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 323 } 324 if (hp->clkbase == 0) { 325 if (sc->sc_clkbase == 0) { 326 /* The attachment driver must tell us. */ 327 aprint_error_dev(sc->sc_dev, 328 "unknown base clock frequency\n"); 329 goto err; 330 } 331 hp->clkbase = sc->sc_clkbase; 332 } 333 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 334 /* SDHC 1.0 supports only 10-63 MHz. */ 335 aprint_error_dev(sc->sc_dev, 336 "base clock frequency out of range: %u MHz\n", 337 hp->clkbase / 1000); 338 goto err; 339 } 340 DPRINTF(1,("%s: base clock frequency %u MHz\n", 341 device_xname(sc->sc_dev), hp->clkbase / 1000)); 342 343 /* 344 * XXX Set the data timeout counter value according to 345 * capabilities. (2.2.15) 346 */ 347 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 348 #if 1 349 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 350 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 351 #endif 352 353 /* 354 * Determine SD bus voltage levels supported by the controller. 355 */ 356 if (ISSET(caps, SDHC_EMBEDDED_SLOT) && 357 ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 358 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 359 } 360 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 361 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 362 } 363 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 364 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 365 } 366 367 /* 368 * Determine the maximum block length supported by the host 369 * controller. (2.2.24) 370 */ 371 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 372 case SDHC_MAX_BLK_LEN_512: 373 hp->maxblklen = 512; 374 break; 375 376 case SDHC_MAX_BLK_LEN_1024: 377 hp->maxblklen = 1024; 378 break; 379 380 case SDHC_MAX_BLK_LEN_2048: 381 hp->maxblklen = 2048; 382 break; 383 384 case SDHC_MAX_BLK_LEN_4096: 385 hp->maxblklen = 4096; 386 break; 387 388 default: 389 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 390 goto err; 391 } 392 DPRINTF(1, ("%s: max block length %u byte%s\n", 393 device_xname(sc->sc_dev), hp->maxblklen, 394 hp->maxblklen > 1 ? "s" : "")); 395 396 /* 397 * Attach the generic SD/MMC bus driver. (The bus driver must 398 * not invoke any chipset functions before it is attached.) 399 */ 400 memset(&saa, 0, sizeof(saa)); 401 saa.saa_busname = "sdmmc"; 402 saa.saa_sct = &sdhc_functions; 403 saa.saa_sch = hp; 404 saa.saa_dmat = hp->dmat; 405 saa.saa_clkmax = hp->clkbase; 406 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 407 saa.saa_clkmin = hp->clkbase / 256 / 2046; 408 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 409 saa.saa_clkmin = hp->clkbase / 256 / 16; 410 else if (hp->sc->sc_clkmsk != 0) 411 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >> 412 (ffs(hp->sc->sc_clkmsk) - 1)); 413 else if (hp->specver == SDHC_SPEC_VERS_300) 414 saa.saa_clkmin = hp->clkbase / 0x3ff; 415 else 416 saa.saa_clkmin = hp->clkbase / 256; 417 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 418 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 419 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 420 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 421 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 422 if (ISSET(hp->flags, SHF_USE_DMA)) { 423 saa.saa_caps |= SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA; 424 } 425 if (ISSET(sc->sc_flags, SDHC_FLAG_SINGLE_ONLY)) 426 saa.saa_caps |= SMC_CAPS_SINGLE_ONLY; 427 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint); 428 429 return 0; 430 431 err: 432 cv_destroy(&hp->intr_cv); 433 mutex_destroy(&hp->intr_mtx); 434 mutex_destroy(&hp->host_mtx); 435 free(hp, M_DEVBUF); 436 sc->sc_host[--sc->sc_nhosts] = NULL; 437 err1: 438 return 1; 439 } 440 441 int 442 sdhc_detach(struct sdhc_softc *sc, int flags) 443 { 444 struct sdhc_host *hp; 445 int rv = 0; 446 447 for (size_t n = 0; n < sc->sc_nhosts; n++) { 448 hp = sc->sc_host[n]; 449 if (hp == NULL) 450 continue; 451 if (hp->sdmmc != NULL) { 452 rv = config_detach(hp->sdmmc, flags); 453 if (rv) 454 break; 455 hp->sdmmc = NULL; 456 } 457 /* disable interrupts */ 458 if ((flags & DETACH_FORCE) == 0) { 459 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 460 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 461 } else { 462 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 463 } 464 sdhc_soft_reset(hp, SDHC_RESET_ALL); 465 } 466 cv_destroy(&hp->intr_cv); 467 mutex_destroy(&hp->intr_mtx); 468 mutex_destroy(&hp->host_mtx); 469 if (hp->ios > 0) { 470 bus_space_unmap(hp->iot, hp->ioh, hp->ios); 471 hp->ios = 0; 472 } 473 free(hp, M_DEVBUF); 474 sc->sc_host[n] = NULL; 475 } 476 477 return rv; 478 } 479 480 bool 481 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 482 { 483 struct sdhc_softc *sc = device_private(dev); 484 struct sdhc_host *hp; 485 size_t i; 486 487 /* XXX poll for command completion or suspend command 488 * in progress */ 489 490 /* Save the host controller state. */ 491 for (size_t n = 0; n < sc->sc_nhosts; n++) { 492 hp = sc->sc_host[n]; 493 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 494 for (i = 0; i < sizeof hp->regs; i += 4) { 495 uint32_t v = HREAD4(hp, i); 496 hp->regs[i + 0] = (v >> 0); 497 hp->regs[i + 1] = (v >> 8); 498 if (i + 3 < sizeof hp->regs) { 499 hp->regs[i + 2] = (v >> 16); 500 hp->regs[i + 3] = (v >> 24); 501 } 502 } 503 } else { 504 for (i = 0; i < sizeof hp->regs; i++) { 505 hp->regs[i] = HREAD1(hp, i); 506 } 507 } 508 } 509 return true; 510 } 511 512 bool 513 sdhc_resume(device_t dev, const pmf_qual_t *qual) 514 { 515 struct sdhc_softc *sc = device_private(dev); 516 struct sdhc_host *hp; 517 size_t i; 518 519 /* Restore the host controller state. */ 520 for (size_t n = 0; n < sc->sc_nhosts; n++) { 521 hp = sc->sc_host[n]; 522 (void)sdhc_host_reset(hp); 523 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 524 for (i = 0; i < sizeof hp->regs; i += 4) { 525 if (i + 3 < sizeof hp->regs) { 526 HWRITE4(hp, i, 527 (hp->regs[i + 0] << 0) 528 | (hp->regs[i + 1] << 8) 529 | (hp->regs[i + 2] << 16) 530 | (hp->regs[i + 3] << 24)); 531 } else { 532 HWRITE4(hp, i, 533 (hp->regs[i + 0] << 0) 534 | (hp->regs[i + 1] << 8)); 535 } 536 } 537 } else { 538 for (i = 0; i < sizeof hp->regs; i++) { 539 HWRITE1(hp, i, hp->regs[i]); 540 } 541 } 542 } 543 return true; 544 } 545 546 bool 547 sdhc_shutdown(device_t dev, int flags) 548 { 549 struct sdhc_softc *sc = device_private(dev); 550 struct sdhc_host *hp; 551 552 /* XXX chip locks up if we don't disable it before reboot. */ 553 for (size_t i = 0; i < sc->sc_nhosts; i++) { 554 hp = sc->sc_host[i]; 555 (void)sdhc_host_reset(hp); 556 } 557 return true; 558 } 559 560 /* 561 * Reset the host controller. Called during initialization, when 562 * cards are removed, upon resume, and during error recovery. 563 */ 564 static int 565 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 566 { 567 struct sdhc_host *hp = (struct sdhc_host *)sch; 568 uint32_t sdhcimask; 569 int error; 570 571 /* Don't lock. */ 572 573 /* Disable all interrupts. */ 574 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 575 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 576 } else { 577 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 578 } 579 580 /* 581 * Reset the entire host controller and wait up to 100ms for 582 * the controller to clear the reset bit. 583 */ 584 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 585 if (error) 586 goto out; 587 588 /* Set data timeout counter value to max for now. */ 589 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 590 #if 1 591 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 592 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 593 #endif 594 595 /* Enable interrupts. */ 596 mutex_enter(&hp->intr_mtx); 597 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 598 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 599 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 600 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 601 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 602 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 603 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 604 sdhcimask ^= 605 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 606 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 607 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 608 } else { 609 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 610 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 611 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 612 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 613 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 614 } 615 mutex_exit(&hp->intr_mtx); 616 617 out: 618 return error; 619 } 620 621 static int 622 sdhc_host_reset(sdmmc_chipset_handle_t sch) 623 { 624 struct sdhc_host *hp = (struct sdhc_host *)sch; 625 int error; 626 627 mutex_enter(&hp->host_mtx); 628 error = sdhc_host_reset1(sch); 629 mutex_exit(&hp->host_mtx); 630 631 return error; 632 } 633 634 static uint32_t 635 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 636 { 637 struct sdhc_host *hp = (struct sdhc_host *)sch; 638 639 return hp->ocr; 640 } 641 642 static int 643 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 644 { 645 struct sdhc_host *hp = (struct sdhc_host *)sch; 646 647 return hp->maxblklen; 648 } 649 650 /* 651 * Return non-zero if the card is currently inserted. 652 */ 653 static int 654 sdhc_card_detect(sdmmc_chipset_handle_t sch) 655 { 656 struct sdhc_host *hp = (struct sdhc_host *)sch; 657 int r; 658 659 if (hp->sc->sc_vendor_card_detect) 660 return (*hp->sc->sc_vendor_card_detect)(hp->sc); 661 662 mutex_enter(&hp->host_mtx); 663 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 664 mutex_exit(&hp->host_mtx); 665 666 return r ? 1 : 0; 667 } 668 669 /* 670 * Return non-zero if the card is currently write-protected. 671 */ 672 static int 673 sdhc_write_protect(sdmmc_chipset_handle_t sch) 674 { 675 struct sdhc_host *hp = (struct sdhc_host *)sch; 676 int r; 677 678 if (hp->sc->sc_vendor_write_protect) 679 return (*hp->sc->sc_vendor_write_protect)(hp->sc); 680 681 mutex_enter(&hp->host_mtx); 682 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 683 mutex_exit(&hp->host_mtx); 684 685 return r ? 0 : 1; 686 } 687 688 /* 689 * Set or change SD bus voltage and enable or disable SD bus power. 690 * Return zero on success. 691 */ 692 static int 693 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 694 { 695 struct sdhc_host *hp = (struct sdhc_host *)sch; 696 uint8_t vdd; 697 int error = 0; 698 const uint32_t pcmask = 699 ~(SDHC_BUS_POWER | (SDHC_VOLTAGE_MASK << SDHC_VOLTAGE_SHIFT)); 700 701 mutex_enter(&hp->host_mtx); 702 703 /* 704 * Disable bus power before voltage change. 705 */ 706 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 707 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 708 HWRITE1(hp, SDHC_POWER_CTL, 0); 709 710 /* If power is disabled, reset the host and return now. */ 711 if (ocr == 0) { 712 (void)sdhc_host_reset1(hp); 713 goto out; 714 } 715 716 /* 717 * Select the lowest voltage according to capabilities. 718 */ 719 ocr &= hp->ocr; 720 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 721 vdd = SDHC_VOLTAGE_1_8V; 722 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 723 vdd = SDHC_VOLTAGE_3_0V; 724 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 725 vdd = SDHC_VOLTAGE_3_3V; 726 } else { 727 /* Unsupported voltage level requested. */ 728 error = EINVAL; 729 goto out; 730 } 731 732 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 733 /* 734 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 735 * voltage ramp until power rises. 736 */ 737 HWRITE1(hp, SDHC_POWER_CTL, 738 HREAD1(hp, SDHC_POWER_CTL) & pcmask); 739 sdmmc_delay(1); 740 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT)); 741 sdmmc_delay(1); 742 HSET1(hp, SDHC_POWER_CTL, SDHC_BUS_POWER); 743 sdmmc_delay(10000); 744 745 /* 746 * The host system may not power the bus due to battery low, 747 * etc. In that case, the host controller should clear the 748 * bus power bit. 749 */ 750 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 751 error = ENXIO; 752 goto out; 753 } 754 } 755 756 out: 757 mutex_exit(&hp->host_mtx); 758 759 return error; 760 } 761 762 /* 763 * Return the smallest possible base clock frequency divisor value 764 * for the CLOCK_CTL register to produce `freq' (KHz). 765 */ 766 static bool 767 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 768 { 769 u_int div; 770 771 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 772 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 773 if ((hp->clkbase / div) <= freq) { 774 *divp = SDHC_SDCLK_CGM 775 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 776 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 777 //freq = hp->clkbase / div; 778 return true; 779 } 780 } 781 /* No divisor found. */ 782 return false; 783 } 784 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 785 u_int dvs = (hp->clkbase + freq - 1) / freq; 786 u_int roundup = dvs & 1; 787 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 788 if (dvs + roundup <= 16) { 789 dvs += roundup - 1; 790 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 791 | (dvs << SDHC_SDCLK_DVS_SHIFT); 792 DPRINTF(2, 793 ("%s: divisor for freq %u is %u * %u\n", 794 HDEVNAME(hp), freq, div * 2, dvs + 1)); 795 //freq = hp->clkbase / (div * 2) * (dvs + 1); 796 return true; 797 } 798 /* 799 * If we drop bits, we need to round up the divisor. 800 */ 801 roundup |= dvs & 1; 802 } 803 /* No divisor found. */ 804 return false; 805 } 806 if (hp->sc->sc_clkmsk != 0) { 807 div = howmany(hp->clkbase, freq); 808 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1))) 809 return false; 810 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1); 811 //freq = hp->clkbase / div; 812 return true; 813 } 814 if (hp->specver == SDHC_SPEC_VERS_300) { 815 div = howmany(hp->clkbase, freq); 816 if (div > 0x3ff) 817 return false; 818 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 819 << SDHC_SDCLK_XDIV_SHIFT) | 820 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 821 << SDHC_SDCLK_DIV_SHIFT); 822 //freq = hp->clkbase / div; 823 return true; 824 } else { 825 for (div = 1; div <= 256; div *= 2) { 826 if ((hp->clkbase / div) <= freq) { 827 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 828 //freq = hp->clkbase / div; 829 return true; 830 } 831 } 832 /* No divisor found. */ 833 return false; 834 } 835 /* No divisor found. */ 836 return false; 837 } 838 839 /* 840 * Set or change SDCLK frequency or disable the SD clock. 841 * Return zero on success. 842 */ 843 static int 844 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 845 { 846 struct sdhc_host *hp = (struct sdhc_host *)sch; 847 u_int div; 848 u_int timo; 849 int16_t reg; 850 int error = 0; 851 #ifdef DIAGNOSTIC 852 bool present; 853 854 mutex_enter(&hp->host_mtx); 855 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 856 mutex_exit(&hp->host_mtx); 857 858 /* Must not stop the clock if commands are in progress. */ 859 if (present && sdhc_card_detect(hp)) { 860 aprint_normal_dev(hp->sc->sc_dev, 861 "%s: command in progress\n", __func__); 862 } 863 #endif 864 865 mutex_enter(&hp->host_mtx); 866 867 if (hp->sc->sc_vendor_bus_clock) { 868 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq); 869 if (error != 0) 870 goto out; 871 } 872 873 /* 874 * Stop SD clock before changing the frequency. 875 */ 876 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 877 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 878 if (freq == SDMMC_SDCLK_OFF) { 879 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 880 goto out; 881 } 882 } else { 883 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 884 if (freq == SDMMC_SDCLK_OFF) 885 goto out; 886 } 887 888 /* 889 * Set the minimum base clock frequency divisor. 890 */ 891 if (!sdhc_clock_divisor(hp, freq, &div)) { 892 /* Invalid base clock frequency or `freq' value. */ 893 error = EINVAL; 894 goto out; 895 } 896 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 897 HWRITE4(hp, SDHC_CLOCK_CTL, 898 div | (SDHC_TIMEOUT_MAX << 16)); 899 } else { 900 reg = HREAD2(hp, SDHC_CLOCK_CTL); 901 reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE); 902 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div); 903 } 904 905 /* 906 * Start internal clock. Wait 10ms for stabilization. 907 */ 908 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 909 sdmmc_delay(10000); 910 HSET4(hp, SDHC_CLOCK_CTL, 911 8 | SDHC_INTCLK_ENABLE | SDHC_INTCLK_STABLE); 912 } else { 913 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 914 for (timo = 1000; timo > 0; timo--) { 915 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), 916 SDHC_INTCLK_STABLE)) 917 break; 918 sdmmc_delay(10); 919 } 920 if (timo == 0) { 921 error = ETIMEDOUT; 922 goto out; 923 } 924 } 925 926 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 927 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 928 /* 929 * Sending 80 clocks at 400kHz takes 200us. 930 * So delay for that time + slop and then 931 * check a few times for completion. 932 */ 933 sdmmc_delay(210); 934 for (timo = 10; timo > 0; timo--) { 935 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 936 SDHC_INIT_ACTIVE)) 937 break; 938 sdmmc_delay(10); 939 } 940 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 941 942 /* 943 * Enable SD clock. 944 */ 945 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 946 } else { 947 /* 948 * Enable SD clock. 949 */ 950 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 951 952 if (freq > 25000 && 953 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 954 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 955 else 956 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 957 } 958 959 out: 960 mutex_exit(&hp->host_mtx); 961 962 return error; 963 } 964 965 static int 966 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 967 { 968 struct sdhc_host *hp = (struct sdhc_host *)sch; 969 int reg; 970 971 switch (width) { 972 case 1: 973 case 4: 974 break; 975 976 case 8: 977 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 978 break; 979 /* FALLTHROUGH */ 980 default: 981 DPRINTF(0,("%s: unsupported bus width (%d)\n", 982 HDEVNAME(hp), width)); 983 return 1; 984 } 985 986 mutex_enter(&hp->host_mtx); 987 reg = HREAD1(hp, SDHC_HOST_CTL); 988 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 989 reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE); 990 if (width == 4) 991 reg |= SDHC_4BIT_MODE; 992 else if (width == 8) 993 reg |= SDHC_ESDHC_8BIT_MODE; 994 } else { 995 reg &= ~SDHC_4BIT_MODE; 996 if (width == 4) 997 reg |= SDHC_4BIT_MODE; 998 } 999 HWRITE1(hp, SDHC_HOST_CTL, reg); 1000 mutex_exit(&hp->host_mtx); 1001 1002 return 0; 1003 } 1004 1005 static int 1006 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 1007 { 1008 struct sdhc_host *hp = (struct sdhc_host *)sch; 1009 1010 if (hp->sc->sc_vendor_rod) 1011 return (*hp->sc->sc_vendor_rod)(hp->sc, on); 1012 1013 return 0; 1014 } 1015 1016 static void 1017 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1018 { 1019 struct sdhc_host *hp = (struct sdhc_host *)sch; 1020 1021 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1022 mutex_enter(&hp->intr_mtx); 1023 if (enable) { 1024 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1025 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1026 } else { 1027 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 1028 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1029 } 1030 mutex_exit(&hp->intr_mtx); 1031 } 1032 } 1033 1034 static void 1035 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 1036 { 1037 struct sdhc_host *hp = (struct sdhc_host *)sch; 1038 1039 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1040 mutex_enter(&hp->intr_mtx); 1041 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1042 mutex_exit(&hp->intr_mtx); 1043 } 1044 } 1045 1046 static int 1047 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 1048 { 1049 uint32_t state; 1050 int timeout; 1051 1052 for (timeout = 10; timeout > 0; timeout--) { 1053 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 1054 return 0; 1055 sdmmc_delay(10000); 1056 } 1057 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 1058 value, state)); 1059 return ETIMEDOUT; 1060 } 1061 1062 static void 1063 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1064 { 1065 struct sdhc_host *hp = (struct sdhc_host *)sch; 1066 int error; 1067 1068 if (cmd->c_data && ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1069 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 1070 mutex_enter(&hp->intr_mtx); 1071 if (ISSET(hp->flags, SHF_USE_DMA)) { 1072 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1073 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 1074 } else { 1075 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 1076 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 1077 } 1078 mutex_exit(&hp->intr_mtx); 1079 } 1080 1081 /* 1082 * Start the MMC command, or mark `cmd' as failed and return. 1083 */ 1084 error = sdhc_start_command(hp, cmd); 1085 if (error) { 1086 cmd->c_error = error; 1087 goto out; 1088 } 1089 1090 /* 1091 * Wait until the command phase is done, or until the command 1092 * is marked done for any other reason. 1093 */ 1094 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1095 cmd->c_error = ETIMEDOUT; 1096 goto out; 1097 } 1098 1099 /* 1100 * The host controller removes bits [0:7] from the response 1101 * data (CRC) and we pass the data up unchanged to the bus 1102 * driver (without padding). 1103 */ 1104 mutex_enter(&hp->host_mtx); 1105 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1106 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1107 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1108 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1109 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1110 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1111 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) { 1112 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1113 (cmd->c_resp[1] << 24); 1114 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1115 (cmd->c_resp[2] << 24); 1116 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1117 (cmd->c_resp[3] << 24); 1118 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1119 } 1120 } 1121 } 1122 mutex_exit(&hp->host_mtx); 1123 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1124 1125 /* 1126 * If the command has data to transfer in any direction, 1127 * execute the transfer now. 1128 */ 1129 if (cmd->c_error == 0 && cmd->c_data != NULL) 1130 sdhc_transfer_data(hp, cmd); 1131 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 1132 if (!sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10)) { 1133 cmd->c_error = ETIMEDOUT; 1134 goto out; 1135 } 1136 } 1137 1138 out: 1139 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1140 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1141 mutex_enter(&hp->host_mtx); 1142 /* Turn off the LED. */ 1143 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1144 mutex_exit(&hp->host_mtx); 1145 } 1146 SET(cmd->c_flags, SCF_ITSDONE); 1147 1148 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1149 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1150 cmd->c_flags, cmd->c_error)); 1151 } 1152 1153 static int 1154 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1155 { 1156 struct sdhc_softc * const sc = hp->sc; 1157 uint16_t blksize = 0; 1158 uint16_t blkcount = 0; 1159 uint16_t mode; 1160 uint16_t command; 1161 int error; 1162 1163 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1164 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1165 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1166 1167 /* 1168 * The maximum block length for commands should be the minimum 1169 * of the host buffer size and the card buffer size. (1.7.2) 1170 */ 1171 1172 /* Fragment the data into proper blocks. */ 1173 if (cmd->c_datalen > 0) { 1174 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1175 blkcount = cmd->c_datalen / blksize; 1176 if (cmd->c_datalen % blksize > 0) { 1177 /* XXX: Split this command. (1.7.4) */ 1178 aprint_error_dev(sc->sc_dev, 1179 "data not a multiple of %u bytes\n", blksize); 1180 return EINVAL; 1181 } 1182 } 1183 1184 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1185 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1186 aprint_error_dev(sc->sc_dev, "too much data\n"); 1187 return EINVAL; 1188 } 1189 1190 /* Prepare transfer mode register value. (2.2.5) */ 1191 mode = SDHC_BLOCK_COUNT_ENABLE; 1192 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1193 mode |= SDHC_READ_MODE; 1194 if (blkcount > 1) { 1195 mode |= SDHC_MULTI_BLOCK_MODE; 1196 /* XXX only for memory commands? */ 1197 mode |= SDHC_AUTO_CMD12_ENABLE; 1198 } 1199 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0 && 1200 !ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) { 1201 mode |= SDHC_DMA_ENABLE; 1202 } 1203 1204 /* 1205 * Prepare command register value. (2.2.6) 1206 */ 1207 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1208 1209 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1210 command |= SDHC_CRC_CHECK_ENABLE; 1211 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1212 command |= SDHC_INDEX_CHECK_ENABLE; 1213 if (cmd->c_data != NULL) 1214 command |= SDHC_DATA_PRESENT_SELECT; 1215 1216 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1217 command |= SDHC_NO_RESPONSE; 1218 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1219 command |= SDHC_RESP_LEN_136; 1220 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1221 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1222 else 1223 command |= SDHC_RESP_LEN_48; 1224 1225 /* Wait until command and data inhibit bits are clear. (1.5) */ 1226 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1227 if (error) 1228 return error; 1229 1230 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1231 HDEVNAME(hp), blksize, blkcount, mode, command)); 1232 1233 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1234 blksize |= (MAX(0, PAGE_SHIFT - 12) & SDHC_DMA_BOUNDARY_MASK) << 1235 SDHC_DMA_BOUNDARY_SHIFT; /* PAGE_SIZE DMA boundary */ 1236 } 1237 1238 mutex_enter(&hp->host_mtx); 1239 1240 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1241 /* Alert the user not to remove the card. */ 1242 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1243 } 1244 1245 /* Set DMA start address. */ 1246 if (ISSET(mode, SDHC_DMA_ENABLE)) 1247 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1248 1249 /* 1250 * Start a CPU data transfer. Writing to the high order byte 1251 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1252 */ 1253 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1254 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1255 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1256 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1257 } else { 1258 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1259 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1260 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1261 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1262 HWRITE2(hp, SDHC_COMMAND, command); 1263 } 1264 1265 mutex_exit(&hp->host_mtx); 1266 1267 return 0; 1268 } 1269 1270 static void 1271 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1272 { 1273 int error; 1274 1275 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1276 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1277 1278 #ifdef SDHC_DEBUG 1279 /* XXX I forgot why I wanted to know when this happens :-( */ 1280 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1281 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1282 aprint_error_dev(hp->sc->sc_dev, 1283 "CMD52/53 error response flags %#x\n", 1284 MMC_R1(cmd->c_resp) & 0xff00); 1285 } 1286 #endif 1287 1288 if (cmd->c_dmamap != NULL) { 1289 if (hp->sc->sc_vendor_transfer_data_dma != NULL) { 1290 error = hp->sc->sc_vendor_transfer_data_dma(hp, cmd); 1291 if (error == 0 && !sdhc_wait_intr(hp, 1292 SDHC_TRANSFER_COMPLETE, SDHC_TRANSFER_TIMEOUT)) { 1293 error = ETIMEDOUT; 1294 } 1295 } else { 1296 error = sdhc_transfer_data_dma(hp, cmd); 1297 } 1298 } else 1299 error = sdhc_transfer_data_pio(hp, cmd); 1300 if (error) 1301 cmd->c_error = error; 1302 SET(cmd->c_flags, SCF_ITSDONE); 1303 1304 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1305 HDEVNAME(hp), cmd->c_error)); 1306 } 1307 1308 static int 1309 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1310 { 1311 bus_dma_segment_t *dm_segs = cmd->c_dmamap->dm_segs; 1312 bus_addr_t posaddr; 1313 bus_addr_t segaddr; 1314 bus_size_t seglen; 1315 u_int seg = 0; 1316 int error = 0; 1317 int status; 1318 1319 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1320 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1321 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1322 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1323 1324 for (;;) { 1325 status = sdhc_wait_intr(hp, 1326 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1327 SDHC_DMA_TIMEOUT); 1328 1329 if (status & SDHC_TRANSFER_COMPLETE) { 1330 break; 1331 } 1332 if (!status) { 1333 error = ETIMEDOUT; 1334 break; 1335 } 1336 if ((status & SDHC_DMA_INTERRUPT) == 0) { 1337 continue; 1338 } 1339 1340 /* DMA Interrupt (boundary crossing) */ 1341 1342 segaddr = dm_segs[seg].ds_addr; 1343 seglen = dm_segs[seg].ds_len; 1344 mutex_enter(&hp->host_mtx); 1345 posaddr = HREAD4(hp, SDHC_DMA_ADDR); 1346 mutex_exit(&hp->host_mtx); 1347 1348 if ((seg == (cmd->c_dmamap->dm_nsegs-1)) && (posaddr == (segaddr + seglen))) { 1349 continue; 1350 } 1351 mutex_enter(&hp->host_mtx); 1352 if ((posaddr >= segaddr) && (posaddr < (segaddr + seglen))) 1353 HWRITE4(hp, SDHC_DMA_ADDR, posaddr); 1354 else if ((posaddr >= segaddr) && (posaddr == (segaddr + seglen)) && (seg + 1) < cmd->c_dmamap->dm_nsegs) 1355 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr); 1356 mutex_exit(&hp->host_mtx); 1357 KASSERT(seg < cmd->c_dmamap->dm_nsegs); 1358 } 1359 1360 return error; 1361 } 1362 1363 static int 1364 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1365 { 1366 uint8_t *data = cmd->c_data; 1367 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1368 u_int len, datalen; 1369 u_int imask; 1370 u_int pmask; 1371 int error = 0; 1372 1373 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1374 imask = SDHC_BUFFER_READ_READY; 1375 pmask = SDHC_BUFFER_READ_ENABLE; 1376 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1377 pio_func = esdhc_read_data_pio; 1378 } else { 1379 pio_func = sdhc_read_data_pio; 1380 } 1381 } else { 1382 imask = SDHC_BUFFER_WRITE_READY; 1383 pmask = SDHC_BUFFER_WRITE_ENABLE; 1384 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1385 pio_func = esdhc_write_data_pio; 1386 } else { 1387 pio_func = sdhc_write_data_pio; 1388 } 1389 } 1390 datalen = cmd->c_datalen; 1391 1392 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1393 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1394 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1395 1396 while (datalen > 0) { 1397 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1398 mutex_enter(&hp->intr_mtx); 1399 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1400 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1401 } else { 1402 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1403 } 1404 mutex_exit(&hp->intr_mtx); 1405 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1406 error = ETIMEDOUT; 1407 break; 1408 } 1409 1410 error = sdhc_wait_state(hp, pmask, pmask); 1411 if (error) 1412 break; 1413 } 1414 1415 len = MIN(datalen, cmd->c_blklen); 1416 (*pio_func)(hp, data, len); 1417 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1418 HDEVNAME(hp), len, data)); 1419 1420 data += len; 1421 datalen -= len; 1422 } 1423 1424 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1425 SDHC_TRANSFER_TIMEOUT)) 1426 error = ETIMEDOUT; 1427 1428 return error; 1429 } 1430 1431 static void 1432 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1433 { 1434 1435 if (((__uintptr_t)data & 3) == 0) { 1436 while (datalen > 3) { 1437 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA)); 1438 data += 4; 1439 datalen -= 4; 1440 } 1441 if (datalen > 1) { 1442 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1443 data += 2; 1444 datalen -= 2; 1445 } 1446 if (datalen > 0) { 1447 *data = HREAD1(hp, SDHC_DATA); 1448 data += 1; 1449 datalen -= 1; 1450 } 1451 } else if (((__uintptr_t)data & 1) == 0) { 1452 while (datalen > 1) { 1453 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA)); 1454 data += 2; 1455 datalen -= 2; 1456 } 1457 if (datalen > 0) { 1458 *data = HREAD1(hp, SDHC_DATA); 1459 data += 1; 1460 datalen -= 1; 1461 } 1462 } else { 1463 while (datalen > 0) { 1464 *data = HREAD1(hp, SDHC_DATA); 1465 data += 1; 1466 datalen -= 1; 1467 } 1468 } 1469 } 1470 1471 static void 1472 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1473 { 1474 1475 if (((__uintptr_t)data & 3) == 0) { 1476 while (datalen > 3) { 1477 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data)); 1478 data += 4; 1479 datalen -= 4; 1480 } 1481 if (datalen > 1) { 1482 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1483 data += 2; 1484 datalen -= 2; 1485 } 1486 if (datalen > 0) { 1487 HWRITE1(hp, SDHC_DATA, *data); 1488 data += 1; 1489 datalen -= 1; 1490 } 1491 } else if (((__uintptr_t)data & 1) == 0) { 1492 while (datalen > 1) { 1493 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data)); 1494 data += 2; 1495 datalen -= 2; 1496 } 1497 if (datalen > 0) { 1498 HWRITE1(hp, SDHC_DATA, *data); 1499 data += 1; 1500 datalen -= 1; 1501 } 1502 } else { 1503 while (datalen > 0) { 1504 HWRITE1(hp, SDHC_DATA, *data); 1505 data += 1; 1506 datalen -= 1; 1507 } 1508 } 1509 } 1510 1511 static void 1512 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1513 { 1514 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1515 uint32_t v; 1516 1517 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1518 size_t count = 0; 1519 1520 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1521 if (count == 0) { 1522 /* 1523 * If we've drained "watermark" words, we need to wait 1524 * a little bit so the read FIFO can refill. 1525 */ 1526 sdmmc_delay(10); 1527 count = watermark; 1528 } 1529 v = HREAD4(hp, SDHC_DATA); 1530 v = le32toh(v); 1531 *(uint32_t *)data = v; 1532 data += 4; 1533 datalen -= 4; 1534 status = HREAD2(hp, SDHC_NINTR_STATUS); 1535 count--; 1536 } 1537 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1538 if (count == 0) { 1539 sdmmc_delay(10); 1540 } 1541 v = HREAD4(hp, SDHC_DATA); 1542 v = le32toh(v); 1543 do { 1544 *data++ = v; 1545 v >>= 8; 1546 } while (--datalen > 0); 1547 } 1548 } 1549 1550 static void 1551 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1552 { 1553 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1554 uint32_t v; 1555 1556 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1557 size_t count = watermark; 1558 1559 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1560 if (count == 0) { 1561 sdmmc_delay(10); 1562 count = watermark; 1563 } 1564 v = *(uint32_t *)data; 1565 v = htole32(v); 1566 HWRITE4(hp, SDHC_DATA, v); 1567 data += 4; 1568 datalen -= 4; 1569 status = HREAD2(hp, SDHC_NINTR_STATUS); 1570 count--; 1571 } 1572 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1573 if (count == 0) { 1574 sdmmc_delay(10); 1575 } 1576 v = *(uint32_t *)data; 1577 v = htole32(v); 1578 HWRITE4(hp, SDHC_DATA, v); 1579 } 1580 } 1581 1582 /* Prepare for another command. */ 1583 static int 1584 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1585 { 1586 int timo; 1587 1588 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1589 1590 /* Request the reset. */ 1591 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1592 1593 /* 1594 * If necessary, wait for the controller to set the bits to 1595 * acknowledge the reset. 1596 */ 1597 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) && 1598 ISSET(mask, (SDHC_RESET_DAT | SDHC_RESET_CMD))) { 1599 for (timo = 10000; timo > 0; timo--) { 1600 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1601 break; 1602 /* Short delay because I worry we may miss it... */ 1603 sdmmc_delay(1); 1604 } 1605 if (timo == 0) 1606 return ETIMEDOUT; 1607 } 1608 1609 /* 1610 * Wait for the controller to clear the bits to indicate that 1611 * the reset has completed. 1612 */ 1613 for (timo = 10; timo > 0; timo--) { 1614 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1615 break; 1616 sdmmc_delay(10000); 1617 } 1618 if (timo == 0) { 1619 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1620 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1621 return ETIMEDOUT; 1622 } 1623 1624 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1625 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int 1632 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1633 { 1634 int status; 1635 1636 mask |= SDHC_ERROR_INTERRUPT; 1637 1638 mutex_enter(&hp->intr_mtx); 1639 status = hp->intr_status & mask; 1640 while (status == 0) { 1641 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1642 == EWOULDBLOCK) { 1643 status |= SDHC_ERROR_INTERRUPT; 1644 break; 1645 } 1646 status = hp->intr_status & mask; 1647 } 1648 hp->intr_status &= ~status; 1649 1650 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1651 hp->intr_error_status)); 1652 1653 /* Command timeout has higher priority than command complete. */ 1654 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1655 hp->intr_error_status = 0; 1656 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1657 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1658 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1659 } 1660 status = 0; 1661 } 1662 mutex_exit(&hp->intr_mtx); 1663 1664 return status; 1665 } 1666 1667 /* 1668 * Established by attachment driver at interrupt priority IPL_SDMMC. 1669 */ 1670 int 1671 sdhc_intr(void *arg) 1672 { 1673 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1674 struct sdhc_host *hp; 1675 int done = 0; 1676 uint16_t status; 1677 uint16_t error; 1678 1679 /* We got an interrupt, but we don't know from which slot. */ 1680 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1681 hp = sc->sc_host[host]; 1682 if (hp == NULL) 1683 continue; 1684 1685 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1686 /* Find out which interrupts are pending. */ 1687 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1688 status = xstatus; 1689 error = xstatus >> 16; 1690 if (error) 1691 xstatus |= SDHC_ERROR_INTERRUPT; 1692 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1693 continue; /* no interrupt for us */ 1694 /* Acknowledge the interrupts we are about to handle. */ 1695 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1696 } else { 1697 /* Find out which interrupts are pending. */ 1698 error = 0; 1699 status = HREAD2(hp, SDHC_NINTR_STATUS); 1700 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1701 continue; /* no interrupt for us */ 1702 /* Acknowledge the interrupts we are about to handle. */ 1703 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1704 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1705 /* Acknowledge error interrupts. */ 1706 error = HREAD2(hp, SDHC_EINTR_STATUS); 1707 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1708 } 1709 } 1710 1711 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1712 status, error)); 1713 1714 mutex_enter(&hp->intr_mtx); 1715 1716 /* Claim this interrupt. */ 1717 done = 1; 1718 1719 /* 1720 * Service error interrupts. 1721 */ 1722 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1723 SDHC_DATA_TIMEOUT_ERROR)) { 1724 hp->intr_error_status |= error; 1725 hp->intr_status |= status; 1726 cv_broadcast(&hp->intr_cv); 1727 } 1728 1729 /* 1730 * Wake up the sdmmc event thread to scan for cards. 1731 */ 1732 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1733 if (hp->sdmmc != NULL) { 1734 sdmmc_needs_discover(hp->sdmmc); 1735 } 1736 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1737 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1738 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1739 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1740 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1741 } 1742 } 1743 1744 /* 1745 * Wake up the blocking process to service command 1746 * related interrupt(s). 1747 */ 1748 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1749 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1750 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1751 hp->intr_status |= status; 1752 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1753 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1754 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1755 } 1756 cv_broadcast(&hp->intr_cv); 1757 } 1758 1759 /* 1760 * Service SD card interrupts. 1761 */ 1762 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1763 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1764 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1765 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1766 sdmmc_card_intr(hp->sdmmc); 1767 } 1768 mutex_exit(&hp->intr_mtx); 1769 } 1770 1771 return done; 1772 } 1773 1774 #ifdef SDHC_DEBUG 1775 void 1776 sdhc_dump_regs(struct sdhc_host *hp) 1777 { 1778 1779 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1780 HREAD4(hp, SDHC_PRESENT_STATE)); 1781 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1782 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1783 HREAD1(hp, SDHC_POWER_CTL)); 1784 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1785 HREAD2(hp, SDHC_NINTR_STATUS)); 1786 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1787 HREAD2(hp, SDHC_EINTR_STATUS)); 1788 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1789 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1790 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1791 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1792 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1793 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1794 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1795 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1796 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1797 HREAD4(hp, SDHC_CAPABILITIES)); 1798 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1799 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1800 } 1801 #endif 1802