1 /* $NetBSD: sdhc.c,v 1.5 2010/01/12 08:41:16 uebayasi Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.5 2010/01/12 08:41:16 uebayasi Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/kthread.h> 32 #include <sys/malloc.h> 33 #include <sys/systm.h> 34 #include <sys/mutex.h> 35 #include <sys/condvar.h> 36 37 #include <dev/sdmmc/sdhcreg.h> 38 #include <dev/sdmmc/sdhcvar.h> 39 #include <dev/sdmmc/sdmmcchip.h> 40 #include <dev/sdmmc/sdmmcreg.h> 41 #include <dev/sdmmc/sdmmcvar.h> 42 43 #ifdef SDHC_DEBUG 44 int sdhcdebug = 1; 45 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 46 void sdhc_dump_regs(struct sdhc_host *); 47 #else 48 #define DPRINTF(n,s) do {} while (0) 49 #endif 50 51 #define SDHC_COMMAND_TIMEOUT hz 52 #define SDHC_BUFFER_TIMEOUT hz 53 #define SDHC_TRANSFER_TIMEOUT hz 54 #define SDHC_DMA_TIMEOUT hz 55 56 struct sdhc_host { 57 struct sdhc_softc *sc; /* host controller device */ 58 59 bus_space_tag_t iot; /* host register set tag */ 60 bus_space_handle_t ioh; /* host register set handle */ 61 bus_dma_tag_t dmat; /* host DMA tag */ 62 63 device_t sdmmc; /* generic SD/MMC device */ 64 65 struct kmutex host_mtx; 66 67 u_int clkbase; /* base clock frequency in KHz */ 68 int maxblklen; /* maximum block length */ 69 uint32_t ocr; /* OCR value from capabilities */ 70 71 uint8_t regs[14]; /* host controller state */ 72 73 uint16_t intr_status; /* soft interrupt status */ 74 uint16_t intr_error_status; /* soft error status */ 75 struct kmutex intr_mtx; 76 struct kcondvar intr_cv; 77 78 uint32_t flags; /* flags for this host */ 79 #define SHF_USE_DMA 0x0001 80 #define SHF_USE_4BIT_MODE 0x0002 81 }; 82 83 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 84 85 #define HREAD1(hp, reg) \ 86 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 87 #define HREAD2(hp, reg) \ 88 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 89 #define HREAD4(hp, reg) \ 90 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 91 #define HWRITE1(hp, reg, val) \ 92 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 93 #define HWRITE2(hp, reg, val) \ 94 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 95 #define HWRITE4(hp, reg, val) \ 96 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 97 #define HCLR1(hp, reg, bits) \ 98 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 99 #define HCLR2(hp, reg, bits) \ 100 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 101 #define HSET1(hp, reg, bits) \ 102 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 103 #define HSET2(hp, reg, bits) \ 104 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 105 106 static int sdhc_host_reset(sdmmc_chipset_handle_t); 107 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 108 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 109 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 110 static int sdhc_card_detect(sdmmc_chipset_handle_t); 111 static int sdhc_write_protect(sdmmc_chipset_handle_t); 112 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 113 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 114 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 115 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 116 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 117 static void sdhc_exec_command(sdmmc_chipset_handle_t, 118 struct sdmmc_command *); 119 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 120 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 121 static int sdhc_soft_reset(struct sdhc_host *, int); 122 static int sdhc_wait_intr(struct sdhc_host *, int, int); 123 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 124 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 125 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int); 126 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int); 127 128 static struct sdmmc_chip_functions sdhc_functions = { 129 /* host controller reset */ 130 sdhc_host_reset, 131 132 /* host controller capabilities */ 133 sdhc_host_ocr, 134 sdhc_host_maxblklen, 135 136 /* card detection */ 137 sdhc_card_detect, 138 139 /* write protect */ 140 sdhc_write_protect, 141 142 /* bus power, clock frequency and width */ 143 sdhc_bus_power, 144 sdhc_bus_clock, 145 sdhc_bus_width, 146 147 /* command execution */ 148 sdhc_exec_command, 149 150 /* card interrupt */ 151 sdhc_card_enable_intr, 152 sdhc_card_intr_ack 153 }; 154 155 /* 156 * Called by attachment driver. For each SD card slot there is one SD 157 * host controller standard register set. (1.3) 158 */ 159 int 160 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 161 bus_space_handle_t ioh, bus_size_t iosize) 162 { 163 struct sdmmcbus_attach_args saa; 164 struct sdhc_host *hp; 165 uint32_t caps; 166 #ifdef SDHC_DEBUG 167 uint16_t sdhcver; 168 169 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 170 aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version "); 171 switch (SDHC_SPEC_VERSION(sdhcver)) { 172 case 0x00: 173 aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 174 break; 175 176 default: 177 aprint_normal(">1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 178 break; 179 } 180 #endif 181 182 /* Allocate one more host structure. */ 183 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 184 if (hp == NULL) { 185 aprint_error_dev(sc->sc_dev, 186 "couldn't alloc memory (sdhc host)\n"); 187 goto err1; 188 } 189 sc->sc_host[sc->sc_nhosts++] = hp; 190 191 /* Fill in the new host structure. */ 192 hp->sc = sc; 193 hp->iot = iot; 194 hp->ioh = ioh; 195 hp->dmat = sc->sc_dmat; 196 197 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 198 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 199 cv_init(&hp->intr_cv, "sdhcintr"); 200 201 /* 202 * Reset the host controller and enable interrupts. 203 */ 204 (void)sdhc_host_reset(hp); 205 206 /* Determine host capabilities. */ 207 mutex_enter(&hp->host_mtx); 208 caps = HREAD4(hp, SDHC_CAPABILITIES); 209 mutex_exit(&hp->host_mtx); 210 211 #if notyet 212 /* Use DMA if the host system and the controller support it. */ 213 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 214 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 215 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 216 SET(hp->flags, SHF_USE_DMA); 217 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 218 } 219 #endif 220 221 /* 222 * Determine the base clock frequency. (2.2.24) 223 */ 224 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 225 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 226 if (hp->clkbase == 0) { 227 /* The attachment driver must tell us. */ 228 aprint_error_dev(sc->sc_dev,"unknown base clock frequency\n"); 229 goto err; 230 } else if (hp->clkbase < 10000 || hp->clkbase > 63000) { 231 /* SDHC 1.0 supports only 10-63 MHz. */ 232 aprint_error_dev(sc->sc_dev, 233 "base clock frequency out of range: %u MHz\n", 234 hp->clkbase / 1000); 235 goto err; 236 } 237 DPRINTF(1,("%s: base clock frequency %u MHz\n", 238 device_xname(sc->sc_dev), hp->clkbase / 1000)); 239 240 /* 241 * XXX Set the data timeout counter value according to 242 * capabilities. (2.2.15) 243 */ 244 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 245 246 /* 247 * Determine SD bus voltage levels supported by the controller. 248 */ 249 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 250 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 251 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 252 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 253 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 254 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 255 256 /* 257 * Determine the maximum block length supported by the host 258 * controller. (2.2.24) 259 */ 260 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 261 case SDHC_MAX_BLK_LEN_512: 262 hp->maxblklen = 512; 263 break; 264 265 case SDHC_MAX_BLK_LEN_1024: 266 hp->maxblklen = 1024; 267 break; 268 269 case SDHC_MAX_BLK_LEN_2048: 270 hp->maxblklen = 2048; 271 break; 272 273 default: 274 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 275 goto err; 276 } 277 DPRINTF(1, ("%s: max block length %u byte%s\n", 278 device_xname(sc->sc_dev), hp->maxblklen, 279 hp->maxblklen > 1 ? "s" : "")); 280 281 /* 282 * Attach the generic SD/MMC bus driver. (The bus driver must 283 * not invoke any chipset functions before it is attached.) 284 */ 285 memset(&saa, 0, sizeof(saa)); 286 saa.saa_busname = "sdmmc"; 287 saa.saa_sct = &sdhc_functions; 288 saa.saa_sch = hp; 289 saa.saa_dmat = hp->dmat; 290 saa.saa_clkmin = hp->clkbase / 256; 291 saa.saa_clkmax = hp->clkbase; 292 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 293 #if notyet 294 if (ISSET(hp->flags, SHF_USE_DMA)) 295 saa.saa_caps |= SMC_CAPS_DMA; 296 #endif 297 298 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 299 300 return 0; 301 302 err: 303 cv_destroy(&hp->intr_cv); 304 mutex_destroy(&hp->intr_mtx); 305 mutex_destroy(&hp->host_mtx); 306 free(hp, M_DEVBUF); 307 sc->sc_host[--sc->sc_nhosts] = NULL; 308 err1: 309 return 1; 310 } 311 312 bool 313 sdhc_suspend(device_t dev, pmf_qual_t qual) 314 { 315 struct sdhc_softc *sc = device_private(dev); 316 struct sdhc_host *hp; 317 int n, i; 318 319 /* XXX poll for command completion or suspend command 320 * in progress */ 321 322 /* Save the host controller state. */ 323 for (n = 0; n < sc->sc_nhosts; n++) { 324 hp = sc->sc_host[n]; 325 for (i = 0; i < sizeof hp->regs; i++) 326 hp->regs[i] = HREAD1(hp, i); 327 } 328 return true; 329 } 330 331 bool 332 sdhc_resume(device_t dev, pmf_qual_t qual) 333 { 334 struct sdhc_softc *sc = device_private(dev); 335 struct sdhc_host *hp; 336 int n, i; 337 338 /* Restore the host controller state. */ 339 for (n = 0; n < sc->sc_nhosts; n++) { 340 hp = sc->sc_host[n]; 341 (void)sdhc_host_reset(hp); 342 for (i = 0; i < sizeof hp->regs; i++) 343 HWRITE1(hp, i, hp->regs[i]); 344 } 345 return true; 346 } 347 348 bool 349 sdhc_shutdown(device_t dev, int flags) 350 { 351 struct sdhc_softc *sc = device_private(dev); 352 struct sdhc_host *hp; 353 int i; 354 355 /* XXX chip locks up if we don't disable it before reboot. */ 356 for (i = 0; i < sc->sc_nhosts; i++) { 357 hp = sc->sc_host[i]; 358 (void)sdhc_host_reset(hp); 359 } 360 return true; 361 } 362 363 /* 364 * Reset the host controller. Called during initialization, when 365 * cards are removed, upon resume, and during error recovery. 366 */ 367 static int 368 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 369 { 370 struct sdhc_host *hp = (struct sdhc_host *)sch; 371 uint16_t sdhcimask; 372 int error; 373 374 /* Don't lock. */ 375 376 /* Disable all interrupts. */ 377 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 378 379 /* 380 * Reset the entire host controller and wait up to 100ms for 381 * the controller to clear the reset bit. 382 */ 383 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 384 if (error) 385 goto out; 386 387 /* Set data timeout counter value to max for now. */ 388 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 389 390 /* Enable interrupts. */ 391 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 392 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 393 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 394 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 395 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 396 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 397 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 398 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 399 400 out: 401 return error; 402 } 403 404 static int 405 sdhc_host_reset(sdmmc_chipset_handle_t sch) 406 { 407 struct sdhc_host *hp = (struct sdhc_host *)sch; 408 int error; 409 410 mutex_enter(&hp->host_mtx); 411 error = sdhc_host_reset1(sch); 412 mutex_exit(&hp->host_mtx); 413 414 return error; 415 } 416 417 static uint32_t 418 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 419 { 420 struct sdhc_host *hp = (struct sdhc_host *)sch; 421 422 return hp->ocr; 423 } 424 425 static int 426 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 427 { 428 struct sdhc_host *hp = (struct sdhc_host *)sch; 429 430 return hp->maxblklen; 431 } 432 433 /* 434 * Return non-zero if the card is currently inserted. 435 */ 436 static int 437 sdhc_card_detect(sdmmc_chipset_handle_t sch) 438 { 439 struct sdhc_host *hp = (struct sdhc_host *)sch; 440 int r; 441 442 mutex_enter(&hp->host_mtx); 443 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 444 mutex_exit(&hp->host_mtx); 445 446 if (r) 447 return 1; 448 return 0; 449 } 450 451 /* 452 * Return non-zero if the card is currently write-protected. 453 */ 454 static int 455 sdhc_write_protect(sdmmc_chipset_handle_t sch) 456 { 457 struct sdhc_host *hp = (struct sdhc_host *)sch; 458 int r; 459 460 mutex_enter(&hp->host_mtx); 461 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 462 mutex_exit(&hp->host_mtx); 463 464 if (!r) 465 return 1; 466 return 0; 467 } 468 469 /* 470 * Set or change SD bus voltage and enable or disable SD bus power. 471 * Return zero on success. 472 */ 473 static int 474 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 475 { 476 struct sdhc_host *hp = (struct sdhc_host *)sch; 477 uint8_t vdd; 478 int error = 0; 479 480 mutex_enter(&hp->host_mtx); 481 482 /* 483 * Disable bus power before voltage change. 484 */ 485 if (!(hp->sc->sc_flags & SDHC_FLAG_NO_PWR0)) 486 HWRITE1(hp, SDHC_POWER_CTL, 0); 487 488 /* If power is disabled, reset the host and return now. */ 489 if (ocr == 0) { 490 (void)sdhc_host_reset1(hp); 491 goto out; 492 } 493 494 /* 495 * Select the lowest voltage according to capabilities. 496 */ 497 ocr &= hp->ocr; 498 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) 499 vdd = SDHC_VOLTAGE_1_8V; 500 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 501 vdd = SDHC_VOLTAGE_3_0V; 502 else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 503 vdd = SDHC_VOLTAGE_3_3V; 504 else { 505 /* Unsupported voltage level requested. */ 506 error = EINVAL; 507 goto out; 508 } 509 510 /* 511 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 512 * voltage ramp until power rises. 513 */ 514 HWRITE1(hp, SDHC_POWER_CTL, 515 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 516 sdmmc_delay(10000); 517 518 /* 519 * The host system may not power the bus due to battery low, 520 * etc. In that case, the host controller should clear the 521 * bus power bit. 522 */ 523 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 524 error = ENXIO; 525 goto out; 526 } 527 528 out: 529 mutex_exit(&hp->host_mtx); 530 531 return error; 532 } 533 534 /* 535 * Return the smallest possible base clock frequency divisor value 536 * for the CLOCK_CTL register to produce `freq' (KHz). 537 */ 538 static int 539 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 540 { 541 int div; 542 543 for (div = 1; div <= 256; div *= 2) 544 if ((hp->clkbase / div) <= freq) 545 return (div / 2); 546 /* No divisor found. */ 547 return -1; 548 } 549 550 /* 551 * Set or change SDCLK frequency or disable the SD clock. 552 * Return zero on success. 553 */ 554 static int 555 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 556 { 557 struct sdhc_host *hp = (struct sdhc_host *)sch; 558 int div; 559 int timo; 560 int error = 0; 561 #ifdef DIAGNOSTIC 562 int ispresent; 563 #endif 564 565 #ifdef DIAGNOSTIC 566 mutex_enter(&hp->host_mtx); 567 ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 568 mutex_exit(&hp->host_mtx); 569 570 /* Must not stop the clock if commands are in progress. */ 571 if (ispresent && sdhc_card_detect(hp)) 572 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 573 device_xname(hp->sc->sc_dev)); 574 #endif 575 576 mutex_enter(&hp->host_mtx); 577 578 /* 579 * Stop SD clock before changing the frequency. 580 */ 581 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 582 if (freq == SDMMC_SDCLK_OFF) 583 goto out; 584 585 /* 586 * Set the minimum base clock frequency divisor. 587 */ 588 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 589 /* Invalid base clock frequency or `freq' value. */ 590 error = EINVAL; 591 goto out; 592 } 593 HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT); 594 595 /* 596 * Start internal clock. Wait 10ms for stabilization. 597 */ 598 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 599 for (timo = 1000; timo > 0; timo--) { 600 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 601 break; 602 sdmmc_delay(10); 603 } 604 if (timo == 0) { 605 error = ETIMEDOUT; 606 goto out; 607 } 608 609 /* 610 * Enable SD clock. 611 */ 612 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 613 614 out: 615 mutex_exit(&hp->host_mtx); 616 617 return error; 618 } 619 620 static int 621 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 622 { 623 struct sdhc_host *hp = (struct sdhc_host *)sch; 624 int reg; 625 626 switch (width) { 627 case 1: 628 case 4: 629 break; 630 631 default: 632 DPRINTF(0,("%s: unsupported bus width (%d)\n", 633 HDEVNAME(hp), width)); 634 return 1; 635 } 636 637 mutex_enter(&hp->host_mtx); 638 reg = HREAD1(hp, SDHC_HOST_CTL); 639 reg &= ~SDHC_4BIT_MODE; 640 if (width == 4) 641 reg |= SDHC_4BIT_MODE; 642 HWRITE1(hp, SDHC_HOST_CTL, reg); 643 mutex_exit(&hp->host_mtx); 644 645 return 0; 646 } 647 648 static void 649 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 650 { 651 struct sdhc_host *hp = (struct sdhc_host *)sch; 652 653 mutex_enter(&hp->host_mtx); 654 if (enable) { 655 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 656 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 657 } else { 658 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 659 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 660 } 661 mutex_exit(&hp->host_mtx); 662 } 663 664 static void 665 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 666 { 667 struct sdhc_host *hp = (struct sdhc_host *)sch; 668 669 mutex_enter(&hp->host_mtx); 670 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 671 mutex_exit(&hp->host_mtx); 672 } 673 674 static int 675 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 676 { 677 uint32_t state; 678 int timeout; 679 680 for (timeout = 10; timeout > 0; timeout--) { 681 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 682 return 0; 683 sdmmc_delay(10000); 684 } 685 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 686 value, state)); 687 return ETIMEDOUT; 688 } 689 690 static void 691 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 692 { 693 struct sdhc_host *hp = (struct sdhc_host *)sch; 694 int error; 695 696 /* 697 * Start the MMC command, or mark `cmd' as failed and return. 698 */ 699 error = sdhc_start_command(hp, cmd); 700 if (error) { 701 cmd->c_error = error; 702 goto out; 703 } 704 705 /* 706 * Wait until the command phase is done, or until the command 707 * is marked done for any other reason. 708 */ 709 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 710 cmd->c_error = ETIMEDOUT; 711 goto out; 712 } 713 714 /* 715 * The host controller removes bits [0:7] from the response 716 * data (CRC) and we pass the data up unchanged to the bus 717 * driver (without padding). 718 */ 719 mutex_enter(&hp->host_mtx); 720 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 721 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 722 uint8_t *p = (uint8_t *)cmd->c_resp; 723 int i; 724 725 for (i = 0; i < 15; i++) 726 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 727 } else { 728 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 729 } 730 } 731 mutex_exit(&hp->host_mtx); 732 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 733 734 /* 735 * If the command has data to transfer in any direction, 736 * execute the transfer now. 737 */ 738 if (cmd->c_error == 0 && cmd->c_data != NULL) 739 sdhc_transfer_data(hp, cmd); 740 741 out: 742 mutex_enter(&hp->host_mtx); 743 /* Turn off the LED. */ 744 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 745 mutex_exit(&hp->host_mtx); 746 SET(cmd->c_flags, SCF_ITSDONE); 747 748 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 749 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 750 cmd->c_flags, cmd->c_error)); 751 } 752 753 static int 754 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 755 { 756 uint16_t blksize = 0; 757 uint16_t blkcount = 0; 758 uint16_t mode; 759 uint16_t command; 760 int error; 761 762 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x " 763 "proc=%p \"%s\"\n", HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, 764 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc, 765 curproc ? curproc->p_comm : "")); 766 767 /* 768 * The maximum block length for commands should be the minimum 769 * of the host buffer size and the card buffer size. (1.7.2) 770 */ 771 772 /* Fragment the data into proper blocks. */ 773 if (cmd->c_datalen > 0) { 774 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 775 blkcount = cmd->c_datalen / blksize; 776 if (cmd->c_datalen % blksize > 0) { 777 /* XXX: Split this command. (1.7.4) */ 778 aprint_error_dev(hp->sc->sc_dev, 779 "data not a multiple of %u bytes\n", blksize); 780 return EINVAL; 781 } 782 } 783 784 /* Check limit imposed by 9-bit block count. (1.7.2) */ 785 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 786 aprint_error_dev(hp->sc->sc_dev, "too much data\n"); 787 return EINVAL; 788 } 789 790 /* Prepare transfer mode register value. (2.2.5) */ 791 mode = 0; 792 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 793 mode |= SDHC_READ_MODE; 794 if (blkcount > 0) { 795 mode |= SDHC_BLOCK_COUNT_ENABLE; 796 if (blkcount > 1) { 797 mode |= SDHC_MULTI_BLOCK_MODE; 798 /* XXX only for memory commands? */ 799 mode |= SDHC_AUTO_CMD12_ENABLE; 800 } 801 } 802 #if notyet 803 if (cmd->c_dmap != NULL && cmd->c_datalen > 0) 804 mode |= SDHC_DMA_ENABLE; 805 #endif 806 807 /* 808 * Prepare command register value. (2.2.6) 809 */ 810 command = 811 (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 812 813 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 814 command |= SDHC_CRC_CHECK_ENABLE; 815 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 816 command |= SDHC_INDEX_CHECK_ENABLE; 817 if (cmd->c_data != NULL) 818 command |= SDHC_DATA_PRESENT_SELECT; 819 820 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 821 command |= SDHC_NO_RESPONSE; 822 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 823 command |= SDHC_RESP_LEN_136; 824 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 825 command |= SDHC_RESP_LEN_48_CHK_BUSY; 826 else 827 command |= SDHC_RESP_LEN_48; 828 829 /* Wait until command and data inhibit bits are clear. (1.5) */ 830 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 831 if (error) 832 return error; 833 834 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 835 HDEVNAME(hp), blksize, blkcount, mode, command)); 836 837 mutex_enter(&hp->host_mtx); 838 839 /* Alert the user not to remove the card. */ 840 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 841 842 /* 843 * Start a CPU data transfer. Writing to the high order byte 844 * of the SDHC_COMMAND register triggers the SD command. (1.5) 845 */ 846 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 847 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 848 if (blkcount > 1) 849 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 850 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 851 HWRITE2(hp, SDHC_COMMAND, command); 852 853 mutex_exit(&hp->host_mtx); 854 855 return 0; 856 } 857 858 static void 859 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 860 { 861 int error; 862 863 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 864 MMC_R1(cmd->c_resp), cmd->c_datalen)); 865 866 #ifdef SDHC_DEBUG 867 /* XXX I forgot why I wanted to know when this happens :-( */ 868 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 869 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 870 aprint_error_dev(hp->sc->sc_dev, 871 "CMD52/53 error response flags %#x\n", 872 MMC_R1(cmd->c_resp) & 0xff00); 873 } 874 #endif 875 876 error = sdhc_transfer_data_pio(hp, cmd); 877 if (error) 878 cmd->c_error = error; 879 SET(cmd->c_flags, SCF_ITSDONE); 880 881 DPRINTF(1,("%s: data transfer done (error=%d)\n", 882 HDEVNAME(hp), cmd->c_error)); 883 } 884 885 static int 886 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 887 { 888 uint8_t *data = cmd->c_data; 889 int len, datalen; 890 int mask; 891 int error = 0; 892 893 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 894 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 895 datalen = cmd->c_datalen; 896 897 while (datalen > 0) { 898 if (!sdhc_wait_intr(hp, 899 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY, 900 SDHC_BUFFER_TIMEOUT)) { 901 error = ETIMEDOUT; 902 break; 903 } 904 905 error = sdhc_wait_state(hp, mask, mask); 906 if (error) 907 break; 908 909 len = MIN(datalen, cmd->c_blklen); 910 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 911 sdhc_read_data_pio(hp, data, len); 912 else 913 sdhc_write_data_pio(hp, data, len); 914 915 data += len; 916 datalen -= len; 917 } 918 919 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 920 SDHC_TRANSFER_TIMEOUT)) 921 error = ETIMEDOUT; 922 923 return error; 924 } 925 926 static void 927 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 928 { 929 930 if (((__uintptr_t)data & 3) == 0) { 931 while (datalen > 3) { 932 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 933 data += 4; 934 datalen -= 4; 935 } 936 if (datalen > 1) { 937 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 938 data += 2; 939 datalen -= 2; 940 } 941 if (datalen > 0) { 942 *data = HREAD1(hp, SDHC_DATA); 943 data += 1; 944 datalen -= 1; 945 } 946 } else if (((__uintptr_t)data & 1) == 0) { 947 while (datalen > 1) { 948 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 949 data += 2; 950 datalen -= 2; 951 } 952 if (datalen > 0) { 953 *data = HREAD1(hp, SDHC_DATA); 954 data += 1; 955 datalen -= 1; 956 } 957 } else { 958 while (datalen > 0) { 959 *data = HREAD1(hp, SDHC_DATA); 960 data += 1; 961 datalen -= 1; 962 } 963 } 964 } 965 966 static void 967 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 968 { 969 970 if (((__uintptr_t)data & 3) == 0) { 971 while (datalen > 3) { 972 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 973 data += 4; 974 datalen -= 4; 975 } 976 if (datalen > 1) { 977 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 978 data += 2; 979 datalen -= 2; 980 } 981 if (datalen > 0) { 982 HWRITE1(hp, SDHC_DATA, *data); 983 data += 1; 984 datalen -= 1; 985 } 986 } else if (((__uintptr_t)data & 1) == 0) { 987 while (datalen > 1) { 988 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 989 data += 2; 990 datalen -= 2; 991 } 992 if (datalen > 0) { 993 HWRITE1(hp, SDHC_DATA, *data); 994 data += 1; 995 datalen -= 1; 996 } 997 } else { 998 while (datalen > 0) { 999 HWRITE1(hp, SDHC_DATA, *data); 1000 data += 1; 1001 datalen -= 1; 1002 } 1003 } 1004 } 1005 1006 /* Prepare for another command. */ 1007 static int 1008 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1009 { 1010 int timo; 1011 1012 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1013 1014 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1015 for (timo = 10; timo > 0; timo--) { 1016 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1017 break; 1018 sdmmc_delay(10000); 1019 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1020 } 1021 if (timo == 0) { 1022 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1023 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1024 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1025 return ETIMEDOUT; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int 1032 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1033 { 1034 int status; 1035 1036 mask |= SDHC_ERROR_INTERRUPT; 1037 1038 mutex_enter(&hp->intr_mtx); 1039 status = hp->intr_status & mask; 1040 while (status == 0) { 1041 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1042 == EWOULDBLOCK) { 1043 status |= SDHC_ERROR_INTERRUPT; 1044 break; 1045 } 1046 status = hp->intr_status & mask; 1047 } 1048 hp->intr_status &= ~status; 1049 1050 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1051 hp->intr_error_status)); 1052 1053 /* Command timeout has higher priority than command complete. */ 1054 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1055 hp->intr_error_status = 0; 1056 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1057 status = 0; 1058 } 1059 mutex_exit(&hp->intr_mtx); 1060 1061 return status; 1062 } 1063 1064 /* 1065 * Established by attachment driver at interrupt priority IPL_SDMMC. 1066 */ 1067 int 1068 sdhc_intr(void *arg) 1069 { 1070 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1071 struct sdhc_host *hp; 1072 int host; 1073 int done = 0; 1074 uint16_t status; 1075 uint16_t error; 1076 1077 /* We got an interrupt, but we don't know from which slot. */ 1078 for (host = 0; host < sc->sc_nhosts; host++) { 1079 hp = sc->sc_host[host]; 1080 if (hp == NULL) 1081 continue; 1082 1083 /* Find out which interrupts are pending. */ 1084 status = HREAD2(hp, SDHC_NINTR_STATUS); 1085 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1086 continue; /* no interrupt for us */ 1087 1088 /* Acknowledge the interrupts we are about to handle. */ 1089 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1090 DPRINTF(2,("%s: interrupt status=%x\n", HDEVNAME(hp), 1091 status)); 1092 1093 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1094 continue; 1095 1096 /* Claim this interrupt. */ 1097 done = 1; 1098 1099 /* 1100 * Service error interrupts. 1101 */ 1102 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1103 /* Acknowledge error interrupts. */ 1104 error = HREAD2(hp, SDHC_EINTR_STATUS); 1105 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1106 DPRINTF(2,("%s: error interrupt, status=%x\n", 1107 HDEVNAME(hp), error)); 1108 1109 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1110 SDHC_DATA_TIMEOUT_ERROR)) { 1111 hp->intr_error_status |= error; 1112 hp->intr_status |= status; 1113 cv_broadcast(&hp->intr_cv); 1114 } 1115 } 1116 1117 /* 1118 * Wake up the sdmmc event thread to scan for cards. 1119 */ 1120 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1121 sdmmc_needs_discover(hp->sdmmc); 1122 1123 /* 1124 * Wake up the blocking process to service command 1125 * related interrupt(s). 1126 */ 1127 if (ISSET(status, SDHC_BUFFER_READ_READY| 1128 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1129 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1130 hp->intr_status |= status; 1131 cv_broadcast(&hp->intr_cv); 1132 } 1133 1134 /* 1135 * Service SD card interrupts. 1136 */ 1137 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1138 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1139 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1140 sdmmc_card_intr(hp->sdmmc); 1141 } 1142 } 1143 1144 return done; 1145 } 1146 1147 #ifdef SDHC_DEBUG 1148 void 1149 sdhc_dump_regs(struct sdhc_host *hp) 1150 { 1151 1152 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1153 HREAD4(hp, SDHC_PRESENT_STATE)); 1154 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1155 HREAD1(hp, SDHC_POWER_CTL)); 1156 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1157 HREAD2(hp, SDHC_NINTR_STATUS)); 1158 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1159 HREAD2(hp, SDHC_EINTR_STATUS)); 1160 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1161 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1162 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1163 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1164 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1165 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1166 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1167 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1168 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1169 HREAD4(hp, SDHC_CAPABILITIES)); 1170 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1171 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1172 } 1173 #endif 1174