1 /* $NetBSD: sdhc.c,v 1.9 2011/06/29 06:21:16 matt Exp $ */ 2 /* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.9 2011/06/29 06:21:16 matt Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/kthread.h> 32 #include <sys/malloc.h> 33 #include <sys/systm.h> 34 #include <sys/mutex.h> 35 #include <sys/condvar.h> 36 37 #include <dev/sdmmc/sdhcreg.h> 38 #include <dev/sdmmc/sdhcvar.h> 39 #include <dev/sdmmc/sdmmcchip.h> 40 #include <dev/sdmmc/sdmmcreg.h> 41 #include <dev/sdmmc/sdmmcvar.h> 42 43 #ifdef SDHC_DEBUG 44 int sdhcdebug = 1; 45 #define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 46 void sdhc_dump_regs(struct sdhc_host *); 47 #else 48 #define DPRINTF(n,s) do {} while (0) 49 #endif 50 51 #define SDHC_COMMAND_TIMEOUT hz 52 #define SDHC_BUFFER_TIMEOUT hz 53 #define SDHC_TRANSFER_TIMEOUT hz 54 #define SDHC_DMA_TIMEOUT hz 55 56 struct sdhc_host { 57 struct sdhc_softc *sc; /* host controller device */ 58 59 bus_space_tag_t iot; /* host register set tag */ 60 bus_space_handle_t ioh; /* host register set handle */ 61 bus_dma_tag_t dmat; /* host DMA tag */ 62 63 device_t sdmmc; /* generic SD/MMC device */ 64 65 struct kmutex host_mtx; 66 67 u_int clkbase; /* base clock frequency in KHz */ 68 int maxblklen; /* maximum block length */ 69 uint32_t ocr; /* OCR value from capabilities */ 70 71 uint8_t regs[14]; /* host controller state */ 72 73 uint16_t intr_status; /* soft interrupt status */ 74 uint16_t intr_error_status; /* soft error status */ 75 struct kmutex intr_mtx; 76 struct kcondvar intr_cv; 77 78 uint32_t flags; /* flags for this host */ 79 #define SHF_USE_DMA 0x0001 80 #define SHF_USE_4BIT_MODE 0x0002 81 }; 82 83 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 84 85 #define HREAD1(hp, reg) \ 86 (bus_space_read_1((hp)->iot, (hp)->ioh, (reg))) 87 #define HREAD2(hp, reg) \ 88 (bus_space_read_2((hp)->iot, (hp)->ioh, (reg))) 89 #define HREAD4(hp, reg) \ 90 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 91 #define HWRITE1(hp, reg, val) \ 92 bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val)) 93 #define HWRITE2(hp, reg, val) \ 94 bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val)) 95 #define HWRITE4(hp, reg, val) \ 96 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 97 #define HCLR1(hp, reg, bits) \ 98 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)) 99 #define HCLR2(hp, reg, bits) \ 100 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)) 101 #define HSET1(hp, reg, bits) \ 102 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)) 103 #define HSET2(hp, reg, bits) \ 104 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)) 105 106 static int sdhc_host_reset(sdmmc_chipset_handle_t); 107 static int sdhc_host_reset1(sdmmc_chipset_handle_t); 108 static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 109 static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 110 static int sdhc_card_detect(sdmmc_chipset_handle_t); 111 static int sdhc_write_protect(sdmmc_chipset_handle_t); 112 static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 113 static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 114 static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 115 static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 116 static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 117 static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 118 static void sdhc_exec_command(sdmmc_chipset_handle_t, 119 struct sdmmc_command *); 120 static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 121 static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 122 static int sdhc_soft_reset(struct sdhc_host *, int); 123 static int sdhc_wait_intr(struct sdhc_host *, int, int); 124 static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 125 static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 126 static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 127 static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int); 128 static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int); 129 130 static struct sdmmc_chip_functions sdhc_functions = { 131 /* host controller reset */ 132 sdhc_host_reset, 133 134 /* host controller capabilities */ 135 sdhc_host_ocr, 136 sdhc_host_maxblklen, 137 138 /* card detection */ 139 sdhc_card_detect, 140 141 /* write protect */ 142 sdhc_write_protect, 143 144 /* bus power, clock frequency and width */ 145 sdhc_bus_power, 146 sdhc_bus_clock, 147 sdhc_bus_width, 148 sdhc_bus_rod, 149 150 /* command execution */ 151 sdhc_exec_command, 152 153 /* card interrupt */ 154 sdhc_card_enable_intr, 155 sdhc_card_intr_ack 156 }; 157 158 /* 159 * Called by attachment driver. For each SD card slot there is one SD 160 * host controller standard register set. (1.3) 161 */ 162 int 163 sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 164 bus_space_handle_t ioh, bus_size_t iosize) 165 { 166 struct sdmmcbus_attach_args saa; 167 struct sdhc_host *hp; 168 uint32_t caps; 169 #ifdef SDHC_DEBUG 170 uint16_t sdhcver; 171 172 sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION); 173 aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version "); 174 switch (SDHC_SPEC_VERSION(sdhcver)) { 175 case 0x00: 176 aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 177 break; 178 179 case 0x01: 180 aprint_normal("2.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 181 break; 182 183 default: 184 aprint_normal(">2.0/%u\n", SDHC_VENDOR_VERSION(sdhcver)); 185 break; 186 } 187 #endif 188 189 /* Allocate one more host structure. */ 190 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 191 if (hp == NULL) { 192 aprint_error_dev(sc->sc_dev, 193 "couldn't alloc memory (sdhc host)\n"); 194 goto err1; 195 } 196 sc->sc_host[sc->sc_nhosts++] = hp; 197 198 /* Fill in the new host structure. */ 199 hp->sc = sc; 200 hp->iot = iot; 201 hp->ioh = ioh; 202 hp->dmat = sc->sc_dmat; 203 204 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 205 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 206 cv_init(&hp->intr_cv, "sdhcintr"); 207 208 /* 209 * Reset the host controller and enable interrupts. 210 */ 211 (void)sdhc_host_reset(hp); 212 213 /* Determine host capabilities. */ 214 mutex_enter(&hp->host_mtx); 215 caps = HREAD4(hp, SDHC_CAPABILITIES); 216 mutex_exit(&hp->host_mtx); 217 218 #if notyet 219 /* Use DMA if the host system and the controller support it. */ 220 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 221 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 222 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 223 SET(hp->flags, SHF_USE_DMA); 224 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 225 } 226 #endif 227 228 /* 229 * Determine the base clock frequency. (2.2.24) 230 */ 231 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 232 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 233 if (hp->clkbase == 0) { 234 if (sc->sc_clkbase == 0) { 235 /* The attachment driver must tell us. */ 236 aprint_error_dev(sc->sc_dev,"unknown base clock frequency\n"); 237 goto err; 238 } 239 hp->clkbase = sc->sc_clkbase; 240 } 241 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 242 /* SDHC 1.0 supports only 10-63 MHz. */ 243 aprint_error_dev(sc->sc_dev, 244 "base clock frequency out of range: %u MHz\n", 245 hp->clkbase / 1000); 246 goto err; 247 } 248 DPRINTF(1,("%s: base clock frequency %u MHz\n", 249 device_xname(sc->sc_dev), hp->clkbase / 1000)); 250 251 /* 252 * XXX Set the data timeout counter value according to 253 * capabilities. (2.2.15) 254 */ 255 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 256 257 /* 258 * Determine SD bus voltage levels supported by the controller. 259 */ 260 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) 261 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 262 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) 263 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 264 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) 265 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 266 267 /* 268 * Determine the maximum block length supported by the host 269 * controller. (2.2.24) 270 */ 271 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 272 case SDHC_MAX_BLK_LEN_512: 273 hp->maxblklen = 512; 274 break; 275 276 case SDHC_MAX_BLK_LEN_1024: 277 hp->maxblklen = 1024; 278 break; 279 280 case SDHC_MAX_BLK_LEN_2048: 281 hp->maxblklen = 2048; 282 break; 283 284 case SDHC_MAX_BLK_LEN_4096: 285 hp->maxblklen = 4096; 286 break; 287 288 default: 289 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 290 goto err; 291 } 292 DPRINTF(1, ("%s: max block length %u byte%s\n", 293 device_xname(sc->sc_dev), hp->maxblklen, 294 hp->maxblklen > 1 ? "s" : "")); 295 296 /* 297 * Attach the generic SD/MMC bus driver. (The bus driver must 298 * not invoke any chipset functions before it is attached.) 299 */ 300 memset(&saa, 0, sizeof(saa)); 301 saa.saa_busname = "sdmmc"; 302 saa.saa_sct = &sdhc_functions; 303 saa.saa_sch = hp; 304 saa.saa_dmat = hp->dmat; 305 saa.saa_clkmin = hp->clkbase / 256; 306 saa.saa_clkmax = hp->clkbase; 307 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 308 saa.saa_clkmin /= 16; 309 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 310 #if notyet 311 if (ISSET(hp->flags, SHF_USE_DMA)) 312 saa.saa_caps |= SMC_CAPS_DMA; 313 #endif 314 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 315 316 return 0; 317 318 err: 319 cv_destroy(&hp->intr_cv); 320 mutex_destroy(&hp->intr_mtx); 321 mutex_destroy(&hp->host_mtx); 322 free(hp, M_DEVBUF); 323 sc->sc_host[--sc->sc_nhosts] = NULL; 324 err1: 325 return 1; 326 } 327 328 int 329 sdhc_detach(device_t dev, int flags) 330 { 331 struct sdhc_host *hp = (struct sdhc_host *)dev; 332 struct sdhc_softc *sc = hp->sc; 333 int rv = 0; 334 335 if (hp->sdmmc) 336 rv = config_detach(hp->sdmmc, flags); 337 338 cv_destroy(&hp->intr_cv); 339 mutex_destroy(&hp->intr_mtx); 340 mutex_destroy(&hp->host_mtx); 341 free(hp, M_DEVBUF); 342 sc->sc_host[--sc->sc_nhosts] = NULL; 343 344 return rv; 345 } 346 347 bool 348 sdhc_suspend(device_t dev, const pmf_qual_t *qual) 349 { 350 struct sdhc_softc *sc = device_private(dev); 351 struct sdhc_host *hp; 352 int n, i; 353 354 /* XXX poll for command completion or suspend command 355 * in progress */ 356 357 /* Save the host controller state. */ 358 for (n = 0; n < sc->sc_nhosts; n++) { 359 hp = sc->sc_host[n]; 360 for (i = 0; i < sizeof hp->regs; i++) 361 hp->regs[i] = HREAD1(hp, i); 362 } 363 return true; 364 } 365 366 bool 367 sdhc_resume(device_t dev, const pmf_qual_t *qual) 368 { 369 struct sdhc_softc *sc = device_private(dev); 370 struct sdhc_host *hp; 371 int n, i; 372 373 /* Restore the host controller state. */ 374 for (n = 0; n < sc->sc_nhosts; n++) { 375 hp = sc->sc_host[n]; 376 (void)sdhc_host_reset(hp); 377 for (i = 0; i < sizeof hp->regs; i++) 378 HWRITE1(hp, i, hp->regs[i]); 379 } 380 return true; 381 } 382 383 bool 384 sdhc_shutdown(device_t dev, int flags) 385 { 386 struct sdhc_softc *sc = device_private(dev); 387 struct sdhc_host *hp; 388 int i; 389 390 /* XXX chip locks up if we don't disable it before reboot. */ 391 for (i = 0; i < sc->sc_nhosts; i++) { 392 hp = sc->sc_host[i]; 393 (void)sdhc_host_reset(hp); 394 } 395 return true; 396 } 397 398 /* 399 * Reset the host controller. Called during initialization, when 400 * cards are removed, upon resume, and during error recovery. 401 */ 402 static int 403 sdhc_host_reset1(sdmmc_chipset_handle_t sch) 404 { 405 struct sdhc_host *hp = (struct sdhc_host *)sch; 406 uint16_t sdhcimask; 407 int error; 408 409 /* Don't lock. */ 410 411 /* Disable all interrupts. */ 412 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 413 414 /* 415 * Reset the entire host controller and wait up to 100ms for 416 * the controller to clear the reset bit. 417 */ 418 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 419 if (error) 420 goto out; 421 422 /* Set data timeout counter value to max for now. */ 423 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 424 425 /* Enable interrupts. */ 426 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 427 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 428 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 429 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 430 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 431 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 432 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 433 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 434 435 out: 436 return error; 437 } 438 439 static int 440 sdhc_host_reset(sdmmc_chipset_handle_t sch) 441 { 442 struct sdhc_host *hp = (struct sdhc_host *)sch; 443 int error; 444 445 mutex_enter(&hp->host_mtx); 446 error = sdhc_host_reset1(sch); 447 mutex_exit(&hp->host_mtx); 448 449 return error; 450 } 451 452 static uint32_t 453 sdhc_host_ocr(sdmmc_chipset_handle_t sch) 454 { 455 struct sdhc_host *hp = (struct sdhc_host *)sch; 456 457 return hp->ocr; 458 } 459 460 static int 461 sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 462 { 463 struct sdhc_host *hp = (struct sdhc_host *)sch; 464 465 return hp->maxblklen; 466 } 467 468 /* 469 * Return non-zero if the card is currently inserted. 470 */ 471 static int 472 sdhc_card_detect(sdmmc_chipset_handle_t sch) 473 { 474 struct sdhc_host *hp = (struct sdhc_host *)sch; 475 int r; 476 477 mutex_enter(&hp->host_mtx); 478 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 479 mutex_exit(&hp->host_mtx); 480 481 if (r) 482 return 1; 483 return 0; 484 } 485 486 /* 487 * Return non-zero if the card is currently write-protected. 488 */ 489 static int 490 sdhc_write_protect(sdmmc_chipset_handle_t sch) 491 { 492 struct sdhc_host *hp = (struct sdhc_host *)sch; 493 int r; 494 495 mutex_enter(&hp->host_mtx); 496 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 497 mutex_exit(&hp->host_mtx); 498 499 if (!r) 500 return 1; 501 return 0; 502 } 503 504 /* 505 * Set or change SD bus voltage and enable or disable SD bus power. 506 * Return zero on success. 507 */ 508 static int 509 sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 510 { 511 struct sdhc_host *hp = (struct sdhc_host *)sch; 512 uint8_t vdd; 513 int error = 0; 514 515 mutex_enter(&hp->host_mtx); 516 517 /* 518 * Disable bus power before voltage change. 519 */ 520 if (!(hp->sc->sc_flags & SDHC_FLAG_NO_PWR0)) 521 HWRITE1(hp, SDHC_POWER_CTL, 0); 522 523 /* If power is disabled, reset the host and return now. */ 524 if (ocr == 0) { 525 (void)sdhc_host_reset1(hp); 526 goto out; 527 } 528 529 /* 530 * Select the lowest voltage according to capabilities. 531 */ 532 ocr &= hp->ocr; 533 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) 534 vdd = SDHC_VOLTAGE_1_8V; 535 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 536 vdd = SDHC_VOLTAGE_3_0V; 537 else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 538 vdd = SDHC_VOLTAGE_3_3V; 539 else { 540 /* Unsupported voltage level requested. */ 541 error = EINVAL; 542 goto out; 543 } 544 545 /* 546 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 547 * voltage ramp until power rises. 548 */ 549 HWRITE1(hp, SDHC_POWER_CTL, 550 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 551 sdmmc_delay(10000); 552 553 /* 554 * The host system may not power the bus due to battery low, 555 * etc. In that case, the host controller should clear the 556 * bus power bit. 557 */ 558 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 559 error = ENXIO; 560 goto out; 561 } 562 563 out: 564 mutex_exit(&hp->host_mtx); 565 566 return error; 567 } 568 569 /* 570 * Return the smallest possible base clock frequency divisor value 571 * for the CLOCK_CTL register to produce `freq' (KHz). 572 */ 573 static int 574 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq) 575 { 576 int div; 577 578 if (hp->sc->sc_flags & SDHC_FLAG_HAVE_DVS) { 579 int dvs = (hp->clkbase + freq - 1) / freq; 580 div = 1; 581 for (div = 1; div <= 256; div <<= 1, dvs >>= 1) { 582 if (dvs <= 16) { 583 div <<= SDHC_SDCLK_DIV_SHIFT; 584 div |= (dvs - 1) << SDHC_SDCLK_DVS_SHIFT; 585 return div; 586 } 587 } 588 } else { 589 for (div = 1; div <= 256; div *= 2) { 590 if ((hp->clkbase / div) <= freq) 591 return (div / 2) << SDHC_SDCLK_DIV_SHIFT; 592 } 593 } 594 595 /* No divisor found. */ 596 return -1; 597 } 598 599 /* 600 * Set or change SDCLK frequency or disable the SD clock. 601 * Return zero on success. 602 */ 603 static int 604 sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 605 { 606 struct sdhc_host *hp = (struct sdhc_host *)sch; 607 int div; 608 int timo; 609 int error = 0; 610 #ifdef DIAGNOSTIC 611 int ispresent; 612 #endif 613 614 #ifdef DIAGNOSTIC 615 mutex_enter(&hp->host_mtx); 616 ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 617 mutex_exit(&hp->host_mtx); 618 619 /* Must not stop the clock if commands are in progress. */ 620 if (ispresent && sdhc_card_detect(hp)) 621 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 622 device_xname(hp->sc->sc_dev)); 623 #endif 624 625 mutex_enter(&hp->host_mtx); 626 627 /* 628 * Stop SD clock before changing the frequency. 629 */ 630 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 631 if (freq == SDMMC_SDCLK_OFF) 632 goto out; 633 634 /* 635 * Set the minimum base clock frequency divisor. 636 */ 637 if ((div = sdhc_clock_divisor(hp, freq)) < 0) { 638 /* Invalid base clock frequency or `freq' value. */ 639 error = EINVAL; 640 goto out; 641 } 642 HWRITE2(hp, SDHC_CLOCK_CTL, div); 643 644 /* 645 * Start internal clock. Wait 10ms for stabilization. 646 */ 647 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 648 for (timo = 1000; timo > 0; timo--) { 649 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 650 break; 651 sdmmc_delay(10); 652 } 653 if (timo == 0) { 654 error = ETIMEDOUT; 655 goto out; 656 } 657 658 /* 659 * Enable SD clock. 660 */ 661 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 662 663 if (freq > 25000) 664 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 665 else 666 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 667 668 out: 669 mutex_exit(&hp->host_mtx); 670 671 return error; 672 } 673 674 static int 675 sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 676 { 677 struct sdhc_host *hp = (struct sdhc_host *)sch; 678 int reg; 679 680 switch (width) { 681 case 1: 682 case 4: 683 break; 684 685 default: 686 DPRINTF(0,("%s: unsupported bus width (%d)\n", 687 HDEVNAME(hp), width)); 688 return 1; 689 } 690 691 mutex_enter(&hp->host_mtx); 692 reg = HREAD1(hp, SDHC_HOST_CTL); 693 reg &= ~SDHC_4BIT_MODE; 694 if (width == 4) 695 reg |= SDHC_4BIT_MODE; 696 HWRITE1(hp, SDHC_HOST_CTL, reg); 697 mutex_exit(&hp->host_mtx); 698 699 return 0; 700 } 701 702 static int 703 sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 704 { 705 706 /* Nothing ?? */ 707 return 0; 708 } 709 710 static void 711 sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 712 { 713 struct sdhc_host *hp = (struct sdhc_host *)sch; 714 715 mutex_enter(&hp->host_mtx); 716 if (enable) { 717 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 718 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 719 } else { 720 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 721 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 722 } 723 mutex_exit(&hp->host_mtx); 724 } 725 726 static void 727 sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 728 { 729 struct sdhc_host *hp = (struct sdhc_host *)sch; 730 731 mutex_enter(&hp->host_mtx); 732 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 733 mutex_exit(&hp->host_mtx); 734 } 735 736 static int 737 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 738 { 739 uint32_t state; 740 int timeout; 741 742 for (timeout = 10; timeout > 0; timeout--) { 743 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 744 return 0; 745 sdmmc_delay(10000); 746 } 747 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 748 value, state)); 749 return ETIMEDOUT; 750 } 751 752 static void 753 sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 754 { 755 struct sdhc_host *hp = (struct sdhc_host *)sch; 756 int error; 757 758 /* 759 * Start the MMC command, or mark `cmd' as failed and return. 760 */ 761 error = sdhc_start_command(hp, cmd); 762 if (error) { 763 cmd->c_error = error; 764 goto out; 765 } 766 767 /* 768 * Wait until the command phase is done, or until the command 769 * is marked done for any other reason. 770 */ 771 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 772 cmd->c_error = ETIMEDOUT; 773 goto out; 774 } 775 776 /* 777 * The host controller removes bits [0:7] from the response 778 * data (CRC) and we pass the data up unchanged to the bus 779 * driver (without padding). 780 */ 781 mutex_enter(&hp->host_mtx); 782 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 783 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 784 uint8_t *p = (uint8_t *)cmd->c_resp; 785 int i; 786 787 for (i = 0; i < 15; i++) 788 *p++ = HREAD1(hp, SDHC_RESPONSE + i); 789 } else { 790 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE); 791 } 792 } 793 mutex_exit(&hp->host_mtx); 794 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 795 796 /* 797 * If the command has data to transfer in any direction, 798 * execute the transfer now. 799 */ 800 if (cmd->c_error == 0 && cmd->c_data != NULL) 801 sdhc_transfer_data(hp, cmd); 802 803 out: 804 mutex_enter(&hp->host_mtx); 805 /* Turn off the LED. */ 806 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 807 mutex_exit(&hp->host_mtx); 808 SET(cmd->c_flags, SCF_ITSDONE); 809 810 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 811 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 812 cmd->c_flags, cmd->c_error)); 813 } 814 815 static int 816 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 817 { 818 uint16_t blksize = 0; 819 uint16_t blkcount = 0; 820 uint16_t mode; 821 uint16_t command; 822 int error; 823 824 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x\n", 825 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 826 cmd->c_datalen, cmd->c_flags)); 827 828 /* 829 * The maximum block length for commands should be the minimum 830 * of the host buffer size and the card buffer size. (1.7.2) 831 */ 832 833 /* Fragment the data into proper blocks. */ 834 if (cmd->c_datalen > 0) { 835 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 836 blkcount = cmd->c_datalen / blksize; 837 if (cmd->c_datalen % blksize > 0) { 838 /* XXX: Split this command. (1.7.4) */ 839 aprint_error_dev(hp->sc->sc_dev, 840 "data not a multiple of %u bytes\n", blksize); 841 return EINVAL; 842 } 843 } 844 845 /* Check limit imposed by 9-bit block count. (1.7.2) */ 846 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 847 aprint_error_dev(hp->sc->sc_dev, "too much data\n"); 848 return EINVAL; 849 } 850 851 /* Prepare transfer mode register value. (2.2.5) */ 852 mode = 0; 853 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 854 mode |= SDHC_READ_MODE; 855 if (blkcount > 0) { 856 mode |= SDHC_BLOCK_COUNT_ENABLE; 857 if (blkcount > 1) { 858 mode |= SDHC_MULTI_BLOCK_MODE; 859 /* XXX only for memory commands? */ 860 mode |= SDHC_AUTO_CMD12_ENABLE; 861 } 862 } 863 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 864 if (cmd->c_dmamap->dm_nsegs == 1) { 865 mode |= SDHC_DMA_ENABLE; 866 } else { 867 cmd->c_dmamap = NULL; 868 } 869 } 870 871 /* 872 * Prepare command register value. (2.2.6) 873 */ 874 command = 875 (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 876 877 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 878 command |= SDHC_CRC_CHECK_ENABLE; 879 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 880 command |= SDHC_INDEX_CHECK_ENABLE; 881 if (cmd->c_data != NULL) 882 command |= SDHC_DATA_PRESENT_SELECT; 883 884 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 885 command |= SDHC_NO_RESPONSE; 886 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 887 command |= SDHC_RESP_LEN_136; 888 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 889 command |= SDHC_RESP_LEN_48_CHK_BUSY; 890 else 891 command |= SDHC_RESP_LEN_48; 892 893 /* Wait until command and data inhibit bits are clear. (1.5) */ 894 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 895 if (error) 896 return error; 897 898 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 899 HDEVNAME(hp), blksize, blkcount, mode, command)); 900 901 mutex_enter(&hp->host_mtx); 902 903 /* Alert the user not to remove the card. */ 904 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 905 906 /* Set DMA start address. */ 907 if (ISSET(mode, SDHC_DMA_ENABLE)) 908 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 909 910 /* 911 * Start a CPU data transfer. Writing to the high order byte 912 * of the SDHC_COMMAND register triggers the SD command. (1.5) 913 */ 914 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 915 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 916 if (blkcount > 1) 917 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 918 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 919 HWRITE2(hp, SDHC_COMMAND, command); 920 921 mutex_exit(&hp->host_mtx); 922 923 return 0; 924 } 925 926 static void 927 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 928 { 929 int error; 930 931 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 932 MMC_R1(cmd->c_resp), cmd->c_datalen)); 933 934 #ifdef SDHC_DEBUG 935 /* XXX I forgot why I wanted to know when this happens :-( */ 936 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 937 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 938 aprint_error_dev(hp->sc->sc_dev, 939 "CMD52/53 error response flags %#x\n", 940 MMC_R1(cmd->c_resp) & 0xff00); 941 } 942 #endif 943 944 if (cmd->c_dmamap != NULL) 945 error = sdhc_transfer_data_dma(hp, cmd); 946 else 947 error = sdhc_transfer_data_pio(hp, cmd); 948 if (error) 949 cmd->c_error = error; 950 SET(cmd->c_flags, SCF_ITSDONE); 951 952 DPRINTF(1,("%s: data transfer done (error=%d)\n", 953 HDEVNAME(hp), cmd->c_error)); 954 } 955 956 static int 957 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 958 { 959 bus_dmamap_t dmap = cmd->c_dmamap; 960 uint16_t blklen = cmd->c_blklen; 961 uint16_t blkcnt = cmd->c_datalen / blklen; 962 uint16_t remain; 963 int error = 0; 964 965 for (;;) { 966 if (!sdhc_wait_intr(hp, 967 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 968 SDHC_DMA_TIMEOUT)) { 969 error = ETIMEDOUT; 970 break; 971 } 972 973 /* single block mode */ 974 if (blkcnt == 1) 975 break; 976 977 /* multi block mode */ 978 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 979 if (remain == 0) 980 break; 981 982 HWRITE4(hp, SDHC_DMA_ADDR, 983 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 984 } 985 986 #if 0 987 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 988 SDHC_TRANSFER_TIMEOUT)) 989 error = ETIMEDOUT; 990 #endif 991 992 return error; 993 } 994 995 static int 996 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 997 { 998 uint8_t *data = cmd->c_data; 999 int len, datalen; 1000 int mask; 1001 int error = 0; 1002 1003 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1004 SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE; 1005 datalen = cmd->c_datalen; 1006 1007 while (datalen > 0) { 1008 if (!sdhc_wait_intr(hp, 1009 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY, 1010 SDHC_BUFFER_TIMEOUT)) { 1011 error = ETIMEDOUT; 1012 break; 1013 } 1014 1015 error = sdhc_wait_state(hp, mask, mask); 1016 if (error) 1017 break; 1018 1019 len = MIN(datalen, cmd->c_blklen); 1020 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1021 sdhc_read_data_pio(hp, data, len); 1022 else 1023 sdhc_write_data_pio(hp, data, len); 1024 1025 data += len; 1026 datalen -= len; 1027 } 1028 1029 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1030 SDHC_TRANSFER_TIMEOUT)) 1031 error = ETIMEDOUT; 1032 1033 return error; 1034 } 1035 1036 static void 1037 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 1038 { 1039 1040 if (((__uintptr_t)data & 3) == 0) { 1041 while (datalen > 3) { 1042 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1043 data += 4; 1044 datalen -= 4; 1045 } 1046 if (datalen > 1) { 1047 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1048 data += 2; 1049 datalen -= 2; 1050 } 1051 if (datalen > 0) { 1052 *data = HREAD1(hp, SDHC_DATA); 1053 data += 1; 1054 datalen -= 1; 1055 } 1056 } else if (((__uintptr_t)data & 1) == 0) { 1057 while (datalen > 1) { 1058 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1059 data += 2; 1060 datalen -= 2; 1061 } 1062 if (datalen > 0) { 1063 *data = HREAD1(hp, SDHC_DATA); 1064 data += 1; 1065 datalen -= 1; 1066 } 1067 } else { 1068 while (datalen > 0) { 1069 *data = HREAD1(hp, SDHC_DATA); 1070 data += 1; 1071 datalen -= 1; 1072 } 1073 } 1074 } 1075 1076 static void 1077 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen) 1078 { 1079 1080 if (((__uintptr_t)data & 3) == 0) { 1081 while (datalen > 3) { 1082 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1083 data += 4; 1084 datalen -= 4; 1085 } 1086 if (datalen > 1) { 1087 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1088 data += 2; 1089 datalen -= 2; 1090 } 1091 if (datalen > 0) { 1092 HWRITE1(hp, SDHC_DATA, *data); 1093 data += 1; 1094 datalen -= 1; 1095 } 1096 } else if (((__uintptr_t)data & 1) == 0) { 1097 while (datalen > 1) { 1098 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1099 data += 2; 1100 datalen -= 2; 1101 } 1102 if (datalen > 0) { 1103 HWRITE1(hp, SDHC_DATA, *data); 1104 data += 1; 1105 datalen -= 1; 1106 } 1107 } else { 1108 while (datalen > 0) { 1109 HWRITE1(hp, SDHC_DATA, *data); 1110 data += 1; 1111 datalen -= 1; 1112 } 1113 } 1114 } 1115 1116 /* Prepare for another command. */ 1117 static int 1118 sdhc_soft_reset(struct sdhc_host *hp, int mask) 1119 { 1120 int timo; 1121 1122 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1123 1124 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1125 for (timo = 10; timo > 0; timo--) { 1126 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1127 break; 1128 sdmmc_delay(10000); 1129 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1130 } 1131 if (timo == 0) { 1132 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1133 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1134 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1135 return ETIMEDOUT; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int 1142 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1143 { 1144 int status; 1145 1146 mask |= SDHC_ERROR_INTERRUPT; 1147 1148 mutex_enter(&hp->intr_mtx); 1149 status = hp->intr_status & mask; 1150 while (status == 0) { 1151 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1152 == EWOULDBLOCK) { 1153 status |= SDHC_ERROR_INTERRUPT; 1154 break; 1155 } 1156 status = hp->intr_status & mask; 1157 } 1158 hp->intr_status &= ~status; 1159 1160 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1161 hp->intr_error_status)); 1162 1163 /* Command timeout has higher priority than command complete. */ 1164 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1165 hp->intr_error_status = 0; 1166 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1167 status = 0; 1168 } 1169 mutex_exit(&hp->intr_mtx); 1170 1171 return status; 1172 } 1173 1174 /* 1175 * Established by attachment driver at interrupt priority IPL_SDMMC. 1176 */ 1177 int 1178 sdhc_intr(void *arg) 1179 { 1180 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1181 struct sdhc_host *hp; 1182 int host; 1183 int done = 0; 1184 uint16_t status; 1185 uint16_t error; 1186 1187 /* We got an interrupt, but we don't know from which slot. */ 1188 for (host = 0; host < sc->sc_nhosts; host++) { 1189 hp = sc->sc_host[host]; 1190 if (hp == NULL) 1191 continue; 1192 1193 /* Find out which interrupts are pending. */ 1194 status = HREAD2(hp, SDHC_NINTR_STATUS); 1195 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1196 continue; /* no interrupt for us */ 1197 1198 /* Acknowledge the interrupts we are about to handle. */ 1199 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1200 DPRINTF(2,("%s: interrupt status=%x\n", HDEVNAME(hp), 1201 status)); 1202 1203 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1204 continue; 1205 1206 /* Claim this interrupt. */ 1207 done = 1; 1208 1209 /* 1210 * Service error interrupts. 1211 */ 1212 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1213 /* Acknowledge error interrupts. */ 1214 error = HREAD2(hp, SDHC_EINTR_STATUS); 1215 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1216 DPRINTF(2,("%s: error interrupt, status=%x\n", 1217 HDEVNAME(hp), error)); 1218 1219 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1220 SDHC_DATA_TIMEOUT_ERROR)) { 1221 hp->intr_error_status |= error; 1222 hp->intr_status |= status; 1223 cv_broadcast(&hp->intr_cv); 1224 } 1225 } 1226 1227 /* 1228 * Wake up the sdmmc event thread to scan for cards. 1229 */ 1230 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1231 sdmmc_needs_discover(hp->sdmmc); 1232 #if 0 1233 HCLR2(hp, SDHC_NINTR_STATUS_EN, 1234 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1235 #endif 1236 } 1237 1238 /* 1239 * Wake up the blocking process to service command 1240 * related interrupt(s). 1241 */ 1242 if (ISSET(status, SDHC_BUFFER_READ_READY| 1243 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE| 1244 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1245 hp->intr_status |= status; 1246 cv_broadcast(&hp->intr_cv); 1247 } 1248 1249 /* 1250 * Service SD card interrupts. 1251 */ 1252 if (ISSET(status, SDHC_CARD_INTERRUPT)) { 1253 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1254 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1255 sdmmc_card_intr(hp->sdmmc); 1256 } 1257 } 1258 1259 return done; 1260 } 1261 1262 #ifdef SDHC_DEBUG 1263 void 1264 sdhc_dump_regs(struct sdhc_host *hp) 1265 { 1266 1267 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1268 HREAD4(hp, SDHC_PRESENT_STATE)); 1269 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1270 HREAD1(hp, SDHC_POWER_CTL)); 1271 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1272 HREAD2(hp, SDHC_NINTR_STATUS)); 1273 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1274 HREAD2(hp, SDHC_EINTR_STATUS)); 1275 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1276 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1277 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1278 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1279 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1280 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1281 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1282 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1283 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1284 HREAD4(hp, SDHC_CAPABILITIES)); 1285 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1286 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1287 } 1288 #endif 1289