1 /* $NetBSD: scsi_disk.h,v 1.27 2004/12/07 23:21:06 thorpej Exp $ */ 2 3 /* 4 * SCSI-specific interface description 5 */ 6 7 /* 8 * Some lines of this file come from a file of the name "scsi.h" 9 * distributed by OSF as part of mach2.5, 10 * so the following disclaimer has been kept. 11 * 12 * Copyright 1990 by Open Software Foundation, 13 * Grenoble, FRANCE 14 * 15 * All Rights Reserved 16 * 17 * Permission to use, copy, modify, and distribute this software and 18 * its documentation for any purpose and without fee is hereby granted, 19 * provided that the above copyright notice appears in all copies and 20 * that both the copyright notice and this permission notice appear in 21 * supporting documentation, and that the name of OSF or Open Software 22 * Foundation not be used in advertising or publicity pertaining to 23 * distribution of the software without specific, written prior 24 * permission. 25 * 26 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 27 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 28 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 29 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 30 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 31 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 32 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 33 */ 34 35 /* 36 * Largely written by Julian Elischer (julian@tfs.com) 37 * for TRW Financial Systems. 38 * 39 * TRW Financial Systems, in accordance with their agreement with Carnegie 40 * Mellon University, makes this software available to CMU to distribute 41 * or use in any manner that they see fit as long as this message is kept with 42 * the software. For this reason TFS also grants any other persons or 43 * organisations permission to use or modify this software. 44 * 45 * TFS supplies this software to be publicly redistributed 46 * on the understanding that TFS is not responsible for the correct 47 * functioning of this software in any circumstances. 48 * 49 * Ported to run under 386BSD by Julian Elischer (julian@tfs.com) Sept 1992 50 */ 51 52 /* 53 * SCSI command format 54 */ 55 #ifndef _DEV_SCSIPI_SCSI_DISK_H_ 56 #define _DEV_SCSIPI_SCSI_DISK_H_ 57 58 /* 59 * XXX Is this also used by ATAPI? 60 */ 61 #define SCSI_FORMAT_UNIT 0x04 62 struct scsi_format_unit { 63 u_int8_t opcode; 64 u_int8_t flags; 65 #define SFU_DLF_MASK 0x07 66 #define SFU_CMPLST 0x08 67 #define SFU_FMTDATA 0x10 68 u_int8_t vendor_specific; 69 u_int8_t interleave[2]; 70 u_int8_t control; 71 }; 72 73 /* 74 * If the FmtData bit is set, a FORMAT UNIT parameter list is transfered 75 * to the target during the DATA OUT phase. The parameter list includes 76 * 77 * Defect list header 78 * Initialization pattern descriptor (if any) 79 * Defect descriptor(s) (if any) 80 */ 81 82 struct scsi_format_unit_defect_list_header { 83 u_int8_t reserved; 84 u_int8_t flags; 85 #define DLH_VS 0x01 /* vendor specific */ 86 #define DLH_IMMED 0x02 /* immediate return */ 87 #define DLH_DSP 0x04 /* disable saving parameters */ 88 #define DLH_IP 0x08 /* initialization pattern */ 89 #define DLH_STPF 0x10 /* stop format */ 90 #define DLH_DCRT 0x20 /* disable certification */ 91 #define DLH_DPRY 0x40 /* disable primary */ 92 #define DLH_FOV 0x80 /* format options valid */ 93 u_int8_t defect_lst_len[2]; 94 }; 95 96 /* 97 * See Table 117 of the SCSI-2 specification for a description of 98 * the IP modifier. 99 */ 100 struct scsi_initialization_pattern_descriptor { 101 u_int8_t ip_modifier; 102 u_int8_t pattern_type; 103 #define IP_TYPE_DEFAULT 0x01 104 #define IP_TYPE_REPEAT 0x01 105 /* 0x02 -> 0x7f: reserved */ 106 /* 0x80 -> 0xff: vendor-specific */ 107 u_int8_t pattern_length[2]; 108 #if 0 109 u_int8_t pattern[...]; 110 #endif 111 }; 112 113 /* 114 * Defect desciptors. These are used as the defect lists in the FORMAT UNIT 115 * and READ DEFECT DATA commands, and as the translate page of the 116 * SEND DIAGNOSTIC and RECEIVE DIAGNOSTIC RESULTS commands. 117 */ 118 119 /* Block format */ 120 struct scsi_defect_descriptor_bf { 121 u_int8_t block_address[4]; 122 }; 123 124 /* Bytes from index format */ 125 struct scsi_defect_descriptor_bfif { 126 u_int8_t cylinder[3]; 127 u_int8_t head; 128 u_int8_t bytes_from_index[4]; 129 }; 130 131 /* Physical sector format */ 132 struct scsi_defect_descriptor_psf { 133 u_int8_t cylinder[3]; 134 u_int8_t head; 135 u_int8_t sector[4]; 136 }; 137 138 /* 139 * XXX for now this isn't in the ATAPI specs, but if there are on day 140 * ATAPI hard disks, it is likely that they implement this command (or a 141 * command like this ? 142 */ 143 #define SCSI_REASSIGN_BLOCKS 0x07 144 struct scsi_reassign_blocks { 145 u_int8_t opcode; 146 u_int8_t byte2; 147 u_int8_t unused[3]; 148 u_int8_t control; 149 }; 150 151 /* 152 * XXX Is this also used by ATAPI? 153 */ 154 #define SCSI_REZERO_UNIT 0x01 155 struct scsi_rezero_unit { 156 u_int8_t opcode; 157 u_int8_t byte2; 158 u_int8_t reserved[3]; 159 u_int8_t control; 160 }; 161 162 #define SCSI_READ_6_COMMAND 0x08 163 #define SCSI_WRITE_6_COMMAND 0x0a 164 struct scsi_rw_6 { 165 u_int8_t opcode; 166 u_int8_t addr[3]; 167 #define SRW_TOPADDR 0x1F /* only 5 bits here */ 168 u_int8_t length; 169 u_int8_t control; 170 }; 171 172 /* 173 * XXX Does ATAPI have an equivalent? 174 */ 175 #define SCSI_SYNCHRONIZE_CACHE_10 0x35 176 struct scsi_synchronize_cache_10 { 177 u_int8_t opcode; 178 u_int8_t flags; 179 #define SSC_RELADR 0x01 /* obsolete */ 180 #define SSC_IMMED 0x02 181 #define SSC_SYNC_NV 0x04 182 u_int8_t addr[4]; 183 u_int8_t byte7; 184 u_int8_t length[2]; 185 u_int8_t control; 186 }; 187 188 #define SCSI_SYNCHRONIZE_CACHE_16 0x91 189 struct scsi_synchronize_cache_16 { 190 u_int8_t opcode; 191 u_int8_t flags; /* see SYNCHRONIZE CACHE (10) */ 192 u_int8_t addr[8]; 193 u_int8_t length[4]; 194 u_int8_t byte15; 195 u_int8_t control; 196 }; 197 198 /* DATAs definitions for the above commands */ 199 200 struct scsi_reassign_blocks_data { 201 u_int8_t reserved[2]; 202 u_int8_t length[2]; 203 struct { 204 u_int8_t dlbaddr[4]; 205 } defect_descriptor[1]; 206 }; 207 208 union scsi_disk_pages { 209 #define DISK_PGCODE 0x3F /* only 6 bits valid */ 210 struct page_disk_format { 211 u_int8_t pg_code; /* page code (should be 3) */ 212 u_int8_t pg_length; /* page length (should be 0x16) */ 213 u_int8_t trk_z[2]; /* tracks per zone */ 214 u_int8_t alt_sec[2]; /* alternate sectors per zone */ 215 u_int8_t alt_trk_z[2]; /* alternate tracks per zone */ 216 u_int8_t alt_trk_v[2]; /* alternate tracks per volume */ 217 u_int8_t ph_sec_t[2]; /* physical sectors per track */ 218 u_int8_t bytes_s[2]; /* bytes per sector */ 219 u_int8_t interleave[2]; /* interleave */ 220 u_int8_t trk_skew[2]; /* track skew factor */ 221 u_int8_t cyl_skew[2]; /* cylinder skew */ 222 u_int8_t flags; /* various */ 223 #define DISK_FMT_SURF 0x10 224 #define DISK_FMT_RMB 0x20 225 #define DISK_FMT_HSEC 0x40 226 #define DISK_FMT_SSEC 0x80 227 u_int8_t reserved2; 228 u_int8_t reserved3; 229 } disk_format; 230 struct page_rigid_geometry { 231 u_int8_t pg_code; /* page code (should be 4) */ 232 u_int8_t pg_length; /* page length (should be 0x16) */ 233 u_int8_t ncyl[3]; /* number of cylinders */ 234 u_int8_t nheads; /* number of heads */ 235 u_int8_t st_cyl_wp[3]; /* starting cyl., write precomp */ 236 u_int8_t st_cyl_rwc[3]; /* starting cyl., red. write cur */ 237 u_int8_t driv_step[2]; /* drive step rate */ 238 u_int8_t land_zone[3]; /* landing zone cylinder */ 239 u_int8_t sp_sync_ctl; /* spindle synch control */ 240 #define SPINDLE_SYNCH_MASK 0x03 /* mask of valid bits */ 241 #define SPINDLE_SYNCH_NONE 0x00 /* synch disabled or not supported */ 242 #define SPINDLE_SYNCH_SLAVE 0x01 /* disk is a slave */ 243 #define SPINDLE_SYNCH_MASTER 0x02 /* disk is a master */ 244 #define SPINDLE_SYNCH_MCONTROL 0x03 /* disk is a master control */ 245 u_int8_t rot_offset; /* rotational offset (for spindle synch) */ 246 u_int8_t reserved1; 247 u_int8_t rpm[2]; /* media rotation speed */ 248 u_int8_t reserved2; 249 u_int8_t reserved3; 250 } rigid_geometry; 251 struct page_flex_geometry { 252 u_int8_t pg_code; /* page code (should be 5) */ 253 u_int8_t pg_length; /* page length (should be 0x1e) */ 254 u_int8_t xfr_rate[2]; 255 u_int8_t nheads; /* number of heads */ 256 u_int8_t ph_sec_tr; /* physical sectors per track */ 257 u_int8_t bytes_s[2]; /* bytes per sector */ 258 u_int8_t ncyl[2]; /* number of cylinders */ 259 u_int8_t st_cyl_wp[2]; /* start cyl., write precomp */ 260 u_int8_t st_cyl_rwc[2]; /* start cyl., red. write cur */ 261 u_int8_t driv_step[2]; /* drive step rate */ 262 u_int8_t driv_step_w; /* drive step pulse width */ 263 u_int8_t head_settle[2];/* head settle delay */ 264 u_int8_t motor_on; /* motor on delay */ 265 u_int8_t motor_off; /* motor off delay */ 266 u_int8_t flags; /* various flags */ 267 #define MOTOR_ON 0x20 /* motor on (pin 16)? */ 268 #define START_AT_SECTOR_1 0x40 /* start at sector 1 */ 269 #define READY_VALID 0x20 /* RDY (pin 34) valid */ 270 u_int8_t step_p_cyl; /* step pulses per cylinder */ 271 u_int8_t write_pre; /* write precompensation */ 272 u_int8_t head_load; /* head load delay */ 273 u_int8_t head_unload; /* head unload delay */ 274 u_int8_t pin_34_2; /* pin 34 (6) pin 2 (7/11) definition */ 275 u_int8_t pin_4_1; /* pin 4 (8/9) pin 1 (13) definition */ 276 u_int8_t rpm[2]; /* rotational rate */ 277 u_int8_t reserved3; 278 u_int8_t reserved4; 279 } flex_geometry; 280 struct page_caching { 281 u_int8_t pg_code; /* page code (should be 8) */ 282 u_int8_t pg_length; /* page length (should be 0x0a) */ 283 u_int8_t flags; /* cache parameter flags */ 284 #define CACHING_RCD 0x01 /* read cache disable */ 285 #define CACHING_MF 0x02 /* multiplcation factor */ 286 #define CACHING_WCE 0x04 /* write cache enable (write-back) */ 287 #define CACHING_SIZE 0x08 /* use CACHE SEGMENT SIZE */ 288 #define CACHING_DISC 0x10 /* pftch across time discontinuities */ 289 #define CACHING_CAP 0x20 /* caching analysis permitted */ 290 #define CACHING_ABPF 0x40 /* abort prefetch */ 291 #define CACHING_IC 0x80 /* initiator control */ 292 u_int8_t ret_prio; /* retention priority */ 293 #define READ_RET_PRIO_SHIFT 4 294 #define RET_PRIO_DONT_DISTINGUISH 0x0 295 #define RET_PRIO_REPLACE_READ_WRITE 0x1 296 #define RET_PRIO_REPLACE_PREFETCH 0xf 297 u_int8_t dis_prefetch_xfer_len[2]; 298 u_int8_t min_prefetch[2]; 299 u_int8_t max_prefetch[2]; 300 u_int8_t max_prefetch_ceiling[2]; 301 u_int8_t flags2; /* additional cache param flags */ 302 #define CACHING2_VS0 0x08 /* vendor specific bit */ 303 #define CACHING2_VS1 0x10 /* vendor specific bit */ 304 #define CACHING2_DRA 0x20 /* disable read ahead */ 305 #define CACHING2_LBCSS 0x40 /* CACHE SEGMENT SIZE is blocks */ 306 #define CACHING2_FSW 0x80 /* force sequential write */ 307 u_int8_t num_cache_segments; 308 u_int8_t cache_segment_size[2]; 309 u_int8_t reserved1; 310 u_int8_t non_cache_segment_size[2]; 311 } caching_params; 312 struct page_control { 313 u_int8_t pg_code; /* page code (should be 0x0a) */ 314 u_int8_t pg_length; /* page length (should be 0x0a) */ 315 u_int8_t ctl_flags1; /* First set of flags */ 316 #define CTL1_TST_PER_INTR 0x40 /* Task set per initiator */ 317 #define CTL1_TST_FIELD 0xe0 /* Full field */ 318 #define CTL1_D_SENSE 0x04 /* Descriptor-format sense return */ 319 #define CTL1_GLTSD 0x02 /* Glob. Log Targ. Save Disable */ 320 #define CTL1_RLEC 0x01 /* Rpt Logging Exception Condition */ 321 u_int8_t ctl_flags2; /* Second set of flags */ 322 #define CTL2_QAM_UNRESTRICT 0x10 /* Unrestricted reordering allowed */ 323 #define CTL2_QAM_FIELD 0xf0 /* Full Queue alogo. modifier field */ 324 #define CTL2_QERR_ABRT 0x02 /* Queue error - abort all */ 325 #define CTL2_QERR_ABRT_SELF 0x06 /* Queue error - abort intr's */ 326 #define CTL2_QERR_FIELD 0x06 /* Full field */ 327 #define CTL2_DQUE 0x01 /* Disable queuing */ 328 u_int8_t ctl_flags3; /* Third set of flags */ 329 #define CTL3_TAS 0x80 /* other-intr aborts generate status */ 330 #define CTL3_RAC 0x40 /* Report A Check */ 331 #define CTL3_UAIC_RET 0x10 /* retain UA, see SPC-3 */ 332 #define CTL3_UAIC_RET_EST 0x30 /* retain UA and establish UA */ 333 #define CTL3_UA_INTRLOCKS 0x30 /* UA Interlock control field */ 334 #define CTL3_SWP 0x08 /* Software write protect */ 335 #define CTL3_RAERP 0x04 /* (unit) Ready AER Permission */ 336 #define CTL3_UAAERP 0x02 /* Unit Attention AER Permission */ 337 #define CTL3_EAERP 0x01 /* Error AER Permission */ 338 u_int8_t ctl_autoload; /* autoload mode control */ 339 #define CTL_AUTOLOAD_FIELD 0x07 /* autoload field */ 340 u_int8_t ctl_r_hld[2]; /* RAERP holdoff period */ 341 u_int8_t ctl_busy[2]; /* busy timeout period */ 342 u_int8_t ctl_selt[2]; /* extended self-test completion time */ 343 } control_params; 344 }; 345 346 #endif /* _DEV_SCSIPI_SCSI_DISK_H_ */ 347