1 /* $NetBSD: qe.c,v 1.59 2011/07/18 00:58:52 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for the SBus qec+qe QuadEthernet board. 61 * 62 * This driver was written using the AMD MACE Am79C940 documentation, some 63 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 64 * and a loan of a card from Paul Southworth of the Internet Engineering 65 * Group (www.ieng.com). 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.59 2011/07/18 00:58:52 mrg Exp $"); 70 71 #define QEDEBUG 72 73 #include "opt_ddb.h" 74 #include "opt_inet.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/errno.h> 81 #include <sys/ioctl.h> 82 #include <sys/mbuf.h> 83 #include <sys/socket.h> 84 #include <sys/syslog.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_types.h> 94 #include <net/netisr.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_inarp.h> 101 #include <netinet/in_systm.h> 102 #include <netinet/in_var.h> 103 #include <netinet/ip.h> 104 #endif 105 106 107 #include <net/bpf.h> 108 #include <net/bpfdesc.h> 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 #include <machine/autoconf.h> 113 114 #include <dev/sbus/sbusvar.h> 115 #include <dev/sbus/qecreg.h> 116 #include <dev/sbus/qecvar.h> 117 #include <dev/sbus/qereg.h> 118 119 struct qe_softc { 120 device_t sc_dev; 121 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 122 bus_dma_tag_t sc_dmatag; 123 bus_dmamap_t sc_dmamap; 124 struct ethercom sc_ethercom; 125 struct ifmedia sc_ifmedia; /* interface media */ 126 127 struct qec_softc *sc_qec; /* QEC parent */ 128 129 bus_space_handle_t sc_qr; /* QEC registers */ 130 bus_space_handle_t sc_mr; /* MACE registers */ 131 bus_space_handle_t sc_cr; /* channel registers */ 132 133 int sc_channel; /* channel number */ 134 u_int sc_rev; /* board revision */ 135 136 int sc_burst; 137 138 struct qec_ring sc_rb; /* Packet Ring Buffer */ 139 140 /* MAC address */ 141 uint8_t sc_enaddr[6]; 142 143 #ifdef QEDEBUG 144 int sc_debug; 145 #endif 146 }; 147 148 int qematch(device_t, cfdata_t, void *); 149 void qeattach(device_t, device_t, void *); 150 151 void qeinit(struct qe_softc *); 152 void qestart(struct ifnet *); 153 void qestop(struct qe_softc *); 154 void qewatchdog(struct ifnet *); 155 int qeioctl(struct ifnet *, u_long, void *); 156 void qereset(struct qe_softc *); 157 158 int qeintr(void *); 159 int qe_eint(struct qe_softc *, uint32_t); 160 int qe_rint(struct qe_softc *); 161 int qe_tint(struct qe_softc *); 162 void qe_mcreset(struct qe_softc *); 163 164 static int qe_put(struct qe_softc *, int, struct mbuf *); 165 static void qe_read(struct qe_softc *, int, int); 166 static struct mbuf *qe_get(struct qe_softc *, int, int); 167 168 /* ifmedia callbacks */ 169 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 int qe_ifmedia_upd(struct ifnet *); 171 172 CFATTACH_DECL_NEW(qe, sizeof(struct qe_softc), 173 qematch, qeattach, NULL, NULL); 174 175 int 176 qematch(device_t parent, cfdata_t cf, void *aux) 177 { 178 struct sbus_attach_args *sa = aux; 179 180 return (strcmp(cf->cf_name, sa->sa_name) == 0); 181 } 182 183 void 184 qeattach(device_t parent, device_t self, void *aux) 185 { 186 struct sbus_attach_args *sa = aux; 187 struct qec_softc *qec = device_private(parent); 188 struct qe_softc *sc = device_private(self); 189 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 190 int node = sa->sa_node; 191 bus_dma_tag_t dmatag = sa->sa_dmatag; 192 bus_dma_segment_t seg; 193 bus_size_t size; 194 int rseg, error; 195 196 sc->sc_dev = self; 197 198 if (sa->sa_nreg < 2) { 199 printf("%s: only %d register sets\n", 200 device_xname(self), sa->sa_nreg); 201 return; 202 } 203 204 if (bus_space_map(sa->sa_bustag, 205 (bus_addr_t)BUS_ADDR( 206 sa->sa_reg[0].oa_space, 207 sa->sa_reg[0].oa_base), 208 (bus_size_t)sa->sa_reg[0].oa_size, 209 0, &sc->sc_cr) != 0) { 210 aprint_error_dev(self, "cannot map registers\n"); 211 return; 212 } 213 214 if (bus_space_map(sa->sa_bustag, 215 (bus_addr_t)BUS_ADDR( 216 sa->sa_reg[1].oa_space, 217 sa->sa_reg[1].oa_base), 218 (bus_size_t)sa->sa_reg[1].oa_size, 219 0, &sc->sc_mr) != 0) { 220 aprint_error_dev(self, "cannot map registers\n"); 221 return; 222 } 223 224 sc->sc_rev = prom_getpropint(node, "mace-version", -1); 225 printf(" rev %x", sc->sc_rev); 226 227 sc->sc_bustag = sa->sa_bustag; 228 sc->sc_dmatag = sa->sa_dmatag; 229 sc->sc_qec = qec; 230 sc->sc_qr = qec->sc_regs; 231 232 sc->sc_channel = prom_getpropint(node, "channel#", -1); 233 sc->sc_burst = qec->sc_burst; 234 235 qestop(sc); 236 237 /* Note: no interrupt level passed */ 238 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc); 239 prom_getether(node, sc->sc_enaddr); 240 241 /* 242 * Allocate descriptor ring and buffers. 243 */ 244 245 /* for now, allocate as many bufs as there are ring descriptors */ 246 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 247 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 248 249 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 250 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 251 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 252 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 253 254 /* Get a DMA handle */ 255 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 256 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 257 aprint_error_dev(self, "DMA map create error %d\n", 258 error); 259 return; 260 } 261 262 /* Allocate DMA buffer */ 263 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 264 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 265 aprint_error_dev(self, "DMA buffer alloc error %d\n", 266 error); 267 return; 268 } 269 270 /* Map DMA buffer in CPU addressable space */ 271 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 272 &sc->sc_rb.rb_membase, 273 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 274 aprint_error_dev(self, "DMA buffer map error %d\n", 275 error); 276 bus_dmamem_free(dmatag, &seg, rseg); 277 return; 278 } 279 280 /* Load the buffer */ 281 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 282 sc->sc_rb.rb_membase, size, NULL, 283 BUS_DMA_NOWAIT)) != 0) { 284 aprint_error_dev(self, "DMA buffer map load error %d\n", 285 error); 286 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 287 bus_dmamem_free(dmatag, &seg, rseg); 288 return; 289 } 290 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 291 292 /* Initialize media properties */ 293 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 294 ifmedia_add(&sc->sc_ifmedia, 295 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 296 0, NULL); 297 ifmedia_add(&sc->sc_ifmedia, 298 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, 301 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 302 0, NULL); 303 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 304 305 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 306 ifp->if_softc = sc; 307 ifp->if_start = qestart; 308 ifp->if_ioctl = qeioctl; 309 ifp->if_watchdog = qewatchdog; 310 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 311 IFF_MULTICAST; 312 IFQ_SET_READY(&ifp->if_snd); 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, sc->sc_enaddr); 317 318 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 319 } 320 321 /* 322 * Pull data off an interface. 323 * Len is the length of data, with local net header stripped. 324 * We copy the data into mbufs. When full cluster sized units are present, 325 * we copy into clusters. 326 */ 327 static inline struct mbuf * 328 qe_get(struct qe_softc *sc, int idx, int totlen) 329 { 330 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 331 struct mbuf *m; 332 struct mbuf *top, **mp; 333 int len, pad, boff = 0; 334 uint8_t *bp; 335 336 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 337 338 MGETHDR(m, M_DONTWAIT, MT_DATA); 339 if (m == NULL) 340 return (NULL); 341 m->m_pkthdr.rcvif = ifp; 342 m->m_pkthdr.len = totlen; 343 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 344 m->m_data += pad; 345 len = MHLEN - pad; 346 top = NULL; 347 mp = ⊤ 348 349 while (totlen > 0) { 350 if (top) { 351 MGET(m, M_DONTWAIT, MT_DATA); 352 if (m == NULL) { 353 m_freem(top); 354 return (NULL); 355 } 356 len = MLEN; 357 } 358 if (top && totlen >= MINCLSIZE) { 359 MCLGET(m, M_DONTWAIT); 360 if (m->m_flags & M_EXT) 361 len = MCLBYTES; 362 } 363 m->m_len = len = min(totlen, len); 364 memcpy(mtod(m, void *), bp + boff, len); 365 boff += len; 366 totlen -= len; 367 *mp = m; 368 mp = &m->m_next; 369 } 370 371 return (top); 372 } 373 374 /* 375 * Routine to copy from mbuf chain to transmit buffer in 376 * network buffer memory. 377 */ 378 inline int 379 qe_put(struct qe_softc *sc, int idx, struct mbuf *m) 380 { 381 struct mbuf *n; 382 int len, tlen = 0, boff = 0; 383 uint8_t *bp; 384 385 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 386 387 for (; m; m = n) { 388 len = m->m_len; 389 if (len == 0) { 390 MFREE(m, n); 391 continue; 392 } 393 memcpy(bp + boff, mtod(m, void *), len); 394 boff += len; 395 tlen += len; 396 MFREE(m, n); 397 } 398 return (tlen); 399 } 400 401 /* 402 * Pass a packet to the higher levels. 403 */ 404 inline void 405 qe_read(struct qe_softc *sc, int idx, int len) 406 { 407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 408 struct mbuf *m; 409 410 if (len <= sizeof(struct ether_header) || 411 len > ETHERMTU + sizeof(struct ether_header)) { 412 413 printf("%s: invalid packet size %d; dropping\n", 414 ifp->if_xname, len); 415 416 ifp->if_ierrors++; 417 return; 418 } 419 420 /* 421 * Pull packet off interface. 422 */ 423 m = qe_get(sc, idx, len); 424 if (m == NULL) { 425 ifp->if_ierrors++; 426 return; 427 } 428 ifp->if_ipackets++; 429 430 /* 431 * Check if there's a BPF listener on this interface. 432 * If so, hand off the raw packet to BPF. 433 */ 434 bpf_mtap(ifp, m); 435 /* Pass the packet up. */ 436 (*ifp->if_input)(ifp, m); 437 } 438 439 /* 440 * Start output on interface. 441 * We make two assumptions here: 442 * 1) that the current priority is set to splnet _before_ this code 443 * is called *and* is returned to the appropriate priority after 444 * return 445 * 2) that the IFF_OACTIVE flag is checked before this code is called 446 * (i.e. that the output part of the interface is idle) 447 */ 448 void 449 qestart(struct ifnet *ifp) 450 { 451 struct qe_softc *sc = ifp->if_softc; 452 struct qec_xd *txd = sc->sc_rb.rb_txd; 453 struct mbuf *m; 454 unsigned int bix, len; 455 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 456 457 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 458 return; 459 460 bix = sc->sc_rb.rb_tdhead; 461 462 for (;;) { 463 IFQ_DEQUEUE(&ifp->if_snd, m); 464 if (m == 0) 465 break; 466 467 /* 468 * If BPF is listening on this interface, let it see the 469 * packet before we commit it to the wire. 470 */ 471 bpf_mtap(ifp, m); 472 473 /* 474 * Copy the mbuf chain into the transmit buffer. 475 */ 476 len = qe_put(sc, bix, m); 477 478 /* 479 * Initialize transmit registers and start transmission 480 */ 481 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 482 (len & QEC_XD_LENGTH); 483 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 484 QE_CR_CTRL_TWAKEUP); 485 486 if (++bix == QEC_XD_RING_MAXSIZE) 487 bix = 0; 488 489 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 490 ifp->if_flags |= IFF_OACTIVE; 491 break; 492 } 493 } 494 495 sc->sc_rb.rb_tdhead = bix; 496 } 497 498 void 499 qestop(struct qe_softc *sc) 500 { 501 bus_space_tag_t t = sc->sc_bustag; 502 bus_space_handle_t mr = sc->sc_mr; 503 bus_space_handle_t cr = sc->sc_cr; 504 int n; 505 506 #if defined(SUN4U) || defined(__GNUC__) 507 (void)&t; 508 #endif 509 /* Stop the schwurst */ 510 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 511 for (n = 200; n > 0; n--) { 512 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 513 QE_MR_BIUCC_SWRST) == 0) 514 break; 515 DELAY(20); 516 } 517 518 /* then reset */ 519 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 520 for (n = 200; n > 0; n--) { 521 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 522 QE_CR_CTRL_RESET) == 0) 523 break; 524 DELAY(20); 525 } 526 } 527 528 /* 529 * Reset interface. 530 */ 531 void 532 qereset(struct qe_softc *sc) 533 { 534 int s; 535 536 s = splnet(); 537 qestop(sc); 538 qeinit(sc); 539 splx(s); 540 } 541 542 void 543 qewatchdog(struct ifnet *ifp) 544 { 545 struct qe_softc *sc = ifp->if_softc; 546 547 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 548 ifp->if_oerrors++; 549 550 qereset(sc); 551 } 552 553 /* 554 * Interrupt dispatch. 555 */ 556 int 557 qeintr(void *arg) 558 { 559 struct qe_softc *sc = arg; 560 bus_space_tag_t t = sc->sc_bustag; 561 uint32_t qecstat, qestat; 562 int r = 0; 563 564 #if defined(SUN4U) || defined(__GNUC__) 565 (void)&t; 566 #endif 567 /* Read QEC status and channel status */ 568 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 569 #ifdef QEDEBUG 570 if (sc->sc_debug) { 571 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 572 } 573 #endif 574 575 /* Filter out status for this channel */ 576 qecstat = qecstat >> (4 * sc->sc_channel); 577 if ((qecstat & 0xf) == 0) 578 return (r); 579 580 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 581 582 #ifdef QEDEBUG 583 if (sc->sc_debug) { 584 char bits[64]; int i; 585 bus_space_tag_t t1 = sc->sc_bustag; 586 bus_space_handle_t mr = sc->sc_mr; 587 588 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 589 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits); 590 591 printf("MACE registers:\n"); 592 for (i = 0 ; i < 32; i++) { 593 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i)); 594 if (((i+1) & 7) == 0) 595 printf("\n"); 596 } 597 } 598 #endif 599 600 if (qestat & QE_CR_STAT_ALLERRORS) { 601 #ifdef QEDEBUG 602 if (sc->sc_debug) { 603 char bits[64]; 604 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 605 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits); 606 } 607 #endif 608 r |= qe_eint(sc, qestat); 609 if (r == -1) 610 return (1); 611 } 612 613 if (qestat & QE_CR_STAT_TXIRQ) 614 r |= qe_tint(sc); 615 616 if (qestat & QE_CR_STAT_RXIRQ) 617 r |= qe_rint(sc); 618 619 return (r); 620 } 621 622 /* 623 * Transmit interrupt. 624 */ 625 int 626 qe_tint(struct qe_softc *sc) 627 { 628 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 629 unsigned int bix, txflags; 630 631 bix = sc->sc_rb.rb_tdtail; 632 633 for (;;) { 634 if (sc->sc_rb.rb_td_nbusy <= 0) 635 break; 636 637 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 638 639 if (txflags & QEC_XD_OWN) 640 break; 641 642 ifp->if_flags &= ~IFF_OACTIVE; 643 ifp->if_opackets++; 644 645 if (++bix == QEC_XD_RING_MAXSIZE) 646 bix = 0; 647 648 --sc->sc_rb.rb_td_nbusy; 649 } 650 651 sc->sc_rb.rb_tdtail = bix; 652 653 qestart(ifp); 654 655 if (sc->sc_rb.rb_td_nbusy == 0) 656 ifp->if_timer = 0; 657 658 return (1); 659 } 660 661 /* 662 * Receive interrupt. 663 */ 664 int 665 qe_rint(struct qe_softc *sc) 666 { 667 struct qec_xd *xd = sc->sc_rb.rb_rxd; 668 unsigned int bix, len; 669 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 670 #ifdef QEDEBUG 671 int npackets = 0; 672 #endif 673 674 bix = sc->sc_rb.rb_rdtail; 675 676 /* 677 * Process all buffers with valid data. 678 */ 679 for (;;) { 680 len = xd[bix].xd_flags; 681 if (len & QEC_XD_OWN) 682 break; 683 684 #ifdef QEDEBUG 685 npackets++; 686 #endif 687 688 len &= QEC_XD_LENGTH; 689 len -= 4; 690 qe_read(sc, bix, len); 691 692 /* ... */ 693 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 694 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 695 696 if (++bix == QEC_XD_RING_MAXSIZE) 697 bix = 0; 698 } 699 #ifdef QEDEBUG 700 if (npackets == 0 && sc->sc_debug) 701 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 702 device_xname(sc->sc_dev), bix, len); 703 #endif 704 705 sc->sc_rb.rb_rdtail = bix; 706 707 return (1); 708 } 709 710 /* 711 * Error interrupt. 712 */ 713 int 714 qe_eint(struct qe_softc *sc, uint32_t why) 715 { 716 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 717 device_t self = sc->sc_dev; 718 const char *xname = device_xname(self); 719 int r = 0, rst = 0; 720 721 if (why & QE_CR_STAT_EDEFER) { 722 printf("%s: excessive tx defers.\n", xname); 723 r |= 1; 724 ifp->if_oerrors++; 725 } 726 727 if (why & QE_CR_STAT_CLOSS) { 728 printf("%s: no carrier, link down?\n", xname); 729 ifp->if_oerrors++; 730 r |= 1; 731 } 732 733 if (why & QE_CR_STAT_ERETRIES) { 734 printf("%s: excessive tx retries\n", xname); 735 ifp->if_oerrors++; 736 r |= 1; 737 rst = 1; 738 } 739 740 741 if (why & QE_CR_STAT_LCOLL) { 742 printf("%s: late tx transmission\n", xname); 743 ifp->if_oerrors++; 744 r |= 1; 745 rst = 1; 746 } 747 748 if (why & QE_CR_STAT_FUFLOW) { 749 printf("%s: tx fifo underflow\n", xname); 750 ifp->if_oerrors++; 751 r |= 1; 752 rst = 1; 753 } 754 755 if (why & QE_CR_STAT_JERROR) { 756 printf("%s: jabber seen\n", xname); 757 r |= 1; 758 } 759 760 if (why & QE_CR_STAT_BERROR) { 761 printf("%s: babble seen\n", xname); 762 r |= 1; 763 } 764 765 if (why & QE_CR_STAT_TCCOFLOW) { 766 ifp->if_collisions += 256; 767 ifp->if_oerrors += 256; 768 r |= 1; 769 } 770 771 if (why & QE_CR_STAT_TXDERROR) { 772 printf("%s: tx descriptor is bad\n", xname); 773 rst = 1; 774 r |= 1; 775 } 776 777 if (why & QE_CR_STAT_TXLERR) { 778 printf("%s: tx late error\n", xname); 779 ifp->if_oerrors++; 780 rst = 1; 781 r |= 1; 782 } 783 784 if (why & QE_CR_STAT_TXPERR) { 785 printf("%s: tx DMA parity error\n", xname); 786 ifp->if_oerrors++; 787 rst = 1; 788 r |= 1; 789 } 790 791 if (why & QE_CR_STAT_TXSERR) { 792 printf("%s: tx DMA sbus error ack\n", xname); 793 ifp->if_oerrors++; 794 rst = 1; 795 r |= 1; 796 } 797 798 if (why & QE_CR_STAT_RCCOFLOW) { 799 ifp->if_collisions += 256; 800 ifp->if_ierrors += 256; 801 r |= 1; 802 } 803 804 if (why & QE_CR_STAT_RUOFLOW) { 805 ifp->if_ierrors += 256; 806 r |= 1; 807 } 808 809 if (why & QE_CR_STAT_MCOFLOW) { 810 ifp->if_ierrors += 256; 811 r |= 1; 812 } 813 814 if (why & QE_CR_STAT_RXFOFLOW) { 815 printf("%s: rx fifo overflow\n", xname); 816 ifp->if_ierrors++; 817 r |= 1; 818 } 819 820 if (why & QE_CR_STAT_RLCOLL) { 821 printf("%s: rx late collision\n", xname); 822 ifp->if_ierrors++; 823 ifp->if_collisions++; 824 r |= 1; 825 } 826 827 if (why & QE_CR_STAT_FCOFLOW) { 828 ifp->if_ierrors += 256; 829 r |= 1; 830 } 831 832 if (why & QE_CR_STAT_CECOFLOW) { 833 ifp->if_ierrors += 256; 834 r |= 1; 835 } 836 837 if (why & QE_CR_STAT_RXDROP) { 838 printf("%s: rx packet dropped\n", xname); 839 ifp->if_ierrors++; 840 r |= 1; 841 } 842 843 if (why & QE_CR_STAT_RXSMALL) { 844 printf("%s: rx buffer too small\n", xname); 845 ifp->if_ierrors++; 846 r |= 1; 847 rst = 1; 848 } 849 850 if (why & QE_CR_STAT_RXLERR) { 851 printf("%s: rx late error\n", xname); 852 ifp->if_ierrors++; 853 r |= 1; 854 rst = 1; 855 } 856 857 if (why & QE_CR_STAT_RXPERR) { 858 printf("%s: rx DMA parity error\n", xname); 859 ifp->if_ierrors++; 860 r |= 1; 861 rst = 1; 862 } 863 864 if (why & QE_CR_STAT_RXSERR) { 865 printf("%s: rx DMA sbus error ack\n", xname); 866 ifp->if_ierrors++; 867 r |= 1; 868 rst = 1; 869 } 870 871 if (r == 0) 872 aprint_error_dev(self, "unexpected interrupt error: %08x\n", 873 why); 874 875 if (rst) { 876 printf("%s: resetting...\n", xname); 877 qereset(sc); 878 return (-1); 879 } 880 881 return (r); 882 } 883 884 int 885 qeioctl(struct ifnet *ifp, u_long cmd, void *data) 886 { 887 struct qe_softc *sc = ifp->if_softc; 888 struct ifaddr *ifa = data; 889 struct ifreq *ifr = data; 890 int s, error = 0; 891 892 s = splnet(); 893 894 switch (cmd) { 895 case SIOCINITIFADDR: 896 ifp->if_flags |= IFF_UP; 897 qeinit(sc); 898 switch (ifa->ifa_addr->sa_family) { 899 #ifdef INET 900 case AF_INET: 901 arp_ifinit(ifp, ifa); 902 break; 903 #endif /* INET */ 904 default: 905 break; 906 } 907 break; 908 909 case SIOCSIFFLAGS: 910 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 911 break; 912 /* XXX re-use ether_ioctl() */ 913 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 914 case IFF_RUNNING: 915 /* 916 * If interface is marked down and it is running, then 917 * stop it. 918 */ 919 qestop(sc); 920 ifp->if_flags &= ~IFF_RUNNING; 921 break; 922 case IFF_UP: 923 /* 924 * If interface is marked up and it is stopped, then 925 * start it. 926 */ 927 qeinit(sc); 928 break; 929 default: 930 /* 931 * Reset the interface to pick up changes in any other 932 * flags that affect hardware registers. 933 */ 934 qestop(sc); 935 qeinit(sc); 936 break; 937 } 938 #ifdef QEDEBUG 939 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 940 #endif 941 break; 942 943 case SIOCADDMULTI: 944 case SIOCDELMULTI: 945 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 946 /* 947 * Multicast list has changed; set the hardware filter 948 * accordingly. 949 */ 950 if (ifp->if_flags & IFF_RUNNING) 951 qe_mcreset(sc); 952 error = 0; 953 } 954 break; 955 956 case SIOCGIFMEDIA: 957 case SIOCSIFMEDIA: 958 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 959 break; 960 961 default: 962 error = EINVAL; 963 break; 964 } 965 966 splx(s); 967 return (error); 968 } 969 970 971 void 972 qeinit(struct qe_softc *sc) 973 { 974 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 975 bus_space_tag_t t = sc->sc_bustag; 976 bus_space_handle_t cr = sc->sc_cr; 977 bus_space_handle_t mr = sc->sc_mr; 978 struct qec_softc *qec = sc->sc_qec; 979 uint32_t qecaddr; 980 uint8_t *ea; 981 int s; 982 983 #if defined(SUN4U) || defined(__GNUC__) 984 (void)&t; 985 #endif 986 s = splnet(); 987 988 qestop(sc); 989 990 /* 991 * Allocate descriptor ring and buffers 992 */ 993 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 994 995 /* Channel registers: */ 996 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 997 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 998 999 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1000 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1001 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1002 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1003 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1004 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1005 1006 qecaddr = sc->sc_channel * qec->sc_msize; 1007 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1008 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1009 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1010 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1011 1012 /* MACE registers: */ 1013 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1014 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1015 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1016 1017 /* 1018 * Mask MACE's receive interrupt, since we're being notified 1019 * by the QEC after DMA completes. 1020 */ 1021 bus_space_write_1(t, mr, QE_MRI_IMR, 1022 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1023 1024 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1025 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1026 1027 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1028 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1029 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1030 1031 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1032 1033 /* 1034 * Station address 1035 */ 1036 ea = sc->sc_enaddr; 1037 bus_space_write_1(t, mr, QE_MRI_IAC, 1038 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1039 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1040 1041 /* Apply media settings */ 1042 qe_ifmedia_upd(ifp); 1043 1044 /* 1045 * Clear Logical address filter 1046 */ 1047 bus_space_write_1(t, mr, QE_MRI_IAC, 1048 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1049 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1050 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1051 1052 /* Clear missed packet count (register cleared on read) */ 1053 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1054 1055 #if 0 1056 /* test register: */ 1057 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1058 #endif 1059 1060 /* Reset multicast filter */ 1061 qe_mcreset(sc); 1062 1063 ifp->if_flags |= IFF_RUNNING; 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 splx(s); 1066 } 1067 1068 /* 1069 * Reset multicast filter. 1070 */ 1071 void 1072 qe_mcreset(struct qe_softc *sc) 1073 { 1074 struct ethercom *ec = &sc->sc_ethercom; 1075 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1076 bus_space_tag_t t = sc->sc_bustag; 1077 bus_space_handle_t mr = sc->sc_mr; 1078 struct ether_multi *enm; 1079 struct ether_multistep step; 1080 uint32_t crc; 1081 uint16_t hash[4]; 1082 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; 1083 int i, j; 1084 1085 #if defined(SUN4U) || defined(__GNUC__) 1086 (void)&t; 1087 #endif 1088 1089 /* We also enable transmitter & receiver here */ 1090 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1091 1092 if (ifp->if_flags & IFF_PROMISC) { 1093 maccc |= QE_MR_MACCC_PROM; 1094 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1095 return; 1096 } 1097 1098 if (ifp->if_flags & IFF_ALLMULTI) { 1099 bus_space_write_1(t, mr, QE_MRI_IAC, 1100 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1101 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1102 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1103 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1104 return; 1105 } 1106 1107 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1108 1109 ETHER_FIRST_MULTI(step, ec, enm); 1110 while (enm != NULL) { 1111 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1112 ETHER_ADDR_LEN) != 0) { 1113 /* 1114 * We must listen to a range of multicast 1115 * addresses. For now, just accept all 1116 * multicasts, rather than trying to set only 1117 * those filter bits needed to match the range. 1118 * (At this time, the only use of address 1119 * ranges is for IP multicast routing, for 1120 * which the range is big enough to require 1121 * all bits set.) 1122 */ 1123 bus_space_write_1(t, mr, QE_MRI_IAC, 1124 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1125 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1126 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1127 ifp->if_flags |= IFF_ALLMULTI; 1128 break; 1129 } 1130 1131 crc = 0xffffffff; 1132 1133 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1134 octet = enm->enm_addrlo[i]; 1135 1136 for (j = 0; j < 8; j++) { 1137 if ((crc & 1) ^ (octet & 1)) { 1138 crc >>= 1; 1139 crc ^= MC_POLY_LE; 1140 } 1141 else 1142 crc >>= 1; 1143 octet >>= 1; 1144 } 1145 } 1146 1147 crc >>= 26; 1148 hash[crc >> 4] |= 1 << (crc & 0xf); 1149 ETHER_NEXT_MULTI(step, enm); 1150 } 1151 1152 bus_space_write_1(t, mr, QE_MRI_IAC, 1153 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1154 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1155 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1156 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1157 } 1158 1159 /* 1160 * Get current media settings. 1161 */ 1162 void 1163 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1164 { 1165 struct qe_softc *sc = ifp->if_softc; 1166 bus_space_tag_t t = sc->sc_bustag; 1167 bus_space_handle_t mr = sc->sc_mr; 1168 uint8_t v; 1169 1170 #if defined(SUN4U) || defined(__GNUC__) 1171 (void)&t; 1172 #endif 1173 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1174 1175 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1176 case QE_MR_PLSCC_TP: 1177 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1178 break; 1179 case QE_MR_PLSCC_AUI: 1180 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1181 break; 1182 case QE_MR_PLSCC_GPSI: 1183 case QE_MR_PLSCC_DAI: 1184 /* ... */ 1185 break; 1186 } 1187 1188 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1189 ifmr->ifm_status |= IFM_AVALID; 1190 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1191 ifmr->ifm_status &= ~IFM_ACTIVE; 1192 else 1193 ifmr->ifm_status |= IFM_ACTIVE; 1194 1195 } 1196 1197 /* 1198 * Set media options. 1199 */ 1200 int 1201 qe_ifmedia_upd(struct ifnet *ifp) 1202 { 1203 struct qe_softc *sc = ifp->if_softc; 1204 struct ifmedia *ifm = &sc->sc_ifmedia; 1205 bus_space_tag_t t = sc->sc_bustag; 1206 bus_space_handle_t mr = sc->sc_mr; 1207 int newmedia = ifm->ifm_media; 1208 uint8_t plscc, phycc; 1209 1210 #if defined(SUN4U) || defined(__GNUC__) 1211 (void)&t; 1212 #endif 1213 if (IFM_TYPE(newmedia) != IFM_ETHER) 1214 return (EINVAL); 1215 1216 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1217 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1218 1219 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1220 phycc |= QE_MR_PHYCC_ASEL; 1221 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1222 plscc |= QE_MR_PLSCC_TP; 1223 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1224 plscc |= QE_MR_PLSCC_AUI; 1225 1226 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1227 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1228 1229 return (0); 1230 } 1231