1 /* $NetBSD: qe.c,v 1.69 2018/06/26 06:48:02 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for the SBus qec+qe QuadEthernet board. 61 * 62 * This driver was written using the AMD MACE Am79C940 documentation, some 63 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 64 * and a loan of a card from Paul Southworth of the Internet Engineering 65 * Group (www.ieng.com). 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.69 2018/06/26 06:48:02 msaitoh Exp $"); 70 71 #define QEDEBUG 72 73 #include "opt_ddb.h" 74 #include "opt_inet.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/errno.h> 80 #include <sys/ioctl.h> 81 #include <sys/mbuf.h> 82 #include <sys/socket.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 87 #include <net/if.h> 88 #include <net/if_dl.h> 89 #include <net/if_types.h> 90 #include <net/netisr.h> 91 #include <net/if_media.h> 92 #include <net/if_ether.h> 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_inarp.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/in_var.h> 100 #include <netinet/ip.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 #include <dev/sbus/qecreg.h> 109 #include <dev/sbus/qecvar.h> 110 #include <dev/sbus/qereg.h> 111 112 struct qe_softc { 113 device_t sc_dev; 114 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 115 bus_dma_tag_t sc_dmatag; 116 bus_dmamap_t sc_dmamap; 117 struct ethercom sc_ethercom; 118 struct ifmedia sc_ifmedia; /* interface media */ 119 120 struct qec_softc *sc_qec; /* QEC parent */ 121 122 bus_space_handle_t sc_qr; /* QEC registers */ 123 bus_space_handle_t sc_mr; /* MACE registers */ 124 bus_space_handle_t sc_cr; /* channel registers */ 125 126 int sc_channel; /* channel number */ 127 u_int sc_rev; /* board revision */ 128 129 int sc_burst; 130 131 struct qec_ring sc_rb; /* Packet Ring Buffer */ 132 133 /* MAC address */ 134 uint8_t sc_enaddr[6]; 135 136 #ifdef QEDEBUG 137 int sc_debug; 138 #endif 139 }; 140 141 int qematch(device_t, cfdata_t, void *); 142 void qeattach(device_t, device_t, void *); 143 144 void qeinit(struct qe_softc *); 145 void qestart(struct ifnet *); 146 void qestop(struct qe_softc *); 147 void qewatchdog(struct ifnet *); 148 int qeioctl(struct ifnet *, u_long, void *); 149 void qereset(struct qe_softc *); 150 151 int qeintr(void *); 152 int qe_eint(struct qe_softc *, uint32_t); 153 int qe_rint(struct qe_softc *); 154 int qe_tint(struct qe_softc *); 155 void qe_mcreset(struct qe_softc *); 156 157 static int qe_put(struct qe_softc *, int, struct mbuf *); 158 static void qe_read(struct qe_softc *, int, int); 159 static struct mbuf *qe_get(struct qe_softc *, int, int); 160 161 /* ifmedia callbacks */ 162 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 163 int qe_ifmedia_upd(struct ifnet *); 164 165 CFATTACH_DECL_NEW(qe, sizeof(struct qe_softc), 166 qematch, qeattach, NULL, NULL); 167 168 int 169 qematch(device_t parent, cfdata_t cf, void *aux) 170 { 171 struct sbus_attach_args *sa = aux; 172 173 return (strcmp(cf->cf_name, sa->sa_name) == 0); 174 } 175 176 void 177 qeattach(device_t parent, device_t self, void *aux) 178 { 179 struct sbus_attach_args *sa = aux; 180 struct qec_softc *qec = device_private(parent); 181 struct qe_softc *sc = device_private(self); 182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 183 int node = sa->sa_node; 184 bus_dma_tag_t dmatag = sa->sa_dmatag; 185 bus_dma_segment_t seg; 186 bus_size_t size; 187 int rseg, error; 188 189 sc->sc_dev = self; 190 191 if (sa->sa_nreg < 2) { 192 printf("%s: only %d register sets\n", 193 device_xname(self), sa->sa_nreg); 194 return; 195 } 196 197 if (bus_space_map(sa->sa_bustag, 198 (bus_addr_t)BUS_ADDR( 199 sa->sa_reg[0].oa_space, 200 sa->sa_reg[0].oa_base), 201 (bus_size_t)sa->sa_reg[0].oa_size, 202 0, &sc->sc_cr) != 0) { 203 aprint_error_dev(self, "cannot map registers\n"); 204 return; 205 } 206 207 if (bus_space_map(sa->sa_bustag, 208 (bus_addr_t)BUS_ADDR( 209 sa->sa_reg[1].oa_space, 210 sa->sa_reg[1].oa_base), 211 (bus_size_t)sa->sa_reg[1].oa_size, 212 0, &sc->sc_mr) != 0) { 213 aprint_error_dev(self, "cannot map registers\n"); 214 return; 215 } 216 217 sc->sc_rev = prom_getpropint(node, "mace-version", -1); 218 printf(" rev %x", sc->sc_rev); 219 220 sc->sc_bustag = sa->sa_bustag; 221 sc->sc_dmatag = sa->sa_dmatag; 222 sc->sc_qec = qec; 223 sc->sc_qr = qec->sc_regs; 224 225 sc->sc_channel = prom_getpropint(node, "channel#", -1); 226 sc->sc_burst = qec->sc_burst; 227 228 qestop(sc); 229 230 /* Note: no interrupt level passed */ 231 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc); 232 prom_getether(node, sc->sc_enaddr); 233 234 /* 235 * Allocate descriptor ring and buffers. 236 */ 237 238 /* for now, allocate as many bufs as there are ring descriptors */ 239 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 240 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 241 242 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 243 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 244 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 245 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 246 247 /* Get a DMA handle */ 248 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 249 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 250 aprint_error_dev(self, "DMA map create error %d\n", 251 error); 252 return; 253 } 254 255 /* Allocate DMA buffer */ 256 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 257 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 258 aprint_error_dev(self, "DMA buffer alloc error %d\n", 259 error); 260 return; 261 } 262 263 /* Map DMA buffer in CPU addressable space */ 264 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 265 &sc->sc_rb.rb_membase, 266 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 267 aprint_error_dev(self, "DMA buffer map error %d\n", 268 error); 269 bus_dmamem_free(dmatag, &seg, rseg); 270 return; 271 } 272 273 /* Load the buffer */ 274 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 275 sc->sc_rb.rb_membase, size, NULL, 276 BUS_DMA_NOWAIT)) != 0) { 277 aprint_error_dev(self, "DMA buffer map load error %d\n", 278 error); 279 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 280 bus_dmamem_free(dmatag, &seg, rseg); 281 return; 282 } 283 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 284 285 /* Initialize media properties */ 286 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 287 ifmedia_add(&sc->sc_ifmedia, 288 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 289 0, NULL); 290 ifmedia_add(&sc->sc_ifmedia, 291 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 292 0, NULL); 293 ifmedia_add(&sc->sc_ifmedia, 294 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 295 0, NULL); 296 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 297 298 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 299 ifp->if_softc = sc; 300 ifp->if_start = qestart; 301 ifp->if_ioctl = qeioctl; 302 ifp->if_watchdog = qewatchdog; 303 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 304 IFF_MULTICAST; 305 IFQ_SET_READY(&ifp->if_snd); 306 307 /* Attach the interface. */ 308 if_attach(ifp); 309 ether_ifattach(ifp, sc->sc_enaddr); 310 311 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 312 } 313 314 /* 315 * Pull data off an interface. 316 * Len is the length of data, with local net header stripped. 317 * We copy the data into mbufs. When full cluster sized units are present, 318 * we copy into clusters. 319 */ 320 static inline struct mbuf * 321 qe_get(struct qe_softc *sc, int idx, int totlen) 322 { 323 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 324 struct mbuf *m; 325 struct mbuf *top, **mp; 326 int len, pad, boff = 0; 327 uint8_t *bp; 328 329 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 330 331 MGETHDR(m, M_DONTWAIT, MT_DATA); 332 if (m == NULL) 333 return (NULL); 334 m_set_rcvif(m, ifp); 335 m->m_pkthdr.len = totlen; 336 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 337 m->m_data += pad; 338 len = MHLEN - pad; 339 top = NULL; 340 mp = ⊤ 341 342 while (totlen > 0) { 343 if (top) { 344 MGET(m, M_DONTWAIT, MT_DATA); 345 if (m == NULL) { 346 m_freem(top); 347 return (NULL); 348 } 349 len = MLEN; 350 } 351 if (top && totlen >= MINCLSIZE) { 352 MCLGET(m, M_DONTWAIT); 353 if (m->m_flags & M_EXT) 354 len = MCLBYTES; 355 } 356 m->m_len = len = min(totlen, len); 357 memcpy(mtod(m, void *), bp + boff, len); 358 boff += len; 359 totlen -= len; 360 *mp = m; 361 mp = &m->m_next; 362 } 363 364 return (top); 365 } 366 367 /* 368 * Routine to copy from mbuf chain to transmit buffer in 369 * network buffer memory. 370 */ 371 inline int 372 qe_put(struct qe_softc *sc, int idx, struct mbuf *m) 373 { 374 struct mbuf *n; 375 int len, tlen = 0, boff = 0; 376 uint8_t *bp; 377 378 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 379 380 for (; m; m = n) { 381 len = m->m_len; 382 if (len == 0) { 383 n = m_free(m); 384 continue; 385 } 386 memcpy(bp + boff, mtod(m, void *), len); 387 boff += len; 388 tlen += len; 389 n = m_free(m); 390 } 391 return (tlen); 392 } 393 394 /* 395 * Pass a packet to the higher levels. 396 */ 397 inline void 398 qe_read(struct qe_softc *sc, int idx, int len) 399 { 400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 401 struct mbuf *m; 402 403 if (len <= sizeof(struct ether_header) || 404 len > ETHERMTU + sizeof(struct ether_header)) { 405 406 printf("%s: invalid packet size %d; dropping\n", 407 ifp->if_xname, len); 408 409 ifp->if_ierrors++; 410 return; 411 } 412 413 /* 414 * Pull packet off interface. 415 */ 416 m = qe_get(sc, idx, len); 417 if (m == NULL) { 418 ifp->if_ierrors++; 419 return; 420 } 421 422 /* Pass the packet up. */ 423 if_percpuq_enqueue(ifp->if_percpuq, m); 424 } 425 426 /* 427 * Start output on interface. 428 * We make two assumptions here: 429 * 1) that the current priority is set to splnet _before_ this code 430 * is called *and* is returned to the appropriate priority after 431 * return 432 * 2) that the IFF_OACTIVE flag is checked before this code is called 433 * (i.e. that the output part of the interface is idle) 434 */ 435 void 436 qestart(struct ifnet *ifp) 437 { 438 struct qe_softc *sc = ifp->if_softc; 439 struct qec_xd *txd = sc->sc_rb.rb_txd; 440 struct mbuf *m; 441 unsigned int bix, len; 442 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 443 444 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 445 return; 446 447 bix = sc->sc_rb.rb_tdhead; 448 449 for (;;) { 450 IFQ_DEQUEUE(&ifp->if_snd, m); 451 if (m == 0) 452 break; 453 454 /* 455 * If BPF is listening on this interface, let it see the 456 * packet before we commit it to the wire. 457 */ 458 bpf_mtap(ifp, m, BPF_D_OUT); 459 460 /* 461 * Copy the mbuf chain into the transmit buffer. 462 */ 463 len = qe_put(sc, bix, m); 464 465 /* 466 * Initialize transmit registers and start transmission 467 */ 468 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 469 (len & QEC_XD_LENGTH); 470 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 471 QE_CR_CTRL_TWAKEUP); 472 473 if (++bix == QEC_XD_RING_MAXSIZE) 474 bix = 0; 475 476 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 477 ifp->if_flags |= IFF_OACTIVE; 478 break; 479 } 480 } 481 482 sc->sc_rb.rb_tdhead = bix; 483 } 484 485 void 486 qestop(struct qe_softc *sc) 487 { 488 bus_space_tag_t t = sc->sc_bustag; 489 bus_space_handle_t mr = sc->sc_mr; 490 bus_space_handle_t cr = sc->sc_cr; 491 int n; 492 493 #if defined(SUN4U) || defined(__GNUC__) 494 (void)&t; 495 #endif 496 /* Stop the schwurst */ 497 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 498 for (n = 200; n > 0; n--) { 499 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 500 QE_MR_BIUCC_SWRST) == 0) 501 break; 502 DELAY(20); 503 } 504 505 /* then reset */ 506 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 507 for (n = 200; n > 0; n--) { 508 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 509 QE_CR_CTRL_RESET) == 0) 510 break; 511 DELAY(20); 512 } 513 } 514 515 /* 516 * Reset interface. 517 */ 518 void 519 qereset(struct qe_softc *sc) 520 { 521 int s; 522 523 s = splnet(); 524 qestop(sc); 525 qeinit(sc); 526 splx(s); 527 } 528 529 void 530 qewatchdog(struct ifnet *ifp) 531 { 532 struct qe_softc *sc = ifp->if_softc; 533 534 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 535 ifp->if_oerrors++; 536 537 qereset(sc); 538 } 539 540 /* 541 * Interrupt dispatch. 542 */ 543 int 544 qeintr(void *arg) 545 { 546 struct qe_softc *sc = arg; 547 bus_space_tag_t t = sc->sc_bustag; 548 uint32_t qecstat, qestat; 549 int r = 0; 550 551 #if defined(SUN4U) || defined(__GNUC__) 552 (void)&t; 553 #endif 554 /* Read QEC status and channel status */ 555 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 556 #ifdef QEDEBUG 557 if (sc->sc_debug) { 558 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 559 } 560 #endif 561 562 /* Filter out status for this channel */ 563 qecstat = qecstat >> (4 * sc->sc_channel); 564 if ((qecstat & 0xf) == 0) 565 return (r); 566 567 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 568 569 #ifdef QEDEBUG 570 if (sc->sc_debug) { 571 char bits[64]; int i; 572 bus_space_tag_t t1 = sc->sc_bustag; 573 bus_space_handle_t mr = sc->sc_mr; 574 575 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 576 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits); 577 578 printf("MACE registers:\n"); 579 for (i = 0 ; i < 32; i++) { 580 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i)); 581 if (((i+1) & 7) == 0) 582 printf("\n"); 583 } 584 } 585 #endif 586 587 if (qestat & QE_CR_STAT_ALLERRORS) { 588 #ifdef QEDEBUG 589 if (sc->sc_debug) { 590 char bits[64]; 591 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 592 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits); 593 } 594 #endif 595 r |= qe_eint(sc, qestat); 596 if (r == -1) 597 return (1); 598 } 599 600 if (qestat & QE_CR_STAT_TXIRQ) 601 r |= qe_tint(sc); 602 603 if (qestat & QE_CR_STAT_RXIRQ) 604 r |= qe_rint(sc); 605 606 return (r); 607 } 608 609 /* 610 * Transmit interrupt. 611 */ 612 int 613 qe_tint(struct qe_softc *sc) 614 { 615 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 616 unsigned int bix, txflags; 617 618 bix = sc->sc_rb.rb_tdtail; 619 620 for (;;) { 621 if (sc->sc_rb.rb_td_nbusy <= 0) 622 break; 623 624 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 625 626 if (txflags & QEC_XD_OWN) 627 break; 628 629 ifp->if_flags &= ~IFF_OACTIVE; 630 ifp->if_opackets++; 631 632 if (++bix == QEC_XD_RING_MAXSIZE) 633 bix = 0; 634 635 --sc->sc_rb.rb_td_nbusy; 636 } 637 638 sc->sc_rb.rb_tdtail = bix; 639 640 qestart(ifp); 641 642 if (sc->sc_rb.rb_td_nbusy == 0) 643 ifp->if_timer = 0; 644 645 return (1); 646 } 647 648 /* 649 * Receive interrupt. 650 */ 651 int 652 qe_rint(struct qe_softc *sc) 653 { 654 struct qec_xd *xd = sc->sc_rb.rb_rxd; 655 unsigned int bix, len; 656 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 657 #ifdef QEDEBUG 658 int npackets = 0; 659 #endif 660 661 bix = sc->sc_rb.rb_rdtail; 662 663 /* 664 * Process all buffers with valid data. 665 */ 666 for (;;) { 667 len = xd[bix].xd_flags; 668 if (len & QEC_XD_OWN) 669 break; 670 671 #ifdef QEDEBUG 672 npackets++; 673 #endif 674 675 len &= QEC_XD_LENGTH; 676 len -= 4; 677 qe_read(sc, bix, len); 678 679 /* ... */ 680 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 681 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 682 683 if (++bix == QEC_XD_RING_MAXSIZE) 684 bix = 0; 685 } 686 #ifdef QEDEBUG 687 if (npackets == 0 && sc->sc_debug) 688 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 689 device_xname(sc->sc_dev), bix, len); 690 #endif 691 692 sc->sc_rb.rb_rdtail = bix; 693 694 return (1); 695 } 696 697 /* 698 * Error interrupt. 699 */ 700 int 701 qe_eint(struct qe_softc *sc, uint32_t why) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 device_t self = sc->sc_dev; 705 const char *xname = device_xname(self); 706 int r = 0, rst = 0; 707 708 if (why & QE_CR_STAT_EDEFER) { 709 printf("%s: excessive tx defers.\n", xname); 710 r |= 1; 711 ifp->if_oerrors++; 712 } 713 714 if (why & QE_CR_STAT_CLOSS) { 715 printf("%s: no carrier, link down?\n", xname); 716 ifp->if_oerrors++; 717 r |= 1; 718 } 719 720 if (why & QE_CR_STAT_ERETRIES) { 721 printf("%s: excessive tx retries\n", xname); 722 ifp->if_oerrors++; 723 r |= 1; 724 rst = 1; 725 } 726 727 728 if (why & QE_CR_STAT_LCOLL) { 729 printf("%s: late tx transmission\n", xname); 730 ifp->if_oerrors++; 731 r |= 1; 732 rst = 1; 733 } 734 735 if (why & QE_CR_STAT_FUFLOW) { 736 printf("%s: tx fifo underflow\n", xname); 737 ifp->if_oerrors++; 738 r |= 1; 739 rst = 1; 740 } 741 742 if (why & QE_CR_STAT_JERROR) { 743 printf("%s: jabber seen\n", xname); 744 r |= 1; 745 } 746 747 if (why & QE_CR_STAT_BERROR) { 748 printf("%s: babble seen\n", xname); 749 r |= 1; 750 } 751 752 if (why & QE_CR_STAT_TCCOFLOW) { 753 ifp->if_collisions += 256; 754 ifp->if_oerrors += 256; 755 r |= 1; 756 } 757 758 if (why & QE_CR_STAT_TXDERROR) { 759 printf("%s: tx descriptor is bad\n", xname); 760 rst = 1; 761 r |= 1; 762 } 763 764 if (why & QE_CR_STAT_TXLERR) { 765 printf("%s: tx late error\n", xname); 766 ifp->if_oerrors++; 767 rst = 1; 768 r |= 1; 769 } 770 771 if (why & QE_CR_STAT_TXPERR) { 772 printf("%s: tx DMA parity error\n", xname); 773 ifp->if_oerrors++; 774 rst = 1; 775 r |= 1; 776 } 777 778 if (why & QE_CR_STAT_TXSERR) { 779 printf("%s: tx DMA sbus error ack\n", xname); 780 ifp->if_oerrors++; 781 rst = 1; 782 r |= 1; 783 } 784 785 if (why & QE_CR_STAT_RCCOFLOW) { 786 ifp->if_collisions += 256; 787 ifp->if_ierrors += 256; 788 r |= 1; 789 } 790 791 if (why & QE_CR_STAT_RUOFLOW) { 792 ifp->if_ierrors += 256; 793 r |= 1; 794 } 795 796 if (why & QE_CR_STAT_MCOFLOW) { 797 ifp->if_ierrors += 256; 798 r |= 1; 799 } 800 801 if (why & QE_CR_STAT_RXFOFLOW) { 802 printf("%s: rx fifo overflow\n", xname); 803 ifp->if_ierrors++; 804 r |= 1; 805 } 806 807 if (why & QE_CR_STAT_RLCOLL) { 808 printf("%s: rx late collision\n", xname); 809 ifp->if_ierrors++; 810 ifp->if_collisions++; 811 r |= 1; 812 } 813 814 if (why & QE_CR_STAT_FCOFLOW) { 815 ifp->if_ierrors += 256; 816 r |= 1; 817 } 818 819 if (why & QE_CR_STAT_CECOFLOW) { 820 ifp->if_ierrors += 256; 821 r |= 1; 822 } 823 824 if (why & QE_CR_STAT_RXDROP) { 825 printf("%s: rx packet dropped\n", xname); 826 ifp->if_ierrors++; 827 r |= 1; 828 } 829 830 if (why & QE_CR_STAT_RXSMALL) { 831 printf("%s: rx buffer too small\n", xname); 832 ifp->if_ierrors++; 833 r |= 1; 834 rst = 1; 835 } 836 837 if (why & QE_CR_STAT_RXLERR) { 838 printf("%s: rx late error\n", xname); 839 ifp->if_ierrors++; 840 r |= 1; 841 rst = 1; 842 } 843 844 if (why & QE_CR_STAT_RXPERR) { 845 printf("%s: rx DMA parity error\n", xname); 846 ifp->if_ierrors++; 847 r |= 1; 848 rst = 1; 849 } 850 851 if (why & QE_CR_STAT_RXSERR) { 852 printf("%s: rx DMA sbus error ack\n", xname); 853 ifp->if_ierrors++; 854 r |= 1; 855 rst = 1; 856 } 857 858 if (r == 0) 859 aprint_error_dev(self, "unexpected interrupt error: %08x\n", 860 why); 861 862 if (rst) { 863 printf("%s: resetting...\n", xname); 864 qereset(sc); 865 return (-1); 866 } 867 868 return (r); 869 } 870 871 int 872 qeioctl(struct ifnet *ifp, u_long cmd, void *data) 873 { 874 struct qe_softc *sc = ifp->if_softc; 875 struct ifaddr *ifa = data; 876 struct ifreq *ifr = data; 877 int s, error = 0; 878 879 s = splnet(); 880 881 switch (cmd) { 882 case SIOCINITIFADDR: 883 ifp->if_flags |= IFF_UP; 884 qeinit(sc); 885 switch (ifa->ifa_addr->sa_family) { 886 #ifdef INET 887 case AF_INET: 888 arp_ifinit(ifp, ifa); 889 break; 890 #endif /* INET */ 891 default: 892 break; 893 } 894 break; 895 896 case SIOCSIFFLAGS: 897 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 898 break; 899 /* XXX re-use ether_ioctl() */ 900 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 901 case IFF_RUNNING: 902 /* 903 * If interface is marked down and it is running, then 904 * stop it. 905 */ 906 qestop(sc); 907 ifp->if_flags &= ~IFF_RUNNING; 908 break; 909 case IFF_UP: 910 /* 911 * If interface is marked up and it is stopped, then 912 * start it. 913 */ 914 qeinit(sc); 915 break; 916 default: 917 /* 918 * Reset the interface to pick up changes in any other 919 * flags that affect hardware registers. 920 */ 921 qestop(sc); 922 qeinit(sc); 923 break; 924 } 925 #ifdef QEDEBUG 926 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 927 #endif 928 break; 929 930 case SIOCADDMULTI: 931 case SIOCDELMULTI: 932 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 933 /* 934 * Multicast list has changed; set the hardware filter 935 * accordingly. 936 */ 937 if (ifp->if_flags & IFF_RUNNING) 938 qe_mcreset(sc); 939 error = 0; 940 } 941 break; 942 943 case SIOCGIFMEDIA: 944 case SIOCSIFMEDIA: 945 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 946 break; 947 948 default: 949 error = ether_ioctl(ifp, cmd, data); 950 break; 951 } 952 953 splx(s); 954 return (error); 955 } 956 957 958 void 959 qeinit(struct qe_softc *sc) 960 { 961 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 962 bus_space_tag_t t = sc->sc_bustag; 963 bus_space_handle_t cr = sc->sc_cr; 964 bus_space_handle_t mr = sc->sc_mr; 965 struct qec_softc *qec = sc->sc_qec; 966 uint32_t qecaddr; 967 uint8_t *ea; 968 int s; 969 970 #if defined(SUN4U) || defined(__GNUC__) 971 (void)&t; 972 #endif 973 s = splnet(); 974 975 qestop(sc); 976 977 /* 978 * Allocate descriptor ring and buffers 979 */ 980 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 981 982 /* Channel registers: */ 983 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 984 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 985 986 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 987 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 988 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 989 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 990 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 991 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 992 993 qecaddr = sc->sc_channel * qec->sc_msize; 994 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 995 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 996 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 997 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 998 999 /* MACE registers: */ 1000 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1001 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1002 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1003 1004 /* 1005 * Mask MACE's receive interrupt, since we're being notified 1006 * by the QEC after DMA completes. 1007 */ 1008 bus_space_write_1(t, mr, QE_MRI_IMR, 1009 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1010 1011 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1012 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1013 1014 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1015 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1016 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1017 1018 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1019 1020 /* 1021 * Station address 1022 */ 1023 ea = sc->sc_enaddr; 1024 bus_space_write_1(t, mr, QE_MRI_IAC, 1025 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1026 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1027 1028 /* Apply media settings */ 1029 qe_ifmedia_upd(ifp); 1030 1031 /* 1032 * Clear Logical address filter 1033 */ 1034 bus_space_write_1(t, mr, QE_MRI_IAC, 1035 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1036 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1037 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1038 1039 /* Clear missed packet count (register cleared on read) */ 1040 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1041 1042 #if 0 1043 /* test register: */ 1044 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1045 #endif 1046 1047 /* Reset multicast filter */ 1048 qe_mcreset(sc); 1049 1050 ifp->if_flags |= IFF_RUNNING; 1051 ifp->if_flags &= ~IFF_OACTIVE; 1052 splx(s); 1053 } 1054 1055 /* 1056 * Reset multicast filter. 1057 */ 1058 void 1059 qe_mcreset(struct qe_softc *sc) 1060 { 1061 struct ethercom *ec = &sc->sc_ethercom; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 bus_space_tag_t t = sc->sc_bustag; 1064 bus_space_handle_t mr = sc->sc_mr; 1065 struct ether_multi *enm; 1066 struct ether_multistep step; 1067 uint32_t crc; 1068 uint16_t hash[4]; 1069 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; 1070 int i; 1071 1072 #if defined(SUN4U) || defined(__GNUC__) 1073 (void)&t; 1074 #endif 1075 1076 /* We also enable transmitter & receiver here */ 1077 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1078 1079 if (ifp->if_flags & IFF_PROMISC) { 1080 maccc |= QE_MR_MACCC_PROM; 1081 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1082 return; 1083 } 1084 1085 if (ifp->if_flags & IFF_ALLMULTI) { 1086 bus_space_write_1(t, mr, QE_MRI_IAC, 1087 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1088 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1089 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1090 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1091 return; 1092 } 1093 1094 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1095 1096 ETHER_FIRST_MULTI(step, ec, enm); 1097 while (enm != NULL) { 1098 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1099 ETHER_ADDR_LEN) != 0) { 1100 /* 1101 * We must listen to a range of multicast 1102 * addresses. For now, just accept all 1103 * multicasts, rather than trying to set only 1104 * those filter bits needed to match the range. 1105 * (At this time, the only use of address 1106 * ranges is for IP multicast routing, for 1107 * which the range is big enough to require 1108 * all bits set.) 1109 */ 1110 bus_space_write_1(t, mr, QE_MRI_IAC, 1111 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1112 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1113 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1114 ifp->if_flags |= IFF_ALLMULTI; 1115 break; 1116 } 1117 1118 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1119 crc >>= 26; 1120 hash[crc >> 4] |= 1 << (crc & 0xf); 1121 ETHER_NEXT_MULTI(step, enm); 1122 } 1123 1124 /* We need to byte-swap the hash before writing to the chip. */ 1125 for (i = 0; i < 7; i += 2) { 1126 octet = ladrp[i]; 1127 ladrp[i] = ladrp[i + 1]; 1128 ladrp[i + 1] = octet; 1129 } 1130 bus_space_write_1(t, mr, QE_MRI_IAC, 1131 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1132 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1133 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1134 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1135 } 1136 1137 /* 1138 * Get current media settings. 1139 */ 1140 void 1141 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1142 { 1143 struct qe_softc *sc = ifp->if_softc; 1144 bus_space_tag_t t = sc->sc_bustag; 1145 bus_space_handle_t mr = sc->sc_mr; 1146 uint8_t v; 1147 1148 #if defined(SUN4U) || defined(__GNUC__) 1149 (void)&t; 1150 #endif 1151 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1152 1153 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1154 case QE_MR_PLSCC_TP: 1155 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1156 break; 1157 case QE_MR_PLSCC_AUI: 1158 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1159 break; 1160 case QE_MR_PLSCC_GPSI: 1161 case QE_MR_PLSCC_DAI: 1162 /* ... */ 1163 break; 1164 } 1165 1166 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1167 ifmr->ifm_status |= IFM_AVALID; 1168 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1169 ifmr->ifm_status &= ~IFM_ACTIVE; 1170 else 1171 ifmr->ifm_status |= IFM_ACTIVE; 1172 1173 } 1174 1175 /* 1176 * Set media options. 1177 */ 1178 int 1179 qe_ifmedia_upd(struct ifnet *ifp) 1180 { 1181 struct qe_softc *sc = ifp->if_softc; 1182 struct ifmedia *ifm = &sc->sc_ifmedia; 1183 bus_space_tag_t t = sc->sc_bustag; 1184 bus_space_handle_t mr = sc->sc_mr; 1185 int newmedia = ifm->ifm_media; 1186 uint8_t plscc, phycc; 1187 1188 #if defined(SUN4U) || defined(__GNUC__) 1189 (void)&t; 1190 #endif 1191 if (IFM_TYPE(newmedia) != IFM_ETHER) 1192 return (EINVAL); 1193 1194 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1195 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1196 1197 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1198 phycc |= QE_MR_PHYCC_ASEL; 1199 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1200 plscc |= QE_MR_PLSCC_TP; 1201 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1202 plscc |= QE_MR_PLSCC_AUI; 1203 1204 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1205 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1206 1207 return (0); 1208 } 1209