1 /* $NetBSD: qe.c,v 1.57 2010/01/19 22:07:43 pooka Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for the SBus qec+qe QuadEthernet board. 61 * 62 * This driver was written using the AMD MACE Am79C940 documentation, some 63 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 64 * and a loan of a card from Paul Southworth of the Internet Engineering 65 * Group (www.ieng.com). 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.57 2010/01/19 22:07:43 pooka Exp $"); 70 71 #define QEDEBUG 72 73 #include "opt_ddb.h" 74 #include "opt_inet.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/kernel.h> 80 #include <sys/errno.h> 81 #include <sys/ioctl.h> 82 #include <sys/mbuf.h> 83 #include <sys/socket.h> 84 #include <sys/syslog.h> 85 #include <sys/device.h> 86 #include <sys/malloc.h> 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_types.h> 94 #include <net/netisr.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_inarp.h> 101 #include <netinet/in_systm.h> 102 #include <netinet/in_var.h> 103 #include <netinet/ip.h> 104 #endif 105 106 107 #include <net/bpf.h> 108 #include <net/bpfdesc.h> 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 #include <machine/autoconf.h> 113 114 #include <dev/sbus/sbusvar.h> 115 #include <dev/sbus/qecreg.h> 116 #include <dev/sbus/qecvar.h> 117 #include <dev/sbus/qereg.h> 118 119 struct qe_softc { 120 struct device sc_dev; /* base device */ 121 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 122 bus_dma_tag_t sc_dmatag; 123 bus_dmamap_t sc_dmamap; 124 struct ethercom sc_ethercom; 125 struct ifmedia sc_ifmedia; /* interface media */ 126 127 struct qec_softc *sc_qec; /* QEC parent */ 128 129 bus_space_handle_t sc_qr; /* QEC registers */ 130 bus_space_handle_t sc_mr; /* MACE registers */ 131 bus_space_handle_t sc_cr; /* channel registers */ 132 133 int sc_channel; /* channel number */ 134 u_int sc_rev; /* board revision */ 135 136 int sc_burst; 137 138 struct qec_ring sc_rb; /* Packet Ring Buffer */ 139 140 /* MAC address */ 141 uint8_t sc_enaddr[6]; 142 143 #ifdef QEDEBUG 144 int sc_debug; 145 #endif 146 }; 147 148 int qematch(device_t, cfdata_t, void *); 149 void qeattach(device_t, device_t, void *); 150 151 void qeinit(struct qe_softc *); 152 void qestart(struct ifnet *); 153 void qestop(struct qe_softc *); 154 void qewatchdog(struct ifnet *); 155 int qeioctl(struct ifnet *, u_long, void *); 156 void qereset(struct qe_softc *); 157 158 int qeintr(void *); 159 int qe_eint(struct qe_softc *, uint32_t); 160 int qe_rint(struct qe_softc *); 161 int qe_tint(struct qe_softc *); 162 void qe_mcreset(struct qe_softc *); 163 164 static int qe_put(struct qe_softc *, int, struct mbuf *); 165 static void qe_read(struct qe_softc *, int, int); 166 static struct mbuf *qe_get(struct qe_softc *, int, int); 167 168 /* ifmedia callbacks */ 169 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 int qe_ifmedia_upd(struct ifnet *); 171 172 CFATTACH_DECL(qe, sizeof(struct qe_softc), 173 qematch, qeattach, NULL, NULL); 174 175 int 176 qematch(device_t parent, cfdata_t cf, void *aux) 177 { 178 struct sbus_attach_args *sa = aux; 179 180 return (strcmp(cf->cf_name, sa->sa_name) == 0); 181 } 182 183 void 184 qeattach(device_t parent, device_t self, void *aux) 185 { 186 struct sbus_attach_args *sa = aux; 187 struct qec_softc *qec = device_private(parent); 188 struct qe_softc *sc = device_private(self); 189 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 190 int node = sa->sa_node; 191 bus_dma_tag_t dmatag = sa->sa_dmatag; 192 bus_dma_segment_t seg; 193 bus_size_t size; 194 int rseg, error; 195 196 if (sa->sa_nreg < 2) { 197 printf("%s: only %d register sets\n", 198 device_xname(self), sa->sa_nreg); 199 return; 200 } 201 202 if (bus_space_map(sa->sa_bustag, 203 (bus_addr_t)BUS_ADDR( 204 sa->sa_reg[0].oa_space, 205 sa->sa_reg[0].oa_base), 206 (bus_size_t)sa->sa_reg[0].oa_size, 207 0, &sc->sc_cr) != 0) { 208 aprint_error_dev(self, "cannot map registers\n"); 209 return; 210 } 211 212 if (bus_space_map(sa->sa_bustag, 213 (bus_addr_t)BUS_ADDR( 214 sa->sa_reg[1].oa_space, 215 sa->sa_reg[1].oa_base), 216 (bus_size_t)sa->sa_reg[1].oa_size, 217 0, &sc->sc_mr) != 0) { 218 aprint_error_dev(self, "cannot map registers\n"); 219 return; 220 } 221 222 sc->sc_rev = prom_getpropint(node, "mace-version", -1); 223 printf(" rev %x", sc->sc_rev); 224 225 sc->sc_bustag = sa->sa_bustag; 226 sc->sc_dmatag = sa->sa_dmatag; 227 sc->sc_qec = qec; 228 sc->sc_qr = qec->sc_regs; 229 230 sc->sc_channel = prom_getpropint(node, "channel#", -1); 231 sc->sc_burst = qec->sc_burst; 232 233 qestop(sc); 234 235 /* Note: no interrupt level passed */ 236 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc); 237 prom_getether(node, sc->sc_enaddr); 238 239 /* 240 * Allocate descriptor ring and buffers. 241 */ 242 243 /* for now, allocate as many bufs as there are ring descriptors */ 244 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 245 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 246 247 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 248 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 249 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 250 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 251 252 /* Get a DMA handle */ 253 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 254 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 255 aprint_error_dev(self, "DMA map create error %d\n", 256 error); 257 return; 258 } 259 260 /* Allocate DMA buffer */ 261 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 262 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 263 aprint_error_dev(self, "DMA buffer alloc error %d\n", 264 error); 265 return; 266 } 267 268 /* Map DMA buffer in CPU addressable space */ 269 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 270 &sc->sc_rb.rb_membase, 271 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 272 aprint_error_dev(self, "DMA buffer map error %d\n", 273 error); 274 bus_dmamem_free(dmatag, &seg, rseg); 275 return; 276 } 277 278 /* Load the buffer */ 279 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 280 sc->sc_rb.rb_membase, size, NULL, 281 BUS_DMA_NOWAIT)) != 0) { 282 aprint_error_dev(self, "DMA buffer map load error %d\n", 283 error); 284 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 285 bus_dmamem_free(dmatag, &seg, rseg); 286 return; 287 } 288 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 289 290 /* Initialize media properties */ 291 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 292 ifmedia_add(&sc->sc_ifmedia, 293 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 294 0, NULL); 295 ifmedia_add(&sc->sc_ifmedia, 296 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 297 0, NULL); 298 ifmedia_add(&sc->sc_ifmedia, 299 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 300 0, NULL); 301 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 302 303 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 304 ifp->if_softc = sc; 305 ifp->if_start = qestart; 306 ifp->if_ioctl = qeioctl; 307 ifp->if_watchdog = qewatchdog; 308 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 309 IFF_MULTICAST; 310 IFQ_SET_READY(&ifp->if_snd); 311 312 /* Attach the interface. */ 313 if_attach(ifp); 314 ether_ifattach(ifp, sc->sc_enaddr); 315 316 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 317 } 318 319 /* 320 * Pull data off an interface. 321 * Len is the length of data, with local net header stripped. 322 * We copy the data into mbufs. When full cluster sized units are present, 323 * we copy into clusters. 324 */ 325 static inline struct mbuf * 326 qe_get(struct qe_softc *sc, int idx, int totlen) 327 { 328 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 329 struct mbuf *m; 330 struct mbuf *top, **mp; 331 int len, pad, boff = 0; 332 uint8_t *bp; 333 334 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 335 336 MGETHDR(m, M_DONTWAIT, MT_DATA); 337 if (m == NULL) 338 return (NULL); 339 m->m_pkthdr.rcvif = ifp; 340 m->m_pkthdr.len = totlen; 341 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 342 m->m_data += pad; 343 len = MHLEN - pad; 344 top = NULL; 345 mp = ⊤ 346 347 while (totlen > 0) { 348 if (top) { 349 MGET(m, M_DONTWAIT, MT_DATA); 350 if (m == NULL) { 351 m_freem(top); 352 return (NULL); 353 } 354 len = MLEN; 355 } 356 if (top && totlen >= MINCLSIZE) { 357 MCLGET(m, M_DONTWAIT); 358 if (m->m_flags & M_EXT) 359 len = MCLBYTES; 360 } 361 m->m_len = len = min(totlen, len); 362 memcpy(mtod(m, void *), bp + boff, len); 363 boff += len; 364 totlen -= len; 365 *mp = m; 366 mp = &m->m_next; 367 } 368 369 return (top); 370 } 371 372 /* 373 * Routine to copy from mbuf chain to transmit buffer in 374 * network buffer memory. 375 */ 376 inline int 377 qe_put(struct qe_softc *sc, int idx, struct mbuf *m) 378 { 379 struct mbuf *n; 380 int len, tlen = 0, boff = 0; 381 uint8_t *bp; 382 383 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 384 385 for (; m; m = n) { 386 len = m->m_len; 387 if (len == 0) { 388 MFREE(m, n); 389 continue; 390 } 391 memcpy(bp + boff, mtod(m, void *), len); 392 boff += len; 393 tlen += len; 394 MFREE(m, n); 395 } 396 return (tlen); 397 } 398 399 /* 400 * Pass a packet to the higher levels. 401 */ 402 inline void 403 qe_read(struct qe_softc *sc, int idx, int len) 404 { 405 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 406 struct mbuf *m; 407 408 if (len <= sizeof(struct ether_header) || 409 len > ETHERMTU + sizeof(struct ether_header)) { 410 411 printf("%s: invalid packet size %d; dropping\n", 412 ifp->if_xname, len); 413 414 ifp->if_ierrors++; 415 return; 416 } 417 418 /* 419 * Pull packet off interface. 420 */ 421 m = qe_get(sc, idx, len); 422 if (m == NULL) { 423 ifp->if_ierrors++; 424 return; 425 } 426 ifp->if_ipackets++; 427 428 /* 429 * Check if there's a BPF listener on this interface. 430 * If so, hand off the raw packet to BPF. 431 */ 432 if (ifp->if_bpf) 433 bpf_ops->bpf_mtap(ifp->if_bpf, m); 434 /* Pass the packet up. */ 435 (*ifp->if_input)(ifp, m); 436 } 437 438 /* 439 * Start output on interface. 440 * We make two assumptions here: 441 * 1) that the current priority is set to splnet _before_ this code 442 * is called *and* is returned to the appropriate priority after 443 * return 444 * 2) that the IFF_OACTIVE flag is checked before this code is called 445 * (i.e. that the output part of the interface is idle) 446 */ 447 void 448 qestart(struct ifnet *ifp) 449 { 450 struct qe_softc *sc = ifp->if_softc; 451 struct qec_xd *txd = sc->sc_rb.rb_txd; 452 struct mbuf *m; 453 unsigned int bix, len; 454 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 455 456 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 457 return; 458 459 bix = sc->sc_rb.rb_tdhead; 460 461 for (;;) { 462 IFQ_DEQUEUE(&ifp->if_snd, m); 463 if (m == 0) 464 break; 465 466 /* 467 * If BPF is listening on this interface, let it see the 468 * packet before we commit it to the wire. 469 */ 470 if (ifp->if_bpf) 471 bpf_ops->bpf_mtap(ifp->if_bpf, m); 472 473 /* 474 * Copy the mbuf chain into the transmit buffer. 475 */ 476 len = qe_put(sc, bix, m); 477 478 /* 479 * Initialize transmit registers and start transmission 480 */ 481 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 482 (len & QEC_XD_LENGTH); 483 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 484 QE_CR_CTRL_TWAKEUP); 485 486 if (++bix == QEC_XD_RING_MAXSIZE) 487 bix = 0; 488 489 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 490 ifp->if_flags |= IFF_OACTIVE; 491 break; 492 } 493 } 494 495 sc->sc_rb.rb_tdhead = bix; 496 } 497 498 void 499 qestop(struct qe_softc *sc) 500 { 501 bus_space_tag_t t = sc->sc_bustag; 502 bus_space_handle_t mr = sc->sc_mr; 503 bus_space_handle_t cr = sc->sc_cr; 504 int n; 505 506 #if defined(SUN4U) || defined(__GNUC__) 507 (void)&t; 508 #endif 509 /* Stop the schwurst */ 510 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 511 for (n = 200; n > 0; n--) { 512 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 513 QE_MR_BIUCC_SWRST) == 0) 514 break; 515 DELAY(20); 516 } 517 518 /* then reset */ 519 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 520 for (n = 200; n > 0; n--) { 521 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 522 QE_CR_CTRL_RESET) == 0) 523 break; 524 DELAY(20); 525 } 526 } 527 528 /* 529 * Reset interface. 530 */ 531 void 532 qereset(struct qe_softc *sc) 533 { 534 int s; 535 536 s = splnet(); 537 qestop(sc); 538 qeinit(sc); 539 splx(s); 540 } 541 542 void 543 qewatchdog(struct ifnet *ifp) 544 { 545 struct qe_softc *sc = ifp->if_softc; 546 547 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 548 ifp->if_oerrors++; 549 550 qereset(sc); 551 } 552 553 /* 554 * Interrupt dispatch. 555 */ 556 int 557 qeintr(void *arg) 558 { 559 struct qe_softc *sc = arg; 560 bus_space_tag_t t = sc->sc_bustag; 561 uint32_t qecstat, qestat; 562 int r = 0; 563 564 #if defined(SUN4U) || defined(__GNUC__) 565 (void)&t; 566 #endif 567 /* Read QEC status and channel status */ 568 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 569 #ifdef QEDEBUG 570 if (sc->sc_debug) { 571 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 572 } 573 #endif 574 575 /* Filter out status for this channel */ 576 qecstat = qecstat >> (4 * sc->sc_channel); 577 if ((qecstat & 0xf) == 0) 578 return (r); 579 580 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 581 582 #ifdef QEDEBUG 583 if (sc->sc_debug) { 584 char bits[64]; int i; 585 bus_space_tag_t t1 = sc->sc_bustag; 586 bus_space_handle_t mr = sc->sc_mr; 587 588 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 589 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits); 590 591 printf("MACE registers:\n"); 592 for (i = 0 ; i < 32; i++) { 593 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i)); 594 if (((i+1) & 7) == 0) 595 printf("\n"); 596 } 597 } 598 #endif 599 600 if (qestat & QE_CR_STAT_ALLERRORS) { 601 #ifdef QEDEBUG 602 if (sc->sc_debug) { 603 char bits[64]; 604 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 605 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits); 606 } 607 #endif 608 r |= qe_eint(sc, qestat); 609 if (r == -1) 610 return (1); 611 } 612 613 if (qestat & QE_CR_STAT_TXIRQ) 614 r |= qe_tint(sc); 615 616 if (qestat & QE_CR_STAT_RXIRQ) 617 r |= qe_rint(sc); 618 619 return (r); 620 } 621 622 /* 623 * Transmit interrupt. 624 */ 625 int 626 qe_tint(struct qe_softc *sc) 627 { 628 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 629 unsigned int bix, txflags; 630 631 bix = sc->sc_rb.rb_tdtail; 632 633 for (;;) { 634 if (sc->sc_rb.rb_td_nbusy <= 0) 635 break; 636 637 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 638 639 if (txflags & QEC_XD_OWN) 640 break; 641 642 ifp->if_flags &= ~IFF_OACTIVE; 643 ifp->if_opackets++; 644 645 if (++bix == QEC_XD_RING_MAXSIZE) 646 bix = 0; 647 648 --sc->sc_rb.rb_td_nbusy; 649 } 650 651 sc->sc_rb.rb_tdtail = bix; 652 653 qestart(ifp); 654 655 if (sc->sc_rb.rb_td_nbusy == 0) 656 ifp->if_timer = 0; 657 658 return (1); 659 } 660 661 /* 662 * Receive interrupt. 663 */ 664 int 665 qe_rint(struct qe_softc *sc) 666 { 667 struct qec_xd *xd = sc->sc_rb.rb_rxd; 668 unsigned int bix, len; 669 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 670 #ifdef QEDEBUG 671 int npackets = 0; 672 #endif 673 674 bix = sc->sc_rb.rb_rdtail; 675 676 /* 677 * Process all buffers with valid data. 678 */ 679 for (;;) { 680 len = xd[bix].xd_flags; 681 if (len & QEC_XD_OWN) 682 break; 683 684 #ifdef QEDEBUG 685 npackets++; 686 #endif 687 688 len &= QEC_XD_LENGTH; 689 len -= 4; 690 qe_read(sc, bix, len); 691 692 /* ... */ 693 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 694 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 695 696 if (++bix == QEC_XD_RING_MAXSIZE) 697 bix = 0; 698 } 699 #ifdef QEDEBUG 700 if (npackets == 0 && sc->sc_debug) 701 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 702 device_xname(&sc->sc_dev), bix, len); 703 #endif 704 705 sc->sc_rb.rb_rdtail = bix; 706 707 return (1); 708 } 709 710 /* 711 * Error interrupt. 712 */ 713 int 714 qe_eint(struct qe_softc *sc, uint32_t why) 715 { 716 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 717 device_t self = &sc->sc_dev; 718 int r = 0, rst = 0; 719 720 if (why & QE_CR_STAT_EDEFER) { 721 printf("%s: excessive tx defers.\n", device_xname(self)); 722 r |= 1; 723 ifp->if_oerrors++; 724 } 725 726 if (why & QE_CR_STAT_CLOSS) { 727 printf("%s: no carrier, link down?\n", device_xname(self)); 728 ifp->if_oerrors++; 729 r |= 1; 730 } 731 732 if (why & QE_CR_STAT_ERETRIES) { 733 printf("%s: excessive tx retries\n", device_xname(self)); 734 ifp->if_oerrors++; 735 r |= 1; 736 rst = 1; 737 } 738 739 740 if (why & QE_CR_STAT_LCOLL) { 741 printf("%s: late tx transmission\n", device_xname(self)); 742 ifp->if_oerrors++; 743 r |= 1; 744 rst = 1; 745 } 746 747 if (why & QE_CR_STAT_FUFLOW) { 748 printf("%s: tx fifo underflow\n", device_xname(self)); 749 ifp->if_oerrors++; 750 r |= 1; 751 rst = 1; 752 } 753 754 if (why & QE_CR_STAT_JERROR) { 755 printf("%s: jabber seen\n", device_xname(self)); 756 r |= 1; 757 } 758 759 if (why & QE_CR_STAT_BERROR) { 760 printf("%s: babble seen\n", device_xname(self)); 761 r |= 1; 762 } 763 764 if (why & QE_CR_STAT_TCCOFLOW) { 765 ifp->if_collisions += 256; 766 ifp->if_oerrors += 256; 767 r |= 1; 768 } 769 770 if (why & QE_CR_STAT_TXDERROR) { 771 printf("%s: tx descriptor is bad\n", device_xname(self)); 772 rst = 1; 773 r |= 1; 774 } 775 776 if (why & QE_CR_STAT_TXLERR) { 777 printf("%s: tx late error\n", device_xname(self)); 778 ifp->if_oerrors++; 779 rst = 1; 780 r |= 1; 781 } 782 783 if (why & QE_CR_STAT_TXPERR) { 784 printf("%s: tx DMA parity error\n", device_xname(self)); 785 ifp->if_oerrors++; 786 rst = 1; 787 r |= 1; 788 } 789 790 if (why & QE_CR_STAT_TXSERR) { 791 printf("%s: tx DMA sbus error ack\n", device_xname(self)); 792 ifp->if_oerrors++; 793 rst = 1; 794 r |= 1; 795 } 796 797 if (why & QE_CR_STAT_RCCOFLOW) { 798 ifp->if_collisions += 256; 799 ifp->if_ierrors += 256; 800 r |= 1; 801 } 802 803 if (why & QE_CR_STAT_RUOFLOW) { 804 ifp->if_ierrors += 256; 805 r |= 1; 806 } 807 808 if (why & QE_CR_STAT_MCOFLOW) { 809 ifp->if_ierrors += 256; 810 r |= 1; 811 } 812 813 if (why & QE_CR_STAT_RXFOFLOW) { 814 printf("%s: rx fifo overflow\n", device_xname(self)); 815 ifp->if_ierrors++; 816 r |= 1; 817 } 818 819 if (why & QE_CR_STAT_RLCOLL) { 820 printf("%s: rx late collision\n", device_xname(self)); 821 ifp->if_ierrors++; 822 ifp->if_collisions++; 823 r |= 1; 824 } 825 826 if (why & QE_CR_STAT_FCOFLOW) { 827 ifp->if_ierrors += 256; 828 r |= 1; 829 } 830 831 if (why & QE_CR_STAT_CECOFLOW) { 832 ifp->if_ierrors += 256; 833 r |= 1; 834 } 835 836 if (why & QE_CR_STAT_RXDROP) { 837 printf("%s: rx packet dropped\n", device_xname(self)); 838 ifp->if_ierrors++; 839 r |= 1; 840 } 841 842 if (why & QE_CR_STAT_RXSMALL) { 843 printf("%s: rx buffer too small\n", device_xname(self)); 844 ifp->if_ierrors++; 845 r |= 1; 846 rst = 1; 847 } 848 849 if (why & QE_CR_STAT_RXLERR) { 850 printf("%s: rx late error\n", device_xname(self)); 851 ifp->if_ierrors++; 852 r |= 1; 853 rst = 1; 854 } 855 856 if (why & QE_CR_STAT_RXPERR) { 857 printf("%s: rx DMA parity error\n", device_xname(self)); 858 ifp->if_ierrors++; 859 r |= 1; 860 rst = 1; 861 } 862 863 if (why & QE_CR_STAT_RXSERR) { 864 printf("%s: rx DMA sbus error ack\n", device_xname(self)); 865 ifp->if_ierrors++; 866 r |= 1; 867 rst = 1; 868 } 869 870 if (r == 0) 871 aprint_error_dev(self, "unexpected interrupt error: %08x\n", 872 why); 873 874 if (rst) { 875 printf("%s: resetting...\n", device_xname(self)); 876 qereset(sc); 877 return (-1); 878 } 879 880 return (r); 881 } 882 883 int 884 qeioctl(struct ifnet *ifp, u_long cmd, void *data) 885 { 886 struct qe_softc *sc = ifp->if_softc; 887 struct ifaddr *ifa = data; 888 struct ifreq *ifr = data; 889 int s, error = 0; 890 891 s = splnet(); 892 893 switch (cmd) { 894 case SIOCINITIFADDR: 895 ifp->if_flags |= IFF_UP; 896 qeinit(sc); 897 switch (ifa->ifa_addr->sa_family) { 898 #ifdef INET 899 case AF_INET: 900 arp_ifinit(ifp, ifa); 901 break; 902 #endif /* INET */ 903 default: 904 break; 905 } 906 break; 907 908 case SIOCSIFFLAGS: 909 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 910 break; 911 /* XXX re-use ether_ioctl() */ 912 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 913 case IFF_RUNNING: 914 /* 915 * If interface is marked down and it is running, then 916 * stop it. 917 */ 918 qestop(sc); 919 ifp->if_flags &= ~IFF_RUNNING; 920 break; 921 case IFF_UP: 922 /* 923 * If interface is marked up and it is stopped, then 924 * start it. 925 */ 926 qeinit(sc); 927 break; 928 default: 929 /* 930 * Reset the interface to pick up changes in any other 931 * flags that affect hardware registers. 932 */ 933 qestop(sc); 934 qeinit(sc); 935 break; 936 } 937 #ifdef QEDEBUG 938 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 939 #endif 940 break; 941 942 case SIOCADDMULTI: 943 case SIOCDELMULTI: 944 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 945 /* 946 * Multicast list has changed; set the hardware filter 947 * accordingly. 948 */ 949 if (ifp->if_flags & IFF_RUNNING) 950 qe_mcreset(sc); 951 error = 0; 952 } 953 break; 954 955 case SIOCGIFMEDIA: 956 case SIOCSIFMEDIA: 957 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 958 break; 959 960 default: 961 error = EINVAL; 962 break; 963 } 964 965 splx(s); 966 return (error); 967 } 968 969 970 void 971 qeinit(struct qe_softc *sc) 972 { 973 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 974 bus_space_tag_t t = sc->sc_bustag; 975 bus_space_handle_t cr = sc->sc_cr; 976 bus_space_handle_t mr = sc->sc_mr; 977 struct qec_softc *qec = sc->sc_qec; 978 uint32_t qecaddr; 979 uint8_t *ea; 980 int s; 981 982 #if defined(SUN4U) || defined(__GNUC__) 983 (void)&t; 984 #endif 985 s = splnet(); 986 987 qestop(sc); 988 989 /* 990 * Allocate descriptor ring and buffers 991 */ 992 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 993 994 /* Channel registers: */ 995 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 996 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 997 998 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 999 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1000 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1001 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1002 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1003 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1004 1005 qecaddr = sc->sc_channel * qec->sc_msize; 1006 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1007 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1008 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1009 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1010 1011 /* MACE registers: */ 1012 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1013 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1014 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1015 1016 /* 1017 * Mask MACE's receive interrupt, since we're being notified 1018 * by the QEC after DMA completes. 1019 */ 1020 bus_space_write_1(t, mr, QE_MRI_IMR, 1021 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1022 1023 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1024 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1025 1026 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1027 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1028 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1029 1030 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1031 1032 /* 1033 * Station address 1034 */ 1035 ea = sc->sc_enaddr; 1036 bus_space_write_1(t, mr, QE_MRI_IAC, 1037 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1038 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1039 1040 /* Apply media settings */ 1041 qe_ifmedia_upd(ifp); 1042 1043 /* 1044 * Clear Logical address filter 1045 */ 1046 bus_space_write_1(t, mr, QE_MRI_IAC, 1047 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1048 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1049 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1050 1051 /* Clear missed packet count (register cleared on read) */ 1052 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1053 1054 #if 0 1055 /* test register: */ 1056 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1057 #endif 1058 1059 /* Reset multicast filter */ 1060 qe_mcreset(sc); 1061 1062 ifp->if_flags |= IFF_RUNNING; 1063 ifp->if_flags &= ~IFF_OACTIVE; 1064 splx(s); 1065 } 1066 1067 /* 1068 * Reset multicast filter. 1069 */ 1070 void 1071 qe_mcreset(struct qe_softc *sc) 1072 { 1073 struct ethercom *ec = &sc->sc_ethercom; 1074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1075 bus_space_tag_t t = sc->sc_bustag; 1076 bus_space_handle_t mr = sc->sc_mr; 1077 struct ether_multi *enm; 1078 struct ether_multistep step; 1079 uint32_t crc; 1080 uint16_t hash[4]; 1081 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; 1082 int i, j; 1083 1084 #if defined(SUN4U) || defined(__GNUC__) 1085 (void)&t; 1086 #endif 1087 1088 /* We also enable transmitter & receiver here */ 1089 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1090 1091 if (ifp->if_flags & IFF_PROMISC) { 1092 maccc |= QE_MR_MACCC_PROM; 1093 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1094 return; 1095 } 1096 1097 if (ifp->if_flags & IFF_ALLMULTI) { 1098 bus_space_write_1(t, mr, QE_MRI_IAC, 1099 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1100 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1101 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1102 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1103 return; 1104 } 1105 1106 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1107 1108 ETHER_FIRST_MULTI(step, ec, enm); 1109 while (enm != NULL) { 1110 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1111 ETHER_ADDR_LEN) != 0) { 1112 /* 1113 * We must listen to a range of multicast 1114 * addresses. For now, just accept all 1115 * multicasts, rather than trying to set only 1116 * those filter bits needed to match the range. 1117 * (At this time, the only use of address 1118 * ranges is for IP multicast routing, for 1119 * which the range is big enough to require 1120 * all bits set.) 1121 */ 1122 bus_space_write_1(t, mr, QE_MRI_IAC, 1123 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1124 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1125 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1126 ifp->if_flags |= IFF_ALLMULTI; 1127 break; 1128 } 1129 1130 crc = 0xffffffff; 1131 1132 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1133 octet = enm->enm_addrlo[i]; 1134 1135 for (j = 0; j < 8; j++) { 1136 if ((crc & 1) ^ (octet & 1)) { 1137 crc >>= 1; 1138 crc ^= MC_POLY_LE; 1139 } 1140 else 1141 crc >>= 1; 1142 octet >>= 1; 1143 } 1144 } 1145 1146 crc >>= 26; 1147 hash[crc >> 4] |= 1 << (crc & 0xf); 1148 ETHER_NEXT_MULTI(step, enm); 1149 } 1150 1151 bus_space_write_1(t, mr, QE_MRI_IAC, 1152 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1153 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1154 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1155 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1156 } 1157 1158 /* 1159 * Get current media settings. 1160 */ 1161 void 1162 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1163 { 1164 struct qe_softc *sc = ifp->if_softc; 1165 bus_space_tag_t t = sc->sc_bustag; 1166 bus_space_handle_t mr = sc->sc_mr; 1167 uint8_t v; 1168 1169 #if defined(SUN4U) || defined(__GNUC__) 1170 (void)&t; 1171 #endif 1172 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1173 1174 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1175 case QE_MR_PLSCC_TP: 1176 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1177 break; 1178 case QE_MR_PLSCC_AUI: 1179 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1180 break; 1181 case QE_MR_PLSCC_GPSI: 1182 case QE_MR_PLSCC_DAI: 1183 /* ... */ 1184 break; 1185 } 1186 1187 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1188 ifmr->ifm_status |= IFM_AVALID; 1189 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1190 ifmr->ifm_status &= ~IFM_ACTIVE; 1191 else 1192 ifmr->ifm_status |= IFM_ACTIVE; 1193 1194 } 1195 1196 /* 1197 * Set media options. 1198 */ 1199 int 1200 qe_ifmedia_upd(struct ifnet *ifp) 1201 { 1202 struct qe_softc *sc = ifp->if_softc; 1203 struct ifmedia *ifm = &sc->sc_ifmedia; 1204 bus_space_tag_t t = sc->sc_bustag; 1205 bus_space_handle_t mr = sc->sc_mr; 1206 int newmedia = ifm->ifm_media; 1207 uint8_t plscc, phycc; 1208 1209 #if defined(SUN4U) || defined(__GNUC__) 1210 (void)&t; 1211 #endif 1212 if (IFM_TYPE(newmedia) != IFM_ETHER) 1213 return (EINVAL); 1214 1215 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1216 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1217 1218 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1219 phycc |= QE_MR_PHYCC_ASEL; 1220 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1221 plscc |= QE_MR_PLSCC_TP; 1222 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1223 plscc |= QE_MR_PLSCC_AUI; 1224 1225 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1226 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1227 1228 return (0); 1229 } 1230