1 /* $NetBSD: qe.c,v 1.67 2016/12/15 09:28:06 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for the SBus qec+qe QuadEthernet board. 61 * 62 * This driver was written using the AMD MACE Am79C940 documentation, some 63 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 64 * and a loan of a card from Paul Southworth of the Internet Engineering 65 * Group (www.ieng.com). 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.67 2016/12/15 09:28:06 ozaki-r Exp $"); 70 71 #define QEDEBUG 72 73 #include "opt_ddb.h" 74 #include "opt_inet.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/errno.h> 80 #include <sys/ioctl.h> 81 #include <sys/mbuf.h> 82 #include <sys/socket.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 87 #include <net/if.h> 88 #include <net/if_dl.h> 89 #include <net/if_types.h> 90 #include <net/netisr.h> 91 #include <net/if_media.h> 92 #include <net/if_ether.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_inarp.h> 97 #include <netinet/in_systm.h> 98 #include <netinet/in_var.h> 99 #include <netinet/ip.h> 100 #endif 101 102 103 #include <net/bpf.h> 104 #include <net/bpfdesc.h> 105 106 #include <sys/bus.h> 107 #include <sys/intr.h> 108 #include <machine/autoconf.h> 109 110 #include <dev/sbus/sbusvar.h> 111 #include <dev/sbus/qecreg.h> 112 #include <dev/sbus/qecvar.h> 113 #include <dev/sbus/qereg.h> 114 115 struct qe_softc { 116 device_t sc_dev; 117 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 118 bus_dma_tag_t sc_dmatag; 119 bus_dmamap_t sc_dmamap; 120 struct ethercom sc_ethercom; 121 struct ifmedia sc_ifmedia; /* interface media */ 122 123 struct qec_softc *sc_qec; /* QEC parent */ 124 125 bus_space_handle_t sc_qr; /* QEC registers */ 126 bus_space_handle_t sc_mr; /* MACE registers */ 127 bus_space_handle_t sc_cr; /* channel registers */ 128 129 int sc_channel; /* channel number */ 130 u_int sc_rev; /* board revision */ 131 132 int sc_burst; 133 134 struct qec_ring sc_rb; /* Packet Ring Buffer */ 135 136 /* MAC address */ 137 uint8_t sc_enaddr[6]; 138 139 #ifdef QEDEBUG 140 int sc_debug; 141 #endif 142 }; 143 144 int qematch(device_t, cfdata_t, void *); 145 void qeattach(device_t, device_t, void *); 146 147 void qeinit(struct qe_softc *); 148 void qestart(struct ifnet *); 149 void qestop(struct qe_softc *); 150 void qewatchdog(struct ifnet *); 151 int qeioctl(struct ifnet *, u_long, void *); 152 void qereset(struct qe_softc *); 153 154 int qeintr(void *); 155 int qe_eint(struct qe_softc *, uint32_t); 156 int qe_rint(struct qe_softc *); 157 int qe_tint(struct qe_softc *); 158 void qe_mcreset(struct qe_softc *); 159 160 static int qe_put(struct qe_softc *, int, struct mbuf *); 161 static void qe_read(struct qe_softc *, int, int); 162 static struct mbuf *qe_get(struct qe_softc *, int, int); 163 164 /* ifmedia callbacks */ 165 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 int qe_ifmedia_upd(struct ifnet *); 167 168 CFATTACH_DECL_NEW(qe, sizeof(struct qe_softc), 169 qematch, qeattach, NULL, NULL); 170 171 int 172 qematch(device_t parent, cfdata_t cf, void *aux) 173 { 174 struct sbus_attach_args *sa = aux; 175 176 return (strcmp(cf->cf_name, sa->sa_name) == 0); 177 } 178 179 void 180 qeattach(device_t parent, device_t self, void *aux) 181 { 182 struct sbus_attach_args *sa = aux; 183 struct qec_softc *qec = device_private(parent); 184 struct qe_softc *sc = device_private(self); 185 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 186 int node = sa->sa_node; 187 bus_dma_tag_t dmatag = sa->sa_dmatag; 188 bus_dma_segment_t seg; 189 bus_size_t size; 190 int rseg, error; 191 192 sc->sc_dev = self; 193 194 if (sa->sa_nreg < 2) { 195 printf("%s: only %d register sets\n", 196 device_xname(self), sa->sa_nreg); 197 return; 198 } 199 200 if (bus_space_map(sa->sa_bustag, 201 (bus_addr_t)BUS_ADDR( 202 sa->sa_reg[0].oa_space, 203 sa->sa_reg[0].oa_base), 204 (bus_size_t)sa->sa_reg[0].oa_size, 205 0, &sc->sc_cr) != 0) { 206 aprint_error_dev(self, "cannot map registers\n"); 207 return; 208 } 209 210 if (bus_space_map(sa->sa_bustag, 211 (bus_addr_t)BUS_ADDR( 212 sa->sa_reg[1].oa_space, 213 sa->sa_reg[1].oa_base), 214 (bus_size_t)sa->sa_reg[1].oa_size, 215 0, &sc->sc_mr) != 0) { 216 aprint_error_dev(self, "cannot map registers\n"); 217 return; 218 } 219 220 sc->sc_rev = prom_getpropint(node, "mace-version", -1); 221 printf(" rev %x", sc->sc_rev); 222 223 sc->sc_bustag = sa->sa_bustag; 224 sc->sc_dmatag = sa->sa_dmatag; 225 sc->sc_qec = qec; 226 sc->sc_qr = qec->sc_regs; 227 228 sc->sc_channel = prom_getpropint(node, "channel#", -1); 229 sc->sc_burst = qec->sc_burst; 230 231 qestop(sc); 232 233 /* Note: no interrupt level passed */ 234 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc); 235 prom_getether(node, sc->sc_enaddr); 236 237 /* 238 * Allocate descriptor ring and buffers. 239 */ 240 241 /* for now, allocate as many bufs as there are ring descriptors */ 242 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 243 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 244 245 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 246 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 247 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 248 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 249 250 /* Get a DMA handle */ 251 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 252 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 253 aprint_error_dev(self, "DMA map create error %d\n", 254 error); 255 return; 256 } 257 258 /* Allocate DMA buffer */ 259 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 260 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 261 aprint_error_dev(self, "DMA buffer alloc error %d\n", 262 error); 263 return; 264 } 265 266 /* Map DMA buffer in CPU addressable space */ 267 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 268 &sc->sc_rb.rb_membase, 269 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 270 aprint_error_dev(self, "DMA buffer map error %d\n", 271 error); 272 bus_dmamem_free(dmatag, &seg, rseg); 273 return; 274 } 275 276 /* Load the buffer */ 277 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 278 sc->sc_rb.rb_membase, size, NULL, 279 BUS_DMA_NOWAIT)) != 0) { 280 aprint_error_dev(self, "DMA buffer map load error %d\n", 281 error); 282 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 283 bus_dmamem_free(dmatag, &seg, rseg); 284 return; 285 } 286 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 287 288 /* Initialize media properties */ 289 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 290 ifmedia_add(&sc->sc_ifmedia, 291 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 292 0, NULL); 293 ifmedia_add(&sc->sc_ifmedia, 294 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 295 0, NULL); 296 ifmedia_add(&sc->sc_ifmedia, 297 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 298 0, NULL); 299 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 300 301 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 302 ifp->if_softc = sc; 303 ifp->if_start = qestart; 304 ifp->if_ioctl = qeioctl; 305 ifp->if_watchdog = qewatchdog; 306 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 307 IFF_MULTICAST; 308 IFQ_SET_READY(&ifp->if_snd); 309 310 /* Attach the interface. */ 311 if_attach(ifp); 312 ether_ifattach(ifp, sc->sc_enaddr); 313 314 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 315 } 316 317 /* 318 * Pull data off an interface. 319 * Len is the length of data, with local net header stripped. 320 * We copy the data into mbufs. When full cluster sized units are present, 321 * we copy into clusters. 322 */ 323 static inline struct mbuf * 324 qe_get(struct qe_softc *sc, int idx, int totlen) 325 { 326 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 327 struct mbuf *m; 328 struct mbuf *top, **mp; 329 int len, pad, boff = 0; 330 uint8_t *bp; 331 332 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 333 334 MGETHDR(m, M_DONTWAIT, MT_DATA); 335 if (m == NULL) 336 return (NULL); 337 m_set_rcvif(m, ifp); 338 m->m_pkthdr.len = totlen; 339 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 340 m->m_data += pad; 341 len = MHLEN - pad; 342 top = NULL; 343 mp = ⊤ 344 345 while (totlen > 0) { 346 if (top) { 347 MGET(m, M_DONTWAIT, MT_DATA); 348 if (m == NULL) { 349 m_freem(top); 350 return (NULL); 351 } 352 len = MLEN; 353 } 354 if (top && totlen >= MINCLSIZE) { 355 MCLGET(m, M_DONTWAIT); 356 if (m->m_flags & M_EXT) 357 len = MCLBYTES; 358 } 359 m->m_len = len = min(totlen, len); 360 memcpy(mtod(m, void *), bp + boff, len); 361 boff += len; 362 totlen -= len; 363 *mp = m; 364 mp = &m->m_next; 365 } 366 367 return (top); 368 } 369 370 /* 371 * Routine to copy from mbuf chain to transmit buffer in 372 * network buffer memory. 373 */ 374 inline int 375 qe_put(struct qe_softc *sc, int idx, struct mbuf *m) 376 { 377 struct mbuf *n; 378 int len, tlen = 0, boff = 0; 379 uint8_t *bp; 380 381 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 382 383 for (; m; m = n) { 384 len = m->m_len; 385 if (len == 0) { 386 n = m_free(m); 387 continue; 388 } 389 memcpy(bp + boff, mtod(m, void *), len); 390 boff += len; 391 tlen += len; 392 n = m_free(m); 393 } 394 return (tlen); 395 } 396 397 /* 398 * Pass a packet to the higher levels. 399 */ 400 inline void 401 qe_read(struct qe_softc *sc, int idx, int len) 402 { 403 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 404 struct mbuf *m; 405 406 if (len <= sizeof(struct ether_header) || 407 len > ETHERMTU + sizeof(struct ether_header)) { 408 409 printf("%s: invalid packet size %d; dropping\n", 410 ifp->if_xname, len); 411 412 ifp->if_ierrors++; 413 return; 414 } 415 416 /* 417 * Pull packet off interface. 418 */ 419 m = qe_get(sc, idx, len); 420 if (m == NULL) { 421 ifp->if_ierrors++; 422 return; 423 } 424 425 /* Pass the packet up. */ 426 if_percpuq_enqueue(ifp->if_percpuq, m); 427 } 428 429 /* 430 * Start output on interface. 431 * We make two assumptions here: 432 * 1) that the current priority is set to splnet _before_ this code 433 * is called *and* is returned to the appropriate priority after 434 * return 435 * 2) that the IFF_OACTIVE flag is checked before this code is called 436 * (i.e. that the output part of the interface is idle) 437 */ 438 void 439 qestart(struct ifnet *ifp) 440 { 441 struct qe_softc *sc = ifp->if_softc; 442 struct qec_xd *txd = sc->sc_rb.rb_txd; 443 struct mbuf *m; 444 unsigned int bix, len; 445 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 446 447 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 448 return; 449 450 bix = sc->sc_rb.rb_tdhead; 451 452 for (;;) { 453 IFQ_DEQUEUE(&ifp->if_snd, m); 454 if (m == 0) 455 break; 456 457 /* 458 * If BPF is listening on this interface, let it see the 459 * packet before we commit it to the wire. 460 */ 461 bpf_mtap(ifp, m); 462 463 /* 464 * Copy the mbuf chain into the transmit buffer. 465 */ 466 len = qe_put(sc, bix, m); 467 468 /* 469 * Initialize transmit registers and start transmission 470 */ 471 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 472 (len & QEC_XD_LENGTH); 473 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 474 QE_CR_CTRL_TWAKEUP); 475 476 if (++bix == QEC_XD_RING_MAXSIZE) 477 bix = 0; 478 479 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 480 ifp->if_flags |= IFF_OACTIVE; 481 break; 482 } 483 } 484 485 sc->sc_rb.rb_tdhead = bix; 486 } 487 488 void 489 qestop(struct qe_softc *sc) 490 { 491 bus_space_tag_t t = sc->sc_bustag; 492 bus_space_handle_t mr = sc->sc_mr; 493 bus_space_handle_t cr = sc->sc_cr; 494 int n; 495 496 #if defined(SUN4U) || defined(__GNUC__) 497 (void)&t; 498 #endif 499 /* Stop the schwurst */ 500 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 501 for (n = 200; n > 0; n--) { 502 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 503 QE_MR_BIUCC_SWRST) == 0) 504 break; 505 DELAY(20); 506 } 507 508 /* then reset */ 509 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 510 for (n = 200; n > 0; n--) { 511 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 512 QE_CR_CTRL_RESET) == 0) 513 break; 514 DELAY(20); 515 } 516 } 517 518 /* 519 * Reset interface. 520 */ 521 void 522 qereset(struct qe_softc *sc) 523 { 524 int s; 525 526 s = splnet(); 527 qestop(sc); 528 qeinit(sc); 529 splx(s); 530 } 531 532 void 533 qewatchdog(struct ifnet *ifp) 534 { 535 struct qe_softc *sc = ifp->if_softc; 536 537 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 538 ifp->if_oerrors++; 539 540 qereset(sc); 541 } 542 543 /* 544 * Interrupt dispatch. 545 */ 546 int 547 qeintr(void *arg) 548 { 549 struct qe_softc *sc = arg; 550 bus_space_tag_t t = sc->sc_bustag; 551 uint32_t qecstat, qestat; 552 int r = 0; 553 554 #if defined(SUN4U) || defined(__GNUC__) 555 (void)&t; 556 #endif 557 /* Read QEC status and channel status */ 558 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 559 #ifdef QEDEBUG 560 if (sc->sc_debug) { 561 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 562 } 563 #endif 564 565 /* Filter out status for this channel */ 566 qecstat = qecstat >> (4 * sc->sc_channel); 567 if ((qecstat & 0xf) == 0) 568 return (r); 569 570 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 571 572 #ifdef QEDEBUG 573 if (sc->sc_debug) { 574 char bits[64]; int i; 575 bus_space_tag_t t1 = sc->sc_bustag; 576 bus_space_handle_t mr = sc->sc_mr; 577 578 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 579 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits); 580 581 printf("MACE registers:\n"); 582 for (i = 0 ; i < 32; i++) { 583 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i)); 584 if (((i+1) & 7) == 0) 585 printf("\n"); 586 } 587 } 588 #endif 589 590 if (qestat & QE_CR_STAT_ALLERRORS) { 591 #ifdef QEDEBUG 592 if (sc->sc_debug) { 593 char bits[64]; 594 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 595 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits); 596 } 597 #endif 598 r |= qe_eint(sc, qestat); 599 if (r == -1) 600 return (1); 601 } 602 603 if (qestat & QE_CR_STAT_TXIRQ) 604 r |= qe_tint(sc); 605 606 if (qestat & QE_CR_STAT_RXIRQ) 607 r |= qe_rint(sc); 608 609 return (r); 610 } 611 612 /* 613 * Transmit interrupt. 614 */ 615 int 616 qe_tint(struct qe_softc *sc) 617 { 618 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 619 unsigned int bix, txflags; 620 621 bix = sc->sc_rb.rb_tdtail; 622 623 for (;;) { 624 if (sc->sc_rb.rb_td_nbusy <= 0) 625 break; 626 627 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 628 629 if (txflags & QEC_XD_OWN) 630 break; 631 632 ifp->if_flags &= ~IFF_OACTIVE; 633 ifp->if_opackets++; 634 635 if (++bix == QEC_XD_RING_MAXSIZE) 636 bix = 0; 637 638 --sc->sc_rb.rb_td_nbusy; 639 } 640 641 sc->sc_rb.rb_tdtail = bix; 642 643 qestart(ifp); 644 645 if (sc->sc_rb.rb_td_nbusy == 0) 646 ifp->if_timer = 0; 647 648 return (1); 649 } 650 651 /* 652 * Receive interrupt. 653 */ 654 int 655 qe_rint(struct qe_softc *sc) 656 { 657 struct qec_xd *xd = sc->sc_rb.rb_rxd; 658 unsigned int bix, len; 659 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 660 #ifdef QEDEBUG 661 int npackets = 0; 662 #endif 663 664 bix = sc->sc_rb.rb_rdtail; 665 666 /* 667 * Process all buffers with valid data. 668 */ 669 for (;;) { 670 len = xd[bix].xd_flags; 671 if (len & QEC_XD_OWN) 672 break; 673 674 #ifdef QEDEBUG 675 npackets++; 676 #endif 677 678 len &= QEC_XD_LENGTH; 679 len -= 4; 680 qe_read(sc, bix, len); 681 682 /* ... */ 683 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 684 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 685 686 if (++bix == QEC_XD_RING_MAXSIZE) 687 bix = 0; 688 } 689 #ifdef QEDEBUG 690 if (npackets == 0 && sc->sc_debug) 691 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 692 device_xname(sc->sc_dev), bix, len); 693 #endif 694 695 sc->sc_rb.rb_rdtail = bix; 696 697 return (1); 698 } 699 700 /* 701 * Error interrupt. 702 */ 703 int 704 qe_eint(struct qe_softc *sc, uint32_t why) 705 { 706 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 707 device_t self = sc->sc_dev; 708 const char *xname = device_xname(self); 709 int r = 0, rst = 0; 710 711 if (why & QE_CR_STAT_EDEFER) { 712 printf("%s: excessive tx defers.\n", xname); 713 r |= 1; 714 ifp->if_oerrors++; 715 } 716 717 if (why & QE_CR_STAT_CLOSS) { 718 printf("%s: no carrier, link down?\n", xname); 719 ifp->if_oerrors++; 720 r |= 1; 721 } 722 723 if (why & QE_CR_STAT_ERETRIES) { 724 printf("%s: excessive tx retries\n", xname); 725 ifp->if_oerrors++; 726 r |= 1; 727 rst = 1; 728 } 729 730 731 if (why & QE_CR_STAT_LCOLL) { 732 printf("%s: late tx transmission\n", xname); 733 ifp->if_oerrors++; 734 r |= 1; 735 rst = 1; 736 } 737 738 if (why & QE_CR_STAT_FUFLOW) { 739 printf("%s: tx fifo underflow\n", xname); 740 ifp->if_oerrors++; 741 r |= 1; 742 rst = 1; 743 } 744 745 if (why & QE_CR_STAT_JERROR) { 746 printf("%s: jabber seen\n", xname); 747 r |= 1; 748 } 749 750 if (why & QE_CR_STAT_BERROR) { 751 printf("%s: babble seen\n", xname); 752 r |= 1; 753 } 754 755 if (why & QE_CR_STAT_TCCOFLOW) { 756 ifp->if_collisions += 256; 757 ifp->if_oerrors += 256; 758 r |= 1; 759 } 760 761 if (why & QE_CR_STAT_TXDERROR) { 762 printf("%s: tx descriptor is bad\n", xname); 763 rst = 1; 764 r |= 1; 765 } 766 767 if (why & QE_CR_STAT_TXLERR) { 768 printf("%s: tx late error\n", xname); 769 ifp->if_oerrors++; 770 rst = 1; 771 r |= 1; 772 } 773 774 if (why & QE_CR_STAT_TXPERR) { 775 printf("%s: tx DMA parity error\n", xname); 776 ifp->if_oerrors++; 777 rst = 1; 778 r |= 1; 779 } 780 781 if (why & QE_CR_STAT_TXSERR) { 782 printf("%s: tx DMA sbus error ack\n", xname); 783 ifp->if_oerrors++; 784 rst = 1; 785 r |= 1; 786 } 787 788 if (why & QE_CR_STAT_RCCOFLOW) { 789 ifp->if_collisions += 256; 790 ifp->if_ierrors += 256; 791 r |= 1; 792 } 793 794 if (why & QE_CR_STAT_RUOFLOW) { 795 ifp->if_ierrors += 256; 796 r |= 1; 797 } 798 799 if (why & QE_CR_STAT_MCOFLOW) { 800 ifp->if_ierrors += 256; 801 r |= 1; 802 } 803 804 if (why & QE_CR_STAT_RXFOFLOW) { 805 printf("%s: rx fifo overflow\n", xname); 806 ifp->if_ierrors++; 807 r |= 1; 808 } 809 810 if (why & QE_CR_STAT_RLCOLL) { 811 printf("%s: rx late collision\n", xname); 812 ifp->if_ierrors++; 813 ifp->if_collisions++; 814 r |= 1; 815 } 816 817 if (why & QE_CR_STAT_FCOFLOW) { 818 ifp->if_ierrors += 256; 819 r |= 1; 820 } 821 822 if (why & QE_CR_STAT_CECOFLOW) { 823 ifp->if_ierrors += 256; 824 r |= 1; 825 } 826 827 if (why & QE_CR_STAT_RXDROP) { 828 printf("%s: rx packet dropped\n", xname); 829 ifp->if_ierrors++; 830 r |= 1; 831 } 832 833 if (why & QE_CR_STAT_RXSMALL) { 834 printf("%s: rx buffer too small\n", xname); 835 ifp->if_ierrors++; 836 r |= 1; 837 rst = 1; 838 } 839 840 if (why & QE_CR_STAT_RXLERR) { 841 printf("%s: rx late error\n", xname); 842 ifp->if_ierrors++; 843 r |= 1; 844 rst = 1; 845 } 846 847 if (why & QE_CR_STAT_RXPERR) { 848 printf("%s: rx DMA parity error\n", xname); 849 ifp->if_ierrors++; 850 r |= 1; 851 rst = 1; 852 } 853 854 if (why & QE_CR_STAT_RXSERR) { 855 printf("%s: rx DMA sbus error ack\n", xname); 856 ifp->if_ierrors++; 857 r |= 1; 858 rst = 1; 859 } 860 861 if (r == 0) 862 aprint_error_dev(self, "unexpected interrupt error: %08x\n", 863 why); 864 865 if (rst) { 866 printf("%s: resetting...\n", xname); 867 qereset(sc); 868 return (-1); 869 } 870 871 return (r); 872 } 873 874 int 875 qeioctl(struct ifnet *ifp, u_long cmd, void *data) 876 { 877 struct qe_softc *sc = ifp->if_softc; 878 struct ifaddr *ifa = data; 879 struct ifreq *ifr = data; 880 int s, error = 0; 881 882 s = splnet(); 883 884 switch (cmd) { 885 case SIOCINITIFADDR: 886 ifp->if_flags |= IFF_UP; 887 qeinit(sc); 888 switch (ifa->ifa_addr->sa_family) { 889 #ifdef INET 890 case AF_INET: 891 arp_ifinit(ifp, ifa); 892 break; 893 #endif /* INET */ 894 default: 895 break; 896 } 897 break; 898 899 case SIOCSIFFLAGS: 900 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 901 break; 902 /* XXX re-use ether_ioctl() */ 903 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 904 case IFF_RUNNING: 905 /* 906 * If interface is marked down and it is running, then 907 * stop it. 908 */ 909 qestop(sc); 910 ifp->if_flags &= ~IFF_RUNNING; 911 break; 912 case IFF_UP: 913 /* 914 * If interface is marked up and it is stopped, then 915 * start it. 916 */ 917 qeinit(sc); 918 break; 919 default: 920 /* 921 * Reset the interface to pick up changes in any other 922 * flags that affect hardware registers. 923 */ 924 qestop(sc); 925 qeinit(sc); 926 break; 927 } 928 #ifdef QEDEBUG 929 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 930 #endif 931 break; 932 933 case SIOCADDMULTI: 934 case SIOCDELMULTI: 935 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 936 /* 937 * Multicast list has changed; set the hardware filter 938 * accordingly. 939 */ 940 if (ifp->if_flags & IFF_RUNNING) 941 qe_mcreset(sc); 942 error = 0; 943 } 944 break; 945 946 case SIOCGIFMEDIA: 947 case SIOCSIFMEDIA: 948 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 949 break; 950 951 default: 952 error = ether_ioctl(ifp, cmd, data); 953 break; 954 } 955 956 splx(s); 957 return (error); 958 } 959 960 961 void 962 qeinit(struct qe_softc *sc) 963 { 964 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 965 bus_space_tag_t t = sc->sc_bustag; 966 bus_space_handle_t cr = sc->sc_cr; 967 bus_space_handle_t mr = sc->sc_mr; 968 struct qec_softc *qec = sc->sc_qec; 969 uint32_t qecaddr; 970 uint8_t *ea; 971 int s; 972 973 #if defined(SUN4U) || defined(__GNUC__) 974 (void)&t; 975 #endif 976 s = splnet(); 977 978 qestop(sc); 979 980 /* 981 * Allocate descriptor ring and buffers 982 */ 983 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 984 985 /* Channel registers: */ 986 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 987 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 988 989 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 990 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 991 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 992 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 993 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 994 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 995 996 qecaddr = sc->sc_channel * qec->sc_msize; 997 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 998 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 999 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1000 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1001 1002 /* MACE registers: */ 1003 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1004 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1005 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1006 1007 /* 1008 * Mask MACE's receive interrupt, since we're being notified 1009 * by the QEC after DMA completes. 1010 */ 1011 bus_space_write_1(t, mr, QE_MRI_IMR, 1012 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1013 1014 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1015 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1016 1017 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1018 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1019 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1020 1021 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1022 1023 /* 1024 * Station address 1025 */ 1026 ea = sc->sc_enaddr; 1027 bus_space_write_1(t, mr, QE_MRI_IAC, 1028 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1029 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1030 1031 /* Apply media settings */ 1032 qe_ifmedia_upd(ifp); 1033 1034 /* 1035 * Clear Logical address filter 1036 */ 1037 bus_space_write_1(t, mr, QE_MRI_IAC, 1038 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1039 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1040 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1041 1042 /* Clear missed packet count (register cleared on read) */ 1043 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1044 1045 #if 0 1046 /* test register: */ 1047 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1048 #endif 1049 1050 /* Reset multicast filter */ 1051 qe_mcreset(sc); 1052 1053 ifp->if_flags |= IFF_RUNNING; 1054 ifp->if_flags &= ~IFF_OACTIVE; 1055 splx(s); 1056 } 1057 1058 /* 1059 * Reset multicast filter. 1060 */ 1061 void 1062 qe_mcreset(struct qe_softc *sc) 1063 { 1064 struct ethercom *ec = &sc->sc_ethercom; 1065 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1066 bus_space_tag_t t = sc->sc_bustag; 1067 bus_space_handle_t mr = sc->sc_mr; 1068 struct ether_multi *enm; 1069 struct ether_multistep step; 1070 uint32_t crc; 1071 uint16_t hash[4]; 1072 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; 1073 int i; 1074 1075 #if defined(SUN4U) || defined(__GNUC__) 1076 (void)&t; 1077 #endif 1078 1079 /* We also enable transmitter & receiver here */ 1080 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1081 1082 if (ifp->if_flags & IFF_PROMISC) { 1083 maccc |= QE_MR_MACCC_PROM; 1084 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1085 return; 1086 } 1087 1088 if (ifp->if_flags & IFF_ALLMULTI) { 1089 bus_space_write_1(t, mr, QE_MRI_IAC, 1090 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1091 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1092 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1093 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1094 return; 1095 } 1096 1097 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1098 1099 ETHER_FIRST_MULTI(step, ec, enm); 1100 while (enm != NULL) { 1101 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1102 ETHER_ADDR_LEN) != 0) { 1103 /* 1104 * We must listen to a range of multicast 1105 * addresses. For now, just accept all 1106 * multicasts, rather than trying to set only 1107 * those filter bits needed to match the range. 1108 * (At this time, the only use of address 1109 * ranges is for IP multicast routing, for 1110 * which the range is big enough to require 1111 * all bits set.) 1112 */ 1113 bus_space_write_1(t, mr, QE_MRI_IAC, 1114 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1115 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1116 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1117 ifp->if_flags |= IFF_ALLMULTI; 1118 break; 1119 } 1120 1121 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1122 crc >>= 26; 1123 hash[crc >> 4] |= 1 << (crc & 0xf); 1124 ETHER_NEXT_MULTI(step, enm); 1125 } 1126 1127 /* We need to byte-swap the hash before writing to the chip. */ 1128 for (i = 0; i < 7; i += 2) { 1129 octet = ladrp[i]; 1130 ladrp[i] = ladrp[i + 1]; 1131 ladrp[i + 1] = octet; 1132 } 1133 bus_space_write_1(t, mr, QE_MRI_IAC, 1134 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1135 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1136 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1137 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1138 } 1139 1140 /* 1141 * Get current media settings. 1142 */ 1143 void 1144 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1145 { 1146 struct qe_softc *sc = ifp->if_softc; 1147 bus_space_tag_t t = sc->sc_bustag; 1148 bus_space_handle_t mr = sc->sc_mr; 1149 uint8_t v; 1150 1151 #if defined(SUN4U) || defined(__GNUC__) 1152 (void)&t; 1153 #endif 1154 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1155 1156 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1157 case QE_MR_PLSCC_TP: 1158 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1159 break; 1160 case QE_MR_PLSCC_AUI: 1161 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1162 break; 1163 case QE_MR_PLSCC_GPSI: 1164 case QE_MR_PLSCC_DAI: 1165 /* ... */ 1166 break; 1167 } 1168 1169 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1170 ifmr->ifm_status |= IFM_AVALID; 1171 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1172 ifmr->ifm_status &= ~IFM_ACTIVE; 1173 else 1174 ifmr->ifm_status |= IFM_ACTIVE; 1175 1176 } 1177 1178 /* 1179 * Set media options. 1180 */ 1181 int 1182 qe_ifmedia_upd(struct ifnet *ifp) 1183 { 1184 struct qe_softc *sc = ifp->if_softc; 1185 struct ifmedia *ifm = &sc->sc_ifmedia; 1186 bus_space_tag_t t = sc->sc_bustag; 1187 bus_space_handle_t mr = sc->sc_mr; 1188 int newmedia = ifm->ifm_media; 1189 uint8_t plscc, phycc; 1190 1191 #if defined(SUN4U) || defined(__GNUC__) 1192 (void)&t; 1193 #endif 1194 if (IFM_TYPE(newmedia) != IFM_ETHER) 1195 return (EINVAL); 1196 1197 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1198 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1199 1200 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1201 phycc |= QE_MR_PHYCC_ASEL; 1202 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1203 plscc |= QE_MR_PLSCC_TP; 1204 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1205 plscc |= QE_MR_PLSCC_AUI; 1206 1207 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1208 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1209 1210 return (0); 1211 } 1212