xref: /netbsd-src/sys/dev/sbus/qe.c (revision 6a493d6bc668897c91594964a732d38505b70cbb)
1 /*	$NetBSD: qe.c,v 1.62 2012/06/23 17:21:12 jdc Exp $	*/
2 
3 /*-
4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Paul Kranenburg.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Copyright (c) 1998 Jason L. Wright.
34  * All rights reserved.
35  *
36  * Redistribution and use in source and binary forms, with or without
37  * modification, are permitted provided that the following conditions
38  * are met:
39  * 1. Redistributions of source code must retain the above copyright
40  *    notice, this list of conditions and the following disclaimer.
41  * 2. Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in the
43  *    documentation and/or other materials provided with the distribution.
44  * 3. The name of the authors may not be used to endorse or promote products
45  *    derived from this software without specific prior written permission.
46  *
47  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
48  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
51  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57  */
58 
59 /*
60  * Driver for the SBus qec+qe QuadEthernet board.
61  *
62  * This driver was written using the AMD MACE Am79C940 documentation, some
63  * ideas gleaned from the S/Linux driver for this card, Solaris header files,
64  * and a loan of a card from Paul Southworth of the Internet Engineering
65  * Group (www.ieng.com).
66  */
67 
68 #include <sys/cdefs.h>
69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.62 2012/06/23 17:21:12 jdc Exp $");
70 
71 #define QEDEBUG
72 
73 #include "opt_ddb.h"
74 #include "opt_inet.h"
75 
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/kernel.h>
79 #include <sys/errno.h>
80 #include <sys/ioctl.h>
81 #include <sys/mbuf.h>
82 #include <sys/socket.h>
83 #include <sys/syslog.h>
84 #include <sys/device.h>
85 #include <sys/malloc.h>
86 #include <sys/rnd.h>
87 
88 #include <net/if.h>
89 #include <net/if_dl.h>
90 #include <net/if_types.h>
91 #include <net/netisr.h>
92 #include <net/if_media.h>
93 #include <net/if_ether.h>
94 
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/if_inarp.h>
98 #include <netinet/in_systm.h>
99 #include <netinet/in_var.h>
100 #include <netinet/ip.h>
101 #endif
102 
103 
104 #include <net/bpf.h>
105 #include <net/bpfdesc.h>
106 
107 #include <sys/bus.h>
108 #include <sys/intr.h>
109 #include <machine/autoconf.h>
110 
111 #include <dev/sbus/sbusvar.h>
112 #include <dev/sbus/qecreg.h>
113 #include <dev/sbus/qecvar.h>
114 #include <dev/sbus/qereg.h>
115 
116 struct qe_softc {
117 	device_t	sc_dev;
118 	bus_space_tag_t	sc_bustag;	/* bus & DMA tags */
119 	bus_dma_tag_t	sc_dmatag;
120 	bus_dmamap_t	sc_dmamap;
121 	struct	ethercom sc_ethercom;
122 	struct	ifmedia sc_ifmedia;	/* interface media */
123 
124 	struct	qec_softc *sc_qec;	/* QEC parent */
125 
126 	bus_space_handle_t	sc_qr;	/* QEC registers */
127 	bus_space_handle_t	sc_mr;	/* MACE registers */
128 	bus_space_handle_t	sc_cr;	/* channel registers */
129 
130 	int	sc_channel;		/* channel number */
131 	u_int	sc_rev;			/* board revision */
132 
133 	int	sc_burst;
134 
135 	struct  qec_ring	sc_rb;	/* Packet Ring Buffer */
136 
137 	/* MAC address */
138 	uint8_t sc_enaddr[6];
139 
140 #ifdef QEDEBUG
141 	int	sc_debug;
142 #endif
143 };
144 
145 int	qematch(device_t, cfdata_t, void *);
146 void	qeattach(device_t, device_t, void *);
147 
148 void	qeinit(struct qe_softc *);
149 void	qestart(struct ifnet *);
150 void	qestop(struct qe_softc *);
151 void	qewatchdog(struct ifnet *);
152 int	qeioctl(struct ifnet *, u_long, void *);
153 void	qereset(struct qe_softc *);
154 
155 int	qeintr(void *);
156 int	qe_eint(struct qe_softc *, uint32_t);
157 int	qe_rint(struct qe_softc *);
158 int	qe_tint(struct qe_softc *);
159 void	qe_mcreset(struct qe_softc *);
160 
161 static int	qe_put(struct qe_softc *, int, struct mbuf *);
162 static void	qe_read(struct qe_softc *, int, int);
163 static struct mbuf	*qe_get(struct qe_softc *, int, int);
164 
165 /* ifmedia callbacks */
166 void	qe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
167 int	qe_ifmedia_upd(struct ifnet *);
168 
169 CFATTACH_DECL_NEW(qe, sizeof(struct qe_softc),
170     qematch, qeattach, NULL, NULL);
171 
172 int
173 qematch(device_t parent, cfdata_t cf, void *aux)
174 {
175 	struct sbus_attach_args *sa = aux;
176 
177 	return (strcmp(cf->cf_name, sa->sa_name) == 0);
178 }
179 
180 void
181 qeattach(device_t parent, device_t self, void *aux)
182 {
183 	struct sbus_attach_args *sa = aux;
184 	struct qec_softc *qec = device_private(parent);
185 	struct qe_softc *sc = device_private(self);
186 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
187 	int node = sa->sa_node;
188 	bus_dma_tag_t dmatag = sa->sa_dmatag;
189 	bus_dma_segment_t seg;
190 	bus_size_t size;
191 	int rseg, error;
192 
193 	sc->sc_dev = self;
194 
195 	if (sa->sa_nreg < 2) {
196 		printf("%s: only %d register sets\n",
197 			device_xname(self), sa->sa_nreg);
198 		return;
199 	}
200 
201 	if (bus_space_map(sa->sa_bustag,
202 			  (bus_addr_t)BUS_ADDR(
203 				sa->sa_reg[0].oa_space,
204 				sa->sa_reg[0].oa_base),
205 			  (bus_size_t)sa->sa_reg[0].oa_size,
206 			  0, &sc->sc_cr) != 0) {
207 		aprint_error_dev(self, "cannot map registers\n");
208 		return;
209 	}
210 
211 	if (bus_space_map(sa->sa_bustag,
212 			  (bus_addr_t)BUS_ADDR(
213 				sa->sa_reg[1].oa_space,
214 				sa->sa_reg[1].oa_base),
215 			  (bus_size_t)sa->sa_reg[1].oa_size,
216 			  0, &sc->sc_mr) != 0) {
217 		aprint_error_dev(self, "cannot map registers\n");
218 		return;
219 	}
220 
221 	sc->sc_rev = prom_getpropint(node, "mace-version", -1);
222 	printf(" rev %x", sc->sc_rev);
223 
224 	sc->sc_bustag = sa->sa_bustag;
225 	sc->sc_dmatag = sa->sa_dmatag;
226 	sc->sc_qec = qec;
227 	sc->sc_qr = qec->sc_regs;
228 
229 	sc->sc_channel = prom_getpropint(node, "channel#", -1);
230 	sc->sc_burst = qec->sc_burst;
231 
232 	qestop(sc);
233 
234 	/* Note: no interrupt level passed */
235 	(void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc);
236 	prom_getether(node, sc->sc_enaddr);
237 
238 	/*
239 	 * Allocate descriptor ring and buffers.
240 	 */
241 
242 	/* for now, allocate as many bufs as there are ring descriptors */
243 	sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
244 	sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
245 
246 	size =	QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
247 		QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
248 		sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ +
249 		sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ;
250 
251 	/* Get a DMA handle */
252 	if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
253 				    BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
254 		aprint_error_dev(self, "DMA map create error %d\n",
255 			error);
256 		return;
257 	}
258 
259 	/* Allocate DMA buffer */
260 	if ((error = bus_dmamem_alloc(dmatag, size, 0, 0,
261 				      &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
262 		aprint_error_dev(self, "DMA buffer alloc error %d\n",
263 			error);
264 		return;
265 	}
266 
267 	/* Map DMA buffer in CPU addressable space */
268 	if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
269 			            &sc->sc_rb.rb_membase,
270 			            BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
271 		aprint_error_dev(self, "DMA buffer map error %d\n",
272 			error);
273 		bus_dmamem_free(dmatag, &seg, rseg);
274 		return;
275 	}
276 
277 	/* Load the buffer */
278 	if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
279 				     sc->sc_rb.rb_membase, size, NULL,
280 				     BUS_DMA_NOWAIT)) != 0) {
281 		aprint_error_dev(self, "DMA buffer map load error %d\n",
282 			error);
283 		bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
284 		bus_dmamem_free(dmatag, &seg, rseg);
285 		return;
286 	}
287 	sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
288 
289 	/* Initialize media properties */
290 	ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts);
291 	ifmedia_add(&sc->sc_ifmedia,
292 		    IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0),
293 		    0, NULL);
294 	ifmedia_add(&sc->sc_ifmedia,
295 		    IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0),
296 		    0, NULL);
297 	ifmedia_add(&sc->sc_ifmedia,
298 		    IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0),
299 		    0, NULL);
300 	ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
301 
302 	memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
303 	ifp->if_softc = sc;
304 	ifp->if_start = qestart;
305 	ifp->if_ioctl = qeioctl;
306 	ifp->if_watchdog = qewatchdog;
307 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS |
308 	    IFF_MULTICAST;
309 	IFQ_SET_READY(&ifp->if_snd);
310 
311 	/* Attach the interface. */
312 	if_attach(ifp);
313 	ether_ifattach(ifp, sc->sc_enaddr);
314 
315 	printf(" address %s\n", ether_sprintf(sc->sc_enaddr));
316 }
317 
318 /*
319  * Pull data off an interface.
320  * Len is the length of data, with local net header stripped.
321  * We copy the data into mbufs.  When full cluster sized units are present,
322  * we copy into clusters.
323  */
324 static inline struct mbuf *
325 qe_get(struct qe_softc *sc, int idx, int totlen)
326 {
327 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
328 	struct mbuf *m;
329 	struct mbuf *top, **mp;
330 	int len, pad, boff = 0;
331 	uint8_t *bp;
332 
333 	bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ;
334 
335 	MGETHDR(m, M_DONTWAIT, MT_DATA);
336 	if (m == NULL)
337 		return (NULL);
338 	m->m_pkthdr.rcvif = ifp;
339 	m->m_pkthdr.len = totlen;
340 	pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
341 	m->m_data += pad;
342 	len = MHLEN - pad;
343 	top = NULL;
344 	mp = &top;
345 
346 	while (totlen > 0) {
347 		if (top) {
348 			MGET(m, M_DONTWAIT, MT_DATA);
349 			if (m == NULL) {
350 				m_freem(top);
351 				return (NULL);
352 			}
353 			len = MLEN;
354 		}
355 		if (top && totlen >= MINCLSIZE) {
356 			MCLGET(m, M_DONTWAIT);
357 			if (m->m_flags & M_EXT)
358 				len = MCLBYTES;
359 		}
360 		m->m_len = len = min(totlen, len);
361 		memcpy(mtod(m, void *), bp + boff, len);
362 		boff += len;
363 		totlen -= len;
364 		*mp = m;
365 		mp = &m->m_next;
366 	}
367 
368 	return (top);
369 }
370 
371 /*
372  * Routine to copy from mbuf chain to transmit buffer in
373  * network buffer memory.
374  */
375 inline int
376 qe_put(struct qe_softc *sc, int idx, struct mbuf *m)
377 {
378 	struct mbuf *n;
379 	int len, tlen = 0, boff = 0;
380 	uint8_t *bp;
381 
382 	bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ;
383 
384 	for (; m; m = n) {
385 		len = m->m_len;
386 		if (len == 0) {
387 			MFREE(m, n);
388 			continue;
389 		}
390 		memcpy(bp + boff, mtod(m, void *), len);
391 		boff += len;
392 		tlen += len;
393 		MFREE(m, n);
394 	}
395 	return (tlen);
396 }
397 
398 /*
399  * Pass a packet to the higher levels.
400  */
401 inline void
402 qe_read(struct qe_softc *sc, int idx, int len)
403 {
404 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
405 	struct mbuf *m;
406 
407 	if (len <= sizeof(struct ether_header) ||
408 	    len > ETHERMTU + sizeof(struct ether_header)) {
409 
410 		printf("%s: invalid packet size %d; dropping\n",
411 			ifp->if_xname, len);
412 
413 		ifp->if_ierrors++;
414 		return;
415 	}
416 
417 	/*
418 	 * Pull packet off interface.
419 	 */
420 	m = qe_get(sc, idx, len);
421 	if (m == NULL) {
422 		ifp->if_ierrors++;
423 		return;
424 	}
425 	ifp->if_ipackets++;
426 
427 	/*
428 	 * Check if there's a BPF listener on this interface.
429 	 * If so, hand off the raw packet to BPF.
430 	 */
431 	bpf_mtap(ifp, m);
432 	/* Pass the packet up. */
433 	(*ifp->if_input)(ifp, m);
434 }
435 
436 /*
437  * Start output on interface.
438  * We make two assumptions here:
439  *  1) that the current priority is set to splnet _before_ this code
440  *     is called *and* is returned to the appropriate priority after
441  *     return
442  *  2) that the IFF_OACTIVE flag is checked before this code is called
443  *     (i.e. that the output part of the interface is idle)
444  */
445 void
446 qestart(struct ifnet *ifp)
447 {
448 	struct qe_softc *sc = ifp->if_softc;
449 	struct qec_xd *txd = sc->sc_rb.rb_txd;
450 	struct mbuf *m;
451 	unsigned int bix, len;
452 	unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
453 
454 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
455 		return;
456 
457 	bix = sc->sc_rb.rb_tdhead;
458 
459 	for (;;) {
460 		IFQ_DEQUEUE(&ifp->if_snd, m);
461 		if (m == 0)
462 			break;
463 
464 		/*
465 		 * If BPF is listening on this interface, let it see the
466 		 * packet before we commit it to the wire.
467 		 */
468 		bpf_mtap(ifp, m);
469 
470 		/*
471 		 * Copy the mbuf chain into the transmit buffer.
472 		 */
473 		len = qe_put(sc, bix, m);
474 
475 		/*
476 		 * Initialize transmit registers and start transmission
477 		 */
478 		txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
479 				    (len & QEC_XD_LENGTH);
480 		bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL,
481 				  QE_CR_CTRL_TWAKEUP);
482 
483 		if (++bix == QEC_XD_RING_MAXSIZE)
484 			bix = 0;
485 
486 		if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
487 			ifp->if_flags |= IFF_OACTIVE;
488 			break;
489 		}
490 	}
491 
492 	sc->sc_rb.rb_tdhead = bix;
493 }
494 
495 void
496 qestop(struct qe_softc *sc)
497 {
498 	bus_space_tag_t t = sc->sc_bustag;
499 	bus_space_handle_t mr = sc->sc_mr;
500 	bus_space_handle_t cr = sc->sc_cr;
501 	int n;
502 
503 #if defined(SUN4U) || defined(__GNUC__)
504 	(void)&t;
505 #endif
506 	/* Stop the schwurst */
507 	bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST);
508 	for (n = 200; n > 0; n--) {
509 		if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) &
510 			QE_MR_BIUCC_SWRST) == 0)
511 			break;
512 		DELAY(20);
513 	}
514 
515 	/* then reset */
516 	bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET);
517 	for (n = 200; n > 0; n--) {
518 		if ((bus_space_read_4(t, cr, QE_CRI_CTRL) &
519 			QE_CR_CTRL_RESET) == 0)
520 			break;
521 		DELAY(20);
522 	}
523 }
524 
525 /*
526  * Reset interface.
527  */
528 void
529 qereset(struct qe_softc *sc)
530 {
531 	int s;
532 
533 	s = splnet();
534 	qestop(sc);
535 	qeinit(sc);
536 	splx(s);
537 }
538 
539 void
540 qewatchdog(struct ifnet *ifp)
541 {
542 	struct qe_softc *sc = ifp->if_softc;
543 
544 	log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
545 	ifp->if_oerrors++;
546 
547 	qereset(sc);
548 }
549 
550 /*
551  * Interrupt dispatch.
552  */
553 int
554 qeintr(void *arg)
555 {
556 	struct qe_softc *sc = arg;
557 	bus_space_tag_t t = sc->sc_bustag;
558 	uint32_t qecstat, qestat;
559 	int r = 0;
560 
561 #if defined(SUN4U) || defined(__GNUC__)
562 	(void)&t;
563 #endif
564 	/* Read QEC status and channel status */
565 	qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
566 #ifdef QEDEBUG
567 	if (sc->sc_debug) {
568 		printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat);
569 	}
570 #endif
571 
572 	/* Filter out status for this channel */
573 	qecstat = qecstat >> (4 * sc->sc_channel);
574 	if ((qecstat & 0xf) == 0)
575 		return (r);
576 
577 	qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT);
578 
579 #ifdef QEDEBUG
580 	if (sc->sc_debug) {
581 		char bits[64]; int i;
582 		bus_space_tag_t t1 = sc->sc_bustag;
583 		bus_space_handle_t mr = sc->sc_mr;
584 
585 		snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat);
586 		printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits);
587 
588 		printf("MACE registers:\n");
589 		for (i = 0 ; i < 32; i++) {
590 			printf("  m[%d]=%x,", i, bus_space_read_1(t1, mr, i));
591 			if (((i+1) & 7) == 0)
592 				printf("\n");
593 		}
594 	}
595 #endif
596 
597 	if (qestat & QE_CR_STAT_ALLERRORS) {
598 #ifdef QEDEBUG
599 		if (sc->sc_debug) {
600 			char bits[64];
601 			snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat);
602 			printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits);
603 		}
604 #endif
605 		r |= qe_eint(sc, qestat);
606 		if (r == -1)
607 			return (1);
608 	}
609 
610 	if (qestat & QE_CR_STAT_TXIRQ)
611 		r |= qe_tint(sc);
612 
613 	if (qestat & QE_CR_STAT_RXIRQ)
614 		r |= qe_rint(sc);
615 
616 	return (r);
617 }
618 
619 /*
620  * Transmit interrupt.
621  */
622 int
623 qe_tint(struct qe_softc *sc)
624 {
625 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
626 	unsigned int bix, txflags;
627 
628 	bix = sc->sc_rb.rb_tdtail;
629 
630 	for (;;) {
631 		if (sc->sc_rb.rb_td_nbusy <= 0)
632 			break;
633 
634 		txflags = sc->sc_rb.rb_txd[bix].xd_flags;
635 
636 		if (txflags & QEC_XD_OWN)
637 			break;
638 
639 		ifp->if_flags &= ~IFF_OACTIVE;
640 		ifp->if_opackets++;
641 
642 		if (++bix == QEC_XD_RING_MAXSIZE)
643 			bix = 0;
644 
645 		--sc->sc_rb.rb_td_nbusy;
646 	}
647 
648 	sc->sc_rb.rb_tdtail = bix;
649 
650 	qestart(ifp);
651 
652 	if (sc->sc_rb.rb_td_nbusy == 0)
653 		ifp->if_timer = 0;
654 
655 	return (1);
656 }
657 
658 /*
659  * Receive interrupt.
660  */
661 int
662 qe_rint(struct qe_softc *sc)
663 {
664 	struct qec_xd *xd = sc->sc_rb.rb_rxd;
665 	unsigned int bix, len;
666 	unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
667 #ifdef QEDEBUG
668 	int npackets = 0;
669 #endif
670 
671 	bix = sc->sc_rb.rb_rdtail;
672 
673 	/*
674 	 * Process all buffers with valid data.
675 	 */
676 	for (;;) {
677 		len = xd[bix].xd_flags;
678 		if (len & QEC_XD_OWN)
679 			break;
680 
681 #ifdef QEDEBUG
682 		npackets++;
683 #endif
684 
685 		len &= QEC_XD_LENGTH;
686 		len -= 4;
687 		qe_read(sc, bix, len);
688 
689 		/* ... */
690 		xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
691 			QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH);
692 
693 		if (++bix == QEC_XD_RING_MAXSIZE)
694 			bix = 0;
695 	}
696 #ifdef QEDEBUG
697 	if (npackets == 0 && sc->sc_debug)
698 		printf("%s: rint: no packets; rb index %d; status 0x%x\n",
699 			device_xname(sc->sc_dev), bix, len);
700 #endif
701 
702 	sc->sc_rb.rb_rdtail = bix;
703 
704 	return (1);
705 }
706 
707 /*
708  * Error interrupt.
709  */
710 int
711 qe_eint(struct qe_softc *sc, uint32_t why)
712 {
713 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
714 	device_t self = sc->sc_dev;
715 	const char *xname = device_xname(self);
716 	int r = 0, rst = 0;
717 
718 	if (why & QE_CR_STAT_EDEFER) {
719 		printf("%s: excessive tx defers.\n", xname);
720 		r |= 1;
721 		ifp->if_oerrors++;
722 	}
723 
724 	if (why & QE_CR_STAT_CLOSS) {
725 		printf("%s: no carrier, link down?\n", xname);
726 		ifp->if_oerrors++;
727 		r |= 1;
728 	}
729 
730 	if (why & QE_CR_STAT_ERETRIES) {
731 		printf("%s: excessive tx retries\n", xname);
732 		ifp->if_oerrors++;
733 		r |= 1;
734 		rst = 1;
735 	}
736 
737 
738 	if (why & QE_CR_STAT_LCOLL) {
739 		printf("%s: late tx transmission\n", xname);
740 		ifp->if_oerrors++;
741 		r |= 1;
742 		rst = 1;
743 	}
744 
745 	if (why & QE_CR_STAT_FUFLOW) {
746 		printf("%s: tx fifo underflow\n", xname);
747 		ifp->if_oerrors++;
748 		r |= 1;
749 		rst = 1;
750 	}
751 
752 	if (why & QE_CR_STAT_JERROR) {
753 		printf("%s: jabber seen\n", xname);
754 		r |= 1;
755 	}
756 
757 	if (why & QE_CR_STAT_BERROR) {
758 		printf("%s: babble seen\n", xname);
759 		r |= 1;
760 	}
761 
762 	if (why & QE_CR_STAT_TCCOFLOW) {
763 		ifp->if_collisions += 256;
764 		ifp->if_oerrors += 256;
765 		r |= 1;
766 	}
767 
768 	if (why & QE_CR_STAT_TXDERROR) {
769 		printf("%s: tx descriptor is bad\n", xname);
770 		rst = 1;
771 		r |= 1;
772 	}
773 
774 	if (why & QE_CR_STAT_TXLERR) {
775 		printf("%s: tx late error\n", xname);
776 		ifp->if_oerrors++;
777 		rst = 1;
778 		r |= 1;
779 	}
780 
781 	if (why & QE_CR_STAT_TXPERR) {
782 		printf("%s: tx DMA parity error\n", xname);
783 		ifp->if_oerrors++;
784 		rst = 1;
785 		r |= 1;
786 	}
787 
788 	if (why & QE_CR_STAT_TXSERR) {
789 		printf("%s: tx DMA sbus error ack\n", xname);
790 		ifp->if_oerrors++;
791 		rst = 1;
792 		r |= 1;
793 	}
794 
795 	if (why & QE_CR_STAT_RCCOFLOW) {
796 		ifp->if_collisions += 256;
797 		ifp->if_ierrors += 256;
798 		r |= 1;
799 	}
800 
801 	if (why & QE_CR_STAT_RUOFLOW) {
802 		ifp->if_ierrors += 256;
803 		r |= 1;
804 	}
805 
806 	if (why & QE_CR_STAT_MCOFLOW) {
807 		ifp->if_ierrors += 256;
808 		r |= 1;
809 	}
810 
811 	if (why & QE_CR_STAT_RXFOFLOW) {
812 		printf("%s: rx fifo overflow\n", xname);
813 		ifp->if_ierrors++;
814 		r |= 1;
815 	}
816 
817 	if (why & QE_CR_STAT_RLCOLL) {
818 		printf("%s: rx late collision\n", xname);
819 		ifp->if_ierrors++;
820 		ifp->if_collisions++;
821 		r |= 1;
822 	}
823 
824 	if (why & QE_CR_STAT_FCOFLOW) {
825 		ifp->if_ierrors += 256;
826 		r |= 1;
827 	}
828 
829 	if (why & QE_CR_STAT_CECOFLOW) {
830 		ifp->if_ierrors += 256;
831 		r |= 1;
832 	}
833 
834 	if (why & QE_CR_STAT_RXDROP) {
835 		printf("%s: rx packet dropped\n", xname);
836 		ifp->if_ierrors++;
837 		r |= 1;
838 	}
839 
840 	if (why & QE_CR_STAT_RXSMALL) {
841 		printf("%s: rx buffer too small\n", xname);
842 		ifp->if_ierrors++;
843 		r |= 1;
844 		rst = 1;
845 	}
846 
847 	if (why & QE_CR_STAT_RXLERR) {
848 		printf("%s: rx late error\n", xname);
849 		ifp->if_ierrors++;
850 		r |= 1;
851 		rst = 1;
852 	}
853 
854 	if (why & QE_CR_STAT_RXPERR) {
855 		printf("%s: rx DMA parity error\n", xname);
856 		ifp->if_ierrors++;
857 		r |= 1;
858 		rst = 1;
859 	}
860 
861 	if (why & QE_CR_STAT_RXSERR) {
862 		printf("%s: rx DMA sbus error ack\n", xname);
863 		ifp->if_ierrors++;
864 		r |= 1;
865 		rst = 1;
866 	}
867 
868 	if (r == 0)
869 		aprint_error_dev(self, "unexpected interrupt error: %08x\n",
870 			why);
871 
872 	if (rst) {
873 		printf("%s: resetting...\n", xname);
874 		qereset(sc);
875 		return (-1);
876 	}
877 
878 	return (r);
879 }
880 
881 int
882 qeioctl(struct ifnet *ifp, u_long cmd, void *data)
883 {
884 	struct qe_softc *sc = ifp->if_softc;
885 	struct ifaddr *ifa = data;
886 	struct ifreq *ifr = data;
887 	int s, error = 0;
888 
889 	s = splnet();
890 
891 	switch (cmd) {
892 	case SIOCINITIFADDR:
893 		ifp->if_flags |= IFF_UP;
894 		qeinit(sc);
895 		switch (ifa->ifa_addr->sa_family) {
896 #ifdef INET
897 		case AF_INET:
898 			arp_ifinit(ifp, ifa);
899 			break;
900 #endif /* INET */
901 		default:
902 			break;
903 		}
904 		break;
905 
906 	case SIOCSIFFLAGS:
907 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
908 			break;
909 		/* XXX re-use ether_ioctl() */
910 		switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
911 		case IFF_RUNNING:
912 			/*
913 			 * If interface is marked down and it is running, then
914 			 * stop it.
915 			 */
916 			qestop(sc);
917 			ifp->if_flags &= ~IFF_RUNNING;
918 			break;
919 		case IFF_UP:
920 			/*
921 			 * If interface is marked up and it is stopped, then
922 			 * start it.
923 			 */
924 			qeinit(sc);
925 			break;
926 		default:
927 			/*
928 			 * Reset the interface to pick up changes in any other
929 			 * flags that affect hardware registers.
930 			 */
931 			qestop(sc);
932 			qeinit(sc);
933 			break;
934 		}
935 #ifdef QEDEBUG
936 		sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
937 #endif
938 		break;
939 
940 	case SIOCADDMULTI:
941 	case SIOCDELMULTI:
942 		if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
943 			/*
944 			 * Multicast list has changed; set the hardware filter
945 			 * accordingly.
946 			 */
947 			if (ifp->if_flags & IFF_RUNNING)
948 				qe_mcreset(sc);
949 			error = 0;
950 		}
951 		break;
952 
953 	case SIOCGIFMEDIA:
954 	case SIOCSIFMEDIA:
955 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
956 		break;
957 
958 	default:
959 		error = ether_ioctl(ifp, cmd, data);
960 		break;
961 	}
962 
963 	splx(s);
964 	return (error);
965 }
966 
967 
968 void
969 qeinit(struct qe_softc *sc)
970 {
971 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
972 	bus_space_tag_t t = sc->sc_bustag;
973 	bus_space_handle_t cr = sc->sc_cr;
974 	bus_space_handle_t mr = sc->sc_mr;
975 	struct qec_softc *qec = sc->sc_qec;
976 	uint32_t qecaddr;
977 	uint8_t *ea;
978 	int s;
979 
980 #if defined(SUN4U) || defined(__GNUC__)
981 	(void)&t;
982 #endif
983 	s = splnet();
984 
985 	qestop(sc);
986 
987 	/*
988 	 * Allocate descriptor ring and buffers
989 	 */
990 	qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
991 
992 	/* Channel registers: */
993 	bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
994 	bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
995 
996 	bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
997 	bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
998 	bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
999 	bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
1000 	bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
1001 	bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
1002 
1003 	qecaddr = sc->sc_channel * qec->sc_msize;
1004 	bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
1005 	bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
1006 	bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1007 	bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1008 
1009 	/* MACE registers: */
1010 	bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
1011 	bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
1012 	bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
1013 
1014 	/*
1015 	 * Mask MACE's receive interrupt, since we're being notified
1016 	 * by the QEC after DMA completes.
1017 	 */
1018 	bus_space_write_1(t, mr, QE_MRI_IMR,
1019 			  QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
1020 
1021 	bus_space_write_1(t, mr, QE_MRI_BIUCC,
1022 			  QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
1023 
1024 	bus_space_write_1(t, mr, QE_MRI_FIFOFC,
1025 			  QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
1026 			  QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
1027 
1028 	bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
1029 
1030 	/*
1031 	 * Station address
1032 	 */
1033 	ea = sc->sc_enaddr;
1034 	bus_space_write_1(t, mr, QE_MRI_IAC,
1035 			  QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
1036 	bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
1037 
1038 	/* Apply media settings */
1039 	qe_ifmedia_upd(ifp);
1040 
1041 	/*
1042 	 * Clear Logical address filter
1043 	 */
1044 	bus_space_write_1(t, mr, QE_MRI_IAC,
1045 			  QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1046 	bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
1047 	bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1048 
1049 	/* Clear missed packet count (register cleared on read) */
1050 	(void)bus_space_read_1(t, mr, QE_MRI_MPC);
1051 
1052 #if 0
1053 	/* test register: */
1054 	bus_space_write_1(t, mr, QE_MRI_UTR, 0);
1055 #endif
1056 
1057 	/* Reset multicast filter */
1058 	qe_mcreset(sc);
1059 
1060 	ifp->if_flags |= IFF_RUNNING;
1061 	ifp->if_flags &= ~IFF_OACTIVE;
1062 	splx(s);
1063 }
1064 
1065 /*
1066  * Reset multicast filter.
1067  */
1068 void
1069 qe_mcreset(struct qe_softc *sc)
1070 {
1071 	struct ethercom *ec = &sc->sc_ethercom;
1072 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1073 	bus_space_tag_t t = sc->sc_bustag;
1074 	bus_space_handle_t mr = sc->sc_mr;
1075 	struct ether_multi *enm;
1076 	struct ether_multistep step;
1077 	uint32_t crc;
1078 	uint16_t hash[4];
1079 	uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0];
1080 	int i;
1081 
1082 #if defined(SUN4U) || defined(__GNUC__)
1083 	(void)&t;
1084 #endif
1085 
1086 	/* We also enable transmitter & receiver here */
1087 	maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
1088 
1089 	if (ifp->if_flags & IFF_PROMISC) {
1090 		maccc |= QE_MR_MACCC_PROM;
1091 		bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1092 		return;
1093 	}
1094 
1095 	if (ifp->if_flags & IFF_ALLMULTI) {
1096 		bus_space_write_1(t, mr, QE_MRI_IAC,
1097 				  QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1098 		bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1099 		bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1100 		bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1101 		return;
1102 	}
1103 
1104 	hash[3] = hash[2] = hash[1] = hash[0] = 0;
1105 
1106 	ETHER_FIRST_MULTI(step, ec, enm);
1107 	while (enm != NULL) {
1108 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1109 			 ETHER_ADDR_LEN) != 0) {
1110 			/*
1111 			 * We must listen to a range of multicast
1112 			 * addresses. For now, just accept all
1113 			 * multicasts, rather than trying to set only
1114 			 * those filter bits needed to match the range.
1115 			 * (At this time, the only use of address
1116 			 * ranges is for IP multicast routing, for
1117 			 * which the range is big enough to require
1118 			 * all bits set.)
1119 			 */
1120 			bus_space_write_1(t, mr, QE_MRI_IAC,
1121 				 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1122 			bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1123 			bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1124 			ifp->if_flags |= IFF_ALLMULTI;
1125 			break;
1126 		}
1127 
1128 		crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1129 		crc >>= 26;
1130 		hash[crc >> 4] |= 1 << (crc & 0xf);
1131 		ETHER_NEXT_MULTI(step, enm);
1132 	}
1133 
1134 	/* We need to byte-swap the hash before writing to the chip. */
1135 	for (i = 0; i < 7; i += 2) {
1136 		octet = ladrp[i];
1137 		ladrp[i] = ladrp[i + 1];
1138 		ladrp[i + 1] = octet;
1139 	}
1140 	bus_space_write_1(t, mr, QE_MRI_IAC,
1141 			  QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1142 	bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
1143 	bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1144 	bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1145 }
1146 
1147 /*
1148  * Get current media settings.
1149  */
1150 void
1151 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1152 {
1153 	struct qe_softc *sc = ifp->if_softc;
1154 	bus_space_tag_t t = sc->sc_bustag;
1155 	bus_space_handle_t mr = sc->sc_mr;
1156 	uint8_t v;
1157 
1158 #if defined(SUN4U) || defined(__GNUC__)
1159 	(void)&t;
1160 #endif
1161 	v = bus_space_read_1(t, mr, QE_MRI_PLSCC);
1162 
1163 	switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) {
1164 	case QE_MR_PLSCC_TP:
1165 		ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1166 		break;
1167 	case QE_MR_PLSCC_AUI:
1168 		ifmr->ifm_active = IFM_ETHER | IFM_10_5;
1169 		break;
1170 	case QE_MR_PLSCC_GPSI:
1171 	case QE_MR_PLSCC_DAI:
1172 		/* ... */
1173 		break;
1174 	}
1175 
1176 	v = bus_space_read_1(t, mr, QE_MRI_PHYCC);
1177 	ifmr->ifm_status |=  IFM_AVALID;
1178 	if ((v & QE_MR_PHYCC_LNKFL) != 0)
1179 		ifmr->ifm_status &= ~IFM_ACTIVE;
1180 	else
1181 		ifmr->ifm_status |=  IFM_ACTIVE;
1182 
1183 }
1184 
1185 /*
1186  * Set media options.
1187  */
1188 int
1189 qe_ifmedia_upd(struct ifnet *ifp)
1190 {
1191 	struct qe_softc *sc = ifp->if_softc;
1192 	struct ifmedia *ifm = &sc->sc_ifmedia;
1193 	bus_space_tag_t t = sc->sc_bustag;
1194 	bus_space_handle_t mr = sc->sc_mr;
1195 	int newmedia = ifm->ifm_media;
1196 	uint8_t plscc, phycc;
1197 
1198 #if defined(SUN4U) || defined(__GNUC__)
1199 	(void)&t;
1200 #endif
1201 	if (IFM_TYPE(newmedia) != IFM_ETHER)
1202 		return (EINVAL);
1203 
1204 	plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK;
1205 	phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL;
1206 
1207 	if (IFM_SUBTYPE(newmedia) == IFM_AUTO)
1208 		phycc |= QE_MR_PHYCC_ASEL;
1209 	else if (IFM_SUBTYPE(newmedia) == IFM_10_T)
1210 		plscc |= QE_MR_PLSCC_TP;
1211 	else if (IFM_SUBTYPE(newmedia) == IFM_10_5)
1212 		plscc |= QE_MR_PLSCC_AUI;
1213 
1214 	bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc);
1215 	bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc);
1216 
1217 	return (0);
1218 }
1219