1 /* $NetBSD: qe.c,v 1.56 2009/09/22 13:13:46 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 /* 60 * Driver for the SBus qec+qe QuadEthernet board. 61 * 62 * This driver was written using the AMD MACE Am79C940 documentation, some 63 * ideas gleaned from the S/Linux driver for this card, Solaris header files, 64 * and a loan of a card from Paul Southworth of the Internet Engineering 65 * Group (www.ieng.com). 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.56 2009/09/22 13:13:46 tsutsui Exp $"); 70 71 #define QEDEBUG 72 73 #include "opt_ddb.h" 74 #include "opt_inet.h" 75 #include "bpfilter.h" 76 #include "rnd.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/errno.h> 82 #include <sys/ioctl.h> 83 #include <sys/mbuf.h> 84 #include <sys/socket.h> 85 #include <sys/syslog.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_types.h> 95 #include <net/netisr.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 #include <machine/autoconf.h> 116 117 #include <dev/sbus/sbusvar.h> 118 #include <dev/sbus/qecreg.h> 119 #include <dev/sbus/qecvar.h> 120 #include <dev/sbus/qereg.h> 121 122 struct qe_softc { 123 struct device sc_dev; /* base device */ 124 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 125 bus_dma_tag_t sc_dmatag; 126 bus_dmamap_t sc_dmamap; 127 struct ethercom sc_ethercom; 128 struct ifmedia sc_ifmedia; /* interface media */ 129 130 struct qec_softc *sc_qec; /* QEC parent */ 131 132 bus_space_handle_t sc_qr; /* QEC registers */ 133 bus_space_handle_t sc_mr; /* MACE registers */ 134 bus_space_handle_t sc_cr; /* channel registers */ 135 136 int sc_channel; /* channel number */ 137 u_int sc_rev; /* board revision */ 138 139 int sc_burst; 140 141 struct qec_ring sc_rb; /* Packet Ring Buffer */ 142 143 /* MAC address */ 144 uint8_t sc_enaddr[6]; 145 146 #ifdef QEDEBUG 147 int sc_debug; 148 #endif 149 }; 150 151 int qematch(device_t, cfdata_t, void *); 152 void qeattach(device_t, device_t, void *); 153 154 void qeinit(struct qe_softc *); 155 void qestart(struct ifnet *); 156 void qestop(struct qe_softc *); 157 void qewatchdog(struct ifnet *); 158 int qeioctl(struct ifnet *, u_long, void *); 159 void qereset(struct qe_softc *); 160 161 int qeintr(void *); 162 int qe_eint(struct qe_softc *, uint32_t); 163 int qe_rint(struct qe_softc *); 164 int qe_tint(struct qe_softc *); 165 void qe_mcreset(struct qe_softc *); 166 167 static int qe_put(struct qe_softc *, int, struct mbuf *); 168 static void qe_read(struct qe_softc *, int, int); 169 static struct mbuf *qe_get(struct qe_softc *, int, int); 170 171 /* ifmedia callbacks */ 172 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 173 int qe_ifmedia_upd(struct ifnet *); 174 175 CFATTACH_DECL(qe, sizeof(struct qe_softc), 176 qematch, qeattach, NULL, NULL); 177 178 int 179 qematch(device_t parent, cfdata_t cf, void *aux) 180 { 181 struct sbus_attach_args *sa = aux; 182 183 return (strcmp(cf->cf_name, sa->sa_name) == 0); 184 } 185 186 void 187 qeattach(device_t parent, device_t self, void *aux) 188 { 189 struct sbus_attach_args *sa = aux; 190 struct qec_softc *qec = device_private(parent); 191 struct qe_softc *sc = device_private(self); 192 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 193 int node = sa->sa_node; 194 bus_dma_tag_t dmatag = sa->sa_dmatag; 195 bus_dma_segment_t seg; 196 bus_size_t size; 197 int rseg, error; 198 199 if (sa->sa_nreg < 2) { 200 printf("%s: only %d register sets\n", 201 device_xname(self), sa->sa_nreg); 202 return; 203 } 204 205 if (bus_space_map(sa->sa_bustag, 206 (bus_addr_t)BUS_ADDR( 207 sa->sa_reg[0].oa_space, 208 sa->sa_reg[0].oa_base), 209 (bus_size_t)sa->sa_reg[0].oa_size, 210 0, &sc->sc_cr) != 0) { 211 aprint_error_dev(self, "cannot map registers\n"); 212 return; 213 } 214 215 if (bus_space_map(sa->sa_bustag, 216 (bus_addr_t)BUS_ADDR( 217 sa->sa_reg[1].oa_space, 218 sa->sa_reg[1].oa_base), 219 (bus_size_t)sa->sa_reg[1].oa_size, 220 0, &sc->sc_mr) != 0) { 221 aprint_error_dev(self, "cannot map registers\n"); 222 return; 223 } 224 225 sc->sc_rev = prom_getpropint(node, "mace-version", -1); 226 printf(" rev %x", sc->sc_rev); 227 228 sc->sc_bustag = sa->sa_bustag; 229 sc->sc_dmatag = sa->sa_dmatag; 230 sc->sc_qec = qec; 231 sc->sc_qr = qec->sc_regs; 232 233 sc->sc_channel = prom_getpropint(node, "channel#", -1); 234 sc->sc_burst = qec->sc_burst; 235 236 qestop(sc); 237 238 /* Note: no interrupt level passed */ 239 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc); 240 prom_getether(node, sc->sc_enaddr); 241 242 /* 243 * Allocate descriptor ring and buffers. 244 */ 245 246 /* for now, allocate as many bufs as there are ring descriptors */ 247 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 248 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 249 250 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 251 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 252 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ + 253 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ; 254 255 /* Get a DMA handle */ 256 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 257 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 258 aprint_error_dev(self, "DMA map create error %d\n", 259 error); 260 return; 261 } 262 263 /* Allocate DMA buffer */ 264 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0, 265 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 266 aprint_error_dev(self, "DMA buffer alloc error %d\n", 267 error); 268 return; 269 } 270 271 /* Map DMA buffer in CPU addressable space */ 272 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 273 &sc->sc_rb.rb_membase, 274 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 275 aprint_error_dev(self, "DMA buffer map error %d\n", 276 error); 277 bus_dmamem_free(dmatag, &seg, rseg); 278 return; 279 } 280 281 /* Load the buffer */ 282 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 283 sc->sc_rb.rb_membase, size, NULL, 284 BUS_DMA_NOWAIT)) != 0) { 285 aprint_error_dev(self, "DMA buffer map load error %d\n", 286 error); 287 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 288 bus_dmamem_free(dmatag, &seg, rseg); 289 return; 290 } 291 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 292 293 /* Initialize media properties */ 294 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts); 295 ifmedia_add(&sc->sc_ifmedia, 296 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 297 0, NULL); 298 ifmedia_add(&sc->sc_ifmedia, 299 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 300 0, NULL); 301 ifmedia_add(&sc->sc_ifmedia, 302 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 303 0, NULL); 304 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 305 306 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 307 ifp->if_softc = sc; 308 ifp->if_start = qestart; 309 ifp->if_ioctl = qeioctl; 310 ifp->if_watchdog = qewatchdog; 311 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | 312 IFF_MULTICAST; 313 IFQ_SET_READY(&ifp->if_snd); 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, sc->sc_enaddr); 318 319 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 320 } 321 322 /* 323 * Pull data off an interface. 324 * Len is the length of data, with local net header stripped. 325 * We copy the data into mbufs. When full cluster sized units are present, 326 * we copy into clusters. 327 */ 328 static inline struct mbuf * 329 qe_get(struct qe_softc *sc, int idx, int totlen) 330 { 331 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 332 struct mbuf *m; 333 struct mbuf *top, **mp; 334 int len, pad, boff = 0; 335 uint8_t *bp; 336 337 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ; 338 339 MGETHDR(m, M_DONTWAIT, MT_DATA); 340 if (m == NULL) 341 return (NULL); 342 m->m_pkthdr.rcvif = ifp; 343 m->m_pkthdr.len = totlen; 344 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 345 m->m_data += pad; 346 len = MHLEN - pad; 347 top = NULL; 348 mp = ⊤ 349 350 while (totlen > 0) { 351 if (top) { 352 MGET(m, M_DONTWAIT, MT_DATA); 353 if (m == NULL) { 354 m_freem(top); 355 return (NULL); 356 } 357 len = MLEN; 358 } 359 if (top && totlen >= MINCLSIZE) { 360 MCLGET(m, M_DONTWAIT); 361 if (m->m_flags & M_EXT) 362 len = MCLBYTES; 363 } 364 m->m_len = len = min(totlen, len); 365 memcpy(mtod(m, void *), bp + boff, len); 366 boff += len; 367 totlen -= len; 368 *mp = m; 369 mp = &m->m_next; 370 } 371 372 return (top); 373 } 374 375 /* 376 * Routine to copy from mbuf chain to transmit buffer in 377 * network buffer memory. 378 */ 379 inline int 380 qe_put(struct qe_softc *sc, int idx, struct mbuf *m) 381 { 382 struct mbuf *n; 383 int len, tlen = 0, boff = 0; 384 uint8_t *bp; 385 386 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ; 387 388 for (; m; m = n) { 389 len = m->m_len; 390 if (len == 0) { 391 MFREE(m, n); 392 continue; 393 } 394 memcpy(bp + boff, mtod(m, void *), len); 395 boff += len; 396 tlen += len; 397 MFREE(m, n); 398 } 399 return (tlen); 400 } 401 402 /* 403 * Pass a packet to the higher levels. 404 */ 405 inline void 406 qe_read(struct qe_softc *sc, int idx, int len) 407 { 408 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 409 struct mbuf *m; 410 411 if (len <= sizeof(struct ether_header) || 412 len > ETHERMTU + sizeof(struct ether_header)) { 413 414 printf("%s: invalid packet size %d; dropping\n", 415 ifp->if_xname, len); 416 417 ifp->if_ierrors++; 418 return; 419 } 420 421 /* 422 * Pull packet off interface. 423 */ 424 m = qe_get(sc, idx, len); 425 if (m == NULL) { 426 ifp->if_ierrors++; 427 return; 428 } 429 ifp->if_ipackets++; 430 431 #if NBPFILTER > 0 432 /* 433 * Check if there's a BPF listener on this interface. 434 * If so, hand off the raw packet to BPF. 435 */ 436 if (ifp->if_bpf) 437 bpf_mtap(ifp->if_bpf, m); 438 #endif 439 /* Pass the packet up. */ 440 (*ifp->if_input)(ifp, m); 441 } 442 443 /* 444 * Start output on interface. 445 * We make two assumptions here: 446 * 1) that the current priority is set to splnet _before_ this code 447 * is called *and* is returned to the appropriate priority after 448 * return 449 * 2) that the IFF_OACTIVE flag is checked before this code is called 450 * (i.e. that the output part of the interface is idle) 451 */ 452 void 453 qestart(struct ifnet *ifp) 454 { 455 struct qe_softc *sc = ifp->if_softc; 456 struct qec_xd *txd = sc->sc_rb.rb_txd; 457 struct mbuf *m; 458 unsigned int bix, len; 459 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 460 461 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 462 return; 463 464 bix = sc->sc_rb.rb_tdhead; 465 466 for (;;) { 467 IFQ_DEQUEUE(&ifp->if_snd, m); 468 if (m == 0) 469 break; 470 471 #if NBPFILTER > 0 472 /* 473 * If BPF is listening on this interface, let it see the 474 * packet before we commit it to the wire. 475 */ 476 if (ifp->if_bpf) 477 bpf_mtap(ifp->if_bpf, m); 478 #endif 479 480 /* 481 * Copy the mbuf chain into the transmit buffer. 482 */ 483 len = qe_put(sc, bix, m); 484 485 /* 486 * Initialize transmit registers and start transmission 487 */ 488 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 489 (len & QEC_XD_LENGTH); 490 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL, 491 QE_CR_CTRL_TWAKEUP); 492 493 if (++bix == QEC_XD_RING_MAXSIZE) 494 bix = 0; 495 496 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 497 ifp->if_flags |= IFF_OACTIVE; 498 break; 499 } 500 } 501 502 sc->sc_rb.rb_tdhead = bix; 503 } 504 505 void 506 qestop(struct qe_softc *sc) 507 { 508 bus_space_tag_t t = sc->sc_bustag; 509 bus_space_handle_t mr = sc->sc_mr; 510 bus_space_handle_t cr = sc->sc_cr; 511 int n; 512 513 #if defined(SUN4U) || defined(__GNUC__) 514 (void)&t; 515 #endif 516 /* Stop the schwurst */ 517 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST); 518 for (n = 200; n > 0; n--) { 519 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) & 520 QE_MR_BIUCC_SWRST) == 0) 521 break; 522 DELAY(20); 523 } 524 525 /* then reset */ 526 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET); 527 for (n = 200; n > 0; n--) { 528 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) & 529 QE_CR_CTRL_RESET) == 0) 530 break; 531 DELAY(20); 532 } 533 } 534 535 /* 536 * Reset interface. 537 */ 538 void 539 qereset(struct qe_softc *sc) 540 { 541 int s; 542 543 s = splnet(); 544 qestop(sc); 545 qeinit(sc); 546 splx(s); 547 } 548 549 void 550 qewatchdog(struct ifnet *ifp) 551 { 552 struct qe_softc *sc = ifp->if_softc; 553 554 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 555 ifp->if_oerrors++; 556 557 qereset(sc); 558 } 559 560 /* 561 * Interrupt dispatch. 562 */ 563 int 564 qeintr(void *arg) 565 { 566 struct qe_softc *sc = arg; 567 bus_space_tag_t t = sc->sc_bustag; 568 uint32_t qecstat, qestat; 569 int r = 0; 570 571 #if defined(SUN4U) || defined(__GNUC__) 572 (void)&t; 573 #endif 574 /* Read QEC status and channel status */ 575 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 576 #ifdef QEDEBUG 577 if (sc->sc_debug) { 578 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat); 579 } 580 #endif 581 582 /* Filter out status for this channel */ 583 qecstat = qecstat >> (4 * sc->sc_channel); 584 if ((qecstat & 0xf) == 0) 585 return (r); 586 587 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT); 588 589 #ifdef QEDEBUG 590 if (sc->sc_debug) { 591 char bits[64]; int i; 592 bus_space_tag_t t1 = sc->sc_bustag; 593 bus_space_handle_t mr = sc->sc_mr; 594 595 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 596 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits); 597 598 printf("MACE registers:\n"); 599 for (i = 0 ; i < 32; i++) { 600 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i)); 601 if (((i+1) & 7) == 0) 602 printf("\n"); 603 } 604 } 605 #endif 606 607 if (qestat & QE_CR_STAT_ALLERRORS) { 608 #ifdef QEDEBUG 609 if (sc->sc_debug) { 610 char bits[64]; 611 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat); 612 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits); 613 } 614 #endif 615 r |= qe_eint(sc, qestat); 616 if (r == -1) 617 return (1); 618 } 619 620 if (qestat & QE_CR_STAT_TXIRQ) 621 r |= qe_tint(sc); 622 623 if (qestat & QE_CR_STAT_RXIRQ) 624 r |= qe_rint(sc); 625 626 return (r); 627 } 628 629 /* 630 * Transmit interrupt. 631 */ 632 int 633 qe_tint(struct qe_softc *sc) 634 { 635 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 636 unsigned int bix, txflags; 637 638 bix = sc->sc_rb.rb_tdtail; 639 640 for (;;) { 641 if (sc->sc_rb.rb_td_nbusy <= 0) 642 break; 643 644 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 645 646 if (txflags & QEC_XD_OWN) 647 break; 648 649 ifp->if_flags &= ~IFF_OACTIVE; 650 ifp->if_opackets++; 651 652 if (++bix == QEC_XD_RING_MAXSIZE) 653 bix = 0; 654 655 --sc->sc_rb.rb_td_nbusy; 656 } 657 658 sc->sc_rb.rb_tdtail = bix; 659 660 qestart(ifp); 661 662 if (sc->sc_rb.rb_td_nbusy == 0) 663 ifp->if_timer = 0; 664 665 return (1); 666 } 667 668 /* 669 * Receive interrupt. 670 */ 671 int 672 qe_rint(struct qe_softc *sc) 673 { 674 struct qec_xd *xd = sc->sc_rb.rb_rxd; 675 unsigned int bix, len; 676 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 677 #ifdef QEDEBUG 678 int npackets = 0; 679 #endif 680 681 bix = sc->sc_rb.rb_rdtail; 682 683 /* 684 * Process all buffers with valid data. 685 */ 686 for (;;) { 687 len = xd[bix].xd_flags; 688 if (len & QEC_XD_OWN) 689 break; 690 691 #ifdef QEDEBUG 692 npackets++; 693 #endif 694 695 len &= QEC_XD_LENGTH; 696 len -= 4; 697 qe_read(sc, bix, len); 698 699 /* ... */ 700 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 701 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH); 702 703 if (++bix == QEC_XD_RING_MAXSIZE) 704 bix = 0; 705 } 706 #ifdef QEDEBUG 707 if (npackets == 0 && sc->sc_debug) 708 printf("%s: rint: no packets; rb index %d; status 0x%x\n", 709 device_xname(&sc->sc_dev), bix, len); 710 #endif 711 712 sc->sc_rb.rb_rdtail = bix; 713 714 return (1); 715 } 716 717 /* 718 * Error interrupt. 719 */ 720 int 721 qe_eint(struct qe_softc *sc, uint32_t why) 722 { 723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 724 device_t self = &sc->sc_dev; 725 int r = 0, rst = 0; 726 727 if (why & QE_CR_STAT_EDEFER) { 728 printf("%s: excessive tx defers.\n", device_xname(self)); 729 r |= 1; 730 ifp->if_oerrors++; 731 } 732 733 if (why & QE_CR_STAT_CLOSS) { 734 printf("%s: no carrier, link down?\n", device_xname(self)); 735 ifp->if_oerrors++; 736 r |= 1; 737 } 738 739 if (why & QE_CR_STAT_ERETRIES) { 740 printf("%s: excessive tx retries\n", device_xname(self)); 741 ifp->if_oerrors++; 742 r |= 1; 743 rst = 1; 744 } 745 746 747 if (why & QE_CR_STAT_LCOLL) { 748 printf("%s: late tx transmission\n", device_xname(self)); 749 ifp->if_oerrors++; 750 r |= 1; 751 rst = 1; 752 } 753 754 if (why & QE_CR_STAT_FUFLOW) { 755 printf("%s: tx fifo underflow\n", device_xname(self)); 756 ifp->if_oerrors++; 757 r |= 1; 758 rst = 1; 759 } 760 761 if (why & QE_CR_STAT_JERROR) { 762 printf("%s: jabber seen\n", device_xname(self)); 763 r |= 1; 764 } 765 766 if (why & QE_CR_STAT_BERROR) { 767 printf("%s: babble seen\n", device_xname(self)); 768 r |= 1; 769 } 770 771 if (why & QE_CR_STAT_TCCOFLOW) { 772 ifp->if_collisions += 256; 773 ifp->if_oerrors += 256; 774 r |= 1; 775 } 776 777 if (why & QE_CR_STAT_TXDERROR) { 778 printf("%s: tx descriptor is bad\n", device_xname(self)); 779 rst = 1; 780 r |= 1; 781 } 782 783 if (why & QE_CR_STAT_TXLERR) { 784 printf("%s: tx late error\n", device_xname(self)); 785 ifp->if_oerrors++; 786 rst = 1; 787 r |= 1; 788 } 789 790 if (why & QE_CR_STAT_TXPERR) { 791 printf("%s: tx DMA parity error\n", device_xname(self)); 792 ifp->if_oerrors++; 793 rst = 1; 794 r |= 1; 795 } 796 797 if (why & QE_CR_STAT_TXSERR) { 798 printf("%s: tx DMA sbus error ack\n", device_xname(self)); 799 ifp->if_oerrors++; 800 rst = 1; 801 r |= 1; 802 } 803 804 if (why & QE_CR_STAT_RCCOFLOW) { 805 ifp->if_collisions += 256; 806 ifp->if_ierrors += 256; 807 r |= 1; 808 } 809 810 if (why & QE_CR_STAT_RUOFLOW) { 811 ifp->if_ierrors += 256; 812 r |= 1; 813 } 814 815 if (why & QE_CR_STAT_MCOFLOW) { 816 ifp->if_ierrors += 256; 817 r |= 1; 818 } 819 820 if (why & QE_CR_STAT_RXFOFLOW) { 821 printf("%s: rx fifo overflow\n", device_xname(self)); 822 ifp->if_ierrors++; 823 r |= 1; 824 } 825 826 if (why & QE_CR_STAT_RLCOLL) { 827 printf("%s: rx late collision\n", device_xname(self)); 828 ifp->if_ierrors++; 829 ifp->if_collisions++; 830 r |= 1; 831 } 832 833 if (why & QE_CR_STAT_FCOFLOW) { 834 ifp->if_ierrors += 256; 835 r |= 1; 836 } 837 838 if (why & QE_CR_STAT_CECOFLOW) { 839 ifp->if_ierrors += 256; 840 r |= 1; 841 } 842 843 if (why & QE_CR_STAT_RXDROP) { 844 printf("%s: rx packet dropped\n", device_xname(self)); 845 ifp->if_ierrors++; 846 r |= 1; 847 } 848 849 if (why & QE_CR_STAT_RXSMALL) { 850 printf("%s: rx buffer too small\n", device_xname(self)); 851 ifp->if_ierrors++; 852 r |= 1; 853 rst = 1; 854 } 855 856 if (why & QE_CR_STAT_RXLERR) { 857 printf("%s: rx late error\n", device_xname(self)); 858 ifp->if_ierrors++; 859 r |= 1; 860 rst = 1; 861 } 862 863 if (why & QE_CR_STAT_RXPERR) { 864 printf("%s: rx DMA parity error\n", device_xname(self)); 865 ifp->if_ierrors++; 866 r |= 1; 867 rst = 1; 868 } 869 870 if (why & QE_CR_STAT_RXSERR) { 871 printf("%s: rx DMA sbus error ack\n", device_xname(self)); 872 ifp->if_ierrors++; 873 r |= 1; 874 rst = 1; 875 } 876 877 if (r == 0) 878 aprint_error_dev(self, "unexpected interrupt error: %08x\n", 879 why); 880 881 if (rst) { 882 printf("%s: resetting...\n", device_xname(self)); 883 qereset(sc); 884 return (-1); 885 } 886 887 return (r); 888 } 889 890 int 891 qeioctl(struct ifnet *ifp, u_long cmd, void *data) 892 { 893 struct qe_softc *sc = ifp->if_softc; 894 struct ifaddr *ifa = data; 895 struct ifreq *ifr = data; 896 int s, error = 0; 897 898 s = splnet(); 899 900 switch (cmd) { 901 case SIOCINITIFADDR: 902 ifp->if_flags |= IFF_UP; 903 qeinit(sc); 904 switch (ifa->ifa_addr->sa_family) { 905 #ifdef INET 906 case AF_INET: 907 arp_ifinit(ifp, ifa); 908 break; 909 #endif /* INET */ 910 default: 911 break; 912 } 913 break; 914 915 case SIOCSIFFLAGS: 916 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 917 break; 918 /* XXX re-use ether_ioctl() */ 919 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 920 case IFF_RUNNING: 921 /* 922 * If interface is marked down and it is running, then 923 * stop it. 924 */ 925 qestop(sc); 926 ifp->if_flags &= ~IFF_RUNNING; 927 break; 928 case IFF_UP: 929 /* 930 * If interface is marked up and it is stopped, then 931 * start it. 932 */ 933 qeinit(sc); 934 break; 935 default: 936 /* 937 * Reset the interface to pick up changes in any other 938 * flags that affect hardware registers. 939 */ 940 qestop(sc); 941 qeinit(sc); 942 break; 943 } 944 #ifdef QEDEBUG 945 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 946 #endif 947 break; 948 949 case SIOCADDMULTI: 950 case SIOCDELMULTI: 951 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 952 /* 953 * Multicast list has changed; set the hardware filter 954 * accordingly. 955 */ 956 if (ifp->if_flags & IFF_RUNNING) 957 qe_mcreset(sc); 958 error = 0; 959 } 960 break; 961 962 case SIOCGIFMEDIA: 963 case SIOCSIFMEDIA: 964 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 965 break; 966 967 default: 968 error = EINVAL; 969 break; 970 } 971 972 splx(s); 973 return (error); 974 } 975 976 977 void 978 qeinit(struct qe_softc *sc) 979 { 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 bus_space_tag_t t = sc->sc_bustag; 982 bus_space_handle_t cr = sc->sc_cr; 983 bus_space_handle_t mr = sc->sc_mr; 984 struct qec_softc *qec = sc->sc_qec; 985 uint32_t qecaddr; 986 uint8_t *ea; 987 int s; 988 989 #if defined(SUN4U) || defined(__GNUC__) 990 (void)&t; 991 #endif 992 s = splnet(); 993 994 qestop(sc); 995 996 /* 997 * Allocate descriptor ring and buffers 998 */ 999 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ); 1000 1001 /* Channel registers: */ 1002 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1003 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1004 1005 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0); 1006 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0); 1007 bus_space_write_4(t, cr, QE_CRI_QMASK, 0); 1008 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL); 1009 bus_space_write_4(t, cr, QE_CRI_CCNT, 0); 1010 bus_space_write_4(t, cr, QE_CRI_PIPG, 0); 1011 1012 qecaddr = sc->sc_channel * qec->sc_msize; 1013 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr); 1014 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr); 1015 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1016 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1017 1018 /* MACE registers: */ 1019 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL); 1020 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT); 1021 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0); 1022 1023 /* 1024 * Mask MACE's receive interrupt, since we're being notified 1025 * by the QEC after DMA completes. 1026 */ 1027 bus_space_write_1(t, mr, QE_MRI_IMR, 1028 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM); 1029 1030 bus_space_write_1(t, mr, QE_MRI_BIUCC, 1031 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS); 1032 1033 bus_space_write_1(t, mr, QE_MRI_FIFOFC, 1034 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 | 1035 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU); 1036 1037 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP); 1038 1039 /* 1040 * Station address 1041 */ 1042 ea = sc->sc_enaddr; 1043 bus_space_write_1(t, mr, QE_MRI_IAC, 1044 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR); 1045 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6); 1046 1047 /* Apply media settings */ 1048 qe_ifmedia_upd(ifp); 1049 1050 /* 1051 * Clear Logical address filter 1052 */ 1053 bus_space_write_1(t, mr, QE_MRI_IAC, 1054 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1055 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8); 1056 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1057 1058 /* Clear missed packet count (register cleared on read) */ 1059 (void)bus_space_read_1(t, mr, QE_MRI_MPC); 1060 1061 #if 0 1062 /* test register: */ 1063 bus_space_write_1(t, mr, QE_MRI_UTR, 0); 1064 #endif 1065 1066 /* Reset multicast filter */ 1067 qe_mcreset(sc); 1068 1069 ifp->if_flags |= IFF_RUNNING; 1070 ifp->if_flags &= ~IFF_OACTIVE; 1071 splx(s); 1072 } 1073 1074 /* 1075 * Reset multicast filter. 1076 */ 1077 void 1078 qe_mcreset(struct qe_softc *sc) 1079 { 1080 struct ethercom *ec = &sc->sc_ethercom; 1081 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1082 bus_space_tag_t t = sc->sc_bustag; 1083 bus_space_handle_t mr = sc->sc_mr; 1084 struct ether_multi *enm; 1085 struct ether_multistep step; 1086 uint32_t crc; 1087 uint16_t hash[4]; 1088 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0]; 1089 int i, j; 1090 1091 #if defined(SUN4U) || defined(__GNUC__) 1092 (void)&t; 1093 #endif 1094 1095 /* We also enable transmitter & receiver here */ 1096 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV; 1097 1098 if (ifp->if_flags & IFF_PROMISC) { 1099 maccc |= QE_MR_MACCC_PROM; 1100 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1101 return; 1102 } 1103 1104 if (ifp->if_flags & IFF_ALLMULTI) { 1105 bus_space_write_1(t, mr, QE_MRI_IAC, 1106 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1107 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1108 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1109 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1110 return; 1111 } 1112 1113 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1114 1115 ETHER_FIRST_MULTI(step, ec, enm); 1116 while (enm != NULL) { 1117 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1118 ETHER_ADDR_LEN) != 0) { 1119 /* 1120 * We must listen to a range of multicast 1121 * addresses. For now, just accept all 1122 * multicasts, rather than trying to set only 1123 * those filter bits needed to match the range. 1124 * (At this time, the only use of address 1125 * ranges is for IP multicast routing, for 1126 * which the range is big enough to require 1127 * all bits set.) 1128 */ 1129 bus_space_write_1(t, mr, QE_MRI_IAC, 1130 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1131 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8); 1132 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1133 ifp->if_flags |= IFF_ALLMULTI; 1134 break; 1135 } 1136 1137 crc = 0xffffffff; 1138 1139 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1140 octet = enm->enm_addrlo[i]; 1141 1142 for (j = 0; j < 8; j++) { 1143 if ((crc & 1) ^ (octet & 1)) { 1144 crc >>= 1; 1145 crc ^= MC_POLY_LE; 1146 } 1147 else 1148 crc >>= 1; 1149 octet >>= 1; 1150 } 1151 } 1152 1153 crc >>= 26; 1154 hash[crc >> 4] |= 1 << (crc & 0xf); 1155 ETHER_NEXT_MULTI(step, enm); 1156 } 1157 1158 bus_space_write_1(t, mr, QE_MRI_IAC, 1159 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR); 1160 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8); 1161 bus_space_write_1(t, mr, QE_MRI_IAC, 0); 1162 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc); 1163 } 1164 1165 /* 1166 * Get current media settings. 1167 */ 1168 void 1169 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1170 { 1171 struct qe_softc *sc = ifp->if_softc; 1172 bus_space_tag_t t = sc->sc_bustag; 1173 bus_space_handle_t mr = sc->sc_mr; 1174 uint8_t v; 1175 1176 #if defined(SUN4U) || defined(__GNUC__) 1177 (void)&t; 1178 #endif 1179 v = bus_space_read_1(t, mr, QE_MRI_PLSCC); 1180 1181 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) { 1182 case QE_MR_PLSCC_TP: 1183 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1184 break; 1185 case QE_MR_PLSCC_AUI: 1186 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 1187 break; 1188 case QE_MR_PLSCC_GPSI: 1189 case QE_MR_PLSCC_DAI: 1190 /* ... */ 1191 break; 1192 } 1193 1194 v = bus_space_read_1(t, mr, QE_MRI_PHYCC); 1195 ifmr->ifm_status |= IFM_AVALID; 1196 if ((v & QE_MR_PHYCC_LNKFL) != 0) 1197 ifmr->ifm_status &= ~IFM_ACTIVE; 1198 else 1199 ifmr->ifm_status |= IFM_ACTIVE; 1200 1201 } 1202 1203 /* 1204 * Set media options. 1205 */ 1206 int 1207 qe_ifmedia_upd(struct ifnet *ifp) 1208 { 1209 struct qe_softc *sc = ifp->if_softc; 1210 struct ifmedia *ifm = &sc->sc_ifmedia; 1211 bus_space_tag_t t = sc->sc_bustag; 1212 bus_space_handle_t mr = sc->sc_mr; 1213 int newmedia = ifm->ifm_media; 1214 uint8_t plscc, phycc; 1215 1216 #if defined(SUN4U) || defined(__GNUC__) 1217 (void)&t; 1218 #endif 1219 if (IFM_TYPE(newmedia) != IFM_ETHER) 1220 return (EINVAL); 1221 1222 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK; 1223 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL; 1224 1225 if (IFM_SUBTYPE(newmedia) == IFM_AUTO) 1226 phycc |= QE_MR_PHYCC_ASEL; 1227 else if (IFM_SUBTYPE(newmedia) == IFM_10_T) 1228 plscc |= QE_MR_PLSCC_TP; 1229 else if (IFM_SUBTYPE(newmedia) == IFM_10_5) 1230 plscc |= QE_MR_PLSCC_AUI; 1231 1232 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc); 1233 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc); 1234 1235 return (0); 1236 } 1237