1 /* $NetBSD: esp_sbus.c,v 1.38 2007/10/19 12:01:10 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: esp_sbus.c,v 1.38 2007/10/19 12:01:10 ad Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 #include <sys/malloc.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsiconf.h> 52 #include <dev/scsipi/scsi_message.h> 53 54 #include <sys/bus.h> 55 #include <sys/intr.h> 56 #include <machine/autoconf.h> 57 58 #include <dev/ic/lsi64854reg.h> 59 #include <dev/ic/lsi64854var.h> 60 61 #include <dev/ic/ncr53c9xreg.h> 62 #include <dev/ic/ncr53c9xvar.h> 63 64 #include <dev/sbus/sbusvar.h> 65 66 #include "opt_ddb.h" 67 68 /* #define ESP_SBUS_DEBUG */ 69 70 struct esp_softc { 71 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 72 struct sbusdev sc_sd; /* sbus device */ 73 74 bus_space_tag_t sc_bustag; 75 bus_dma_tag_t sc_dmatag; 76 77 bus_space_handle_t sc_reg; /* the registers */ 78 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 79 80 int sc_pri; /* SBUS priority */ 81 }; 82 83 void espattach_sbus(struct device *, struct device *, void *); 84 void espattach_dma(struct device *, struct device *, void *); 85 int espmatch_sbus(struct device *, struct cfdata *, void *); 86 87 88 CFATTACH_DECL(esp_sbus, sizeof(struct esp_softc), 89 espmatch_sbus, espattach_sbus, NULL, NULL); 90 91 CFATTACH_DECL(esp_dma, sizeof(struct esp_softc), 92 espmatch_sbus, espattach_dma, NULL, NULL); 93 94 /* 95 * Functions and the switch for the MI code. 96 */ 97 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 98 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 99 static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 100 static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 101 static int esp_dma_isintr(struct ncr53c9x_softc *); 102 static void esp_dma_reset(struct ncr53c9x_softc *); 103 static int esp_dma_intr(struct ncr53c9x_softc *); 104 static int esp_dma_setup(struct ncr53c9x_softc *, void **, 105 size_t *, int, size_t *); 106 static void esp_dma_go(struct ncr53c9x_softc *); 107 static void esp_dma_stop(struct ncr53c9x_softc *); 108 static int esp_dma_isactive(struct ncr53c9x_softc *); 109 110 #ifdef DDB 111 static void esp_init_ddb_cmds(void); 112 #endif 113 114 static struct ncr53c9x_glue esp_sbus_glue = { 115 esp_read_reg, 116 esp_write_reg, 117 esp_dma_isintr, 118 esp_dma_reset, 119 esp_dma_intr, 120 esp_dma_setup, 121 esp_dma_go, 122 esp_dma_stop, 123 esp_dma_isactive, 124 NULL, /* gl_clear_latched_intr */ 125 }; 126 127 static struct ncr53c9x_glue esp_sbus_glue1 = { 128 esp_rdreg1, 129 esp_wrreg1, 130 esp_dma_isintr, 131 esp_dma_reset, 132 esp_dma_intr, 133 esp_dma_setup, 134 esp_dma_go, 135 esp_dma_stop, 136 esp_dma_isactive, 137 NULL, /* gl_clear_latched_intr */ 138 }; 139 140 static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 141 142 int 143 espmatch_sbus(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 int rv; 149 struct sbus_attach_args *sa = aux; 150 151 if (strcmp("SUNW,fas", sa->sa_name) == 0) 152 return 1; 153 154 rv = (strcmp(cf->cf_name, sa->sa_name) == 0 || 155 strcmp("ptscII", sa->sa_name) == 0); 156 return (rv); 157 } 158 159 void 160 espattach_sbus(parent, self, aux) 161 struct device *parent, *self; 162 void *aux; 163 { 164 struct esp_softc *esc = (void *)self; 165 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 166 struct sbus_attach_args *sa = aux; 167 struct lsi64854_softc *lsc; 168 int burst, sbusburst; 169 170 #ifdef DDB 171 esp_init_ddb_cmds(); 172 #endif 173 174 esc->sc_bustag = sa->sa_bustag; 175 esc->sc_dmatag = sa->sa_dmatag; 176 177 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7); 178 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1); 179 if (sc->sc_freq < 0) 180 sc->sc_freq = ((struct sbus_softc *) 181 device_parent(&sc->sc_dev))->sc_clockfreq; 182 183 #ifdef ESP_SBUS_DEBUG 184 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 185 self->dv_xname, sc->sc_id, sc->sc_freq); 186 #endif 187 188 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 189 190 /* 191 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 192 */ 193 if (sa->sa_nreg != 2) { 194 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 195 return; 196 } 197 198 /* 199 * allocate space for dma, in SUNW,fas there are no separate 200 * dma device 201 */ 202 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 203 204 if (lsc == NULL) { 205 printf("%s: out of memory (lsi64854_softc)\n", 206 self->dv_xname); 207 return; 208 } 209 esc->sc_dma = lsc; 210 211 lsc->sc_bustag = sa->sa_bustag; 212 lsc->sc_dmatag = sa->sa_dmatag; 213 214 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 215 sizeof (lsc->sc_dev.dv_xname)); 216 217 /* Map dma registers */ 218 if (sa->sa_npromvaddrs) { 219 sbus_promaddr_to_handle(sa->sa_bustag, 220 sa->sa_promvaddrs[0], &lsc->sc_regs); 221 } else { 222 if (sbus_bus_map(sa->sa_bustag, 223 sa->sa_reg[0].oa_space, 224 sa->sa_reg[0].oa_base, 225 sa->sa_reg[0].oa_size, 226 0, &lsc->sc_regs) != 0) { 227 printf("%s: cannot map dma registers\n", 228 self->dv_xname); 229 return; 230 } 231 } 232 233 /* 234 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 235 * 236 * Get transfer burst size from PROM and plug it into the 237 * controller registers. This is needed on the Sun4m; do 238 * others need it too? 239 */ 240 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 241 if (sbusburst == 0) 242 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 243 244 burst = prom_getpropint(sa->sa_node, "burst-sizes", -1); 245 246 #if ESP_SBUS_DEBUG 247 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 248 burst, sbusburst); 249 #endif 250 251 if (burst == -1) 252 /* take SBus burst sizes */ 253 burst = sbusburst; 254 255 /* Clamp at parent's burst sizes */ 256 burst &= sbusburst; 257 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 258 (burst & SBUS_BURST_16) ? 16 : 0; 259 260 lsc->sc_channel = L64854_CHANNEL_SCSI; 261 lsc->sc_client = sc; 262 263 lsi64854_attach(lsc); 264 265 /* 266 * map SCSI core registers 267 */ 268 if (sa->sa_npromvaddrs > 1) { 269 sbus_promaddr_to_handle(sa->sa_bustag, 270 sa->sa_promvaddrs[1], &esc->sc_reg); 271 } else { 272 if (sbus_bus_map(sa->sa_bustag, 273 sa->sa_reg[1].oa_space, 274 sa->sa_reg[1].oa_base, 275 sa->sa_reg[1].oa_size, 276 0, &esc->sc_reg) != 0) { 277 printf("%s @ sbus: " 278 "cannot map scsi core registers\n", 279 self->dv_xname); 280 return; 281 } 282 } 283 284 if (sa->sa_nintr == 0) { 285 printf("\n%s: no interrupt property\n", self->dv_xname); 286 return; 287 } 288 289 esc->sc_pri = sa->sa_pri; 290 291 /* add me to the sbus structures */ 292 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 293 sbus_establish(&esc->sc_sd, &sc->sc_dev); 294 295 espattach(esc, &esp_sbus_glue); 296 297 return; 298 } 299 300 /* 301 * Find the DMA by poking around the dma device structures 302 * 303 * What happens here is that if the dma driver has not been 304 * configured, then this returns a NULL pointer. Then when the 305 * dma actually gets configured, it does the opposing test, and 306 * if the sc->sc_esp field in it's softc is NULL, then tries to 307 * find the matching esp driver. 308 */ 309 esc->sc_dma = (struct lsi64854_softc *) 310 getdevunit("dma", device_unit(&sc->sc_dev)); 311 312 /* 313 * and a back pointer to us, for DMA 314 */ 315 if (esc->sc_dma) 316 esc->sc_dma->sc_client = sc; 317 else { 318 printf("\n"); 319 panic("espattach: no dma found"); 320 } 321 322 /* 323 * The `ESC' DMA chip must be reset before we can access 324 * the esp registers. 325 */ 326 if (esc->sc_dma->sc_rev == DMAREV_ESC) 327 DMA_RESET(esc->sc_dma); 328 329 /* 330 * Map my registers in, if they aren't already in virtual 331 * address space. 332 */ 333 if (sa->sa_npromvaddrs) { 334 sbus_promaddr_to_handle(sa->sa_bustag, 335 sa->sa_promvaddrs[0], &esc->sc_reg); 336 } else { 337 if (sbus_bus_map(sa->sa_bustag, 338 sa->sa_slot, sa->sa_offset, sa->sa_size, 339 0, &esc->sc_reg) != 0) { 340 printf("%s @ sbus: cannot map registers\n", 341 self->dv_xname); 342 return; 343 } 344 } 345 346 if (sa->sa_nintr == 0) { 347 /* 348 * No interrupt properties: we quit; this might 349 * happen on e.g. a Sparc X terminal. 350 */ 351 printf("\n%s: no interrupt property\n", self->dv_xname); 352 return; 353 } 354 355 esc->sc_pri = sa->sa_pri; 356 357 /* add me to the sbus structures */ 358 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 359 sbus_establish(&esc->sc_sd, &sc->sc_dev); 360 361 if (strcmp("ptscII", sa->sa_name) == 0) { 362 espattach(esc, &esp_sbus_glue1); 363 } else { 364 espattach(esc, &esp_sbus_glue); 365 } 366 } 367 368 void 369 espattach_dma(parent, self, aux) 370 struct device *parent, *self; 371 void *aux; 372 { 373 struct esp_softc *esc = (void *)self; 374 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 375 struct sbus_attach_args *sa = aux; 376 377 if (strcmp("ptscII", sa->sa_name) == 0) { 378 return; 379 } 380 381 esc->sc_bustag = sa->sa_bustag; 382 esc->sc_dmatag = sa->sa_dmatag; 383 384 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7); 385 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1); 386 387 esc->sc_dma = (struct lsi64854_softc *)parent; 388 esc->sc_dma->sc_client = sc; 389 390 /* 391 * Map my registers in, if they aren't already in virtual 392 * address space. 393 */ 394 if (sa->sa_npromvaddrs) { 395 sbus_promaddr_to_handle(sa->sa_bustag, 396 sa->sa_promvaddrs[0], &esc->sc_reg); 397 } else { 398 if (sbus_bus_map(sa->sa_bustag, 399 sa->sa_slot, sa->sa_offset, sa->sa_size, 400 0, &esc->sc_reg) != 0) { 401 printf("%s @ dma: cannot map registers\n", 402 self->dv_xname); 403 return; 404 } 405 } 406 407 if (sa->sa_nintr == 0) { 408 /* 409 * No interrupt properties: we quit; this might 410 * happen on e.g. a Sparc X terminal. 411 */ 412 printf("\n%s: no interrupt property\n", self->dv_xname); 413 return; 414 } 415 416 esc->sc_pri = sa->sa_pri; 417 418 /* Assume SBus is grandparent */ 419 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 420 sbus_establish(&esc->sc_sd, parent); 421 422 espattach(esc, &esp_sbus_glue); 423 } 424 425 426 /* 427 * Attach this instance, and then all the sub-devices 428 */ 429 void 430 espattach(esc, gluep) 431 struct esp_softc *esc; 432 struct ncr53c9x_glue *gluep; 433 { 434 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 435 void *icookie; 436 unsigned int uid = 0; 437 438 /* 439 * Set up glue for MI code early; we use some of it here. 440 */ 441 sc->sc_glue = gluep; 442 443 /* gimme MHz */ 444 sc->sc_freq /= 1000000; 445 446 /* 447 * XXX More of this should be in ncr53c9x_attach(), but 448 * XXX should we really poke around the chip that much in 449 * XXX the MI code? Think about this more... 450 */ 451 452 /* 453 * It is necessary to try to load the 2nd config register here, 454 * to find out what rev the esp chip is, else the ncr53c9x_reset 455 * will not set up the defaults correctly. 456 */ 457 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 458 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 459 sc->sc_cfg3 = NCRCFG3_CDB; 460 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 461 462 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 463 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 464 sc->sc_rev = NCR_VARIANT_ESP100; 465 } else { 466 sc->sc_cfg2 = NCRCFG2_SCSI2; 467 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 468 sc->sc_cfg3 = 0; 469 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 470 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 471 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 472 if (NCR_READ_REG(sc, NCR_CFG3) != 473 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 474 sc->sc_rev = NCR_VARIANT_ESP100A; 475 } else { 476 /* NCRCFG2_FE enables > 64K transfers */ 477 sc->sc_cfg2 |= NCRCFG2_FE; 478 sc->sc_cfg3 = 0; 479 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 480 sc->sc_rev = NCR_VARIANT_ESP200; 481 482 /* XXX spec says it's valid after power up or chip reset */ 483 uid = NCR_READ_REG(sc, NCR_UID); 484 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 485 sc->sc_rev = NCR_VARIANT_FAS366; 486 } 487 } 488 489 #ifdef ESP_SBUS_DEBUG 490 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 491 #endif 492 493 /* 494 * XXX minsync and maxxfer _should_ be set up in MI code, 495 * XXX but it appears to have some dependency on what sort 496 * XXX of DMA we're hooked up to, etc. 497 */ 498 499 /* 500 * This is the value used to start sync negotiations 501 * Note that the NCR register "SYNCTP" is programmed 502 * in "clocks per byte", and has a minimum value of 4. 503 * The SCSI period used in negotiation is one-fourth 504 * of the time (in nanoseconds) needed to transfer one byte. 505 * Since the chip's clock is given in MHz, we have the following 506 * formula: 4 * period = (1000 / freq) * 4 507 */ 508 sc->sc_minsync = 1000 / sc->sc_freq; 509 510 /* 511 * Alas, we must now modify the value a bit, because it's 512 * only valid when can switch on FASTCLK and FASTSCSI bits 513 * in config register 3... 514 */ 515 switch (sc->sc_rev) { 516 case NCR_VARIANT_ESP100: 517 sc->sc_maxxfer = 64 * 1024; 518 sc->sc_minsync = 0; /* No synch on old chip? */ 519 break; 520 521 case NCR_VARIANT_ESP100A: 522 sc->sc_maxxfer = 64 * 1024; 523 /* Min clocks/byte is 5 */ 524 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 525 break; 526 527 case NCR_VARIANT_ESP200: 528 case NCR_VARIANT_FAS366: 529 sc->sc_maxxfer = 16 * 1024 * 1024; 530 /* XXX - do actually set FAST* bits */ 531 break; 532 } 533 534 /* Establish interrupt channel */ 535 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 536 ncr53c9x_intr, sc); 537 538 /* register interrupt stats */ 539 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 540 sc->sc_dev.dv_xname, "intr"); 541 542 /* Turn on target selection using the `dma' method */ 543 if (sc->sc_rev != NCR_VARIANT_FAS366) 544 sc->sc_features |= NCR_F_DMASELECT; 545 546 /* Do the common parts of attachment. */ 547 sc->sc_adapter.adapt_minphys = minphys; 548 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 549 ncr53c9x_attach(sc); 550 551 } 552 553 /* 554 * Glue functions. 555 */ 556 557 #ifdef ESP_SBUS_DEBUG 558 int esp_sbus_debug = 0; 559 560 static struct { 561 char *r_name; 562 int r_flag; 563 } esp__read_regnames [] = { 564 { "TCL", 0}, /* 0/00 */ 565 { "TCM", 0}, /* 1/04 */ 566 { "FIFO", 0}, /* 2/08 */ 567 { "CMD", 0}, /* 3/0c */ 568 { "STAT", 0}, /* 4/10 */ 569 { "INTR", 0}, /* 5/14 */ 570 { "STEP", 0}, /* 6/18 */ 571 { "FFLAGS", 1}, /* 7/1c */ 572 { "CFG1", 1}, /* 8/20 */ 573 { "STAT2", 0}, /* 9/24 */ 574 { "CFG4", 1}, /* a/28 */ 575 { "CFG2", 1}, /* b/2c */ 576 { "CFG3", 1}, /* c/30 */ 577 { "-none", 1}, /* d/34 */ 578 { "TCH", 1}, /* e/38 */ 579 { "TCX", 1}, /* f/3c */ 580 }; 581 582 static struct { 583 char *r_name; 584 int r_flag; 585 } esp__write_regnames[] = { 586 { "TCL", 1}, /* 0/00 */ 587 { "TCM", 1}, /* 1/04 */ 588 { "FIFO", 0}, /* 2/08 */ 589 { "CMD", 0}, /* 3/0c */ 590 { "SELID", 1}, /* 4/10 */ 591 { "TIMEOUT", 1}, /* 5/14 */ 592 { "SYNCTP", 1}, /* 6/18 */ 593 { "SYNCOFF", 1}, /* 7/1c */ 594 { "CFG1", 1}, /* 8/20 */ 595 { "CCF", 1}, /* 9/24 */ 596 { "TEST", 1}, /* a/28 */ 597 { "CFG2", 1}, /* b/2c */ 598 { "CFG3", 1}, /* c/30 */ 599 { "-none", 1}, /* d/34 */ 600 { "TCH", 1}, /* e/38 */ 601 { "TCX", 1}, /* f/3c */ 602 }; 603 #endif 604 605 u_char 606 esp_read_reg(sc, reg) 607 struct ncr53c9x_softc *sc; 608 int reg; 609 { 610 struct esp_softc *esc = (struct esp_softc *)sc; 611 u_char v; 612 613 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 614 #ifdef ESP_SBUS_DEBUG 615 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 616 printf("RD:%x <%s> %x\n", reg * 4, 617 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 618 #endif 619 return v; 620 } 621 622 void 623 esp_write_reg(sc, reg, v) 624 struct ncr53c9x_softc *sc; 625 int reg; 626 u_char v; 627 { 628 struct esp_softc *esc = (struct esp_softc *)sc; 629 630 #ifdef ESP_SBUS_DEBUG 631 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 632 printf("WR:%x <%s> %x\n", reg * 4, 633 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 634 #endif 635 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 636 } 637 638 u_char 639 esp_rdreg1(sc, reg) 640 struct ncr53c9x_softc *sc; 641 int reg; 642 { 643 struct esp_softc *esc = (struct esp_softc *)sc; 644 645 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 646 } 647 648 void 649 esp_wrreg1(sc, reg, v) 650 struct ncr53c9x_softc *sc; 651 int reg; 652 u_char v; 653 { 654 struct esp_softc *esc = (struct esp_softc *)sc; 655 656 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 657 } 658 659 int 660 esp_dma_isintr(sc) 661 struct ncr53c9x_softc *sc; 662 { 663 struct esp_softc *esc = (struct esp_softc *)sc; 664 665 return (DMA_ISINTR(esc->sc_dma)); 666 } 667 668 void 669 esp_dma_reset(sc) 670 struct ncr53c9x_softc *sc; 671 { 672 struct esp_softc *esc = (struct esp_softc *)sc; 673 674 DMA_RESET(esc->sc_dma); 675 } 676 677 int 678 esp_dma_intr(sc) 679 struct ncr53c9x_softc *sc; 680 { 681 struct esp_softc *esc = (struct esp_softc *)sc; 682 683 return (DMA_INTR(esc->sc_dma)); 684 } 685 686 int 687 esp_dma_setup(sc, addr, len, datain, dmasize) 688 struct ncr53c9x_softc *sc; 689 void **addr; 690 size_t *len; 691 int datain; 692 size_t *dmasize; 693 { 694 struct esp_softc *esc = (struct esp_softc *)sc; 695 696 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 697 } 698 699 void 700 esp_dma_go(sc) 701 struct ncr53c9x_softc *sc; 702 { 703 struct esp_softc *esc = (struct esp_softc *)sc; 704 705 DMA_GO(esc->sc_dma); 706 } 707 708 void 709 esp_dma_stop(sc) 710 struct ncr53c9x_softc *sc; 711 { 712 struct esp_softc *esc = (struct esp_softc *)sc; 713 u_int32_t csr; 714 715 csr = L64854_GCSR(esc->sc_dma); 716 csr &= ~D_EN_DMA; 717 L64854_SCSR(esc->sc_dma, csr); 718 } 719 720 int 721 esp_dma_isactive(sc) 722 struct ncr53c9x_softc *sc; 723 { 724 struct esp_softc *esc = (struct esp_softc *)sc; 725 726 return (DMA_ISACTIVE(esc->sc_dma)); 727 } 728 729 #ifdef DDB 730 #include <machine/db_machdep.h> 731 #include <ddb/db_output.h> 732 #include <ddb/db_command.h> 733 734 void db_esp(db_expr_t, bool, db_expr_t, const char*); 735 736 const struct db_command db_esp_command_table[] = { 737 { DDB_ADD_CMD("esp", db_esp, 0, 738 "display status of all esp SCSI controllers and their devices", 739 NULL, NULL) }, 740 { DDB_ADD_CMD(NULL, NULL, 0, NULL, NULL, NULL) } 741 }; 742 743 static void 744 esp_init_ddb_cmds() 745 { 746 static int db_cmds_initialized = 0; 747 748 if (db_cmds_initialized) return; 749 db_cmds_initialized = 1; 750 (void)db_register_tbl(DDB_MACH_CMD, db_esp_command_table); 751 } 752 753 void 754 db_esp(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 755 { 756 struct ncr53c9x_softc *sc; 757 struct ncr53c9x_ecb *ecb; 758 struct ncr53c9x_linfo *li; 759 int u, t, i; 760 761 for (u=0; u<10; u++) { 762 sc = (struct ncr53c9x_softc *) 763 getdevunit("esp", u); 764 if (!sc) continue; 765 766 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 767 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 768 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 769 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 770 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 771 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 772 sc->sc_imess[0]); 773 db_printf("ready: "); 774 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 775 db_printf("ecb %p ", ecb); 776 if (ecb == ecb->chain.tqe_next) { 777 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 778 break; 779 } 780 } 781 db_printf("\n"); 782 783 for (t=0; t<sc->sc_ntarg; t++) { 784 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 785 db_printf("t%d lun %d untagged %p busy %d used %x\n", 786 t, (int)li->lun, li->untagged, li->busy, 787 li->used); 788 for (i=0; i<256; i++) 789 if ((ecb = li->queued[i])) { 790 db_printf("ecb %p tag %x\n", ecb, i); 791 } 792 } 793 } 794 } 795 } 796 #endif 797 798