1 /* $NetBSD: dbri.c,v 1.35 2013/10/19 21:00:32 mrg Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.35 2013/10/19 21:00:32 mrg Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 #include <sys/kmem.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(device_t, device_t, void *); 97 static int dbri_match_sbus(device_t, cfdata_t, void *); 98 99 static int dbri_config_interrupts(device_t); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile uint32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **); 160 161 static void *dbri_malloc(void *, int, size_t); 162 static void dbri_free(void *, void *, size_t); 163 static paddr_t dbri_mappage(void *, void *, off_t, int); 164 static void dbri_set_power(struct dbri_softc *, int); 165 static void dbri_bring_up(struct dbri_softc *); 166 static bool dbri_suspend(device_t, const pmf_qual_t *); 167 static bool dbri_resume(device_t, const pmf_qual_t *); 168 169 /* stupid support routines */ 170 static uint32_t reverse_bytes(uint32_t, int); 171 172 struct audio_device dbri_device = { 173 "CS4215", 174 "", 175 "dbri" 176 }; 177 178 struct audio_hw_if dbri_hw_if = { 179 .open = dbri_open, 180 .close = dbri_close, 181 .query_encoding = dbri_query_encoding, 182 .set_params = dbri_set_params, 183 .round_blocksize = dbri_round_blocksize, 184 .halt_output = dbri_halt_output, 185 .halt_input = dbri_halt_input, 186 .getdev = dbri_getdev, 187 .set_port = dbri_set_port, 188 .get_port = dbri_get_port, 189 .query_devinfo = dbri_query_devinfo, 190 .allocm = dbri_malloc, 191 .freem = dbri_free, 192 .round_buffersize = dbri_round_buffersize, 193 .mappage = dbri_mappage, 194 .get_props = dbri_get_props, 195 .trigger_output = dbri_trigger_output, 196 .trigger_input = dbri_trigger_input, 197 .get_locks = dbri_get_locks, 198 }; 199 200 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 201 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 202 203 #define DBRI_NFORMATS 4 204 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 205 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 206 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 207 48000}}, 208 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 209 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 210 48000}}, 211 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 212 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 213 48000}}, 214 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 215 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 216 48000}},*/ 217 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 218 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 219 48000}}, 220 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 221 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 222 48000}}, 223 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 224 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 225 48000}}, 226 }; 227 228 enum { 229 DBRI_OUTPUT_CLASS, 230 DBRI_VOL_OUTPUT, 231 DBRI_ENABLE_MONO, 232 DBRI_ENABLE_HEADPHONE, 233 DBRI_ENABLE_LINE, 234 DBRI_MONITOR_CLASS, 235 DBRI_VOL_MONITOR, 236 DBRI_INPUT_CLASS, 237 DBRI_INPUT_GAIN, 238 DBRI_INPUT_SELECT, 239 DBRI_RECORD_CLASS, 240 DBRI_ENUM_LAST 241 }; 242 243 /* 244 * Autoconfig routines 245 */ 246 static int 247 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 248 { 249 struct sbus_attach_args *sa = aux; 250 char *ver; 251 int i; 252 253 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 254 return (0); 255 256 ver = &sa->sa_name[9]; 257 258 for (i = 0; dbri_supported[i][0] != '\0'; i++) 259 if (strcmp(dbri_supported[i], ver) == 0) 260 return (1); 261 262 return (0); 263 } 264 265 static void 266 dbri_attach_sbus(device_t parent, device_t self, void *aux) 267 { 268 struct dbri_softc *sc = device_private(self); 269 struct sbus_attach_args *sa = aux; 270 bus_space_handle_t ioh; 271 bus_size_t size; 272 int error, rseg, pwr, i; 273 char *ver = &sa->sa_name[9]; 274 275 sc->sc_dev = self; 276 sc->sc_iot = sa->sa_bustag; 277 sc->sc_dmat = sa->sa_dmatag; 278 sc->sc_powerstate = 1; 279 280 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 281 aprint_normal(": rev %s\n", ver); 282 283 if (pwr) { 284 /* 285 * we can control DBRI power via auxio and we're initially 286 * powered down 287 */ 288 289 sc->sc_have_powerctl = 1; 290 sc->sc_powerstate = 0; 291 dbri_set_power(sc, 1); 292 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 293 aprint_error_dev(self, 294 "cannot set power mgmt handler\n"); 295 } 296 } else { 297 /* we can't control power so we're always up */ 298 sc->sc_have_powerctl = 0; 299 sc->sc_powerstate = 1; 300 } 301 302 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 303 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 304 dbri_softint, &sc->sc_desc[i]); 305 } 306 307 if (sa->sa_npromvaddrs) 308 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 309 else { 310 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 311 sa->sa_offset, sa->sa_size, 312 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 313 aprint_error("%s @ sbus: cannot map registers\n", 314 device_xname(self)); 315 return; 316 } 317 } 318 319 sc->sc_ioh = ioh; 320 321 size = sizeof(struct dbri_dma); 322 323 /* get a DMA handle */ 324 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 325 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 326 aprint_error_dev(self, "DMA map create error %d\n", 327 error); 328 return; 329 } 330 331 /* allocate DMA buffer */ 332 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 333 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 334 aprint_error_dev(self, "DMA buffer alloc error %d\n", 335 error); 336 return; 337 } 338 339 /* map DMA buffer into CPU addressable space */ 340 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 341 &sc->sc_membase, 342 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 343 aprint_error_dev(self, "DMA buffer map error %d\n", 344 error); 345 return; 346 } 347 348 /* load the buffer */ 349 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 350 sc->sc_membase, size, NULL, 351 BUS_DMA_NOWAIT)) != 0) { 352 aprint_error_dev(self, "DMA buffer map load error %d\n", 353 error); 354 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 355 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 356 return; 357 } 358 359 /* map the registers into memory */ 360 361 /* kernel virtual address of DMA buffer */ 362 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 363 /* physical address of DMA buffer */ 364 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 365 sc->sc_bufsiz = size; 366 367 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 368 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 369 370 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 371 sc); 372 373 sc->sc_locked = 0; 374 sc->sc_desc_used = 0; 375 sc->sc_refcount = 0; 376 sc->sc_playing = 0; 377 sc->sc_recording = 0; 378 sc->sc_init_done = 0; 379 config_finalize_register(self, &dbri_config_interrupts); 380 381 return; 382 } 383 384 /* 385 * lowlevel routine to switch power for the DBRI chip 386 */ 387 static void 388 dbri_set_power(struct dbri_softc *sc, int state) 389 { 390 int s; 391 392 if (sc->sc_have_powerctl == 0) 393 return; 394 if (sc->sc_powerstate == state) 395 return; 396 397 if (state) { 398 DPRINTF("%s: waiting to power up... ", 399 device_xname(sc->sc_dev)); 400 s = splhigh(); 401 *AUXIO4M_REG |= (AUXIO4M_MMX); 402 splx(s); 403 delay(10000); 404 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 405 } else { 406 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 407 s = splhigh(); 408 *AUXIO4M_REG &= ~AUXIO4M_MMX; 409 splx(s); 410 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 411 } 412 sc->sc_powerstate = state; 413 } 414 415 /* 416 * power up and re-initialize the chip 417 */ 418 static void 419 dbri_bring_up(struct dbri_softc *sc) 420 { 421 422 if (sc->sc_have_powerctl == 0) 423 return; 424 425 if (sc->sc_powerstate == 1) 426 return; 427 428 /* ok, we really need to do something */ 429 dbri_set_power(sc, 1); 430 431 /* 432 * re-initialize the chip but skip all the probing, don't overwrite 433 * any other settings either 434 */ 435 dbri_init(sc); 436 mmcodec_setgain(sc, 1); 437 mmcodec_pipe_init(sc); 438 mmcodec_init_data(sc); 439 mmcodec_setgain(sc, 0); 440 } 441 442 static int 443 dbri_config_interrupts(device_t dev) 444 { 445 struct dbri_softc *sc = device_private(dev); 446 447 if (sc->sc_init_done != 0) 448 return 0; 449 450 sc->sc_init_done = 1; 451 452 dbri_init(sc); 453 if (mmcodec_init(sc) == -1) { 454 printf("%s: no codec detected, aborting\n", 455 device_xname(dev)); 456 return 0; 457 } 458 459 /* Attach ourselves to the high level audio interface */ 460 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 461 462 /* power down until open() */ 463 dbri_set_power(sc, 0); 464 return 0; 465 } 466 467 static int 468 dbri_intr(void *hdl) 469 { 470 struct dbri_softc *sc = hdl; 471 bus_space_tag_t iot = sc->sc_iot; 472 bus_space_handle_t ioh = sc->sc_ioh; 473 int x; 474 475 mutex_spin_enter(&sc->sc_intr_lock); 476 477 /* clear interrupt */ 478 x = bus_space_read_4(iot, ioh, DBRI_REG1); 479 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 480 uint32_t tmp; 481 482 if (x & DBRI_MRR) 483 aprint_debug_dev(sc->sc_dev, 484 "multiple ack error on sbus\n"); 485 if (x & DBRI_MLE) 486 aprint_debug_dev(sc->sc_dev, 487 "multiple late error on sbus\n"); 488 if (x & DBRI_LBG) 489 aprint_debug_dev(sc->sc_dev, 490 "lost bus grant on sbus\n"); 491 if (x & DBRI_MBE) 492 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 493 494 /* 495 * Some of these errors disable the chip's circuitry. 496 * Re-enable the circuitry and keep on going. 497 */ 498 499 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 500 tmp &= ~(DBRI_DISABLE_MASTER); 501 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 502 } 503 504 #if 0 505 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 506 return (1); 507 #endif 508 509 dbri_process_interrupt_buffer(sc); 510 511 mutex_spin_exit(&sc->sc_intr_lock); 512 513 return (1); 514 } 515 516 static void 517 dbri_softint(void *cookie) 518 { 519 struct dbri_desc *dd = cookie; 520 521 if (dd->callback != NULL) 522 dd->callback(dd->callback_args); 523 } 524 525 static int 526 dbri_init(struct dbri_softc *sc) 527 { 528 bus_space_tag_t iot = sc->sc_iot; 529 bus_space_handle_t ioh = sc->sc_ioh; 530 uint32_t reg; 531 volatile uint32_t *cmd; 532 bus_addr_t dmaaddr; 533 int n; 534 535 dbri_reset(sc); 536 537 cmd = dbri_command_lock(sc); 538 539 /* XXX: Initialize interrupt ring buffer */ 540 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 541 sc->sc_irqp = 1; 542 543 /* Initialize pipes */ 544 for (n = 0; n < DBRI_PIPE_MAX; n++) 545 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 546 547 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 548 sc->sc_dma->intr[n] = 0; 549 } 550 551 /* Disable all SBus bursts */ 552 /* XXX 16 byte bursts cause errors, the rest works */ 553 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 554 555 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 556 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 557 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 558 559 /* setup interrupt queue */ 560 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 561 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 562 *(cmd++) = dmaaddr; 563 564 dbri_command_send(sc, cmd); 565 return (0); 566 } 567 568 static int 569 dbri_reset(struct dbri_softc *sc) 570 { 571 int bail = 0; 572 573 bus_space_tag_t iot = sc->sc_iot; 574 bus_space_handle_t ioh = sc->sc_ioh; 575 576 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 577 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 578 (bail < 100000)) { 579 bail++; 580 delay(10); 581 } 582 if (bail == 100000) 583 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 584 return (0); 585 } 586 587 static volatile uint32_t * 588 dbri_command_lock(struct dbri_softc *sc) 589 { 590 591 if (sc->sc_locked) 592 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 593 594 sc->sc_locked++; 595 596 return (&sc->sc_dma->command[0]); 597 } 598 599 static void 600 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 601 { 602 bus_space_handle_t ioh = sc->sc_ioh; 603 bus_space_tag_t iot = sc->sc_iot; 604 int maxloops = 1000000; 605 606 mutex_spin_enter(&sc->sc_intr_lock); 607 608 sc->sc_locked--; 609 610 if (sc->sc_locked != 0) { 611 aprint_error_dev(sc->sc_dev, 612 "command buffer improperly locked\n"); 613 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 614 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 615 } else { 616 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 617 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 618 sc->sc_waitseen = 0; 619 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 620 while ((--maxloops) > 0 && 621 (bus_space_read_4(iot, ioh, DBRI_REG0) 622 & DBRI_COMMAND_VALID)) { 623 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 624 BUS_SPACE_BARRIER_READ); 625 delay(1000); 626 } 627 628 if (maxloops == 0) { 629 aprint_error_dev(sc->sc_dev, 630 "chip never completed command buffer\n"); 631 } else { 632 633 DPRINTF("%s: command completed\n", 634 device_xname(sc->sc_dev)); 635 636 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 637 dbri_process_interrupt_buffer(sc); 638 if (maxloops == 0) { 639 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 640 } 641 } 642 } 643 644 mutex_spin_exit(&sc->sc_intr_lock); 645 646 return; 647 } 648 649 static void 650 dbri_process_interrupt_buffer(struct dbri_softc *sc) 651 { 652 int32_t i; 653 654 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 655 sc->sc_dma->intr[sc->sc_irqp] = 0; 656 sc->sc_irqp++; 657 658 if (sc->sc_irqp == DBRI_INT_BLOCKS) 659 sc->sc_irqp = 1; 660 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 661 sc->sc_irqp++; 662 663 dbri_process_interrupt(sc, i); 664 } 665 666 return; 667 } 668 669 static void 670 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 671 { 672 #if 0 673 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 674 #endif 675 int val = DBRI_INTR_GETVAL(i); 676 int channel = DBRI_INTR_GETCHAN(i); 677 int command = DBRI_INTR_GETCMD(i); 678 int code = DBRI_INTR_GETCODE(i); 679 #if 0 680 int rval = DBRI_INTR_GETRVAL(i); 681 #endif 682 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 683 sc->sc_waitseen++; 684 685 switch (code) { 686 case DBRI_INTR_XCMP: /* transmission complete */ 687 { 688 int td; 689 struct dbri_desc *dd; 690 691 td = sc->sc_pipe[channel].desc; 692 dd = &sc->sc_desc[td]; 693 694 if (dd->callback != NULL) 695 softint_schedule(dd->softint); 696 break; 697 } 698 case DBRI_INTR_FXDT: /* fixed data change */ 699 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 700 val); 701 #if 0 702 printf("reg: %08x\n", sc->sc_mm.status); 703 #endif 704 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 705 val = reverse_bytes(val, sc->sc_pipe[channel].length); 706 if (sc->sc_pipe[channel].prec) 707 *(sc->sc_pipe[channel].prec) = val; 708 #ifndef DBRI_SPIN 709 DPRINTF("%s: wakeup %p\n", device_xname(sc->sc_dev), sc); 710 wakeup(sc); 711 #endif 712 break; 713 case DBRI_INTR_SBRI: 714 DPRINTF("dbri_intr: SBRI\n"); 715 break; 716 case DBRI_INTR_BRDY: 717 { 718 int td; 719 struct dbri_desc *dd; 720 721 td = sc->sc_pipe[channel].desc; 722 dd = &sc->sc_desc[td]; 723 724 if (dd->callback != NULL) 725 softint_schedule(dd->softint); 726 break; 727 } 728 case DBRI_INTR_UNDR: 729 { 730 volatile uint32_t *cmd; 731 int td = sc->sc_pipe[channel].desc; 732 733 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 734 735 sc->sc_dma->xmit[td].status = 0; 736 737 cmd = dbri_command_lock(sc); 738 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 739 sc->sc_pipe[channel].sdp | 740 DBRI_SDP_VALID_POINTER | 741 DBRI_SDP_CLEAR | 742 DBRI_SDP_2SAME); 743 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 744 dbri_command_send(sc, cmd); 745 break; 746 } 747 case DBRI_INTR_CMDI: 748 DPRINTF("ok"); 749 break; 750 default: 751 752 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 753 code); 754 break; 755 } 756 757 return; 758 } 759 760 /* 761 * mmcodec stuff 762 */ 763 764 static int 765 mmcodec_init(struct dbri_softc *sc) 766 { 767 bus_space_handle_t ioh = sc->sc_ioh; 768 bus_space_tag_t iot = sc->sc_iot; 769 uint32_t reg2; 770 int bail; 771 772 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 773 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 774 775 if (reg2 & DBRI_PIO2) { 776 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 777 sc->sc_mm.onboard = 1; 778 } 779 780 if (reg2 & DBRI_PIO0) { 781 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 782 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 783 sc->sc_mm.onboard = 0; 784 } 785 786 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 787 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 788 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 789 sc->sc_mm.onboard = 0; 790 } 791 792 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 793 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 794 return -1; 795 } 796 797 sc->sc_version = 0xff; 798 799 mmcodec_pipe_init(sc); 800 mmcodec_default(sc); 801 802 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 803 804 /* 805 * mmcodec_setcontrol() sometimes fails right after powerup 806 * so we just try again until we either get a useful response or run 807 * out of time 808 */ 809 bail = 0; 810 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 811 812 bail++; 813 if (bail > 100) { 814 DPRINTF("%s: cs4215 probe failed at offset %d\n", 815 device_xname(sc->sc_dev), sc->sc_mm.offset); 816 return (-1); 817 } 818 delay(10000); 819 } 820 821 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 822 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 823 824 /* set some sane defaults for mmcodec_init_data */ 825 sc->sc_params.channels = 2; 826 sc->sc_params.precision = 16; 827 828 mmcodec_init_data(sc); 829 830 return (0); 831 } 832 833 static void 834 mmcodec_init_data(struct dbri_softc *sc) 835 { 836 bus_space_tag_t iot = sc->sc_iot; 837 bus_space_handle_t ioh = sc->sc_ioh; 838 uint32_t tmp; 839 int data_width; 840 841 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 842 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 843 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 844 845 /* switch CS4215 to data mode - set PIO3 to 1 */ 846 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 847 848 /* XXX */ 849 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 850 851 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 852 chi_reset(sc, CHIslave, 128); 853 854 data_width = sc->sc_params.channels * sc->sc_params.precision; 855 856 if ((data_width != 32) && (data_width != 8)) 857 aprint_error("%s: data_width is %d\n", __func__, data_width); 858 859 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 860 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 861 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 862 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 863 864 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 865 866 mmcodec_setgain(sc, 0); 867 868 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 869 tmp |= DBRI_CHI_ACTIVATE; 870 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 871 872 return; 873 } 874 875 static void 876 mmcodec_pipe_init(struct dbri_softc *sc) 877 { 878 879 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 880 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 881 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 882 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 883 884 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 885 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 886 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 887 888 sc->sc_mm.status = 0; 889 890 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 891 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 892 893 return; 894 } 895 896 static void 897 mmcodec_default(struct dbri_softc *sc) 898 { 899 struct cs4215_state *mm = &sc->sc_mm; 900 901 /* 902 * no action, memory resetting only 903 * 904 * data time slots 5-8 905 * speaker, line and headphone enable. set gain to half. 906 * input is line 907 */ 908 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 909 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 910 sc->sc_linp = 128; 911 sc->sc_rinp = 128; 912 sc->sc_monitor = 0; 913 sc->sc_input = 1; /* line */ 914 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 915 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 916 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 917 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 918 919 920 /* 921 * control time slots 1-4 922 * 923 * 0: default I/O voltage scale 924 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 925 * 2: serial enable, CHI master, 128 bits per frame, clock 1 926 * 3: tests disabled 927 */ 928 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 929 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 930 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 931 mm->c.bcontrol[3] = 0; 932 933 return; 934 } 935 936 static void 937 mmcodec_setgain(struct dbri_softc *sc, int mute) 938 { 939 if (mute) { 940 /* disable all outputs, max. attenuation */ 941 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 942 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 943 } else { 944 945 sc->sc_mm.d.bdata[0] = sc->sc_latt; 946 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 947 } 948 949 /* input stuff */ 950 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 951 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 952 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 953 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 954 955 if (sc->sc_powerstate == 0) 956 return; 957 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 958 959 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 960 /* give the chip some time to execute the command */ 961 delay(250); 962 963 return; 964 } 965 966 static int 967 mmcodec_setcontrol(struct dbri_softc *sc) 968 { 969 bus_space_tag_t iot = sc->sc_iot; 970 bus_space_handle_t ioh = sc->sc_ioh; 971 uint32_t val; 972 uint32_t tmp; 973 int bail = 0; 974 #if DBRI_SPIN 975 int i; 976 #endif 977 978 /* 979 * Temporarily mute outputs and wait 125 us to make sure that it 980 * happens. This avoids clicking noises. 981 */ 982 mmcodec_setgain(sc, 1); 983 delay(125); 984 985 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 986 delay(125); 987 988 /* enable control mode */ 989 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 990 991 /* XXX */ 992 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 993 994 bus_space_write_4(iot, ioh, DBRI_REG2, val); 995 996 delay(34); 997 998 /* 999 * in control mode, the cs4215 is the slave device, so the 1000 * DBRI must act as the CHI master. 1001 * 1002 * in data mode, the cs4215 must be the CHI master to insure 1003 * that the data stream is in sync with its codec 1004 */ 1005 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1006 tmp &= ~DBRI_COMMAND_CHI; 1007 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1008 1009 chi_reset(sc, CHImaster, 128); 1010 1011 /* control mode */ 1012 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1013 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1014 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1015 1016 /* wait for the chip to echo back CLB as zero */ 1017 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1018 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1019 1020 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1021 tmp |= DBRI_CHI_ACTIVATE; 1022 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1023 1024 #if DBRI_SPIN 1025 i = 1024; 1026 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1027 delay(125); 1028 } 1029 1030 if (i == 0) { 1031 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1032 device_xname(sc->sc_dev), sc->sc_mm.status); 1033 return (-1); 1034 } 1035 #else 1036 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1037 DPRINTF("%s: tsleep %p\n", device_xname(sc->sc_dev), sc); 1038 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1039 bail++; 1040 } 1041 #endif 1042 if (bail >= 10) { 1043 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1044 device_xname(sc->sc_dev), sc->sc_mm.status, 1045 bus_space_read_4(iot, ioh, DBRI_REG2)); 1046 return -1; 1047 } 1048 1049 /* copy the version information before it becomes unreadable again */ 1050 sc->sc_version = sc->sc_mm.version; 1051 1052 /* terminate cs4215 control mode */ 1053 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1054 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1055 1056 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1057 delay(250); 1058 1059 mmcodec_setgain(sc, 0); 1060 1061 return (0); 1062 1063 } 1064 1065 /* 1066 * CHI combo 1067 */ 1068 static void 1069 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1070 { 1071 volatile uint32_t *cmd; 1072 int val; 1073 int clockrate, divisor; 1074 1075 cmd = dbri_command_lock(sc); 1076 1077 /* set CHI anchor: pipe 16 */ 1078 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1079 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1080 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1081 *(cmd++) = 0; 1082 1083 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1084 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1085 *(cmd++) = 0; 1086 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1087 1088 sc->sc_pipe[16].sdp = 1; 1089 sc->sc_pipe[16].next = 16; 1090 sc->sc_chi_pipe_in = 16; 1091 sc->sc_chi_pipe_out = 16; 1092 1093 switch (ms) { 1094 case CHIslave: 1095 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1096 break; 1097 case CHImaster: 1098 clockrate = bpf * 8; 1099 divisor = 12288 / clockrate; 1100 1101 if (divisor > 255 || divisor * clockrate != 12288) 1102 aprint_error_dev(sc->sc_dev, 1103 "illegal bits-per-frame %d\n", bpf); 1104 1105 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1106 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1107 break; 1108 default: 1109 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1110 break; 1111 } 1112 1113 sc->sc_chi_bpf = bpf; 1114 1115 /* CHI data mode */ 1116 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1117 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1118 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1119 1120 dbri_command_send(sc, cmd); 1121 1122 return; 1123 } 1124 1125 /* 1126 * pipe stuff 1127 */ 1128 static void 1129 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1130 { 1131 DPRINTF("pipe setup: %d\n", pipe); 1132 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1133 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1134 pipe); 1135 return; 1136 } 1137 1138 if ((sdp & 0xf800) != sdp) 1139 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1140 sdp); 1141 1142 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1143 !(sdp & DBRI_SDP_TO_SER)) 1144 sdp |= DBRI_SDP_CHANGE; 1145 1146 sdp |= DBRI_PIPE(pipe); 1147 1148 sc->sc_pipe[pipe].sdp = sdp; 1149 sc->sc_pipe[pipe].desc = -1; 1150 1151 pipe_reset(sc, pipe); 1152 1153 return; 1154 } 1155 1156 static void 1157 pipe_reset(struct dbri_softc *sc, int pipe) 1158 { 1159 struct dbri_desc *dd; 1160 int sdp; 1161 int desc; 1162 volatile uint32_t *cmd; 1163 1164 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1165 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1166 pipe); 1167 return; 1168 } 1169 1170 sdp = sc->sc_pipe[pipe].sdp; 1171 if (sdp == 0) { 1172 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1173 pipe); 1174 return; 1175 } 1176 1177 cmd = dbri_command_lock(sc); 1178 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1179 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1180 *(cmd++) = 0; 1181 dbri_command_send(sc, cmd); 1182 1183 desc = sc->sc_pipe[pipe].desc; 1184 1185 dd = &sc->sc_desc[desc]; 1186 1187 dd->busy = 0; 1188 1189 #if 0 1190 if (dd->callback) 1191 softint_schedule(dd->softint); 1192 #endif 1193 1194 sc->sc_pipe[pipe].desc = -1; 1195 1196 return; 1197 } 1198 1199 static void 1200 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1201 { 1202 1203 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1204 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1205 pipe); 1206 return; 1207 } 1208 1209 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1210 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1211 pipe); 1212 return; 1213 } 1214 1215 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1216 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1217 pipe); 1218 return; 1219 } 1220 1221 sc->sc_pipe[pipe].prec = prec; 1222 1223 return; 1224 } 1225 1226 static void 1227 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1228 { 1229 volatile uint32_t *cmd; 1230 1231 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1232 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1233 pipe); 1234 return; 1235 } 1236 1237 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1238 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1239 pipe); 1240 return; 1241 } 1242 1243 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1244 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1245 pipe); 1246 return; 1247 } 1248 1249 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1250 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1251 pipe); 1252 return; 1253 } 1254 1255 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1256 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1257 1258 cmd = dbri_command_lock(sc); 1259 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1260 *(cmd++) = data; 1261 1262 dbri_command_send(sc, cmd); 1263 1264 return; 1265 } 1266 1267 static void 1268 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1269 void (*callback)(void *), void *callback_args) 1270 { 1271 volatile uint32_t *cmd; 1272 int i; 1273 #if 0 1274 int td; 1275 int td_first, td_last; 1276 #endif 1277 bus_addr_t dmabuf, dmabase; 1278 struct dbri_desc *dd = &sc->sc_desc[which]; 1279 1280 switch (pipe) { 1281 case 4: 1282 /* output, offset 0 */ 1283 break; 1284 default: 1285 aprint_error("%s: illegal pipe number (%d)\n", 1286 __func__, pipe); 1287 return; 1288 } 1289 1290 #if 0 1291 td = 0; 1292 td_first = td_last = -1; 1293 #endif 1294 1295 if (sc->sc_pipe[pipe].sdp == 0) { 1296 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1297 pipe); 1298 return; 1299 } 1300 1301 dmabuf = dd->dmabase; 1302 dmabase = sc->sc_dmabase; 1303 1304 for (i = 0; i < (num - 1); i++) { 1305 1306 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1307 | TX_EOF | TX_BINT; 1308 sc->sc_dma->xmit[i].ba = dmabuf; 1309 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1310 sc->sc_dma->xmit[i].status = 0; 1311 1312 #if 0 1313 td_last = td; 1314 #endif 1315 dmabuf += blksz; 1316 } 1317 1318 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1319 1320 sc->sc_dma->xmit[i].ba = dmabuf; 1321 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1322 sc->sc_dma->xmit[i].status = 0; 1323 1324 dd->callback = callback; 1325 dd->callback_args = callback_args; 1326 1327 mutex_spin_enter(&sc->sc_intr_lock); 1328 1329 /* the pipe shouldn't be active */ 1330 if (pipe_active(sc, pipe)) { 1331 aprint_error("pipe active (CDP)\n"); 1332 /* pipe is already active */ 1333 #if 0 1334 td_last = sc->sc_pipe[pipe].desc; 1335 while (sc->sc_desc[td_last].next != -1) 1336 td_last = sc->sc_desc[td_last].next; 1337 1338 sc->sc_desc[td_last].next = td_first; 1339 sc->sc_dma->desc[td_last].nda = 1340 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1341 1342 cmd = dbri_command_lock(sc); 1343 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1344 dbri_command_send(sc, cmd); 1345 #endif 1346 } else { 1347 /* 1348 * pipe isn't active - issue an SDP command to start our 1349 * chain of TDs running 1350 */ 1351 sc->sc_pipe[pipe].desc = which; 1352 cmd = dbri_command_lock(sc); 1353 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1354 sc->sc_pipe[pipe].sdp | 1355 DBRI_SDP_VALID_POINTER | 1356 DBRI_SDP_EVERY | 1357 DBRI_SDP_CLEAR); 1358 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1359 dbri_command_send(sc, cmd); 1360 DPRINTF("%s: starting DMA\n", __func__); 1361 } 1362 1363 mutex_spin_exit(&sc->sc_intr_lock); 1364 1365 return; 1366 } 1367 1368 static void 1369 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1370 void (*callback)(void *), void *callback_args) 1371 { 1372 volatile uint32_t *cmd; 1373 int i; 1374 #if 0 1375 int td_first, td_last; 1376 #endif 1377 bus_addr_t dmabuf, dmabase; 1378 struct dbri_desc *dd = &sc->sc_desc[which]; 1379 1380 switch (pipe) { 1381 case 6: 1382 break; 1383 default: 1384 aprint_error("%s: illegal pipe number (%d)\n", 1385 __func__, pipe); 1386 return; 1387 } 1388 1389 #if 0 1390 td_first = td_last = -1; 1391 #endif 1392 1393 if (sc->sc_pipe[pipe].sdp == 0) { 1394 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1395 pipe); 1396 return; 1397 } 1398 1399 dmabuf = dd->dmabase; 1400 dmabase = sc->sc_dmabase; 1401 1402 for (i = 0; i < (num - 1); i++) { 1403 1404 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1405 sc->sc_dma->recv[i].ba = dmabuf; 1406 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1407 sc->sc_dma->recv[i].status = RX_EOF; 1408 1409 #if 0 1410 td_last = i; 1411 #endif 1412 dmabuf += blksz; 1413 } 1414 1415 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1416 1417 sc->sc_dma->recv[i].ba = dmabuf; 1418 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1419 sc->sc_dma->recv[i].status = RX_EOF; 1420 1421 dd->callback = callback; 1422 dd->callback_args = callback_args; 1423 1424 mutex_spin_enter(&sc->sc_intr_lock); 1425 1426 /* the pipe shouldn't be active */ 1427 if (pipe_active(sc, pipe)) { 1428 aprint_error("pipe active (CDP)\n"); 1429 /* pipe is already active */ 1430 #if 0 1431 td_last = sc->sc_pipe[pipe].desc; 1432 while (sc->sc_desc[td_last].next != -1) 1433 td_last = sc->sc_desc[td_last].next; 1434 1435 sc->sc_desc[td_last].next = td_first; 1436 sc->sc_dma->desc[td_last].nda = 1437 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1438 1439 cmd = dbri_command_lock(sc); 1440 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1441 dbri_command_send(sc, cmd); 1442 #endif 1443 } else { 1444 /* 1445 * pipe isn't active - issue an SDP command to start our 1446 * chain of TDs running 1447 */ 1448 sc->sc_pipe[pipe].desc = which; 1449 cmd = dbri_command_lock(sc); 1450 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1451 sc->sc_pipe[pipe].sdp | 1452 DBRI_SDP_VALID_POINTER | 1453 DBRI_SDP_EVERY | 1454 DBRI_SDP_CLEAR); 1455 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1456 dbri_command_send(sc, cmd); 1457 DPRINTF("%s: starting DMA\n", __func__); 1458 } 1459 1460 mutex_spin_exit(&sc->sc_intr_lock); 1461 1462 return; 1463 } 1464 1465 static void 1466 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1467 int len, int cycle) 1468 { 1469 volatile uint32_t *cmd; 1470 int prevpipe, nextpipe; 1471 int val; 1472 1473 DPRINTF("%s: %d\n", __func__, pipe); 1474 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1475 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1476 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1477 pipe, basepipe); 1478 return; 1479 } 1480 1481 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1482 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1483 pipe, basepipe); 1484 return; 1485 } 1486 1487 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1488 cycle = sc->sc_chi_bpf; 1489 1490 if (basepipe == pipe) 1491 prevpipe = nextpipe = pipe; 1492 else { 1493 if (basepipe == 16) { 1494 if (dir == PIPEinput) { 1495 prevpipe = sc->sc_chi_pipe_in; 1496 } else { 1497 prevpipe = sc->sc_chi_pipe_out; 1498 } 1499 } else 1500 prevpipe = basepipe; 1501 1502 nextpipe = sc->sc_pipe[prevpipe].next; 1503 1504 while (sc->sc_pipe[nextpipe].cycle < cycle && 1505 sc->sc_pipe[nextpipe].next != basepipe) { 1506 prevpipe = nextpipe; 1507 nextpipe = sc->sc_pipe[nextpipe].next; 1508 } 1509 } 1510 1511 if (prevpipe == 16) { 1512 if (dir == PIPEinput) { 1513 sc->sc_chi_pipe_in = pipe; 1514 } else { 1515 sc->sc_chi_pipe_out = pipe; 1516 } 1517 } else 1518 sc->sc_pipe[prevpipe].next = pipe; 1519 1520 sc->sc_pipe[pipe].next = nextpipe; 1521 sc->sc_pipe[pipe].cycle = cycle; 1522 sc->sc_pipe[pipe].length = len; 1523 1524 cmd = dbri_command_lock(sc); 1525 1526 switch (dir) { 1527 case PIPEinput: 1528 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1529 val |= pipe; 1530 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1531 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1532 DBRI_TS_NEXT(nextpipe); 1533 *(cmd++) = 0; 1534 break; 1535 case PIPEoutput: 1536 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1537 val |= pipe; 1538 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1539 *(cmd++) = 0; 1540 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1541 DBRI_TS_NEXT(nextpipe); 1542 break; 1543 default: 1544 DPRINTF("%s: should not have happened!\n", 1545 device_xname(sc->sc_dev)); 1546 break; 1547 } 1548 1549 dbri_command_send(sc, cmd); 1550 1551 return; 1552 } 1553 1554 static int 1555 pipe_active(struct dbri_softc *sc, int pipe) 1556 { 1557 1558 return (sc->sc_pipe[pipe].desc != -1); 1559 } 1560 1561 /* 1562 * subroutines required to interface with audio(9) 1563 */ 1564 1565 static int 1566 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1567 { 1568 1569 switch (ae->index) { 1570 case 0: 1571 strcpy(ae->name, AudioEulinear); 1572 ae->encoding = AUDIO_ENCODING_ULINEAR; 1573 ae->precision = 8; 1574 ae->flags = 0; 1575 break; 1576 case 1: 1577 strcpy(ae->name, AudioEmulaw); 1578 ae->encoding = AUDIO_ENCODING_ULAW; 1579 ae->precision = 8; 1580 ae->flags = 0; 1581 break; 1582 case 2: 1583 strcpy(ae->name, AudioEalaw); 1584 ae->encoding = AUDIO_ENCODING_ALAW; 1585 ae->precision = 8; 1586 ae->flags = 0; 1587 break; 1588 case 3: 1589 strcpy(ae->name, AudioEslinear); 1590 ae->encoding = AUDIO_ENCODING_SLINEAR; 1591 ae->precision = 8; 1592 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1593 break; 1594 case 4: 1595 strcpy(ae->name, AudioEslinear_le); 1596 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1597 ae->precision = 16; 1598 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1599 break; 1600 case 5: 1601 strcpy(ae->name, AudioEulinear_le); 1602 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1603 ae->precision = 16; 1604 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1605 break; 1606 case 6: 1607 strcpy(ae->name, AudioEslinear_be); 1608 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1609 ae->precision = 16; 1610 ae->flags = 0; 1611 break; 1612 case 7: 1613 strcpy(ae->name, AudioEulinear_be); 1614 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1615 ae->precision = 16; 1616 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1617 break; 1618 case 8: 1619 strcpy(ae->name, AudioEslinear); 1620 ae->encoding = AUDIO_ENCODING_SLINEAR; 1621 ae->precision = 16; 1622 ae->flags = 0; 1623 break; 1624 default: 1625 return (EINVAL); 1626 } 1627 1628 return (0); 1629 } 1630 1631 static int 1632 dbri_set_params(void *hdl, int setmode, int usemode, 1633 struct audio_params *play, struct audio_params *rec, 1634 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1635 { 1636 struct dbri_softc *sc = hdl; 1637 int rate; 1638 audio_params_t *p = NULL; 1639 stream_filter_list_t *fil; 1640 int mode; 1641 1642 /* 1643 * This device only has one clock, so make the sample rates match. 1644 */ 1645 if (play->sample_rate != rec->sample_rate && 1646 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1647 if (setmode == AUMODE_PLAY) { 1648 rec->sample_rate = play->sample_rate; 1649 setmode |= AUMODE_RECORD; 1650 } else if (setmode == AUMODE_RECORD) { 1651 play->sample_rate = rec->sample_rate; 1652 setmode |= AUMODE_PLAY; 1653 } else 1654 return EINVAL; 1655 } 1656 1657 for (mode = AUMODE_RECORD; mode != -1; 1658 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1659 if ((setmode & mode) == 0) 1660 continue; 1661 1662 p = mode == AUMODE_PLAY ? play : rec; 1663 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1664 DPRINTF("dbri_set_params: invalid rate %d\n", 1665 p->sample_rate); 1666 return EINVAL; 1667 } 1668 1669 fil = mode == AUMODE_PLAY ? pfil : rfil; 1670 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1671 p->sample_rate, p->precision, p->channels); 1672 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1673 mode, p, true, fil) < 0) { 1674 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1675 return EINVAL; 1676 } 1677 if (fil->req_size > 0) 1678 p = &fil->filters[0].param; 1679 } 1680 1681 if (p == NULL) { 1682 DPRINTF("dbri_set_params: no parameters to set\n"); 1683 return 0; 1684 } 1685 1686 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1687 p->sample_rate, p->precision, p->channels); 1688 1689 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1690 if (CS4215_FREQ[rate].freq == p->sample_rate) 1691 break; 1692 1693 if (CS4215_FREQ[rate].freq == 0) 1694 return (EINVAL); 1695 1696 /* set frequency */ 1697 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1698 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1699 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1700 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1701 1702 switch (p->encoding) { 1703 case AUDIO_ENCODING_ULAW: 1704 sc->sc_mm.c.bcontrol[1] &= ~3; 1705 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1706 break; 1707 case AUDIO_ENCODING_ALAW: 1708 sc->sc_mm.c.bcontrol[1] &= ~3; 1709 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1710 break; 1711 case AUDIO_ENCODING_ULINEAR: 1712 sc->sc_mm.c.bcontrol[1] &= ~3; 1713 if (p->precision == 8) { 1714 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1715 } else { 1716 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1717 } 1718 break; 1719 case AUDIO_ENCODING_SLINEAR_BE: 1720 case AUDIO_ENCODING_SLINEAR: 1721 sc->sc_mm.c.bcontrol[1] &= ~3; 1722 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1723 break; 1724 } 1725 1726 switch (p->channels) { 1727 case 1: 1728 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1729 break; 1730 case 2: 1731 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1732 break; 1733 } 1734 1735 return (0); 1736 } 1737 1738 static int 1739 dbri_round_blocksize(void *hdl, int bs, int mode, 1740 const audio_params_t *param) 1741 { 1742 1743 /* 1744 * DBRI DMA segment size can be up to 0x1fff, sixes that are not powers 1745 * of two seem to confuse the upper audio layer so we're going with 1746 * 0x1000 here 1747 */ 1748 return 0x1000; 1749 } 1750 1751 static int 1752 dbri_halt_output(void *hdl) 1753 { 1754 struct dbri_softc *sc = hdl; 1755 1756 if (!sc->sc_playing) 1757 return 0; 1758 1759 sc->sc_playing = 0; 1760 pipe_reset(sc, 4); 1761 return (0); 1762 } 1763 1764 static int 1765 dbri_getdev(void *hdl, struct audio_device *ret) 1766 { 1767 1768 *ret = dbri_device; 1769 return (0); 1770 } 1771 1772 static int 1773 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1774 { 1775 struct dbri_softc *sc = hdl; 1776 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1777 1778 switch (mc->dev) { 1779 case DBRI_VOL_OUTPUT: /* master volume */ 1780 latt = (latt & 0xc0) | (63 - 1781 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1782 ratt = (ratt & 0xc0) | (63 - 1783 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1784 break; 1785 case DBRI_ENABLE_MONO: /* built-in speaker */ 1786 if (mc->un.ord == 1) { 1787 ratt |= CS4215_SE; 1788 } else 1789 ratt &= ~CS4215_SE; 1790 break; 1791 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1792 if (mc->un.ord == 1) { 1793 latt |= CS4215_HE; 1794 } else 1795 latt &= ~CS4215_HE; 1796 break; 1797 case DBRI_ENABLE_LINE: /* line out */ 1798 if (mc->un.ord == 1) { 1799 latt |= CS4215_LE; 1800 } else 1801 latt &= ~CS4215_LE; 1802 break; 1803 case DBRI_VOL_MONITOR: 1804 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1805 sc->sc_monitor) 1806 return 0; 1807 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1808 break; 1809 case DBRI_INPUT_GAIN: 1810 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1811 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1812 break; 1813 case DBRI_INPUT_SELECT: 1814 if (mc->un.mask == sc->sc_input) 1815 return 0; 1816 sc->sc_input = mc->un.mask; 1817 break; 1818 } 1819 1820 sc->sc_latt = latt; 1821 sc->sc_ratt = ratt; 1822 1823 mmcodec_setgain(sc, 0); 1824 1825 return (0); 1826 } 1827 1828 static int 1829 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1830 { 1831 struct dbri_softc *sc = hdl; 1832 1833 switch (mc->dev) { 1834 case DBRI_VOL_OUTPUT: /* master volume */ 1835 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1836 (63 - (sc->sc_latt & 0x3f)) << 2; 1837 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1838 (63 - (sc->sc_ratt & 0x3f)) << 2; 1839 return (0); 1840 case DBRI_ENABLE_MONO: /* built-in speaker */ 1841 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1842 return 0; 1843 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1844 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1845 return 0; 1846 case DBRI_ENABLE_LINE: /* line out */ 1847 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1848 return 0; 1849 case DBRI_VOL_MONITOR: 1850 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1851 return 0; 1852 case DBRI_INPUT_GAIN: 1853 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1854 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1855 return 0; 1856 case DBRI_INPUT_SELECT: 1857 mc->un.mask = sc->sc_input; 1858 return 0; 1859 } 1860 return (EINVAL); 1861 } 1862 1863 static int 1864 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1865 { 1866 1867 switch (di->index) { 1868 case DBRI_MONITOR_CLASS: 1869 di->mixer_class = DBRI_MONITOR_CLASS; 1870 strcpy(di->label.name, AudioCmonitor); 1871 di->type = AUDIO_MIXER_CLASS; 1872 di->next = di->prev = AUDIO_MIXER_LAST; 1873 return 0; 1874 case DBRI_OUTPUT_CLASS: 1875 di->mixer_class = DBRI_OUTPUT_CLASS; 1876 strcpy(di->label.name, AudioCoutputs); 1877 di->type = AUDIO_MIXER_CLASS; 1878 di->next = di->prev = AUDIO_MIXER_LAST; 1879 return 0; 1880 case DBRI_INPUT_CLASS: 1881 di->mixer_class = DBRI_INPUT_CLASS; 1882 strcpy(di->label.name, AudioCinputs); 1883 di->type = AUDIO_MIXER_CLASS; 1884 di->next = di->prev = AUDIO_MIXER_LAST; 1885 return 0; 1886 case DBRI_VOL_OUTPUT: /* master volume */ 1887 di->mixer_class = DBRI_OUTPUT_CLASS; 1888 di->next = di->prev = AUDIO_MIXER_LAST; 1889 strcpy(di->label.name, AudioNmaster); 1890 di->type = AUDIO_MIXER_VALUE; 1891 di->un.v.num_channels = 2; 1892 di->un.v.delta = 16; 1893 strcpy(di->un.v.units.name, AudioNvolume); 1894 return (0); 1895 case DBRI_INPUT_GAIN: /* input gain */ 1896 di->mixer_class = DBRI_INPUT_CLASS; 1897 di->next = di->prev = AUDIO_MIXER_LAST; 1898 strcpy(di->label.name, AudioNrecord); 1899 di->type = AUDIO_MIXER_VALUE; 1900 di->un.v.num_channels = 2; 1901 strcpy(di->un.v.units.name, AudioNvolume); 1902 return (0); 1903 case DBRI_VOL_MONITOR: /* monitor volume */ 1904 di->mixer_class = DBRI_MONITOR_CLASS; 1905 di->next = di->prev = AUDIO_MIXER_LAST; 1906 strcpy(di->label.name, AudioNmonitor); 1907 di->type = AUDIO_MIXER_VALUE; 1908 di->un.v.num_channels = 1; 1909 strcpy(di->un.v.units.name, AudioNvolume); 1910 return (0); 1911 case DBRI_ENABLE_MONO: /* built-in speaker */ 1912 di->mixer_class = DBRI_OUTPUT_CLASS; 1913 di->next = di->prev = AUDIO_MIXER_LAST; 1914 strcpy(di->label.name, AudioNmono); 1915 di->type = AUDIO_MIXER_ENUM; 1916 di->un.e.num_mem = 2; 1917 strcpy(di->un.e.member[0].label.name, AudioNoff); 1918 di->un.e.member[0].ord = 0; 1919 strcpy(di->un.e.member[1].label.name, AudioNon); 1920 di->un.e.member[1].ord = 1; 1921 return (0); 1922 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1923 di->mixer_class = DBRI_OUTPUT_CLASS; 1924 di->next = di->prev = AUDIO_MIXER_LAST; 1925 strcpy(di->label.name, AudioNheadphone); 1926 di->type = AUDIO_MIXER_ENUM; 1927 di->un.e.num_mem = 2; 1928 strcpy(di->un.e.member[0].label.name, AudioNoff); 1929 di->un.e.member[0].ord = 0; 1930 strcpy(di->un.e.member[1].label.name, AudioNon); 1931 di->un.e.member[1].ord = 1; 1932 return (0); 1933 case DBRI_ENABLE_LINE: /* line out */ 1934 di->mixer_class = DBRI_OUTPUT_CLASS; 1935 di->next = di->prev = AUDIO_MIXER_LAST; 1936 strcpy(di->label.name, AudioNline); 1937 di->type = AUDIO_MIXER_ENUM; 1938 di->un.e.num_mem = 2; 1939 strcpy(di->un.e.member[0].label.name, AudioNoff); 1940 di->un.e.member[0].ord = 0; 1941 strcpy(di->un.e.member[1].label.name, AudioNon); 1942 di->un.e.member[1].ord = 1; 1943 return (0); 1944 case DBRI_INPUT_SELECT: 1945 di->mixer_class = DBRI_INPUT_CLASS; 1946 strcpy(di->label.name, AudioNsource); 1947 di->type = AUDIO_MIXER_SET; 1948 di->prev = di->next = AUDIO_MIXER_LAST; 1949 di->un.s.num_mem = 2; 1950 strcpy(di->un.s.member[0].label.name, AudioNline); 1951 di->un.s.member[0].mask = 1 << 0; 1952 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1953 di->un.s.member[1].mask = 1 << 1; 1954 return 0; 1955 } 1956 1957 return (ENXIO); 1958 } 1959 1960 static size_t 1961 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1962 { 1963 #ifdef DBRI_BIG_BUFFER 1964 return 0x20000; /* use 128KB buffer */ 1965 #else 1966 return bufsize; 1967 #endif 1968 } 1969 1970 static int 1971 dbri_get_props(void *hdl) 1972 { 1973 1974 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1975 } 1976 1977 static int 1978 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1979 void (*intr)(void *), void *intrarg, 1980 const struct audio_params *param) 1981 { 1982 struct dbri_softc *sc = hdl; 1983 unsigned long count, num; 1984 1985 if (sc->sc_playing) 1986 return 0; 1987 1988 count = (unsigned long)(((char *)end - (char *)start)); 1989 num = count / blksize; 1990 1991 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1992 (unsigned long)intr, 1993 (unsigned long)intrarg, blksize, count, num); 1994 1995 sc->sc_params = *param; 1996 1997 if (sc->sc_recording == 0) { 1998 /* do not muck with the codec when it's already in use */ 1999 if (mmcodec_setcontrol(sc) != 0) 2000 return -1; 2001 mmcodec_init_data(sc); 2002 } 2003 2004 /* 2005 * always use DMA descriptor 0 for output 2006 * no need to allocate them dynamically since we only ever have 2007 * exactly one input stream and exactly one output stream 2008 */ 2009 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 2010 sc->sc_playing = 1; 2011 return 0; 2012 } 2013 2014 static int 2015 dbri_halt_input(void *cookie) 2016 { 2017 struct dbri_softc *sc = cookie; 2018 2019 if (!sc->sc_recording) 2020 return 0; 2021 2022 sc->sc_recording = 0; 2023 pipe_reset(sc, 6); 2024 return 0; 2025 } 2026 2027 static int 2028 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2029 void (*intr)(void *), void *intrarg, 2030 const struct audio_params *param) 2031 { 2032 struct dbri_softc *sc = hdl; 2033 unsigned long count, num; 2034 2035 if (sc->sc_recording) 2036 return 0; 2037 2038 count = (unsigned long)(((char *)end - (char *)start)); 2039 num = count / blksize; 2040 2041 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2042 (unsigned long)intr, 2043 (unsigned long)intrarg, blksize, count, num); 2044 2045 sc->sc_params = *param; 2046 2047 if (sc->sc_playing == 0) { 2048 2049 /* 2050 * we don't support different parameters for playing and 2051 * recording anyway so don't bother whacking the codec if 2052 * it's already set up 2053 */ 2054 mmcodec_setcontrol(sc); 2055 mmcodec_init_data(sc); 2056 } 2057 2058 sc->sc_recording = 1; 2059 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2060 return 0; 2061 } 2062 2063 static void 2064 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 2065 { 2066 struct dbri_softc *sc = opaque; 2067 2068 *intr = &sc->sc_intr_lock; 2069 *thread = &sc->sc_lock; 2070 } 2071 2072 static uint32_t 2073 reverse_bytes(uint32_t b, int len) 2074 { 2075 switch (len) { 2076 case 32: 2077 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2078 case 16: 2079 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2080 case 8: 2081 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2082 case 4: 2083 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2084 case 2: 2085 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2086 case 1: 2087 case 0: 2088 break; 2089 default: 2090 DPRINTF("reverse_bytes: unsupported length\n"); 2091 }; 2092 2093 return (b); 2094 } 2095 2096 static void * 2097 dbri_malloc(void *v, int dir, size_t s) 2098 { 2099 struct dbri_softc *sc = v; 2100 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2101 int rseg; 2102 2103 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2104 &dd->dmamap) == 0) { 2105 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2106 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2107 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2108 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2109 if (dd->buf != NULL) { 2110 if (bus_dmamap_load(sc->sc_dmat, 2111 dd->dmamap, dd->buf, s, NULL, 2112 BUS_DMA_NOWAIT) == 0) { 2113 dd->len = s; 2114 dd->busy = 0; 2115 dd->callback = NULL; 2116 dd->dmabase = 2117 dd->dmamap->dm_segs[0].ds_addr; 2118 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2119 sc->sc_desc_used, (uint32_t)dd->buf); 2120 sc->sc_desc_used++; 2121 return dd->buf; 2122 } else 2123 aprint_error("dbri_malloc: load failed\n"); 2124 } else 2125 aprint_error("dbri_malloc: map returned NULL\n"); 2126 } else 2127 aprint_error("dbri_malloc: map failed\n"); 2128 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2129 } else 2130 aprint_error("dbri_malloc: malloc() failed\n"); 2131 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2132 } else 2133 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2134 return NULL; 2135 } 2136 2137 static void 2138 dbri_free(void *v, void *p, size_t size) 2139 { 2140 struct dbri_softc *sc = v; 2141 struct dbri_desc *dd; 2142 int i; 2143 2144 for (i = 0; i < sc->sc_desc_used; i++) { 2145 dd = &sc->sc_desc[i]; 2146 if (dd->buf == p) 2147 break; 2148 } 2149 if (i >= sc->sc_desc_used) 2150 return; 2151 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2152 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2153 } 2154 2155 static paddr_t 2156 dbri_mappage(void *v, void *mem, off_t off, int prot) 2157 { 2158 struct dbri_softc *sc = v; 2159 int current; 2160 2161 if (off < 0) 2162 return -1; 2163 2164 current = 0; 2165 while ((current < sc->sc_desc_used) && 2166 (sc->sc_desc[current].buf != mem)) 2167 current++; 2168 2169 if (current < sc->sc_desc_used) { 2170 return bus_dmamem_mmap(sc->sc_dmat, 2171 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2172 } 2173 2174 return -1; 2175 } 2176 2177 static int 2178 dbri_open(void *cookie, int flags) 2179 { 2180 struct dbri_softc *sc = cookie; 2181 2182 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2183 2184 if (sc->sc_refcount == 0) 2185 dbri_bring_up(sc); 2186 2187 sc->sc_refcount++; 2188 2189 return 0; 2190 } 2191 2192 static void 2193 dbri_close(void *cookie) 2194 { 2195 struct dbri_softc *sc = cookie; 2196 2197 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2198 2199 sc->sc_refcount--; 2200 KASSERT(sc->sc_refcount >= 0); 2201 if (sc->sc_refcount > 0) 2202 return; 2203 2204 dbri_set_power(sc, 0); 2205 sc->sc_playing = 0; 2206 sc->sc_recording = 0; 2207 } 2208 2209 static bool 2210 dbri_suspend(device_t self, const pmf_qual_t *qual) 2211 { 2212 struct dbri_softc *sc = device_private(self); 2213 2214 dbri_set_power(sc, 0); 2215 return true; 2216 } 2217 2218 static bool 2219 dbri_resume(device_t self, const pmf_qual_t *qual) 2220 { 2221 struct dbri_softc *sc = device_private(self); 2222 2223 if (sc->sc_powerstate != 0) 2224 return true; 2225 aprint_verbose("resume: %d\n", sc->sc_refcount); 2226 if (sc->sc_playing) { 2227 volatile uint32_t *cmd; 2228 2229 dbri_bring_up(sc); 2230 mutex_spin_enter(&sc->sc_intr_lock); 2231 cmd = dbri_command_lock(sc); 2232 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2233 0, sc->sc_pipe[4].sdp | 2234 DBRI_SDP_VALID_POINTER | 2235 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2236 *(cmd++) = sc->sc_dmabase + 2237 dbri_dma_off(xmit, 0); 2238 dbri_command_send(sc, cmd); 2239 mutex_spin_exit(&sc->sc_intr_lock); 2240 } 2241 return true; 2242 } 2243 2244 #endif /* NAUDIO > 0 */ 2245