1 /* $NetBSD: be.c,v 1.24 2001/01/14 17:38:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #ifdef NS 105 #include <netns/ns.h> 106 #include <netns/ns_if.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 #endif 113 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 #include <machine/autoconf.h> 117 118 #include <dev/sbus/sbusvar.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/sbus/qecreg.h> 124 #include <dev/sbus/qecvar.h> 125 #include <dev/sbus/bereg.h> 126 127 struct be_softc { 128 struct device sc_dev; 129 struct sbusdev sc_sd; /* sbus device */ 130 bus_space_tag_t sc_bustag; /* bus & dma tags */ 131 bus_dma_tag_t sc_dmatag; 132 bus_dmamap_t sc_dmamap; 133 struct ethercom sc_ethercom; 134 /*struct ifmedia sc_ifmedia; -* interface media */ 135 struct mii_data sc_mii; /* MII media control */ 136 #define sc_media sc_mii.mii_media/* shorthand */ 137 int sc_phys[2]; /* MII instance -> phy */ 138 139 struct callout sc_tick_ch; 140 141 /* 142 * Some `mii_softc' items we need to emulate MII operation 143 * for our internal transceiver. 144 */ 145 int sc_mii_inst; /* instance of internal phy */ 146 int sc_mii_active; /* currently active medium */ 147 int sc_mii_ticks; /* tick counter */ 148 int sc_mii_flags; /* phy status flags */ 149 #define MIIF_HAVELINK 0x04000000 150 int sc_intphy_curspeed; /* Established link speed */ 151 152 struct qec_softc *sc_qec; /* QEC parent */ 153 154 bus_space_handle_t sc_qr; /* QEC registers */ 155 bus_space_handle_t sc_br; /* BE registers */ 156 bus_space_handle_t sc_cr; /* channel registers */ 157 bus_space_handle_t sc_tr; /* transceiver registers */ 158 159 u_int sc_rev; 160 161 int sc_channel; /* channel number */ 162 int sc_burst; 163 164 struct qec_ring sc_rb; /* Packet Ring Buffer */ 165 166 /* MAC address */ 167 u_int8_t sc_enaddr[6]; 168 }; 169 170 int bematch __P((struct device *, struct cfdata *, void *)); 171 void beattach __P((struct device *, struct device *, void *)); 172 173 void beinit __P((struct be_softc *)); 174 void bestart __P((struct ifnet *)); 175 void bestop __P((struct be_softc *)); 176 void bewatchdog __P((struct ifnet *)); 177 int beioctl __P((struct ifnet *, u_long, caddr_t)); 178 void bereset __P((struct be_softc *)); 179 180 int beintr __P((void *)); 181 int berint __P((struct be_softc *)); 182 int betint __P((struct be_softc *)); 183 int beqint __P((struct be_softc *, u_int32_t)); 184 int beeint __P((struct be_softc *, u_int32_t)); 185 186 static void be_read __P((struct be_softc *, int, int)); 187 static int be_put __P((struct be_softc *, int, struct mbuf *)); 188 static struct mbuf *be_get __P((struct be_softc *, int, int)); 189 190 void be_pal_gate __P((struct be_softc *, int)); 191 192 /* ifmedia callbacks */ 193 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 194 int be_ifmedia_upd __P((struct ifnet *)); 195 196 void be_mcreset __P((struct be_softc *)); 197 198 /* MII methods & callbacks */ 199 static int be_mii_readreg __P((struct device *, int, int)); 200 static void be_mii_writereg __P((struct device *, int, int, int)); 201 static void be_mii_statchg __P((struct device *)); 202 203 /* MII helpers */ 204 static void be_mii_sync __P((struct be_softc *)); 205 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 206 static int be_mii_reset __P((struct be_softc *, int)); 207 static int be_tcvr_read_bit __P((struct be_softc *, int)); 208 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 209 210 void be_tick __P((void *)); 211 void be_intphy_auto __P((struct be_softc *)); 212 void be_intphy_status __P((struct be_softc *)); 213 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 214 215 216 struct cfattach be_ca = { 217 sizeof(struct be_softc), bematch, beattach 218 }; 219 220 int 221 bematch(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 struct sbus_attach_args *sa = aux; 227 228 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 229 } 230 231 void 232 beattach(parent, self, aux) 233 struct device *parent, *self; 234 void *aux; 235 { 236 struct sbus_attach_args *sa = aux; 237 struct qec_softc *qec = (struct qec_softc *)parent; 238 struct be_softc *sc = (struct be_softc *)self; 239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 240 struct mii_data *mii = &sc->sc_mii; 241 struct mii_softc *child; 242 int node = sa->sa_node; 243 bus_dma_tag_t dmatag = sa->sa_dmatag; 244 bus_dma_segment_t seg; 245 bus_size_t size; 246 int instance; 247 int rseg, error; 248 u_int32_t v; 249 extern void myetheraddr __P((u_char *)); 250 251 if (sa->sa_nreg < 3) { 252 printf("%s: only %d register sets\n", 253 self->dv_xname, sa->sa_nreg); 254 return; 255 } 256 257 if (bus_space_map2(sa->sa_bustag, 258 (bus_type_t)sa->sa_reg[0].sbr_slot, 259 (bus_addr_t)sa->sa_reg[0].sbr_offset, 260 (bus_size_t)sa->sa_reg[0].sbr_size, 261 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 262 printf("beattach: cannot map registers\n"); 263 return; 264 } 265 266 if (bus_space_map2(sa->sa_bustag, 267 (bus_type_t)sa->sa_reg[1].sbr_slot, 268 (bus_addr_t)sa->sa_reg[1].sbr_offset, 269 (bus_size_t)sa->sa_reg[1].sbr_size, 270 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 271 printf("beattach: cannot map registers\n"); 272 return; 273 } 274 275 if (bus_space_map2(sa->sa_bustag, 276 (bus_type_t)sa->sa_reg[2].sbr_slot, 277 (bus_addr_t)sa->sa_reg[2].sbr_offset, 278 (bus_size_t)sa->sa_reg[2].sbr_size, 279 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 280 printf("beattach: cannot map registers\n"); 281 return; 282 } 283 284 sc->sc_qec = qec; 285 sc->sc_qr = qec->sc_regs; 286 287 sc->sc_rev = getpropint(node, "board-version", -1); 288 printf(" rev %x", sc->sc_rev); 289 290 bestop(sc); 291 292 sc->sc_channel = getpropint(node, "channel#", -1); 293 if (sc->sc_channel == -1) 294 sc->sc_channel = 0; 295 296 sc->sc_burst = getpropint(node, "burst-sizes", -1); 297 if (sc->sc_burst == -1) 298 sc->sc_burst = qec->sc_burst; 299 300 /* Clamp at parent's burst sizes */ 301 sc->sc_burst &= qec->sc_burst; 302 303 /* Establish interrupt handler */ 304 if (sa->sa_nintr) 305 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 306 0, beintr, sc); 307 308 myetheraddr(sc->sc_enaddr); 309 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 310 311 /* 312 * Allocate descriptor ring and buffers. 313 */ 314 315 /* for now, allocate as many bufs as there are ring descriptors */ 316 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 317 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 318 319 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 320 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 321 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 322 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 323 324 /* Get a DMA handle */ 325 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 326 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 327 printf("%s: DMA map create error %d\n", self->dv_xname, error); 328 return; 329 } 330 331 /* Allocate DMA buffer */ 332 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 333 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 334 printf("%s: DMA buffer alloc error %d\n", 335 self->dv_xname, error); 336 return; 337 } 338 339 /* Load the buffer */ 340 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 341 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 342 printf("%s: DMA buffer map load error %d\n", 343 self->dv_xname, error); 344 bus_dmamem_free(dmatag, &seg, rseg); 345 return; 346 } 347 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 348 349 /* Map DMA memory in CPU addressable space */ 350 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 351 &sc->sc_rb.rb_membase, 352 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 353 printf("%s: DMA buffer map error %d\n", 354 self->dv_xname, error); 355 bus_dmamap_unload(dmatag, sc->sc_dmamap); 356 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 357 return; 358 } 359 360 /* 361 * Initialize our media structures and MII info. 362 */ 363 mii->mii_ifp = ifp; 364 mii->mii_readreg = be_mii_readreg; 365 mii->mii_writereg = be_mii_writereg; 366 mii->mii_statchg = be_mii_statchg; 367 368 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 369 370 callout_init(&sc->sc_tick_ch); 371 372 /* 373 * Initialize transceiver and determine which PHY connection to use. 374 */ 375 be_mii_sync(sc); 376 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 377 378 instance = 0; 379 380 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 381 382 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 383 MII_OFFSET_ANY, 0); 384 385 child = LIST_FIRST(&mii->mii_phys); 386 if (child == NULL) { 387 /* No PHY attached */ 388 ifmedia_add(&sc->sc_media, 389 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 390 0, NULL); 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 393 } else { 394 /* 395 * Note: we support just one PHY on the external 396 * MII connector. 397 */ 398 #ifdef DIAGNOSTIC 399 if (LIST_NEXT(child, mii_list) != NULL) { 400 printf("%s: spurious MII device %s attached\n", 401 sc->sc_dev.dv_xname, 402 child->mii_dev.dv_xname); 403 } 404 #endif 405 if (child->mii_phy != BE_PHY_EXTERNAL || 406 child->mii_inst > 0) { 407 printf("%s: cannot accomodate MII device %s" 408 " at phy %d, instance %d\n", 409 sc->sc_dev.dv_xname, 410 child->mii_dev.dv_xname, 411 child->mii_phy, child->mii_inst); 412 } else { 413 sc->sc_phys[instance] = child->mii_phy; 414 } 415 416 /* 417 * XXX - we can really do the following ONLY if the 418 * phy indeed has the auto negotiation capability!! 419 */ 420 ifmedia_set(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 422 423 /* Mark our current media setting */ 424 be_pal_gate(sc, BE_PHY_EXTERNAL); 425 instance++; 426 } 427 428 } 429 430 if ((v & MGMT_PAL_INT_MDIO) != 0) { 431 /* 432 * The be internal phy looks vaguely like MII hardware, 433 * but not enough to be able to use the MII device 434 * layer. Hence, we have to take care of media selection 435 * ourselves. 436 */ 437 438 sc->sc_mii_inst = instance; 439 sc->sc_phys[instance] = BE_PHY_INTERNAL; 440 441 /* Use `ifm_data' to store BMCR bits */ 442 ifmedia_add(&sc->sc_media, 443 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 444 0, NULL); 445 ifmedia_add(&sc->sc_media, 446 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 447 BMCR_S100, NULL); 448 ifmedia_add(&sc->sc_media, 449 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 450 0, NULL); 451 452 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 453 self->dv_xname); 454 455 be_mii_reset(sc, BE_PHY_INTERNAL); 456 /* Only set default medium here if there's no external PHY */ 457 if (instance == 0) { 458 be_pal_gate(sc, BE_PHY_INTERNAL); 459 ifmedia_set(&sc->sc_media, 460 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 461 } else 462 be_mii_writereg((void *)sc, 463 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 464 } 465 466 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 467 ifp->if_softc = sc; 468 ifp->if_start = bestart; 469 ifp->if_ioctl = beioctl; 470 ifp->if_watchdog = bewatchdog; 471 ifp->if_flags = 472 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 473 IFQ_SET_READY(&ifp->if_snd); 474 475 /* Attach the interface. */ 476 if_attach(ifp); 477 ether_ifattach(ifp, sc->sc_enaddr); 478 } 479 480 481 /* 482 * Routine to copy from mbuf chain to transmit buffer in 483 * network buffer memory. 484 */ 485 static __inline__ int 486 be_put(sc, idx, m) 487 struct be_softc *sc; 488 int idx; 489 struct mbuf *m; 490 { 491 struct mbuf *n; 492 int len, tlen = 0, boff = 0; 493 caddr_t bp; 494 495 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 496 497 for (; m; m = n) { 498 len = m->m_len; 499 if (len == 0) { 500 MFREE(m, n); 501 continue; 502 } 503 bcopy(mtod(m, caddr_t), bp+boff, len); 504 boff += len; 505 tlen += len; 506 MFREE(m, n); 507 } 508 return (tlen); 509 } 510 511 /* 512 * Pull data off an interface. 513 * Len is the length of data, with local net header stripped. 514 * We copy the data into mbufs. When full cluster sized units are present, 515 * we copy into clusters. 516 */ 517 static __inline__ struct mbuf * 518 be_get(sc, idx, totlen) 519 struct be_softc *sc; 520 int idx, totlen; 521 { 522 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 523 struct mbuf *m; 524 struct mbuf *top, **mp; 525 int len, pad, boff = 0; 526 caddr_t bp; 527 528 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 529 530 MGETHDR(m, M_DONTWAIT, MT_DATA); 531 if (m == NULL) 532 return (NULL); 533 m->m_pkthdr.rcvif = ifp; 534 m->m_pkthdr.len = totlen; 535 536 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 537 m->m_data += pad; 538 len = MHLEN - pad; 539 top = NULL; 540 mp = ⊤ 541 542 while (totlen > 0) { 543 if (top) { 544 MGET(m, M_DONTWAIT, MT_DATA); 545 if (m == NULL) { 546 m_freem(top); 547 return (NULL); 548 } 549 len = MLEN; 550 } 551 if (top && totlen >= MINCLSIZE) { 552 MCLGET(m, M_DONTWAIT); 553 if (m->m_flags & M_EXT) 554 len = MCLBYTES; 555 } 556 m->m_len = len = min(totlen, len); 557 bcopy(bp + boff, mtod(m, caddr_t), len); 558 boff += len; 559 totlen -= len; 560 *mp = m; 561 mp = &m->m_next; 562 } 563 564 return (top); 565 } 566 567 /* 568 * Pass a packet to the higher levels. 569 */ 570 static __inline__ void 571 be_read(sc, idx, len) 572 struct be_softc *sc; 573 int idx, len; 574 { 575 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 576 struct mbuf *m; 577 578 if (len <= sizeof(struct ether_header) || 579 len > ETHERMTU + sizeof(struct ether_header)) { 580 581 printf("%s: invalid packet size %d; dropping\n", 582 ifp->if_xname, len); 583 584 ifp->if_ierrors++; 585 return; 586 } 587 588 /* 589 * Pull packet off interface. 590 */ 591 m = be_get(sc, idx, len); 592 if (m == NULL) { 593 ifp->if_ierrors++; 594 return; 595 } 596 ifp->if_ipackets++; 597 598 #if NBPFILTER > 0 599 /* 600 * Check if there's a BPF listener on this interface. 601 * If so, hand off the raw packet to BPF. 602 */ 603 if (ifp->if_bpf) 604 bpf_mtap(ifp->if_bpf, m); 605 #endif 606 /* Pass the packet up. */ 607 (*ifp->if_input)(ifp, m); 608 } 609 610 /* 611 * Start output on interface. 612 * We make two assumptions here: 613 * 1) that the current priority is set to splnet _before_ this code 614 * is called *and* is returned to the appropriate priority after 615 * return 616 * 2) that the IFF_OACTIVE flag is checked before this code is called 617 * (i.e. that the output part of the interface is idle) 618 */ 619 void 620 bestart(ifp) 621 struct ifnet *ifp; 622 { 623 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 624 struct qec_xd *txd = sc->sc_rb.rb_txd; 625 struct mbuf *m; 626 unsigned int bix, len; 627 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 628 629 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 630 return; 631 632 bix = sc->sc_rb.rb_tdhead; 633 634 for (;;) { 635 IFQ_DEQUEUE(&ifp->if_snd, m); 636 if (m == 0) 637 break; 638 639 #if NBPFILTER > 0 640 /* 641 * If BPF is listening on this interface, let it see the 642 * packet before we commit it to the wire. 643 */ 644 if (ifp->if_bpf) 645 bpf_mtap(ifp->if_bpf, m); 646 #endif 647 648 /* 649 * Copy the mbuf chain into the transmit buffer. 650 */ 651 len = be_put(sc, bix, m); 652 653 /* 654 * Initialize transmit registers and start transmission 655 */ 656 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 657 (len & QEC_XD_LENGTH); 658 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 659 BE_CR_CTRL_TWAKEUP); 660 661 if (++bix == QEC_XD_RING_MAXSIZE) 662 bix = 0; 663 664 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 665 ifp->if_flags |= IFF_OACTIVE; 666 break; 667 } 668 } 669 670 sc->sc_rb.rb_tdhead = bix; 671 } 672 673 void 674 bestop(sc) 675 struct be_softc *sc; 676 { 677 int n; 678 bus_space_tag_t t = sc->sc_bustag; 679 bus_space_handle_t br = sc->sc_br; 680 681 callout_stop(&sc->sc_tick_ch); 682 683 /* Down the MII. */ 684 mii_down(&sc->sc_mii); 685 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 686 687 /* Stop the transmitter */ 688 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 689 for (n = 32; n > 0; n--) { 690 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 691 break; 692 DELAY(20); 693 } 694 695 /* Stop the receiver */ 696 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 697 for (n = 32; n > 0; n--) { 698 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 699 break; 700 DELAY(20); 701 } 702 } 703 704 /* 705 * Reset interface. 706 */ 707 void 708 bereset(sc) 709 struct be_softc *sc; 710 { 711 int s; 712 713 s = splnet(); 714 bestop(sc); 715 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 716 beinit(sc); 717 splx(s); 718 } 719 720 void 721 bewatchdog(ifp) 722 struct ifnet *ifp; 723 { 724 struct be_softc *sc = ifp->if_softc; 725 726 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 727 ++sc->sc_ethercom.ec_if.if_oerrors; 728 729 bereset(sc); 730 } 731 732 int 733 beintr(v) 734 void *v; 735 { 736 struct be_softc *sc = (struct be_softc *)v; 737 bus_space_tag_t t = sc->sc_bustag; 738 u_int32_t whyq, whyb, whyc; 739 int r = 0; 740 741 /* Read QEC status, channel status and BE status */ 742 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 743 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 744 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 745 746 if (whyq & QEC_STAT_BM) 747 r |= beeint(sc, whyb); 748 749 if (whyq & QEC_STAT_ER) 750 r |= beqint(sc, whyc); 751 752 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 753 r |= betint(sc); 754 755 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 756 r |= berint(sc); 757 758 return (r); 759 } 760 761 /* 762 * QEC Interrupt. 763 */ 764 int 765 beqint(sc, why) 766 struct be_softc *sc; 767 u_int32_t why; 768 { 769 int r = 0, rst = 0; 770 771 if (why & BE_CR_STAT_TXIRQ) 772 r |= 1; 773 if (why & BE_CR_STAT_RXIRQ) 774 r |= 1; 775 776 if (why & BE_CR_STAT_BERROR) { 777 r |= 1; 778 rst = 1; 779 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 780 } 781 782 if (why & BE_CR_STAT_TXDERR) { 783 r |= 1; 784 rst = 1; 785 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 786 } 787 788 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 789 r |= 1; 790 rst = 1; 791 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 792 if (why & BE_CR_STAT_TXLERR) 793 printf("Late "); 794 if (why & BE_CR_STAT_TXPERR) 795 printf("Parity "); 796 if (why & BE_CR_STAT_TXSERR) 797 printf("Generic "); 798 printf(")\n"); 799 } 800 801 if (why & BE_CR_STAT_RXDROP) { 802 r |= 1; 803 rst = 1; 804 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 805 } 806 807 if (why & BE_CR_STAT_RXSMALL) { 808 r |= 1; 809 rst = 1; 810 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 811 } 812 813 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 814 r |= 1; 815 rst = 1; 816 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 817 if (why & BE_CR_STAT_RXLERR) 818 printf("Late "); 819 if (why & BE_CR_STAT_RXPERR) 820 printf("Parity "); 821 if (why & BE_CR_STAT_RXSERR) 822 printf("Generic "); 823 printf(")\n"); 824 } 825 826 if (!r) { 827 rst = 1; 828 printf("%s: unexpected error interrupt %08x\n", 829 sc->sc_dev.dv_xname, why); 830 } 831 832 if (rst) { 833 printf("%s: resetting\n", sc->sc_dev.dv_xname); 834 bereset(sc); 835 } 836 837 return (r); 838 } 839 840 /* 841 * Error interrupt. 842 */ 843 int 844 beeint(sc, why) 845 struct be_softc *sc; 846 u_int32_t why; 847 { 848 int r = 0, rst = 0; 849 850 if (why & BE_BR_STAT_RFIFOVF) { 851 r |= 1; 852 rst = 1; 853 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 854 } 855 if (why & BE_BR_STAT_TFIFO_UND) { 856 r |= 1; 857 rst = 1; 858 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 859 } 860 if (why & BE_BR_STAT_MAXPKTERR) { 861 r |= 1; 862 rst = 1; 863 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 864 } 865 866 if (!r) { 867 rst = 1; 868 printf("%s: unexpected error interrupt %08x\n", 869 sc->sc_dev.dv_xname, why); 870 } 871 872 if (rst) { 873 printf("%s: resetting\n", sc->sc_dev.dv_xname); 874 bereset(sc); 875 } 876 877 return (r); 878 } 879 880 /* 881 * Transmit interrupt. 882 */ 883 int 884 betint(sc) 885 struct be_softc *sc; 886 { 887 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 888 bus_space_tag_t t = sc->sc_bustag; 889 bus_space_handle_t br = sc->sc_br; 890 unsigned int bix, txflags; 891 892 /* 893 * Unload collision counters 894 */ 895 ifp->if_collisions += 896 bus_space_read_4(t, br, BE_BRI_NCCNT) + 897 bus_space_read_4(t, br, BE_BRI_FCCNT) + 898 bus_space_read_4(t, br, BE_BRI_EXCNT) + 899 bus_space_read_4(t, br, BE_BRI_LTCNT); 900 901 /* 902 * the clear the hardware counters 903 */ 904 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 905 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 906 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 907 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 908 909 bix = sc->sc_rb.rb_tdtail; 910 911 for (;;) { 912 if (sc->sc_rb.rb_td_nbusy <= 0) 913 break; 914 915 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 916 917 if (txflags & QEC_XD_OWN) 918 break; 919 920 ifp->if_flags &= ~IFF_OACTIVE; 921 ifp->if_opackets++; 922 923 if (++bix == QEC_XD_RING_MAXSIZE) 924 bix = 0; 925 926 --sc->sc_rb.rb_td_nbusy; 927 } 928 929 sc->sc_rb.rb_tdtail = bix; 930 931 bestart(ifp); 932 933 if (sc->sc_rb.rb_td_nbusy == 0) 934 ifp->if_timer = 0; 935 936 return (1); 937 } 938 939 /* 940 * Receive interrupt. 941 */ 942 int 943 berint(sc) 944 struct be_softc *sc; 945 { 946 struct qec_xd *xd = sc->sc_rb.rb_rxd; 947 unsigned int bix, len; 948 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 949 950 bix = sc->sc_rb.rb_rdtail; 951 952 /* 953 * Process all buffers with valid data. 954 */ 955 for (;;) { 956 len = xd[bix].xd_flags; 957 if (len & QEC_XD_OWN) 958 break; 959 960 len &= QEC_XD_LENGTH; 961 be_read(sc, bix, len); 962 963 /* ... */ 964 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 965 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 966 967 if (++bix == QEC_XD_RING_MAXSIZE) 968 bix = 0; 969 } 970 971 sc->sc_rb.rb_rdtail = bix; 972 973 return (1); 974 } 975 976 int 977 beioctl(ifp, cmd, data) 978 struct ifnet *ifp; 979 u_long cmd; 980 caddr_t data; 981 { 982 struct be_softc *sc = ifp->if_softc; 983 struct ifaddr *ifa = (struct ifaddr *)data; 984 struct ifreq *ifr = (struct ifreq *)data; 985 int s, error = 0; 986 987 s = splnet(); 988 989 switch (cmd) { 990 case SIOCSIFADDR: 991 ifp->if_flags |= IFF_UP; 992 switch (ifa->ifa_addr->sa_family) { 993 #ifdef INET 994 case AF_INET: 995 beinit(sc); 996 arp_ifinit(ifp, ifa); 997 break; 998 #endif /* INET */ 999 #ifdef NS 1000 case AF_NS: 1001 { 1002 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1003 1004 if (ns_nullhost(*ina)) 1005 ina->x_host = 1006 *(union ns_host *)LLADDR(ifp->if_sadl); 1007 else 1008 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1009 sizeof(sc->sc_enaddr)); 1010 /* Set new address. */ 1011 beinit(sc); 1012 break; 1013 } 1014 #endif /* NS */ 1015 default: 1016 beinit(sc); 1017 break; 1018 } 1019 break; 1020 1021 case SIOCSIFFLAGS: 1022 if ((ifp->if_flags & IFF_UP) == 0 && 1023 (ifp->if_flags & IFF_RUNNING) != 0) { 1024 /* 1025 * If interface is marked down and it is running, then 1026 * stop it. 1027 */ 1028 bestop(sc); 1029 ifp->if_flags &= ~IFF_RUNNING; 1030 } else if ((ifp->if_flags & IFF_UP) != 0 && 1031 (ifp->if_flags & IFF_RUNNING) == 0) { 1032 /* 1033 * If interface is marked up and it is stopped, then 1034 * start it. 1035 */ 1036 beinit(sc); 1037 } else { 1038 /* 1039 * Reset the interface to pick up changes in any other 1040 * flags that affect hardware registers. 1041 */ 1042 bestop(sc); 1043 beinit(sc); 1044 } 1045 #ifdef BEDEBUG 1046 if (ifp->if_flags & IFF_DEBUG) 1047 sc->sc_debug = 1; 1048 else 1049 sc->sc_debug = 0; 1050 #endif 1051 break; 1052 1053 case SIOCADDMULTI: 1054 case SIOCDELMULTI: 1055 error = (cmd == SIOCADDMULTI) ? 1056 ether_addmulti(ifr, &sc->sc_ethercom): 1057 ether_delmulti(ifr, &sc->sc_ethercom); 1058 1059 if (error == ENETRESET) { 1060 /* 1061 * Multicast list has changed; set the hardware filter 1062 * accordingly. 1063 */ 1064 be_mcreset(sc); 1065 error = 0; 1066 } 1067 break; 1068 case SIOCGIFMEDIA: 1069 case SIOCSIFMEDIA: 1070 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1071 break; 1072 default: 1073 error = EINVAL; 1074 break; 1075 } 1076 splx(s); 1077 return (error); 1078 } 1079 1080 1081 void 1082 beinit(sc) 1083 struct be_softc *sc; 1084 { 1085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1086 bus_space_tag_t t = sc->sc_bustag; 1087 bus_space_handle_t br = sc->sc_br; 1088 bus_space_handle_t cr = sc->sc_cr; 1089 struct qec_softc *qec = sc->sc_qec; 1090 u_int32_t v; 1091 u_int32_t qecaddr; 1092 u_int8_t *ea; 1093 int s; 1094 1095 s = splnet(); 1096 1097 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1098 1099 bestop(sc); 1100 1101 ea = sc->sc_enaddr; 1102 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1103 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1104 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1105 1106 /* Clear hash table */ 1107 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1108 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1109 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1110 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1111 1112 /* Re-initialize RX configuration */ 1113 v = BE_BR_RXCFG_FIFO; 1114 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1115 1116 be_mcreset(sc); 1117 1118 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1119 1120 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1121 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1122 1123 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1124 1125 /* 1126 * Turn off counter expiration interrupts as well as 1127 * 'gotframe' and 'sentframe' 1128 */ 1129 bus_space_write_4(t, br, BE_BRI_IMASK, 1130 BE_BR_IMASK_GOTFRAME | 1131 BE_BR_IMASK_RCNTEXP | 1132 BE_BR_IMASK_ACNTEXP | 1133 BE_BR_IMASK_CCNTEXP | 1134 BE_BR_IMASK_LCNTEXP | 1135 BE_BR_IMASK_CVCNTEXP | 1136 BE_BR_IMASK_SENTFRAME | 1137 BE_BR_IMASK_NCNTEXP | 1138 BE_BR_IMASK_ECNTEXP | 1139 BE_BR_IMASK_LCCNTEXP | 1140 BE_BR_IMASK_FCNTEXP | 1141 BE_BR_IMASK_DTIMEXP); 1142 1143 /* Channel registers: */ 1144 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1145 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1146 1147 qecaddr = sc->sc_channel * qec->sc_msize; 1148 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1149 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1150 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1151 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1152 1153 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1154 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1155 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1156 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1157 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1158 1159 /* Enable transmitter */ 1160 bus_space_write_4(t, br, BE_BRI_TXCFG, 1161 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1162 1163 /* Enable receiver */ 1164 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1165 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1166 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1167 1168 ifp->if_flags |= IFF_RUNNING; 1169 ifp->if_flags &= ~IFF_OACTIVE; 1170 1171 be_ifmedia_upd(ifp); 1172 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1173 splx(s); 1174 } 1175 1176 void 1177 be_mcreset(sc) 1178 struct be_softc *sc; 1179 { 1180 struct ethercom *ec = &sc->sc_ethercom; 1181 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1182 bus_space_tag_t t = sc->sc_bustag; 1183 bus_space_handle_t br = sc->sc_br; 1184 u_int32_t crc; 1185 u_int16_t hash[4]; 1186 u_int8_t octet; 1187 u_int32_t v; 1188 int i, j; 1189 struct ether_multi *enm; 1190 struct ether_multistep step; 1191 1192 if (ifp->if_flags & IFF_PROMISC) { 1193 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1194 v |= BE_BR_RXCFG_PMISC; 1195 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1196 return; 1197 } 1198 1199 if (ifp->if_flags & IFF_ALLMULTI) { 1200 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1201 goto chipit; 1202 } 1203 1204 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1205 1206 ETHER_FIRST_MULTI(step, ec, enm); 1207 while (enm != NULL) { 1208 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1209 /* 1210 * We must listen to a range of multicast 1211 * addresses. For now, just accept all 1212 * multicasts, rather than trying to set only 1213 * those filter bits needed to match the range. 1214 * (At this time, the only use of address 1215 * ranges is for IP multicast routing, for 1216 * which the range is big enough to require 1217 * all bits set.) 1218 */ 1219 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1220 ifp->if_flags |= IFF_ALLMULTI; 1221 goto chipit; 1222 } 1223 1224 crc = 0xffffffff; 1225 1226 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1227 octet = enm->enm_addrlo[i]; 1228 1229 for (j = 0; j < 8; j++) { 1230 if ((crc & 1) ^ (octet & 1)) { 1231 crc >>= 1; 1232 crc ^= MC_POLY_LE; 1233 } 1234 else 1235 crc >>= 1; 1236 octet >>= 1; 1237 } 1238 } 1239 1240 crc >>= 26; 1241 hash[crc >> 4] |= 1 << (crc & 0xf); 1242 ETHER_NEXT_MULTI(step, enm); 1243 } 1244 1245 ifp->if_flags &= ~IFF_ALLMULTI; 1246 1247 chipit: 1248 /* Enable the hash filter */ 1249 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1250 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1251 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1252 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1253 1254 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1255 v &= ~BE_BR_RXCFG_PMISC; 1256 v |= BE_BR_RXCFG_HENABLE; 1257 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1258 } 1259 1260 /* 1261 * Set the tcvr to an idle state 1262 */ 1263 void 1264 be_mii_sync(sc) 1265 struct be_softc *sc; 1266 { 1267 bus_space_tag_t t = sc->sc_bustag; 1268 bus_space_handle_t tr = sc->sc_tr; 1269 int n = 32; 1270 1271 while (n--) { 1272 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1273 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1274 MGMT_PAL_OENAB); 1275 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1276 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1277 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1278 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1279 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1280 } 1281 } 1282 1283 void 1284 be_pal_gate(sc, phy) 1285 struct be_softc *sc; 1286 int phy; 1287 { 1288 bus_space_tag_t t = sc->sc_bustag; 1289 bus_space_handle_t tr = sc->sc_tr; 1290 u_int32_t v; 1291 1292 be_mii_sync(sc); 1293 1294 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1295 if (phy == BE_PHY_INTERNAL) 1296 v &= ~TCVR_PAL_SERIAL; 1297 1298 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1299 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1300 } 1301 1302 static int 1303 be_tcvr_read_bit(sc, phy) 1304 struct be_softc *sc; 1305 int phy; 1306 { 1307 bus_space_tag_t t = sc->sc_bustag; 1308 bus_space_handle_t tr = sc->sc_tr; 1309 int ret; 1310 1311 if (phy == BE_PHY_INTERNAL) { 1312 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1313 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1314 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1315 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1316 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1317 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1318 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1319 } else { 1320 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1321 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1322 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1323 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1324 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1325 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1326 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1327 } 1328 1329 return (ret); 1330 } 1331 1332 static void 1333 be_tcvr_write_bit(sc, phy, bit) 1334 struct be_softc *sc; 1335 int phy; 1336 int bit; 1337 { 1338 bus_space_tag_t t = sc->sc_bustag; 1339 bus_space_handle_t tr = sc->sc_tr; 1340 u_int32_t v; 1341 1342 if (phy == BE_PHY_INTERNAL) { 1343 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1344 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1345 } else { 1346 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1347 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1348 } 1349 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1350 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1351 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1352 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1353 } 1354 1355 static void 1356 be_mii_sendbits(sc, phy, data, nbits) 1357 struct be_softc *sc; 1358 int phy; 1359 u_int32_t data; 1360 int nbits; 1361 { 1362 int i; 1363 1364 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1365 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1366 } 1367 } 1368 1369 static int 1370 be_mii_readreg(self, phy, reg) 1371 struct device *self; 1372 int phy, reg; 1373 { 1374 struct be_softc *sc = (struct be_softc *)self; 1375 int val = 0, i; 1376 1377 /* 1378 * Read the PHY register by manually driving the MII control lines. 1379 */ 1380 be_mii_sync(sc); 1381 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1382 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1383 be_mii_sendbits(sc, phy, phy, 5); 1384 be_mii_sendbits(sc, phy, reg, 5); 1385 1386 (void) be_tcvr_read_bit(sc, phy); 1387 (void) be_tcvr_read_bit(sc, phy); 1388 1389 for (i = 15; i >= 0; i--) 1390 val |= (be_tcvr_read_bit(sc, phy) << i); 1391 1392 (void) be_tcvr_read_bit(sc, phy); 1393 (void) be_tcvr_read_bit(sc, phy); 1394 (void) be_tcvr_read_bit(sc, phy); 1395 1396 return (val); 1397 } 1398 1399 void 1400 be_mii_writereg(self, phy, reg, val) 1401 struct device *self; 1402 int phy, reg, val; 1403 { 1404 struct be_softc *sc = (struct be_softc *)self; 1405 int i; 1406 1407 /* 1408 * Write the PHY register by manually driving the MII control lines. 1409 */ 1410 be_mii_sync(sc); 1411 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1412 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1413 be_mii_sendbits(sc, phy, phy, 5); 1414 be_mii_sendbits(sc, phy, reg, 5); 1415 1416 be_tcvr_write_bit(sc, phy, 1); 1417 be_tcvr_write_bit(sc, phy, 0); 1418 1419 for (i = 15; i >= 0; i--) 1420 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1421 } 1422 1423 int 1424 be_mii_reset(sc, phy) 1425 struct be_softc *sc; 1426 int phy; 1427 { 1428 int n; 1429 1430 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1431 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1432 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1433 1434 for (n = 16; n >= 0; n--) { 1435 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1436 if ((bmcr & BMCR_RESET) == 0) 1437 break; 1438 DELAY(20); 1439 } 1440 if (n == 0) { 1441 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1442 return (EIO); 1443 } 1444 1445 return (0); 1446 } 1447 1448 void 1449 be_tick(arg) 1450 void *arg; 1451 { 1452 struct be_softc *sc = arg; 1453 int s = splnet(); 1454 1455 mii_tick(&sc->sc_mii); 1456 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1457 1458 splx(s); 1459 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1460 } 1461 1462 void 1463 be_mii_statchg(self) 1464 struct device *self; 1465 { 1466 struct be_softc *sc = (struct be_softc *)self; 1467 bus_space_tag_t t = sc->sc_bustag; 1468 bus_space_handle_t br = sc->sc_br; 1469 u_int instance; 1470 u_int32_t v; 1471 1472 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1473 #ifdef DIAGNOSTIC 1474 if (instance > 1) 1475 panic("be_mii_statchg: instance %d out of range", instance); 1476 #endif 1477 1478 /* Update duplex mode in TX configuration */ 1479 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1480 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1481 v |= BE_BR_TXCFG_FULLDPLX; 1482 else 1483 v &= ~BE_BR_TXCFG_FULLDPLX; 1484 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1485 1486 /* Change to appropriate gate in transceiver PAL */ 1487 be_pal_gate(sc, sc->sc_phys[instance]); 1488 } 1489 1490 /* 1491 * Get current media settings. 1492 */ 1493 void 1494 be_ifmedia_sts(ifp, ifmr) 1495 struct ifnet *ifp; 1496 struct ifmediareq *ifmr; 1497 { 1498 struct be_softc *sc = ifp->if_softc; 1499 1500 mii_pollstat(&sc->sc_mii); 1501 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1502 1503 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1504 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1505 return; 1506 } 1507 1508 /* 1509 * Set media options. 1510 */ 1511 int 1512 be_ifmedia_upd(ifp) 1513 struct ifnet *ifp; 1514 { 1515 struct be_softc *sc = ifp->if_softc; 1516 int error; 1517 1518 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1519 return (error); 1520 1521 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1522 } 1523 1524 /* 1525 * Service routine for our pseudo-MII internal transceiver. 1526 */ 1527 int 1528 be_intphy_service(sc, mii, cmd) 1529 struct be_softc *sc; 1530 struct mii_data *mii; 1531 int cmd; 1532 { 1533 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1534 int bmcr, bmsr; 1535 int error; 1536 1537 switch (cmd) { 1538 case MII_POLLSTAT: 1539 /* 1540 * If we're not polling our PHY instance, just return. 1541 */ 1542 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1543 return (0); 1544 1545 break; 1546 1547 case MII_MEDIACHG: 1548 1549 /* 1550 * If the media indicates a different PHY instance, 1551 * isolate ourselves. 1552 */ 1553 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1554 bmcr = be_mii_readreg((void *)sc, 1555 BE_PHY_INTERNAL, MII_BMCR); 1556 be_mii_writereg((void *)sc, 1557 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1558 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1559 sc->sc_intphy_curspeed = 0; 1560 return (0); 1561 } 1562 1563 1564 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1565 return (error); 1566 1567 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1568 1569 /* 1570 * Select the new mode and take out of isolation 1571 */ 1572 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1573 bmcr |= BMCR_S100; 1574 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1575 bmcr &= ~BMCR_S100; 1576 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1577 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1578 bmcr &= ~BMCR_S100; 1579 bmcr |= sc->sc_intphy_curspeed; 1580 } else { 1581 /* Keep isolated until link is up */ 1582 bmcr |= BMCR_ISO; 1583 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1584 } 1585 } 1586 1587 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1588 bmcr |= BMCR_FDX; 1589 else 1590 bmcr &= ~BMCR_FDX; 1591 1592 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1593 break; 1594 1595 case MII_TICK: 1596 /* 1597 * If we're not currently selected, just return. 1598 */ 1599 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1600 return (0); 1601 1602 /* Only used for automatic media selection */ 1603 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1604 return (0); 1605 1606 /* Is the interface even up? */ 1607 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1608 return (0); 1609 1610 /* 1611 * Check link status; if we don't have a link, try another 1612 * speed. We can't detect duplex mode, so half-duplex is 1613 * what we have to settle for. 1614 */ 1615 1616 /* Read twice in case the register is latched */ 1617 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1618 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1619 1620 if ((bmsr & BMSR_LINK) != 0) { 1621 /* We have a carrier */ 1622 bmcr = be_mii_readreg((void *)sc, 1623 BE_PHY_INTERNAL, MII_BMCR); 1624 1625 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1626 bmcr = be_mii_readreg((void *)sc, 1627 BE_PHY_INTERNAL, MII_BMCR); 1628 1629 sc->sc_mii_flags |= MIIF_HAVELINK; 1630 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1631 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1632 1633 bmcr &= ~BMCR_ISO; 1634 be_mii_writereg((void *)sc, 1635 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1636 1637 printf("%s: link up at %s Mbps\n", 1638 sc->sc_dev.dv_xname, 1639 (bmcr & BMCR_S100) ? "100" : "10"); 1640 } 1641 return (0); 1642 } 1643 1644 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1645 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1646 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1647 sc->sc_intphy_curspeed = 0; 1648 printf("%s: link down\n", sc->sc_dev.dv_xname); 1649 } 1650 1651 /* Only retry autonegotiation every 5 seconds. */ 1652 if (++sc->sc_mii_ticks < 5) 1653 return(0); 1654 1655 sc->sc_mii_ticks = 0; 1656 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1657 /* Just flip the fast speed bit */ 1658 bmcr ^= BMCR_S100; 1659 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1660 1661 break; 1662 1663 case MII_DOWN: 1664 /* Isolate this phy */ 1665 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1666 be_mii_writereg((void *)sc, 1667 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1668 return (0); 1669 } 1670 1671 /* Update the media status. */ 1672 be_intphy_status(sc); 1673 1674 /* Callback if something changed. */ 1675 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1676 (*mii->mii_statchg)((struct device *)sc); 1677 sc->sc_mii_active = mii->mii_media_active; 1678 } 1679 return (0); 1680 } 1681 1682 /* 1683 * Determine status of internal transceiver 1684 */ 1685 void 1686 be_intphy_status(sc) 1687 struct be_softc *sc; 1688 { 1689 struct mii_data *mii = &sc->sc_mii; 1690 int media_active, media_status; 1691 int bmcr, bmsr; 1692 1693 media_status = IFM_AVALID; 1694 media_active = 0; 1695 1696 /* 1697 * Internal transceiver; do the work here. 1698 */ 1699 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1700 1701 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1702 case (BMCR_S100 | BMCR_FDX): 1703 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1704 break; 1705 case BMCR_S100: 1706 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1707 break; 1708 case BMCR_FDX: 1709 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1710 break; 1711 case 0: 1712 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1713 break; 1714 } 1715 1716 /* Read twice in case the register is latched */ 1717 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1718 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1719 if (bmsr & BMSR_LINK) 1720 media_status |= IFM_ACTIVE; 1721 1722 mii->mii_media_status = media_status; 1723 mii->mii_media_active = media_active; 1724 } 1725